1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * This code is licensed under the GNU GPLv2 and later. 4 */ 5 6 #include "qemu/osdep.h" 7 #include "qapi/error.h" 8 #include "hw/dma/bcm2835_dma.h" 9 #include "hw/irq.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 13 /* DMA CS Control and Status bits */ 14 #define BCM2708_DMA_ACTIVE (1 << 0) 15 #define BCM2708_DMA_END (1 << 1) /* GE */ 16 #define BCM2708_DMA_INT (1 << 2) 17 #define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */ 18 #define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */ 19 #define BCM2708_DMA_ERR (1 << 8) 20 #define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */ 21 #define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */ 22 23 /* DMA control block "info" field bits */ 24 #define BCM2708_DMA_INT_EN (1 << 0) 25 #define BCM2708_DMA_TDMODE (1 << 1) 26 #define BCM2708_DMA_WAIT_RESP (1 << 3) 27 #define BCM2708_DMA_D_INC (1 << 4) 28 #define BCM2708_DMA_D_WIDTH (1 << 5) 29 #define BCM2708_DMA_D_DREQ (1 << 6) 30 #define BCM2708_DMA_D_IGNORE (1 << 7) 31 #define BCM2708_DMA_S_INC (1 << 8) 32 #define BCM2708_DMA_S_WIDTH (1 << 9) 33 #define BCM2708_DMA_S_DREQ (1 << 10) 34 #define BCM2708_DMA_S_IGNORE (1 << 11) 35 36 /* Register offsets */ 37 #define BCM2708_DMA_CS 0x00 /* Control and Status */ 38 #define BCM2708_DMA_ADDR 0x04 /* Control block address */ 39 /* the current control block appears in the following registers - read only */ 40 #define BCM2708_DMA_INFO 0x08 41 #define BCM2708_DMA_SOURCE_AD 0x0c 42 #define BCM2708_DMA_DEST_AD 0x10 43 #define BCM2708_DMA_TXFR_LEN 0x14 44 #define BCM2708_DMA_STRIDE 0x18 45 #define BCM2708_DMA_NEXTCB 0x1C 46 #define BCM2708_DMA_DEBUG 0x20 47 48 #define BCM2708_DMA_INT_STATUS 0xfe0 /* Interrupt status of each channel */ 49 #define BCM2708_DMA_ENABLE 0xff0 /* Global enable bits for each channel */ 50 51 #define BCM2708_DMA_CS_RW_MASK 0x30ff0001 /* All RW bits in DMA_CS */ 52 53 static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c) 54 { 55 BCM2835DMAChan *ch = &s->chan[c]; 56 uint32_t data, xlen, ylen; 57 int16_t dst_stride, src_stride; 58 59 if (!(s->enable & (1 << c))) { 60 return; 61 } 62 63 while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) { 64 /* CB fetch */ 65 ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad); 66 ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4); 67 ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8); 68 ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12); 69 ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16); 70 ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20); 71 72 if (ch->ti & BCM2708_DMA_TDMODE) { 73 /* 2D transfer mode */ 74 ylen = (ch->txfr_len >> 16) & 0x3fff; 75 xlen = ch->txfr_len & 0xffff; 76 dst_stride = ch->stride >> 16; 77 src_stride = ch->stride & 0xffff; 78 } else { 79 ylen = 1; 80 xlen = ch->txfr_len; 81 dst_stride = 0; 82 src_stride = 0; 83 } 84 85 while (ylen != 0) { 86 /* Normal transfer mode */ 87 while (xlen != 0) { 88 if (ch->ti & BCM2708_DMA_S_IGNORE) { 89 /* Ignore reads */ 90 data = 0; 91 } else { 92 data = ldl_le_phys(&s->dma_as, ch->source_ad); 93 } 94 if (ch->ti & BCM2708_DMA_S_INC) { 95 ch->source_ad += 4; 96 } 97 98 if (ch->ti & BCM2708_DMA_D_IGNORE) { 99 /* Ignore writes */ 100 } else { 101 stl_le_phys(&s->dma_as, ch->dest_ad, data); 102 } 103 if (ch->ti & BCM2708_DMA_D_INC) { 104 ch->dest_ad += 4; 105 } 106 107 /* update remaining transfer length */ 108 xlen -= 4; 109 if (ch->ti & BCM2708_DMA_TDMODE) { 110 ch->txfr_len = (ylen << 16) | xlen; 111 } else { 112 ch->txfr_len = xlen; 113 } 114 } 115 116 if (--ylen != 0) { 117 ch->source_ad += src_stride; 118 ch->dest_ad += dst_stride; 119 } 120 } 121 ch->cs |= BCM2708_DMA_END; 122 if (ch->ti & BCM2708_DMA_INT_EN) { 123 ch->cs |= BCM2708_DMA_INT; 124 s->int_status |= (1 << c); 125 qemu_set_irq(ch->irq, 1); 126 } 127 128 /* Process next CB */ 129 ch->conblk_ad = ch->nextconbk; 130 } 131 132 ch->cs &= ~BCM2708_DMA_ACTIVE; 133 ch->cs |= BCM2708_DMA_ISPAUSED; 134 } 135 136 static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch) 137 { 138 ch->cs = 0; 139 ch->conblk_ad = 0; 140 } 141 142 static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset, 143 unsigned size, unsigned c) 144 { 145 BCM2835DMAChan *ch; 146 uint32_t res = 0; 147 148 assert(size == 4); 149 assert(c < BCM2835_DMA_NCHANS); 150 151 ch = &s->chan[c]; 152 153 switch (offset) { 154 case BCM2708_DMA_CS: 155 res = ch->cs; 156 break; 157 case BCM2708_DMA_ADDR: 158 res = ch->conblk_ad; 159 break; 160 case BCM2708_DMA_INFO: 161 res = ch->ti; 162 break; 163 case BCM2708_DMA_SOURCE_AD: 164 res = ch->source_ad; 165 break; 166 case BCM2708_DMA_DEST_AD: 167 res = ch->dest_ad; 168 break; 169 case BCM2708_DMA_TXFR_LEN: 170 res = ch->txfr_len; 171 break; 172 case BCM2708_DMA_STRIDE: 173 res = ch->stride; 174 break; 175 case BCM2708_DMA_NEXTCB: 176 res = ch->nextconbk; 177 break; 178 case BCM2708_DMA_DEBUG: 179 res = ch->debug; 180 break; 181 default: 182 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 183 __func__, offset); 184 break; 185 } 186 return res; 187 } 188 189 static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset, 190 uint64_t value, unsigned size, unsigned c) 191 { 192 BCM2835DMAChan *ch; 193 uint32_t oldcs; 194 195 assert(size == 4); 196 assert(c < BCM2835_DMA_NCHANS); 197 198 ch = &s->chan[c]; 199 200 switch (offset) { 201 case BCM2708_DMA_CS: 202 oldcs = ch->cs; 203 if (value & BCM2708_DMA_RESET) { 204 bcm2835_dma_chan_reset(ch); 205 } 206 if (value & BCM2708_DMA_ABORT) { 207 /* abort is a no-op, since we always run to completion */ 208 } 209 if (value & BCM2708_DMA_END) { 210 ch->cs &= ~BCM2708_DMA_END; 211 } 212 if (value & BCM2708_DMA_INT) { 213 ch->cs &= ~BCM2708_DMA_INT; 214 s->int_status &= ~(1 << c); 215 qemu_set_irq(ch->irq, 0); 216 } 217 ch->cs &= ~BCM2708_DMA_CS_RW_MASK; 218 ch->cs |= (value & BCM2708_DMA_CS_RW_MASK); 219 if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) { 220 bcm2835_dma_update(s, c); 221 } 222 break; 223 case BCM2708_DMA_ADDR: 224 ch->conblk_ad = value; 225 break; 226 case BCM2708_DMA_DEBUG: 227 ch->debug = value; 228 break; 229 default: 230 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 231 __func__, offset); 232 break; 233 } 234 } 235 236 static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size) 237 { 238 BCM2835DMAState *s = opaque; 239 240 if (offset < 0xf00) { 241 return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf); 242 } else { 243 switch (offset) { 244 case BCM2708_DMA_INT_STATUS: 245 return s->int_status; 246 case BCM2708_DMA_ENABLE: 247 return s->enable; 248 default: 249 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 250 __func__, offset); 251 return 0; 252 } 253 } 254 } 255 256 static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size) 257 { 258 return bcm2835_dma_read(opaque, (offset & 0xff), size, 15); 259 } 260 261 static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value, 262 unsigned size) 263 { 264 BCM2835DMAState *s = opaque; 265 266 if (offset < 0xf00) { 267 bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf); 268 } else { 269 switch (offset) { 270 case BCM2708_DMA_INT_STATUS: 271 break; 272 case BCM2708_DMA_ENABLE: 273 s->enable = (value & 0xffff); 274 break; 275 default: 276 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 277 __func__, offset); 278 } 279 } 280 281 } 282 283 static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value, 284 unsigned size) 285 { 286 bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15); 287 } 288 289 static const MemoryRegionOps bcm2835_dma0_ops = { 290 .read = bcm2835_dma0_read, 291 .write = bcm2835_dma0_write, 292 .endianness = DEVICE_NATIVE_ENDIAN, 293 .valid.min_access_size = 4, 294 .valid.max_access_size = 4, 295 }; 296 297 static const MemoryRegionOps bcm2835_dma15_ops = { 298 .read = bcm2835_dma15_read, 299 .write = bcm2835_dma15_write, 300 .endianness = DEVICE_NATIVE_ENDIAN, 301 .valid.min_access_size = 4, 302 .valid.max_access_size = 4, 303 }; 304 305 static const VMStateDescription vmstate_bcm2835_dma_chan = { 306 .name = TYPE_BCM2835_DMA "-chan", 307 .version_id = 1, 308 .minimum_version_id = 1, 309 .fields = (VMStateField[]) { 310 VMSTATE_UINT32(cs, BCM2835DMAChan), 311 VMSTATE_UINT32(conblk_ad, BCM2835DMAChan), 312 VMSTATE_UINT32(ti, BCM2835DMAChan), 313 VMSTATE_UINT32(source_ad, BCM2835DMAChan), 314 VMSTATE_UINT32(dest_ad, BCM2835DMAChan), 315 VMSTATE_UINT32(txfr_len, BCM2835DMAChan), 316 VMSTATE_UINT32(stride, BCM2835DMAChan), 317 VMSTATE_UINT32(nextconbk, BCM2835DMAChan), 318 VMSTATE_UINT32(debug, BCM2835DMAChan), 319 VMSTATE_END_OF_LIST() 320 } 321 }; 322 323 static const VMStateDescription vmstate_bcm2835_dma = { 324 .name = TYPE_BCM2835_DMA, 325 .version_id = 1, 326 .minimum_version_id = 1, 327 .fields = (VMStateField[]) { 328 VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1, 329 vmstate_bcm2835_dma_chan, BCM2835DMAChan), 330 VMSTATE_UINT32(int_status, BCM2835DMAState), 331 VMSTATE_UINT32(enable, BCM2835DMAState), 332 VMSTATE_END_OF_LIST() 333 } 334 }; 335 336 static void bcm2835_dma_init(Object *obj) 337 { 338 BCM2835DMAState *s = BCM2835_DMA(obj); 339 int n; 340 341 /* DMA channels 0-14 occupy a contiguous block of IO memory, along 342 * with the global enable and interrupt status bits. Channel 15 343 * has the same register map, but is mapped at a discontiguous 344 * address in a separate IO block. 345 */ 346 memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s, 347 TYPE_BCM2835_DMA, 0x1000); 348 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0); 349 350 memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s, 351 TYPE_BCM2835_DMA "-chan15", 0x100); 352 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15); 353 354 for (n = 0; n < 16; n++) { 355 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq); 356 } 357 } 358 359 static void bcm2835_dma_reset(DeviceState *dev) 360 { 361 BCM2835DMAState *s = BCM2835_DMA(dev); 362 int n; 363 364 s->enable = 0xffff; 365 s->int_status = 0; 366 for (n = 0; n < BCM2835_DMA_NCHANS; n++) { 367 bcm2835_dma_chan_reset(&s->chan[n]); 368 } 369 } 370 371 static void bcm2835_dma_realize(DeviceState *dev, Error **errp) 372 { 373 BCM2835DMAState *s = BCM2835_DMA(dev); 374 Error *err = NULL; 375 Object *obj; 376 377 obj = object_property_get_link(OBJECT(dev), "dma-mr", &err); 378 if (obj == NULL) { 379 error_setg(errp, "%s: required dma-mr link not found: %s", 380 __func__, error_get_pretty(err)); 381 return; 382 } 383 384 s->dma_mr = MEMORY_REGION(obj); 385 address_space_init(&s->dma_as, s->dma_mr, NULL); 386 387 bcm2835_dma_reset(dev); 388 } 389 390 static void bcm2835_dma_class_init(ObjectClass *klass, void *data) 391 { 392 DeviceClass *dc = DEVICE_CLASS(klass); 393 394 dc->realize = bcm2835_dma_realize; 395 dc->reset = bcm2835_dma_reset; 396 dc->vmsd = &vmstate_bcm2835_dma; 397 } 398 399 static TypeInfo bcm2835_dma_info = { 400 .name = TYPE_BCM2835_DMA, 401 .parent = TYPE_SYS_BUS_DEVICE, 402 .instance_size = sizeof(BCM2835DMAState), 403 .class_init = bcm2835_dma_class_init, 404 .instance_init = bcm2835_dma_init, 405 }; 406 407 static void bcm2835_dma_register_types(void) 408 { 409 type_register_static(&bcm2835_dma_info); 410 } 411 412 type_init(bcm2835_dma_register_types) 413