1d2c0bd84SPaolo Bonzini /* 2d2c0bd84SPaolo Bonzini * TI OMAP DMA gigacell. 3d2c0bd84SPaolo Bonzini * 4d2c0bd84SPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5d2c0bd84SPaolo Bonzini * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br> 6d2c0bd84SPaolo Bonzini * 7d2c0bd84SPaolo Bonzini * This program is free software; you can redistribute it and/or 8d2c0bd84SPaolo Bonzini * modify it under the terms of the GNU General Public License as 9d2c0bd84SPaolo Bonzini * published by the Free Software Foundation; either version 2 of 10d2c0bd84SPaolo Bonzini * the License, or (at your option) any later version. 11d2c0bd84SPaolo Bonzini * 12d2c0bd84SPaolo Bonzini * This program is distributed in the hope that it will be useful, 13d2c0bd84SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d2c0bd84SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d2c0bd84SPaolo Bonzini * GNU General Public License for more details. 16d2c0bd84SPaolo Bonzini * 17d2c0bd84SPaolo Bonzini * You should have received a copy of the GNU General Public License along 18d2c0bd84SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 19d2c0bd84SPaolo Bonzini */ 20d2c0bd84SPaolo Bonzini #include "qemu-common.h" 21d2c0bd84SPaolo Bonzini #include "qemu/timer.h" 22d2c0bd84SPaolo Bonzini #include "hw/arm/omap.h" 23d2c0bd84SPaolo Bonzini #include "hw/irq.h" 24d2c0bd84SPaolo Bonzini #include "hw/arm/soc_dma.h" 25d2c0bd84SPaolo Bonzini 26d2c0bd84SPaolo Bonzini struct omap_dma_channel_s { 27d2c0bd84SPaolo Bonzini /* transfer data */ 28d2c0bd84SPaolo Bonzini int burst[2]; 29d2c0bd84SPaolo Bonzini int pack[2]; 30d2c0bd84SPaolo Bonzini int endian[2]; 31d2c0bd84SPaolo Bonzini int endian_lock[2]; 32d2c0bd84SPaolo Bonzini int translate[2]; 33d2c0bd84SPaolo Bonzini enum omap_dma_port port[2]; 34d2c0bd84SPaolo Bonzini hwaddr addr[2]; 35d2c0bd84SPaolo Bonzini omap_dma_addressing_t mode[2]; 36d2c0bd84SPaolo Bonzini uint32_t elements; 37d2c0bd84SPaolo Bonzini uint16_t frames; 38d2c0bd84SPaolo Bonzini int32_t frame_index[2]; 39d2c0bd84SPaolo Bonzini int16_t element_index[2]; 40d2c0bd84SPaolo Bonzini int data_type; 41d2c0bd84SPaolo Bonzini 42d2c0bd84SPaolo Bonzini /* transfer type */ 43d2c0bd84SPaolo Bonzini int transparent_copy; 44d2c0bd84SPaolo Bonzini int constant_fill; 45d2c0bd84SPaolo Bonzini uint32_t color; 46d2c0bd84SPaolo Bonzini int prefetch; 47d2c0bd84SPaolo Bonzini 48d2c0bd84SPaolo Bonzini /* auto init and linked channel data */ 49d2c0bd84SPaolo Bonzini int end_prog; 50d2c0bd84SPaolo Bonzini int repeat; 51d2c0bd84SPaolo Bonzini int auto_init; 52d2c0bd84SPaolo Bonzini int link_enabled; 53d2c0bd84SPaolo Bonzini int link_next_ch; 54d2c0bd84SPaolo Bonzini 55d2c0bd84SPaolo Bonzini /* interruption data */ 56d2c0bd84SPaolo Bonzini int interrupts; 57d2c0bd84SPaolo Bonzini int status; 58d2c0bd84SPaolo Bonzini int cstatus; 59d2c0bd84SPaolo Bonzini 60d2c0bd84SPaolo Bonzini /* state data */ 61d2c0bd84SPaolo Bonzini int active; 62d2c0bd84SPaolo Bonzini int enable; 63d2c0bd84SPaolo Bonzini int sync; 64d2c0bd84SPaolo Bonzini int src_sync; 65d2c0bd84SPaolo Bonzini int pending_request; 66d2c0bd84SPaolo Bonzini int waiting_end_prog; 67d2c0bd84SPaolo Bonzini uint16_t cpc; 68d2c0bd84SPaolo Bonzini int set_update; 69d2c0bd84SPaolo Bonzini 70d2c0bd84SPaolo Bonzini /* sync type */ 71d2c0bd84SPaolo Bonzini int fs; 72d2c0bd84SPaolo Bonzini int bs; 73d2c0bd84SPaolo Bonzini 74d2c0bd84SPaolo Bonzini /* compatibility */ 75d2c0bd84SPaolo Bonzini int omap_3_1_compatible_disable; 76d2c0bd84SPaolo Bonzini 77d2c0bd84SPaolo Bonzini qemu_irq irq; 78d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *sibling; 79d2c0bd84SPaolo Bonzini 80d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s { 81d2c0bd84SPaolo Bonzini hwaddr src, dest; 82d2c0bd84SPaolo Bonzini int frame; 83d2c0bd84SPaolo Bonzini int element; 84d2c0bd84SPaolo Bonzini int pck_element; 85d2c0bd84SPaolo Bonzini int frame_delta[2]; 86d2c0bd84SPaolo Bonzini int elem_delta[2]; 87d2c0bd84SPaolo Bonzini int frames; 88d2c0bd84SPaolo Bonzini int elements; 89d2c0bd84SPaolo Bonzini int pck_elements; 90d2c0bd84SPaolo Bonzini } active_set; 91d2c0bd84SPaolo Bonzini 92d2c0bd84SPaolo Bonzini struct soc_dma_ch_s *dma; 93d2c0bd84SPaolo Bonzini 94d2c0bd84SPaolo Bonzini /* unused parameters */ 95d2c0bd84SPaolo Bonzini int write_mode; 96d2c0bd84SPaolo Bonzini int priority; 97d2c0bd84SPaolo Bonzini int interleave_disabled; 98d2c0bd84SPaolo Bonzini int type; 99d2c0bd84SPaolo Bonzini int suspend; 100d2c0bd84SPaolo Bonzini int buf_disable; 101d2c0bd84SPaolo Bonzini }; 102d2c0bd84SPaolo Bonzini 103d2c0bd84SPaolo Bonzini struct omap_dma_s { 104d2c0bd84SPaolo Bonzini struct soc_dma_s *dma; 105d2c0bd84SPaolo Bonzini MemoryRegion iomem; 106d2c0bd84SPaolo Bonzini 107d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu; 108d2c0bd84SPaolo Bonzini omap_clk clk; 109d2c0bd84SPaolo Bonzini qemu_irq irq[4]; 110d2c0bd84SPaolo Bonzini void (*intr_update)(struct omap_dma_s *s); 111d2c0bd84SPaolo Bonzini enum omap_dma_model model; 112d2c0bd84SPaolo Bonzini int omap_3_1_mapping_disabled; 113d2c0bd84SPaolo Bonzini 114d2c0bd84SPaolo Bonzini uint32_t gcr; 115d2c0bd84SPaolo Bonzini uint32_t ocp; 116d2c0bd84SPaolo Bonzini uint32_t caps[5]; 117d2c0bd84SPaolo Bonzini uint32_t irqen[4]; 118d2c0bd84SPaolo Bonzini uint32_t irqstat[4]; 119d2c0bd84SPaolo Bonzini 120d2c0bd84SPaolo Bonzini int chans; 121d2c0bd84SPaolo Bonzini struct omap_dma_channel_s ch[32]; 122d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s lcd_ch; 123d2c0bd84SPaolo Bonzini }; 124d2c0bd84SPaolo Bonzini 125d2c0bd84SPaolo Bonzini /* Interrupts */ 126d2c0bd84SPaolo Bonzini #define TIMEOUT_INTR (1 << 0) 127d2c0bd84SPaolo Bonzini #define EVENT_DROP_INTR (1 << 1) 128d2c0bd84SPaolo Bonzini #define HALF_FRAME_INTR (1 << 2) 129d2c0bd84SPaolo Bonzini #define END_FRAME_INTR (1 << 3) 130d2c0bd84SPaolo Bonzini #define LAST_FRAME_INTR (1 << 4) 131d2c0bd84SPaolo Bonzini #define END_BLOCK_INTR (1 << 5) 132d2c0bd84SPaolo Bonzini #define SYNC (1 << 6) 133d2c0bd84SPaolo Bonzini #define END_PKT_INTR (1 << 7) 134d2c0bd84SPaolo Bonzini #define TRANS_ERR_INTR (1 << 8) 135d2c0bd84SPaolo Bonzini #define MISALIGN_INTR (1 << 11) 136d2c0bd84SPaolo Bonzini 137d2c0bd84SPaolo Bonzini static inline void omap_dma_interrupts_update(struct omap_dma_s *s) 138d2c0bd84SPaolo Bonzini { 139d2c0bd84SPaolo Bonzini return s->intr_update(s); 140d2c0bd84SPaolo Bonzini } 141d2c0bd84SPaolo Bonzini 142d2c0bd84SPaolo Bonzini static void omap_dma_channel_load(struct omap_dma_channel_s *ch) 143d2c0bd84SPaolo Bonzini { 144d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 145d2c0bd84SPaolo Bonzini int i, normal; 146d2c0bd84SPaolo Bonzini int omap_3_1 = !ch->omap_3_1_compatible_disable; 147d2c0bd84SPaolo Bonzini 148d2c0bd84SPaolo Bonzini /* 149d2c0bd84SPaolo Bonzini * TODO: verify address ranges and alignment 150d2c0bd84SPaolo Bonzini * TODO: port endianness 151d2c0bd84SPaolo Bonzini */ 152d2c0bd84SPaolo Bonzini 153d2c0bd84SPaolo Bonzini a->src = ch->addr[0]; 154d2c0bd84SPaolo Bonzini a->dest = ch->addr[1]; 155d2c0bd84SPaolo Bonzini a->frames = ch->frames; 156d2c0bd84SPaolo Bonzini a->elements = ch->elements; 157d2c0bd84SPaolo Bonzini a->pck_elements = ch->frame_index[!ch->src_sync]; 158d2c0bd84SPaolo Bonzini a->frame = 0; 159d2c0bd84SPaolo Bonzini a->element = 0; 160d2c0bd84SPaolo Bonzini a->pck_element = 0; 161d2c0bd84SPaolo Bonzini 162d2c0bd84SPaolo Bonzini if (unlikely(!ch->elements || !ch->frames)) { 163d2c0bd84SPaolo Bonzini printf("%s: bad DMA request\n", __FUNCTION__); 164d2c0bd84SPaolo Bonzini return; 165d2c0bd84SPaolo Bonzini } 166d2c0bd84SPaolo Bonzini 167d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) 168d2c0bd84SPaolo Bonzini switch (ch->mode[i]) { 169d2c0bd84SPaolo Bonzini case constant: 170d2c0bd84SPaolo Bonzini a->elem_delta[i] = 0; 171d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 172d2c0bd84SPaolo Bonzini break; 173d2c0bd84SPaolo Bonzini case post_incremented: 174d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type; 175d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 176d2c0bd84SPaolo Bonzini break; 177d2c0bd84SPaolo Bonzini case single_index: 178d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 179d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 180d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 181d2c0bd84SPaolo Bonzini break; 182d2c0bd84SPaolo Bonzini case double_index: 183d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 184d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 185d2c0bd84SPaolo Bonzini a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - 186d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i]; 187d2c0bd84SPaolo Bonzini break; 188d2c0bd84SPaolo Bonzini default: 189d2c0bd84SPaolo Bonzini break; 190d2c0bd84SPaolo Bonzini } 191d2c0bd84SPaolo Bonzini 192d2c0bd84SPaolo Bonzini normal = !ch->transparent_copy && !ch->constant_fill && 193d2c0bd84SPaolo Bonzini /* FIFO is big-endian so either (ch->endian[n] == 1) OR 194d2c0bd84SPaolo Bonzini * (ch->endian_lock[n] == 1) mean no endianism conversion. */ 195d2c0bd84SPaolo Bonzini (ch->endian[0] | ch->endian_lock[0]) == 196d2c0bd84SPaolo Bonzini (ch->endian[1] | ch->endian_lock[1]); 197d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) { 198d2c0bd84SPaolo Bonzini /* TODO: for a->frame_delta[i] > 0 still use the fast path, just 199d2c0bd84SPaolo Bonzini * limit min_elems in omap_dma_transfer_setup to the nearest frame 200d2c0bd84SPaolo Bonzini * end. */ 201d2c0bd84SPaolo Bonzini if (!a->elem_delta[i] && normal && 202d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 203d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_const; 204d2c0bd84SPaolo Bonzini else if (a->elem_delta[i] == ch->data_type && normal && 205d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 206d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_linear; 207d2c0bd84SPaolo Bonzini else 208d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_other; 209d2c0bd84SPaolo Bonzini 210d2c0bd84SPaolo Bonzini ch->dma->vaddr[i] = ch->addr[i]; 211d2c0bd84SPaolo Bonzini } 212d2c0bd84SPaolo Bonzini soc_dma_ch_update(ch->dma); 213d2c0bd84SPaolo Bonzini } 214d2c0bd84SPaolo Bonzini 215d2c0bd84SPaolo Bonzini static void omap_dma_activate_channel(struct omap_dma_s *s, 216d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 217d2c0bd84SPaolo Bonzini { 218d2c0bd84SPaolo Bonzini if (!ch->active) { 219d2c0bd84SPaolo Bonzini if (ch->set_update) { 220d2c0bd84SPaolo Bonzini /* It's not clear when the active set is supposed to be 221d2c0bd84SPaolo Bonzini * loaded from registers. We're already loading it when the 222d2c0bd84SPaolo Bonzini * channel is enabled, and for some guests this is not enough 223d2c0bd84SPaolo Bonzini * but that may be also because of a race condition (no 224d2c0bd84SPaolo Bonzini * delays in qemu) in the guest code, which we're just 225d2c0bd84SPaolo Bonzini * working around here. */ 226d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 227d2c0bd84SPaolo Bonzini ch->set_update = 0; 228d2c0bd84SPaolo Bonzini } 229d2c0bd84SPaolo Bonzini 230d2c0bd84SPaolo Bonzini ch->active = 1; 231d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 1); 232d2c0bd84SPaolo Bonzini if (ch->sync) 233d2c0bd84SPaolo Bonzini ch->status |= SYNC; 234d2c0bd84SPaolo Bonzini } 235d2c0bd84SPaolo Bonzini } 236d2c0bd84SPaolo Bonzini 237d2c0bd84SPaolo Bonzini static void omap_dma_deactivate_channel(struct omap_dma_s *s, 238d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 239d2c0bd84SPaolo Bonzini { 240d2c0bd84SPaolo Bonzini /* Update cpc */ 241d2c0bd84SPaolo Bonzini ch->cpc = ch->active_set.dest & 0xffff; 242d2c0bd84SPaolo Bonzini 243d2c0bd84SPaolo Bonzini if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { 244d2c0bd84SPaolo Bonzini /* Don't deactivate the channel */ 245d2c0bd84SPaolo Bonzini ch->pending_request = 0; 246d2c0bd84SPaolo Bonzini return; 247d2c0bd84SPaolo Bonzini } 248d2c0bd84SPaolo Bonzini 249d2c0bd84SPaolo Bonzini /* Don't deactive the channel if it is synchronized and the DMA request is 250d2c0bd84SPaolo Bonzini active */ 251*76486736SPeter Maydell if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) 252d2c0bd84SPaolo Bonzini return; 253d2c0bd84SPaolo Bonzini 254d2c0bd84SPaolo Bonzini if (ch->active) { 255d2c0bd84SPaolo Bonzini ch->active = 0; 256d2c0bd84SPaolo Bonzini ch->status &= ~SYNC; 257d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 0); 258d2c0bd84SPaolo Bonzini } 259d2c0bd84SPaolo Bonzini } 260d2c0bd84SPaolo Bonzini 261d2c0bd84SPaolo Bonzini static void omap_dma_enable_channel(struct omap_dma_s *s, 262d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 263d2c0bd84SPaolo Bonzini { 264d2c0bd84SPaolo Bonzini if (!ch->enable) { 265d2c0bd84SPaolo Bonzini ch->enable = 1; 266d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 267d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 268d2c0bd84SPaolo Bonzini /* TODO: theoretically if ch->sync && ch->prefetch && 269d2c0bd84SPaolo Bonzini * !s->dma->drqbmp[ch->sync], we should also activate and fetch 270d2c0bd84SPaolo Bonzini * from source and then stall until signalled. */ 271*76486736SPeter Maydell if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { 272d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 273d2c0bd84SPaolo Bonzini } 274d2c0bd84SPaolo Bonzini } 275*76486736SPeter Maydell } 276d2c0bd84SPaolo Bonzini 277d2c0bd84SPaolo Bonzini static void omap_dma_disable_channel(struct omap_dma_s *s, 278d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 279d2c0bd84SPaolo Bonzini { 280d2c0bd84SPaolo Bonzini if (ch->enable) { 281d2c0bd84SPaolo Bonzini ch->enable = 0; 282d2c0bd84SPaolo Bonzini /* Discard any pending request */ 283d2c0bd84SPaolo Bonzini ch->pending_request = 0; 284d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 285d2c0bd84SPaolo Bonzini } 286d2c0bd84SPaolo Bonzini } 287d2c0bd84SPaolo Bonzini 288d2c0bd84SPaolo Bonzini static void omap_dma_channel_end_prog(struct omap_dma_s *s, 289d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 290d2c0bd84SPaolo Bonzini { 291d2c0bd84SPaolo Bonzini if (ch->waiting_end_prog) { 292d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 293d2c0bd84SPaolo Bonzini if (!ch->sync || ch->pending_request) { 294d2c0bd84SPaolo Bonzini ch->pending_request = 0; 295d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 296d2c0bd84SPaolo Bonzini } 297d2c0bd84SPaolo Bonzini } 298d2c0bd84SPaolo Bonzini } 299d2c0bd84SPaolo Bonzini 300d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) 301d2c0bd84SPaolo Bonzini { 302d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 303d2c0bd84SPaolo Bonzini 304d2c0bd84SPaolo Bonzini /* First three interrupts are shared between two channels each. */ 305d2c0bd84SPaolo Bonzini if (ch[0].status | ch[6].status) 306d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[0].irq); 307d2c0bd84SPaolo Bonzini if (ch[1].status | ch[7].status) 308d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[1].irq); 309d2c0bd84SPaolo Bonzini if (ch[2].status | ch[8].status) 310d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[2].irq); 311d2c0bd84SPaolo Bonzini if (ch[3].status) 312d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[3].irq); 313d2c0bd84SPaolo Bonzini if (ch[4].status) 314d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[4].irq); 315d2c0bd84SPaolo Bonzini if (ch[5].status) 316d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[5].irq); 317d2c0bd84SPaolo Bonzini } 318d2c0bd84SPaolo Bonzini 319d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) 320d2c0bd84SPaolo Bonzini { 321d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 322d2c0bd84SPaolo Bonzini int i; 323d2c0bd84SPaolo Bonzini 324d2c0bd84SPaolo Bonzini for (i = s->chans; i; ch ++, i --) 325d2c0bd84SPaolo Bonzini if (ch->status) 326d2c0bd84SPaolo Bonzini qemu_irq_raise(ch->irq); 327d2c0bd84SPaolo Bonzini } 328d2c0bd84SPaolo Bonzini 329d2c0bd84SPaolo Bonzini static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) 330d2c0bd84SPaolo Bonzini { 331d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 0; 332d2c0bd84SPaolo Bonzini s->chans = 9; 333d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_1_update; 334d2c0bd84SPaolo Bonzini } 335d2c0bd84SPaolo Bonzini 336d2c0bd84SPaolo Bonzini static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) 337d2c0bd84SPaolo Bonzini { 338d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 1; 339d2c0bd84SPaolo Bonzini s->chans = 16; 340d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_2_update; 341d2c0bd84SPaolo Bonzini } 342d2c0bd84SPaolo Bonzini 343d2c0bd84SPaolo Bonzini static void omap_dma_process_request(struct omap_dma_s *s, int request) 344d2c0bd84SPaolo Bonzini { 345d2c0bd84SPaolo Bonzini int channel; 346d2c0bd84SPaolo Bonzini int drop_event = 0; 347d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 348d2c0bd84SPaolo Bonzini 349d2c0bd84SPaolo Bonzini for (channel = 0; channel < s->chans; channel ++, ch ++) { 350d2c0bd84SPaolo Bonzini if (ch->enable && ch->sync == request) { 351d2c0bd84SPaolo Bonzini if (!ch->active) 352d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 353d2c0bd84SPaolo Bonzini else if (!ch->pending_request) 354d2c0bd84SPaolo Bonzini ch->pending_request = 1; 355d2c0bd84SPaolo Bonzini else { 356d2c0bd84SPaolo Bonzini /* Request collision */ 357d2c0bd84SPaolo Bonzini /* Second request received while processing other request */ 358d2c0bd84SPaolo Bonzini ch->status |= EVENT_DROP_INTR; 359d2c0bd84SPaolo Bonzini drop_event = 1; 360d2c0bd84SPaolo Bonzini } 361d2c0bd84SPaolo Bonzini } 362d2c0bd84SPaolo Bonzini } 363d2c0bd84SPaolo Bonzini 364d2c0bd84SPaolo Bonzini if (drop_event) 365d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 366d2c0bd84SPaolo Bonzini } 367d2c0bd84SPaolo Bonzini 368d2c0bd84SPaolo Bonzini static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) 369d2c0bd84SPaolo Bonzini { 370d2c0bd84SPaolo Bonzini uint8_t value[4]; 371d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 372d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 373d2c0bd84SPaolo Bonzini int bytes = dma->bytes; 374d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 375d2c0bd84SPaolo Bonzini uint16_t status = ch->status; 376d2c0bd84SPaolo Bonzini #endif 377d2c0bd84SPaolo Bonzini 378d2c0bd84SPaolo Bonzini do { 379d2c0bd84SPaolo Bonzini /* Transfer a single element */ 380d2c0bd84SPaolo Bonzini /* FIXME: check the endianness */ 381d2c0bd84SPaolo Bonzini if (!ch->constant_fill) 382d2c0bd84SPaolo Bonzini cpu_physical_memory_read(a->src, value, ch->data_type); 383d2c0bd84SPaolo Bonzini else 384d2c0bd84SPaolo Bonzini *(uint32_t *) value = ch->color; 385d2c0bd84SPaolo Bonzini 386d2c0bd84SPaolo Bonzini if (!ch->transparent_copy || *(uint32_t *) value != ch->color) 387d2c0bd84SPaolo Bonzini cpu_physical_memory_write(a->dest, value, ch->data_type); 388d2c0bd84SPaolo Bonzini 389d2c0bd84SPaolo Bonzini a->src += a->elem_delta[0]; 390d2c0bd84SPaolo Bonzini a->dest += a->elem_delta[1]; 391d2c0bd84SPaolo Bonzini a->element ++; 392d2c0bd84SPaolo Bonzini 393d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 394d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 395d2c0bd84SPaolo Bonzini /* End of Frame */ 396d2c0bd84SPaolo Bonzini a->element = 0; 397d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 398d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 399d2c0bd84SPaolo Bonzini a->frame ++; 400d2c0bd84SPaolo Bonzini 401d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 402d2c0bd84SPaolo Bonzini if (!ch->sync) 403d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 404d2c0bd84SPaolo Bonzini } 405d2c0bd84SPaolo Bonzini } while ((bytes -= ch->data_type)); 406d2c0bd84SPaolo Bonzini #else 407d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 408d2c0bd84SPaolo Bonzini if (ch->sync && !ch->fs && !ch->bs) 409d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 410d2c0bd84SPaolo Bonzini 411d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 412d2c0bd84SPaolo Bonzini if (a->element == 1 && a->frame == a->frames - 1) 413d2c0bd84SPaolo Bonzini if (ch->interrupts & LAST_FRAME_INTR) 414d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 415d2c0bd84SPaolo Bonzini 416d2c0bd84SPaolo Bonzini /* If the half of the frame was reached, set the HALF_FRAME 417d2c0bd84SPaolo Bonzini interrupt */ 418d2c0bd84SPaolo Bonzini if (a->element == (a->elements >> 1)) 419d2c0bd84SPaolo Bonzini if (ch->interrupts & HALF_FRAME_INTR) 420d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 421d2c0bd84SPaolo Bonzini 422d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 423d2c0bd84SPaolo Bonzini a->pck_element ++; 424d2c0bd84SPaolo Bonzini /* Check if a full packet has beed transferred. */ 425d2c0bd84SPaolo Bonzini if (a->pck_element == a->pck_elements) { 426d2c0bd84SPaolo Bonzini a->pck_element = 0; 427d2c0bd84SPaolo Bonzini 428d2c0bd84SPaolo Bonzini /* Set the END_PKT interrupt */ 429d2c0bd84SPaolo Bonzini if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) 430d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 431d2c0bd84SPaolo Bonzini 432d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 433d2c0bd84SPaolo Bonzini if (ch->sync) 434d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 435d2c0bd84SPaolo Bonzini } 436d2c0bd84SPaolo Bonzini } 437d2c0bd84SPaolo Bonzini 438d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 439d2c0bd84SPaolo Bonzini /* End of Frame */ 440d2c0bd84SPaolo Bonzini a->element = 0; 441d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 442d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 443d2c0bd84SPaolo Bonzini a->frame ++; 444d2c0bd84SPaolo Bonzini 445d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 446d2c0bd84SPaolo Bonzini if (ch->sync && ch->fs && !ch->bs) 447d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 448d2c0bd84SPaolo Bonzini 449d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 450d2c0bd84SPaolo Bonzini if (!ch->sync) 451d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 452d2c0bd84SPaolo Bonzini 453d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 454d2c0bd84SPaolo Bonzini if (ch->interrupts & END_FRAME_INTR) 455d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 456d2c0bd84SPaolo Bonzini 457d2c0bd84SPaolo Bonzini if (a->frame == a->frames) { 458d2c0bd84SPaolo Bonzini /* End of Block */ 459d2c0bd84SPaolo Bonzini /* Disable the channel */ 460d2c0bd84SPaolo Bonzini 461d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 462d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 463d2c0bd84SPaolo Bonzini if (ch->link_enabled) 464d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, 465d2c0bd84SPaolo Bonzini &s->ch[ch->link_next_ch]); 466d2c0bd84SPaolo Bonzini } else { 467d2c0bd84SPaolo Bonzini if (!ch->auto_init) 468d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 469d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 470d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 471d2c0bd84SPaolo Bonzini else { 472d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 473d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 474d2c0bd84SPaolo Bonzini } 475d2c0bd84SPaolo Bonzini } 476d2c0bd84SPaolo Bonzini 477d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 478d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 479d2c0bd84SPaolo Bonzini } 480d2c0bd84SPaolo Bonzini } 481d2c0bd84SPaolo Bonzini } while (status == ch->status && ch->active); 482d2c0bd84SPaolo Bonzini 483d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 484d2c0bd84SPaolo Bonzini #endif 485d2c0bd84SPaolo Bonzini } 486d2c0bd84SPaolo Bonzini 487d2c0bd84SPaolo Bonzini enum { 488d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 489d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 490d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 491d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 492d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 493d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 494d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 495d2c0bd84SPaolo Bonzini omap_dma_intr_block, 496d2c0bd84SPaolo Bonzini __omap_dma_intr_last, 497d2c0bd84SPaolo Bonzini }; 498d2c0bd84SPaolo Bonzini 499d2c0bd84SPaolo Bonzini static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) 500d2c0bd84SPaolo Bonzini { 501d2c0bd84SPaolo Bonzini struct omap_dma_port_if_s *src_p, *dest_p; 502d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a; 503d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 504d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->dma->opaque; 505d2c0bd84SPaolo Bonzini int frames, min_elems, elements[__omap_dma_intr_last]; 506d2c0bd84SPaolo Bonzini 507d2c0bd84SPaolo Bonzini a = &ch->active_set; 508d2c0bd84SPaolo Bonzini 509d2c0bd84SPaolo Bonzini src_p = &s->mpu->port[ch->port[0]]; 510d2c0bd84SPaolo Bonzini dest_p = &s->mpu->port[ch->port[1]]; 511d2c0bd84SPaolo Bonzini if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || 512d2c0bd84SPaolo Bonzini (!dest_p->addr_valid(s->mpu, a->dest))) { 513d2c0bd84SPaolo Bonzini #if 0 514d2c0bd84SPaolo Bonzini /* Bus time-out */ 515d2c0bd84SPaolo Bonzini if (ch->interrupts & TIMEOUT_INTR) 516d2c0bd84SPaolo Bonzini ch->status |= TIMEOUT_INTR; 517d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 518d2c0bd84SPaolo Bonzini continue; 519d2c0bd84SPaolo Bonzini #endif 520d2c0bd84SPaolo Bonzini printf("%s: Bus time-out in DMA%i operation\n", 521d2c0bd84SPaolo Bonzini __FUNCTION__, dma->num); 522d2c0bd84SPaolo Bonzini } 523d2c0bd84SPaolo Bonzini 524d2c0bd84SPaolo Bonzini min_elems = INT_MAX; 525d2c0bd84SPaolo Bonzini 526d2c0bd84SPaolo Bonzini /* Check all the conditions that terminate the transfer starting 527d2c0bd84SPaolo Bonzini * with those that can occur the soonest. */ 528d2c0bd84SPaolo Bonzini #define INTR_CHECK(cond, id, nelements) \ 529d2c0bd84SPaolo Bonzini if (cond) { \ 530d2c0bd84SPaolo Bonzini elements[id] = nelements; \ 531d2c0bd84SPaolo Bonzini if (elements[id] < min_elems) \ 532d2c0bd84SPaolo Bonzini min_elems = elements[id]; \ 533d2c0bd84SPaolo Bonzini } else \ 534d2c0bd84SPaolo Bonzini elements[id] = INT_MAX; 535d2c0bd84SPaolo Bonzini 536d2c0bd84SPaolo Bonzini /* Elements */ 537d2c0bd84SPaolo Bonzini INTR_CHECK( 538d2c0bd84SPaolo Bonzini ch->sync && !ch->fs && !ch->bs, 539d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 540d2c0bd84SPaolo Bonzini 1) 541d2c0bd84SPaolo Bonzini 542d2c0bd84SPaolo Bonzini /* Frames */ 543d2c0bd84SPaolo Bonzini /* TODO: for transfers where entire frames can be read and written 544d2c0bd84SPaolo Bonzini * using memcpy() but a->frame_delta is non-zero, try to still do 545d2c0bd84SPaolo Bonzini * transfers using soc_dma but limit min_elems to a->elements - ... 546d2c0bd84SPaolo Bonzini * See also the TODO in omap_dma_channel_load. */ 547d2c0bd84SPaolo Bonzini INTR_CHECK( 548d2c0bd84SPaolo Bonzini (ch->interrupts & LAST_FRAME_INTR) && 549d2c0bd84SPaolo Bonzini ((a->frame < a->frames - 1) || !a->element), 550d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 551d2c0bd84SPaolo Bonzini (a->frames - a->frame - 2) * a->elements + 552d2c0bd84SPaolo Bonzini (a->elements - a->element + 1)) 553d2c0bd84SPaolo Bonzini INTR_CHECK( 554d2c0bd84SPaolo Bonzini ch->interrupts & HALF_FRAME_INTR, 555d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 556d2c0bd84SPaolo Bonzini (a->elements >> 1) + 557d2c0bd84SPaolo Bonzini (a->element >= (a->elements >> 1) ? a->elements : 0) - 558d2c0bd84SPaolo Bonzini a->element) 559d2c0bd84SPaolo Bonzini INTR_CHECK( 560d2c0bd84SPaolo Bonzini ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), 561d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 562d2c0bd84SPaolo Bonzini a->elements - a->element) 563d2c0bd84SPaolo Bonzini INTR_CHECK( 564d2c0bd84SPaolo Bonzini ch->sync && ch->fs && !ch->bs, 565d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 566d2c0bd84SPaolo Bonzini a->elements - a->element) 567d2c0bd84SPaolo Bonzini 568d2c0bd84SPaolo Bonzini /* Packets */ 569d2c0bd84SPaolo Bonzini INTR_CHECK( 570d2c0bd84SPaolo Bonzini ch->fs && ch->bs && 571d2c0bd84SPaolo Bonzini (ch->interrupts & END_PKT_INTR) && !ch->src_sync, 572d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 573d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 574d2c0bd84SPaolo Bonzini INTR_CHECK( 575d2c0bd84SPaolo Bonzini ch->fs && ch->bs && ch->sync, 576d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 577d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 578d2c0bd84SPaolo Bonzini 579d2c0bd84SPaolo Bonzini /* Blocks */ 580d2c0bd84SPaolo Bonzini INTR_CHECK( 581d2c0bd84SPaolo Bonzini 1, 582d2c0bd84SPaolo Bonzini omap_dma_intr_block, 583d2c0bd84SPaolo Bonzini (a->frames - a->frame - 1) * a->elements + 584d2c0bd84SPaolo Bonzini (a->elements - a->element)) 585d2c0bd84SPaolo Bonzini 586d2c0bd84SPaolo Bonzini dma->bytes = min_elems * ch->data_type; 587d2c0bd84SPaolo Bonzini 588d2c0bd84SPaolo Bonzini /* Set appropriate interrupts and/or deactivate channels */ 589d2c0bd84SPaolo Bonzini 590d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 591d2c0bd84SPaolo Bonzini /* TODO: should all of this only be done if dma->update, and otherwise 592d2c0bd84SPaolo Bonzini * inside omap_dma_transfer_generic below - check what's faster. */ 593d2c0bd84SPaolo Bonzini if (dma->update) { 594d2c0bd84SPaolo Bonzini #endif 595d2c0bd84SPaolo Bonzini 596d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 597d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_element_sync]) 598d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 599d2c0bd84SPaolo Bonzini 600d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 601d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_last_frame]) 602d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 603d2c0bd84SPaolo Bonzini 604d2c0bd84SPaolo Bonzini /* If exactly half of the frame was reached, set the HALF_FRAME 605d2c0bd84SPaolo Bonzini interrupt */ 606d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_half_frame]) 607d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 608d2c0bd84SPaolo Bonzini 609d2c0bd84SPaolo Bonzini /* If a full packet has been transferred, set the END_PKT interrupt */ 610d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet]) 611d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 612d2c0bd84SPaolo Bonzini 613d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 614d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet_sync]) 615d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 616d2c0bd84SPaolo Bonzini 617d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 618d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame_sync]) 619d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 620d2c0bd84SPaolo Bonzini 621d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 622d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame]) 623d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 624d2c0bd84SPaolo Bonzini 625d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_block]) { 626d2c0bd84SPaolo Bonzini /* End of Block */ 627d2c0bd84SPaolo Bonzini /* Disable the channel */ 628d2c0bd84SPaolo Bonzini 629d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 630d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 631d2c0bd84SPaolo Bonzini if (ch->link_enabled) 632d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); 633d2c0bd84SPaolo Bonzini } else { 634d2c0bd84SPaolo Bonzini if (!ch->auto_init) 635d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 636d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 637d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 638d2c0bd84SPaolo Bonzini else { 639d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 640d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 641d2c0bd84SPaolo Bonzini } 642d2c0bd84SPaolo Bonzini } 643d2c0bd84SPaolo Bonzini 644d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 645d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 646d2c0bd84SPaolo Bonzini } 647d2c0bd84SPaolo Bonzini 648d2c0bd84SPaolo Bonzini /* Update packet number */ 649d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 650d2c0bd84SPaolo Bonzini a->pck_element += min_elems; 651d2c0bd84SPaolo Bonzini a->pck_element %= a->pck_elements; 652d2c0bd84SPaolo Bonzini } 653d2c0bd84SPaolo Bonzini 654d2c0bd84SPaolo Bonzini /* TODO: check if we really need to update anything here or perhaps we 655d2c0bd84SPaolo Bonzini * can skip part of this. */ 656d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 657d2c0bd84SPaolo Bonzini if (dma->update) { 658d2c0bd84SPaolo Bonzini #endif 659d2c0bd84SPaolo Bonzini a->element += min_elems; 660d2c0bd84SPaolo Bonzini 661d2c0bd84SPaolo Bonzini frames = a->element / a->elements; 662d2c0bd84SPaolo Bonzini a->element = a->element % a->elements; 663d2c0bd84SPaolo Bonzini a->frame += frames; 664d2c0bd84SPaolo Bonzini a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; 665d2c0bd84SPaolo Bonzini a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; 666d2c0bd84SPaolo Bonzini 667d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 668d2c0bd84SPaolo Bonzini if (!ch->sync && frames) 669d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 670d2c0bd84SPaolo Bonzini 671d2c0bd84SPaolo Bonzini /* TODO: if the destination port is IMIF or EMIFF, set the dirty 672d2c0bd84SPaolo Bonzini * bits on it. */ 673d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 674d2c0bd84SPaolo Bonzini } 675d2c0bd84SPaolo Bonzini #else 676d2c0bd84SPaolo Bonzini } 677d2c0bd84SPaolo Bonzini #endif 678d2c0bd84SPaolo Bonzini 679d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 680d2c0bd84SPaolo Bonzini } 681d2c0bd84SPaolo Bonzini 682d2c0bd84SPaolo Bonzini void omap_dma_reset(struct soc_dma_s *dma) 683d2c0bd84SPaolo Bonzini { 684d2c0bd84SPaolo Bonzini int i; 685d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 686d2c0bd84SPaolo Bonzini 687d2c0bd84SPaolo Bonzini soc_dma_reset(s->dma); 688d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 689d2c0bd84SPaolo Bonzini s->gcr = 0x0004; 690d2c0bd84SPaolo Bonzini else 691d2c0bd84SPaolo Bonzini s->gcr = 0x00010010; 692d2c0bd84SPaolo Bonzini s->ocp = 0x00000000; 693d2c0bd84SPaolo Bonzini memset(&s->irqstat, 0, sizeof(s->irqstat)); 694d2c0bd84SPaolo Bonzini memset(&s->irqen, 0, sizeof(s->irqen)); 695d2c0bd84SPaolo Bonzini s->lcd_ch.src = emiff; 696d2c0bd84SPaolo Bonzini s->lcd_ch.condition = 0; 697d2c0bd84SPaolo Bonzini s->lcd_ch.interrupts = 0; 698d2c0bd84SPaolo Bonzini s->lcd_ch.dual = 0; 699d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 700d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 701d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 702d2c0bd84SPaolo Bonzini s->ch[i].suspend = 0; 703d2c0bd84SPaolo Bonzini s->ch[i].prefetch = 0; 704d2c0bd84SPaolo Bonzini s->ch[i].buf_disable = 0; 705d2c0bd84SPaolo Bonzini s->ch[i].src_sync = 0; 706d2c0bd84SPaolo Bonzini memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); 707d2c0bd84SPaolo Bonzini memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); 708d2c0bd84SPaolo Bonzini memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); 709d2c0bd84SPaolo Bonzini memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); 710d2c0bd84SPaolo Bonzini memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); 711d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); 712d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); 713d2c0bd84SPaolo Bonzini memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); 714d2c0bd84SPaolo Bonzini s->ch[i].write_mode = 0; 715d2c0bd84SPaolo Bonzini s->ch[i].data_type = 0; 716d2c0bd84SPaolo Bonzini s->ch[i].transparent_copy = 0; 717d2c0bd84SPaolo Bonzini s->ch[i].constant_fill = 0; 718d2c0bd84SPaolo Bonzini s->ch[i].color = 0x00000000; 719d2c0bd84SPaolo Bonzini s->ch[i].end_prog = 0; 720d2c0bd84SPaolo Bonzini s->ch[i].repeat = 0; 721d2c0bd84SPaolo Bonzini s->ch[i].auto_init = 0; 722d2c0bd84SPaolo Bonzini s->ch[i].link_enabled = 0; 723d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 724d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0003; 725d2c0bd84SPaolo Bonzini else 726d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0000; 727d2c0bd84SPaolo Bonzini s->ch[i].status = 0; 728d2c0bd84SPaolo Bonzini s->ch[i].cstatus = 0; 729d2c0bd84SPaolo Bonzini s->ch[i].active = 0; 730d2c0bd84SPaolo Bonzini s->ch[i].enable = 0; 731d2c0bd84SPaolo Bonzini s->ch[i].sync = 0; 732d2c0bd84SPaolo Bonzini s->ch[i].pending_request = 0; 733d2c0bd84SPaolo Bonzini s->ch[i].waiting_end_prog = 0; 734d2c0bd84SPaolo Bonzini s->ch[i].cpc = 0x0000; 735d2c0bd84SPaolo Bonzini s->ch[i].fs = 0; 736d2c0bd84SPaolo Bonzini s->ch[i].bs = 0; 737d2c0bd84SPaolo Bonzini s->ch[i].omap_3_1_compatible_disable = 0; 738d2c0bd84SPaolo Bonzini memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); 739d2c0bd84SPaolo Bonzini s->ch[i].priority = 0; 740d2c0bd84SPaolo Bonzini s->ch[i].interleave_disabled = 0; 741d2c0bd84SPaolo Bonzini s->ch[i].type = 0; 742d2c0bd84SPaolo Bonzini } 743d2c0bd84SPaolo Bonzini } 744d2c0bd84SPaolo Bonzini 745d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_read(struct omap_dma_s *s, 746d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t *value) 747d2c0bd84SPaolo Bonzini { 748d2c0bd84SPaolo Bonzini switch (reg) { 749d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 750d2c0bd84SPaolo Bonzini *value = (ch->burst[1] << 14) | 751d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 752d2c0bd84SPaolo Bonzini (ch->port[1] << 9) | 753d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 754d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 755d2c0bd84SPaolo Bonzini (ch->port[0] << 2) | 756d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 757d2c0bd84SPaolo Bonzini break; 758d2c0bd84SPaolo Bonzini 759d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 760d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 761d2c0bd84SPaolo Bonzini *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ 762d2c0bd84SPaolo Bonzini else 763d2c0bd84SPaolo Bonzini *value = ch->omap_3_1_compatible_disable << 10; 764d2c0bd84SPaolo Bonzini *value |= (ch->mode[1] << 14) | 765d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 766d2c0bd84SPaolo Bonzini (ch->end_prog << 11) | 767d2c0bd84SPaolo Bonzini (ch->repeat << 9) | 768d2c0bd84SPaolo Bonzini (ch->auto_init << 8) | 769d2c0bd84SPaolo Bonzini (ch->enable << 7) | 770d2c0bd84SPaolo Bonzini (ch->priority << 6) | 771d2c0bd84SPaolo Bonzini (ch->fs << 5) | ch->sync; 772d2c0bd84SPaolo Bonzini break; 773d2c0bd84SPaolo Bonzini 774d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 775d2c0bd84SPaolo Bonzini *value = ch->interrupts; 776d2c0bd84SPaolo Bonzini break; 777d2c0bd84SPaolo Bonzini 778d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 779d2c0bd84SPaolo Bonzini *value = ch->status; 780d2c0bd84SPaolo Bonzini ch->status &= SYNC; 781d2c0bd84SPaolo Bonzini if (!ch->omap_3_1_compatible_disable && ch->sibling) { 782d2c0bd84SPaolo Bonzini *value |= (ch->sibling->status & 0x3f) << 6; 783d2c0bd84SPaolo Bonzini ch->sibling->status &= SYNC; 784d2c0bd84SPaolo Bonzini } 785d2c0bd84SPaolo Bonzini qemu_irq_lower(ch->irq); 786d2c0bd84SPaolo Bonzini break; 787d2c0bd84SPaolo Bonzini 788d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 789d2c0bd84SPaolo Bonzini *value = ch->addr[0] & 0x0000ffff; 790d2c0bd84SPaolo Bonzini break; 791d2c0bd84SPaolo Bonzini 792d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 793d2c0bd84SPaolo Bonzini *value = ch->addr[0] >> 16; 794d2c0bd84SPaolo Bonzini break; 795d2c0bd84SPaolo Bonzini 796d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 797d2c0bd84SPaolo Bonzini *value = ch->addr[1] & 0x0000ffff; 798d2c0bd84SPaolo Bonzini break; 799d2c0bd84SPaolo Bonzini 800d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 801d2c0bd84SPaolo Bonzini *value = ch->addr[1] >> 16; 802d2c0bd84SPaolo Bonzini break; 803d2c0bd84SPaolo Bonzini 804d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 805d2c0bd84SPaolo Bonzini *value = ch->elements; 806d2c0bd84SPaolo Bonzini break; 807d2c0bd84SPaolo Bonzini 808d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 809d2c0bd84SPaolo Bonzini *value = ch->frames; 810d2c0bd84SPaolo Bonzini break; 811d2c0bd84SPaolo Bonzini 812d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 813d2c0bd84SPaolo Bonzini *value = ch->frame_index[0]; 814d2c0bd84SPaolo Bonzini break; 815d2c0bd84SPaolo Bonzini 816d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 817d2c0bd84SPaolo Bonzini *value = ch->element_index[0]; 818d2c0bd84SPaolo Bonzini break; 819d2c0bd84SPaolo Bonzini 820d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 821d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) 822d2c0bd84SPaolo Bonzini *value = ch->active_set.src & 0xffff; /* CSAC */ 823d2c0bd84SPaolo Bonzini else 824d2c0bd84SPaolo Bonzini *value = ch->cpc; 825d2c0bd84SPaolo Bonzini break; 826d2c0bd84SPaolo Bonzini 827d2c0bd84SPaolo Bonzini case 0x1a: /* DMA_CDAC */ 828d2c0bd84SPaolo Bonzini *value = ch->active_set.dest & 0xffff; /* CDAC */ 829d2c0bd84SPaolo Bonzini break; 830d2c0bd84SPaolo Bonzini 831d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 832d2c0bd84SPaolo Bonzini *value = ch->element_index[1]; 833d2c0bd84SPaolo Bonzini break; 834d2c0bd84SPaolo Bonzini 835d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 836d2c0bd84SPaolo Bonzini *value = ch->frame_index[1]; 837d2c0bd84SPaolo Bonzini break; 838d2c0bd84SPaolo Bonzini 839d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 840d2c0bd84SPaolo Bonzini *value = ch->color & 0xffff; 841d2c0bd84SPaolo Bonzini break; 842d2c0bd84SPaolo Bonzini 843d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 844d2c0bd84SPaolo Bonzini *value = ch->color >> 16; 845d2c0bd84SPaolo Bonzini break; 846d2c0bd84SPaolo Bonzini 847d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 848d2c0bd84SPaolo Bonzini *value = (ch->bs << 2) | 849d2c0bd84SPaolo Bonzini (ch->transparent_copy << 1) | 850d2c0bd84SPaolo Bonzini ch->constant_fill; 851d2c0bd84SPaolo Bonzini break; 852d2c0bd84SPaolo Bonzini 853d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 854d2c0bd84SPaolo Bonzini *value = (ch->link_enabled << 15) | 855d2c0bd84SPaolo Bonzini (ch->link_next_ch & 0xf); 856d2c0bd84SPaolo Bonzini break; 857d2c0bd84SPaolo Bonzini 858d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 859d2c0bd84SPaolo Bonzini *value = (ch->interleave_disabled << 15) | 860d2c0bd84SPaolo Bonzini ch->type; 861d2c0bd84SPaolo Bonzini break; 862d2c0bd84SPaolo Bonzini 863d2c0bd84SPaolo Bonzini default: 864d2c0bd84SPaolo Bonzini return 1; 865d2c0bd84SPaolo Bonzini } 866d2c0bd84SPaolo Bonzini return 0; 867d2c0bd84SPaolo Bonzini } 868d2c0bd84SPaolo Bonzini 869d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_write(struct omap_dma_s *s, 870d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t value) 871d2c0bd84SPaolo Bonzini { 872d2c0bd84SPaolo Bonzini switch (reg) { 873d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 874d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 875d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 876d2c0bd84SPaolo Bonzini ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); 877d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 878d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 879d2c0bd84SPaolo Bonzini ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); 880d2c0bd84SPaolo Bonzini ch->data_type = 1 << (value & 3); 881d2c0bd84SPaolo Bonzini if (ch->port[0] >= __omap_dma_port_last) 882d2c0bd84SPaolo Bonzini printf("%s: invalid DMA port %i\n", __FUNCTION__, 883d2c0bd84SPaolo Bonzini ch->port[0]); 884d2c0bd84SPaolo Bonzini if (ch->port[1] >= __omap_dma_port_last) 885d2c0bd84SPaolo Bonzini printf("%s: invalid DMA port %i\n", __FUNCTION__, 886d2c0bd84SPaolo Bonzini ch->port[1]); 887d2c0bd84SPaolo Bonzini if ((value & 3) == 3) 888d2c0bd84SPaolo Bonzini printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 889d2c0bd84SPaolo Bonzini break; 890d2c0bd84SPaolo Bonzini 891d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 892d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 893d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 894d2c0bd84SPaolo Bonzini ch->end_prog = (value & 0x0800) >> 11; 895d2c0bd84SPaolo Bonzini if (s->model >= omap_dma_3_2) 896d2c0bd84SPaolo Bonzini ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; 897d2c0bd84SPaolo Bonzini ch->repeat = (value & 0x0200) >> 9; 898d2c0bd84SPaolo Bonzini ch->auto_init = (value & 0x0100) >> 8; 899d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 900d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 901d2c0bd84SPaolo Bonzini ch->sync = value & 0x001f; 902d2c0bd84SPaolo Bonzini 903d2c0bd84SPaolo Bonzini if (value & 0x0080) 904d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 905d2c0bd84SPaolo Bonzini else 906d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 907d2c0bd84SPaolo Bonzini 908d2c0bd84SPaolo Bonzini if (ch->end_prog) 909d2c0bd84SPaolo Bonzini omap_dma_channel_end_prog(s, ch); 910d2c0bd84SPaolo Bonzini 911d2c0bd84SPaolo Bonzini break; 912d2c0bd84SPaolo Bonzini 913d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 914d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x3f; 915d2c0bd84SPaolo Bonzini break; 916d2c0bd84SPaolo Bonzini 917d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 918d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 919d2c0bd84SPaolo Bonzini break; 920d2c0bd84SPaolo Bonzini 921d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 922d2c0bd84SPaolo Bonzini ch->addr[0] &= 0xffff0000; 923d2c0bd84SPaolo Bonzini ch->addr[0] |= value; 924d2c0bd84SPaolo Bonzini break; 925d2c0bd84SPaolo Bonzini 926d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 927d2c0bd84SPaolo Bonzini ch->addr[0] &= 0x0000ffff; 928d2c0bd84SPaolo Bonzini ch->addr[0] |= (uint32_t) value << 16; 929d2c0bd84SPaolo Bonzini break; 930d2c0bd84SPaolo Bonzini 931d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 932d2c0bd84SPaolo Bonzini ch->addr[1] &= 0xffff0000; 933d2c0bd84SPaolo Bonzini ch->addr[1] |= value; 934d2c0bd84SPaolo Bonzini break; 935d2c0bd84SPaolo Bonzini 936d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 937d2c0bd84SPaolo Bonzini ch->addr[1] &= 0x0000ffff; 938d2c0bd84SPaolo Bonzini ch->addr[1] |= (uint32_t) value << 16; 939d2c0bd84SPaolo Bonzini break; 940d2c0bd84SPaolo Bonzini 941d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 942d2c0bd84SPaolo Bonzini ch->elements = value; 943d2c0bd84SPaolo Bonzini break; 944d2c0bd84SPaolo Bonzini 945d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 946d2c0bd84SPaolo Bonzini ch->frames = value; 947d2c0bd84SPaolo Bonzini break; 948d2c0bd84SPaolo Bonzini 949d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 950d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int16_t) value; 951d2c0bd84SPaolo Bonzini break; 952d2c0bd84SPaolo Bonzini 953d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 954d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 955d2c0bd84SPaolo Bonzini break; 956d2c0bd84SPaolo Bonzini 957d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 958d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 959d2c0bd84SPaolo Bonzini break; 960d2c0bd84SPaolo Bonzini 961d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 962d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 963d2c0bd84SPaolo Bonzini break; 964d2c0bd84SPaolo Bonzini 965d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 966d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int16_t) value; 967d2c0bd84SPaolo Bonzini break; 968d2c0bd84SPaolo Bonzini 969d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 970d2c0bd84SPaolo Bonzini ch->color &= 0xffff0000; 971d2c0bd84SPaolo Bonzini ch->color |= value; 972d2c0bd84SPaolo Bonzini break; 973d2c0bd84SPaolo Bonzini 974d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 975d2c0bd84SPaolo Bonzini ch->color &= 0xffff; 976d2c0bd84SPaolo Bonzini ch->color |= value << 16; 977d2c0bd84SPaolo Bonzini break; 978d2c0bd84SPaolo Bonzini 979d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 980d2c0bd84SPaolo Bonzini ch->bs = (value >> 2) & 0x1; 981d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 1) & 0x1; 982d2c0bd84SPaolo Bonzini ch->constant_fill = value & 0x1; 983d2c0bd84SPaolo Bonzini break; 984d2c0bd84SPaolo Bonzini 985d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 986d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 987d2c0bd84SPaolo Bonzini if (value & (1 << 14)) { /* Stop_Lnk */ 988d2c0bd84SPaolo Bonzini ch->link_enabled = 0; 989d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 990d2c0bd84SPaolo Bonzini } 991d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 992d2c0bd84SPaolo Bonzini break; 993d2c0bd84SPaolo Bonzini 994d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 995d2c0bd84SPaolo Bonzini ch->interleave_disabled = (value >> 15) & 0x1; 996d2c0bd84SPaolo Bonzini ch->type = value & 0xf; 997d2c0bd84SPaolo Bonzini break; 998d2c0bd84SPaolo Bonzini 999d2c0bd84SPaolo Bonzini default: 1000d2c0bd84SPaolo Bonzini return 1; 1001d2c0bd84SPaolo Bonzini } 1002d2c0bd84SPaolo Bonzini return 0; 1003d2c0bd84SPaolo Bonzini } 1004d2c0bd84SPaolo Bonzini 1005d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1006d2c0bd84SPaolo Bonzini uint16_t value) 1007d2c0bd84SPaolo Bonzini { 1008d2c0bd84SPaolo Bonzini switch (offset) { 1009d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1010d2c0bd84SPaolo Bonzini s->brust_f2 = (value >> 14) & 0x3; 1011d2c0bd84SPaolo Bonzini s->pack_f2 = (value >> 13) & 0x1; 1012d2c0bd84SPaolo Bonzini s->data_type_f2 = (1 << ((value >> 11) & 0x3)); 1013d2c0bd84SPaolo Bonzini s->brust_f1 = (value >> 7) & 0x3; 1014d2c0bd84SPaolo Bonzini s->pack_f1 = (value >> 6) & 0x1; 1015d2c0bd84SPaolo Bonzini s->data_type_f1 = (1 << ((value >> 0) & 0x3)); 1016d2c0bd84SPaolo Bonzini break; 1017d2c0bd84SPaolo Bonzini 1018d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1019d2c0bd84SPaolo Bonzini s->mode_f2 = (value >> 14) & 0x3; 1020d2c0bd84SPaolo Bonzini s->mode_f1 = (value >> 12) & 0x3; 1021d2c0bd84SPaolo Bonzini s->end_prog = (value >> 11) & 0x1; 1022d2c0bd84SPaolo Bonzini s->omap_3_1_compatible_disable = (value >> 10) & 0x1; 1023d2c0bd84SPaolo Bonzini s->repeat = (value >> 9) & 0x1; 1024d2c0bd84SPaolo Bonzini s->auto_init = (value >> 8) & 0x1; 1025d2c0bd84SPaolo Bonzini s->running = (value >> 7) & 0x1; 1026d2c0bd84SPaolo Bonzini s->priority = (value >> 6) & 0x1; 1027d2c0bd84SPaolo Bonzini s->bs = (value >> 4) & 0x1; 1028d2c0bd84SPaolo Bonzini break; 1029d2c0bd84SPaolo Bonzini 1030d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1031d2c0bd84SPaolo Bonzini s->dst = (value >> 8) & 0x1; 1032d2c0bd84SPaolo Bonzini s->src = ((value >> 6) & 0x3) << 1; 1033d2c0bd84SPaolo Bonzini s->condition = 0; 1034d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1035d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1036d2c0bd84SPaolo Bonzini s->dual = value & 1; 1037d2c0bd84SPaolo Bonzini break; 1038d2c0bd84SPaolo Bonzini 1039d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1040d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1041d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1042d2c0bd84SPaolo Bonzini break; 1043d2c0bd84SPaolo Bonzini 1044d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1045d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 1046d2c0bd84SPaolo Bonzini s->src_f1_top |= value << 16; 1047d2c0bd84SPaolo Bonzini break; 1048d2c0bd84SPaolo Bonzini 1049d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1050d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1051d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1052d2c0bd84SPaolo Bonzini break; 1053d2c0bd84SPaolo Bonzini 1054d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1055d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 1056d2c0bd84SPaolo Bonzini s->src_f1_bottom |= (uint32_t) value << 16; 1057d2c0bd84SPaolo Bonzini break; 1058d2c0bd84SPaolo Bonzini 1059d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1060d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1061d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1062d2c0bd84SPaolo Bonzini break; 1063d2c0bd84SPaolo Bonzini 1064d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1065d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 1066d2c0bd84SPaolo Bonzini s->src_f2_top |= (uint32_t) value << 16; 1067d2c0bd84SPaolo Bonzini break; 1068d2c0bd84SPaolo Bonzini 1069d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1070d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1071d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1072d2c0bd84SPaolo Bonzini break; 1073d2c0bd84SPaolo Bonzini 1074d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1075d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 1076d2c0bd84SPaolo Bonzini s->src_f2_bottom |= (uint32_t) value << 16; 1077d2c0bd84SPaolo Bonzini break; 1078d2c0bd84SPaolo Bonzini 1079d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1080d2c0bd84SPaolo Bonzini s->element_index_f1 = value; 1081d2c0bd84SPaolo Bonzini break; 1082d2c0bd84SPaolo Bonzini 1083d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1084d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0xffff0000; 1085d2c0bd84SPaolo Bonzini s->frame_index_f1 |= 0x0000ffff & value; 1086d2c0bd84SPaolo Bonzini break; 1087d2c0bd84SPaolo Bonzini 1088d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1089d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0x0000ffff; 1090d2c0bd84SPaolo Bonzini s->frame_index_f1 |= (uint32_t) value << 16; 1091d2c0bd84SPaolo Bonzini break; 1092d2c0bd84SPaolo Bonzini 1093d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1094d2c0bd84SPaolo Bonzini s->element_index_f2 = value; 1095d2c0bd84SPaolo Bonzini break; 1096d2c0bd84SPaolo Bonzini 1097d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1098d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0xffff0000; 1099d2c0bd84SPaolo Bonzini s->frame_index_f2 |= 0x0000ffff & value; 1100d2c0bd84SPaolo Bonzini break; 1101d2c0bd84SPaolo Bonzini 1102d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1103d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0x0000ffff; 1104d2c0bd84SPaolo Bonzini s->frame_index_f2 |= (uint32_t) value << 16; 1105d2c0bd84SPaolo Bonzini break; 1106d2c0bd84SPaolo Bonzini 1107d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1108d2c0bd84SPaolo Bonzini s->elements_f1 = value; 1109d2c0bd84SPaolo Bonzini break; 1110d2c0bd84SPaolo Bonzini 1111d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1112d2c0bd84SPaolo Bonzini s->frames_f1 = value; 1113d2c0bd84SPaolo Bonzini break; 1114d2c0bd84SPaolo Bonzini 1115d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1116d2c0bd84SPaolo Bonzini s->elements_f2 = value; 1117d2c0bd84SPaolo Bonzini break; 1118d2c0bd84SPaolo Bonzini 1119d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1120d2c0bd84SPaolo Bonzini s->frames_f2 = value; 1121d2c0bd84SPaolo Bonzini break; 1122d2c0bd84SPaolo Bonzini 1123d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1124d2c0bd84SPaolo Bonzini s->lch_type = value & 0xf; 1125d2c0bd84SPaolo Bonzini break; 1126d2c0bd84SPaolo Bonzini 1127d2c0bd84SPaolo Bonzini default: 1128d2c0bd84SPaolo Bonzini return 1; 1129d2c0bd84SPaolo Bonzini } 1130d2c0bd84SPaolo Bonzini return 0; 1131d2c0bd84SPaolo Bonzini } 1132d2c0bd84SPaolo Bonzini 1133d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1134d2c0bd84SPaolo Bonzini uint16_t *ret) 1135d2c0bd84SPaolo Bonzini { 1136d2c0bd84SPaolo Bonzini switch (offset) { 1137d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1138d2c0bd84SPaolo Bonzini *ret = (s->brust_f2 << 14) | 1139d2c0bd84SPaolo Bonzini (s->pack_f2 << 13) | 1140d2c0bd84SPaolo Bonzini ((s->data_type_f2 >> 1) << 11) | 1141d2c0bd84SPaolo Bonzini (s->brust_f1 << 7) | 1142d2c0bd84SPaolo Bonzini (s->pack_f1 << 6) | 1143d2c0bd84SPaolo Bonzini ((s->data_type_f1 >> 1) << 0); 1144d2c0bd84SPaolo Bonzini break; 1145d2c0bd84SPaolo Bonzini 1146d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1147d2c0bd84SPaolo Bonzini *ret = (s->mode_f2 << 14) | 1148d2c0bd84SPaolo Bonzini (s->mode_f1 << 12) | 1149d2c0bd84SPaolo Bonzini (s->end_prog << 11) | 1150d2c0bd84SPaolo Bonzini (s->omap_3_1_compatible_disable << 10) | 1151d2c0bd84SPaolo Bonzini (s->repeat << 9) | 1152d2c0bd84SPaolo Bonzini (s->auto_init << 8) | 1153d2c0bd84SPaolo Bonzini (s->running << 7) | 1154d2c0bd84SPaolo Bonzini (s->priority << 6) | 1155d2c0bd84SPaolo Bonzini (s->bs << 4); 1156d2c0bd84SPaolo Bonzini break; 1157d2c0bd84SPaolo Bonzini 1158d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1159d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1160d2c0bd84SPaolo Bonzini *ret = (s->dst << 8) | 1161d2c0bd84SPaolo Bonzini ((s->src & 0x6) << 5) | 1162d2c0bd84SPaolo Bonzini (s->condition << 3) | 1163d2c0bd84SPaolo Bonzini (s->interrupts << 1) | 1164d2c0bd84SPaolo Bonzini s->dual; 1165d2c0bd84SPaolo Bonzini break; 1166d2c0bd84SPaolo Bonzini 1167d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1168d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1169d2c0bd84SPaolo Bonzini break; 1170d2c0bd84SPaolo Bonzini 1171d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1172d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1173d2c0bd84SPaolo Bonzini break; 1174d2c0bd84SPaolo Bonzini 1175d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1176d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1177d2c0bd84SPaolo Bonzini break; 1178d2c0bd84SPaolo Bonzini 1179d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1180d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1181d2c0bd84SPaolo Bonzini break; 1182d2c0bd84SPaolo Bonzini 1183d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1184d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1185d2c0bd84SPaolo Bonzini break; 1186d2c0bd84SPaolo Bonzini 1187d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1188d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1189d2c0bd84SPaolo Bonzini break; 1190d2c0bd84SPaolo Bonzini 1191d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1192d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1193d2c0bd84SPaolo Bonzini break; 1194d2c0bd84SPaolo Bonzini 1195d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1196d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1197d2c0bd84SPaolo Bonzini break; 1198d2c0bd84SPaolo Bonzini 1199d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1200d2c0bd84SPaolo Bonzini *ret = s->element_index_f1; 1201d2c0bd84SPaolo Bonzini break; 1202d2c0bd84SPaolo Bonzini 1203d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1204d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 & 0xffff; 1205d2c0bd84SPaolo Bonzini break; 1206d2c0bd84SPaolo Bonzini 1207d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1208d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 >> 16; 1209d2c0bd84SPaolo Bonzini break; 1210d2c0bd84SPaolo Bonzini 1211d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1212d2c0bd84SPaolo Bonzini *ret = s->element_index_f2; 1213d2c0bd84SPaolo Bonzini break; 1214d2c0bd84SPaolo Bonzini 1215d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1216d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 & 0xffff; 1217d2c0bd84SPaolo Bonzini break; 1218d2c0bd84SPaolo Bonzini 1219d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1220d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 >> 16; 1221d2c0bd84SPaolo Bonzini break; 1222d2c0bd84SPaolo Bonzini 1223d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1224d2c0bd84SPaolo Bonzini *ret = s->elements_f1; 1225d2c0bd84SPaolo Bonzini break; 1226d2c0bd84SPaolo Bonzini 1227d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1228d2c0bd84SPaolo Bonzini *ret = s->frames_f1; 1229d2c0bd84SPaolo Bonzini break; 1230d2c0bd84SPaolo Bonzini 1231d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1232d2c0bd84SPaolo Bonzini *ret = s->elements_f2; 1233d2c0bd84SPaolo Bonzini break; 1234d2c0bd84SPaolo Bonzini 1235d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1236d2c0bd84SPaolo Bonzini *ret = s->frames_f2; 1237d2c0bd84SPaolo Bonzini break; 1238d2c0bd84SPaolo Bonzini 1239d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1240d2c0bd84SPaolo Bonzini *ret = s->lch_type; 1241d2c0bd84SPaolo Bonzini break; 1242d2c0bd84SPaolo Bonzini 1243d2c0bd84SPaolo Bonzini default: 1244d2c0bd84SPaolo Bonzini return 1; 1245d2c0bd84SPaolo Bonzini } 1246d2c0bd84SPaolo Bonzini return 0; 1247d2c0bd84SPaolo Bonzini } 1248d2c0bd84SPaolo Bonzini 1249d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1250d2c0bd84SPaolo Bonzini uint16_t value) 1251d2c0bd84SPaolo Bonzini { 1252d2c0bd84SPaolo Bonzini switch (offset) { 1253d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1254d2c0bd84SPaolo Bonzini s->src = (value & 0x40) ? imif : emiff; 1255d2c0bd84SPaolo Bonzini s->condition = 0; 1256d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1257d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1258d2c0bd84SPaolo Bonzini s->dual = value & 1; 1259d2c0bd84SPaolo Bonzini break; 1260d2c0bd84SPaolo Bonzini 1261d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1262d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1263d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1264d2c0bd84SPaolo Bonzini break; 1265d2c0bd84SPaolo Bonzini 1266d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1267d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 1268d2c0bd84SPaolo Bonzini s->src_f1_top |= value << 16; 1269d2c0bd84SPaolo Bonzini break; 1270d2c0bd84SPaolo Bonzini 1271d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1272d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1273d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1274d2c0bd84SPaolo Bonzini break; 1275d2c0bd84SPaolo Bonzini 1276d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1277d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 1278d2c0bd84SPaolo Bonzini s->src_f1_bottom |= value << 16; 1279d2c0bd84SPaolo Bonzini break; 1280d2c0bd84SPaolo Bonzini 1281d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1282d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1283d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1284d2c0bd84SPaolo Bonzini break; 1285d2c0bd84SPaolo Bonzini 1286d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1287d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 1288d2c0bd84SPaolo Bonzini s->src_f2_top |= value << 16; 1289d2c0bd84SPaolo Bonzini break; 1290d2c0bd84SPaolo Bonzini 1291d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1292d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1293d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1294d2c0bd84SPaolo Bonzini break; 1295d2c0bd84SPaolo Bonzini 1296d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1297d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 1298d2c0bd84SPaolo Bonzini s->src_f2_bottom |= value << 16; 1299d2c0bd84SPaolo Bonzini break; 1300d2c0bd84SPaolo Bonzini 1301d2c0bd84SPaolo Bonzini default: 1302d2c0bd84SPaolo Bonzini return 1; 1303d2c0bd84SPaolo Bonzini } 1304d2c0bd84SPaolo Bonzini return 0; 1305d2c0bd84SPaolo Bonzini } 1306d2c0bd84SPaolo Bonzini 1307d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1308d2c0bd84SPaolo Bonzini uint16_t *ret) 1309d2c0bd84SPaolo Bonzini { 1310d2c0bd84SPaolo Bonzini int i; 1311d2c0bd84SPaolo Bonzini 1312d2c0bd84SPaolo Bonzini switch (offset) { 1313d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1314d2c0bd84SPaolo Bonzini i = s->condition; 1315d2c0bd84SPaolo Bonzini s->condition = 0; 1316d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1317d2c0bd84SPaolo Bonzini *ret = ((s->src == imif) << 6) | (i << 3) | 1318d2c0bd84SPaolo Bonzini (s->interrupts << 1) | s->dual; 1319d2c0bd84SPaolo Bonzini break; 1320d2c0bd84SPaolo Bonzini 1321d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1322d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1323d2c0bd84SPaolo Bonzini break; 1324d2c0bd84SPaolo Bonzini 1325d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1326d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1327d2c0bd84SPaolo Bonzini break; 1328d2c0bd84SPaolo Bonzini 1329d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1330d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1331d2c0bd84SPaolo Bonzini break; 1332d2c0bd84SPaolo Bonzini 1333d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1334d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1335d2c0bd84SPaolo Bonzini break; 1336d2c0bd84SPaolo Bonzini 1337d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1338d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1339d2c0bd84SPaolo Bonzini break; 1340d2c0bd84SPaolo Bonzini 1341d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1342d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1343d2c0bd84SPaolo Bonzini break; 1344d2c0bd84SPaolo Bonzini 1345d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1346d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1347d2c0bd84SPaolo Bonzini break; 1348d2c0bd84SPaolo Bonzini 1349d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1350d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1351d2c0bd84SPaolo Bonzini break; 1352d2c0bd84SPaolo Bonzini 1353d2c0bd84SPaolo Bonzini default: 1354d2c0bd84SPaolo Bonzini return 1; 1355d2c0bd84SPaolo Bonzini } 1356d2c0bd84SPaolo Bonzini return 0; 1357d2c0bd84SPaolo Bonzini } 1358d2c0bd84SPaolo Bonzini 1359d2c0bd84SPaolo Bonzini static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) 1360d2c0bd84SPaolo Bonzini { 1361d2c0bd84SPaolo Bonzini switch (offset) { 1362d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1363d2c0bd84SPaolo Bonzini s->gcr = value; 1364d2c0bd84SPaolo Bonzini break; 1365d2c0bd84SPaolo Bonzini 1366d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1367d2c0bd84SPaolo Bonzini if (value & 0x8) 1368d2c0bd84SPaolo Bonzini omap_dma_disable_3_1_mapping(s); 1369d2c0bd84SPaolo Bonzini else 1370d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 1371d2c0bd84SPaolo Bonzini break; 1372d2c0bd84SPaolo Bonzini 1373d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1374d2c0bd84SPaolo Bonzini if (value & 0x1) 1375d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1376d2c0bd84SPaolo Bonzini break; 1377d2c0bd84SPaolo Bonzini 1378d2c0bd84SPaolo Bonzini default: 1379d2c0bd84SPaolo Bonzini return 1; 1380d2c0bd84SPaolo Bonzini } 1381d2c0bd84SPaolo Bonzini return 0; 1382d2c0bd84SPaolo Bonzini } 1383d2c0bd84SPaolo Bonzini 1384d2c0bd84SPaolo Bonzini static int omap_dma_sys_read(struct omap_dma_s *s, int offset, 1385d2c0bd84SPaolo Bonzini uint16_t *ret) 1386d2c0bd84SPaolo Bonzini { 1387d2c0bd84SPaolo Bonzini switch (offset) { 1388d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1389d2c0bd84SPaolo Bonzini *ret = s->gcr; 1390d2c0bd84SPaolo Bonzini break; 1391d2c0bd84SPaolo Bonzini 1392d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1393d2c0bd84SPaolo Bonzini *ret = s->omap_3_1_mapping_disabled << 3; 1394d2c0bd84SPaolo Bonzini break; 1395d2c0bd84SPaolo Bonzini 1396d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1397d2c0bd84SPaolo Bonzini *ret = 0; 1398d2c0bd84SPaolo Bonzini break; 1399d2c0bd84SPaolo Bonzini 1400d2c0bd84SPaolo Bonzini case 0x442: /* DMA_HW_ID */ 1401d2c0bd84SPaolo Bonzini case 0x444: /* DMA_PCh2_ID */ 1402d2c0bd84SPaolo Bonzini case 0x446: /* DMA_PCh0_ID */ 1403d2c0bd84SPaolo Bonzini case 0x448: /* DMA_PCh1_ID */ 1404d2c0bd84SPaolo Bonzini case 0x44a: /* DMA_PChG_ID */ 1405d2c0bd84SPaolo Bonzini case 0x44c: /* DMA_PChD_ID */ 1406d2c0bd84SPaolo Bonzini *ret = 1; 1407d2c0bd84SPaolo Bonzini break; 1408d2c0bd84SPaolo Bonzini 1409d2c0bd84SPaolo Bonzini case 0x44e: /* DMA_CAPS_0_U */ 1410d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 16) & 0xffff; 1411d2c0bd84SPaolo Bonzini break; 1412d2c0bd84SPaolo Bonzini case 0x450: /* DMA_CAPS_0_L */ 1413d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 0) & 0xffff; 1414d2c0bd84SPaolo Bonzini break; 1415d2c0bd84SPaolo Bonzini 1416d2c0bd84SPaolo Bonzini case 0x452: /* DMA_CAPS_1_U */ 1417d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 16) & 0xffff; 1418d2c0bd84SPaolo Bonzini break; 1419d2c0bd84SPaolo Bonzini case 0x454: /* DMA_CAPS_1_L */ 1420d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 0) & 0xffff; 1421d2c0bd84SPaolo Bonzini break; 1422d2c0bd84SPaolo Bonzini 1423d2c0bd84SPaolo Bonzini case 0x456: /* DMA_CAPS_2 */ 1424d2c0bd84SPaolo Bonzini *ret = s->caps[2]; 1425d2c0bd84SPaolo Bonzini break; 1426d2c0bd84SPaolo Bonzini 1427d2c0bd84SPaolo Bonzini case 0x458: /* DMA_CAPS_3 */ 1428d2c0bd84SPaolo Bonzini *ret = s->caps[3]; 1429d2c0bd84SPaolo Bonzini break; 1430d2c0bd84SPaolo Bonzini 1431d2c0bd84SPaolo Bonzini case 0x45a: /* DMA_CAPS_4 */ 1432d2c0bd84SPaolo Bonzini *ret = s->caps[4]; 1433d2c0bd84SPaolo Bonzini break; 1434d2c0bd84SPaolo Bonzini 1435d2c0bd84SPaolo Bonzini case 0x460: /* DMA_PCh2_SR */ 1436d2c0bd84SPaolo Bonzini case 0x480: /* DMA_PCh0_SR */ 1437d2c0bd84SPaolo Bonzini case 0x482: /* DMA_PCh1_SR */ 1438d2c0bd84SPaolo Bonzini case 0x4c0: /* DMA_PChD_SR_0 */ 1439d2c0bd84SPaolo Bonzini printf("%s: Physical Channel Status Registers not implemented.\n", 1440d2c0bd84SPaolo Bonzini __FUNCTION__); 1441d2c0bd84SPaolo Bonzini *ret = 0xff; 1442d2c0bd84SPaolo Bonzini break; 1443d2c0bd84SPaolo Bonzini 1444d2c0bd84SPaolo Bonzini default: 1445d2c0bd84SPaolo Bonzini return 1; 1446d2c0bd84SPaolo Bonzini } 1447d2c0bd84SPaolo Bonzini return 0; 1448d2c0bd84SPaolo Bonzini } 1449d2c0bd84SPaolo Bonzini 1450d2c0bd84SPaolo Bonzini static uint64_t omap_dma_read(void *opaque, hwaddr addr, 1451d2c0bd84SPaolo Bonzini unsigned size) 1452d2c0bd84SPaolo Bonzini { 1453d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1454d2c0bd84SPaolo Bonzini int reg, ch; 1455d2c0bd84SPaolo Bonzini uint16_t ret; 1456d2c0bd84SPaolo Bonzini 1457d2c0bd84SPaolo Bonzini if (size != 2) { 1458d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1459d2c0bd84SPaolo Bonzini } 1460d2c0bd84SPaolo Bonzini 1461d2c0bd84SPaolo Bonzini switch (addr) { 1462d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1463d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1464d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) 1465d2c0bd84SPaolo Bonzini break; 1466d2c0bd84SPaolo Bonzini return ret; 1467d2c0bd84SPaolo Bonzini } 1468d2c0bd84SPaolo Bonzini /* Fall through. */ 1469d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1470d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1471d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1472d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) 1473d2c0bd84SPaolo Bonzini break; 1474d2c0bd84SPaolo Bonzini return ret; 1475d2c0bd84SPaolo Bonzini 1476d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1477d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1478d2c0bd84SPaolo Bonzini break; 1479d2c0bd84SPaolo Bonzini /* Fall through. */ 1480d2c0bd84SPaolo Bonzini case 0x400: 1481d2c0bd84SPaolo Bonzini if (omap_dma_sys_read(s, addr, &ret)) 1482d2c0bd84SPaolo Bonzini break; 1483d2c0bd84SPaolo Bonzini return ret; 1484d2c0bd84SPaolo Bonzini 1485d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1486d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1487d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret)) 1488d2c0bd84SPaolo Bonzini break; 1489d2c0bd84SPaolo Bonzini return ret; 1490d2c0bd84SPaolo Bonzini } 1491d2c0bd84SPaolo Bonzini break; 1492d2c0bd84SPaolo Bonzini } 1493d2c0bd84SPaolo Bonzini 1494d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1495d2c0bd84SPaolo Bonzini return 0; 1496d2c0bd84SPaolo Bonzini } 1497d2c0bd84SPaolo Bonzini 1498d2c0bd84SPaolo Bonzini static void omap_dma_write(void *opaque, hwaddr addr, 1499d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1500d2c0bd84SPaolo Bonzini { 1501d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1502d2c0bd84SPaolo Bonzini int reg, ch; 1503d2c0bd84SPaolo Bonzini 1504d2c0bd84SPaolo Bonzini if (size != 2) { 1505d2c0bd84SPaolo Bonzini return omap_badwidth_write16(opaque, addr, value); 1506d2c0bd84SPaolo Bonzini } 1507d2c0bd84SPaolo Bonzini 1508d2c0bd84SPaolo Bonzini switch (addr) { 1509d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1510d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1511d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) 1512d2c0bd84SPaolo Bonzini break; 1513d2c0bd84SPaolo Bonzini return; 1514d2c0bd84SPaolo Bonzini } 1515d2c0bd84SPaolo Bonzini /* Fall through. */ 1516d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1517d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1518d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1519d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) 1520d2c0bd84SPaolo Bonzini break; 1521d2c0bd84SPaolo Bonzini return; 1522d2c0bd84SPaolo Bonzini 1523d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1524d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1525d2c0bd84SPaolo Bonzini break; 1526d2c0bd84SPaolo Bonzini case 0x400: 1527d2c0bd84SPaolo Bonzini /* Fall through. */ 1528d2c0bd84SPaolo Bonzini if (omap_dma_sys_write(s, addr, value)) 1529d2c0bd84SPaolo Bonzini break; 1530d2c0bd84SPaolo Bonzini return; 1531d2c0bd84SPaolo Bonzini 1532d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1533d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1534d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value)) 1535d2c0bd84SPaolo Bonzini break; 1536d2c0bd84SPaolo Bonzini return; 1537d2c0bd84SPaolo Bonzini } 1538d2c0bd84SPaolo Bonzini break; 1539d2c0bd84SPaolo Bonzini } 1540d2c0bd84SPaolo Bonzini 1541d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1542d2c0bd84SPaolo Bonzini } 1543d2c0bd84SPaolo Bonzini 1544d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma_ops = { 1545d2c0bd84SPaolo Bonzini .read = omap_dma_read, 1546d2c0bd84SPaolo Bonzini .write = omap_dma_write, 1547d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1548d2c0bd84SPaolo Bonzini }; 1549d2c0bd84SPaolo Bonzini 1550d2c0bd84SPaolo Bonzini static void omap_dma_request(void *opaque, int drq, int req) 1551d2c0bd84SPaolo Bonzini { 1552d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1553d2c0bd84SPaolo Bonzini /* The request pins are level triggered in QEMU. */ 1554d2c0bd84SPaolo Bonzini if (req) { 1555*76486736SPeter Maydell if (~s->dma->drqbmp & (1ULL << drq)) { 1556*76486736SPeter Maydell s->dma->drqbmp |= 1ULL << drq; 1557d2c0bd84SPaolo Bonzini omap_dma_process_request(s, drq); 1558d2c0bd84SPaolo Bonzini } 1559d2c0bd84SPaolo Bonzini } else 1560*76486736SPeter Maydell s->dma->drqbmp &= ~(1ULL << drq); 1561d2c0bd84SPaolo Bonzini } 1562d2c0bd84SPaolo Bonzini 1563d2c0bd84SPaolo Bonzini /* XXX: this won't be needed once soc_dma knows about clocks. */ 1564d2c0bd84SPaolo Bonzini static void omap_dma_clk_update(void *opaque, int line, int on) 1565d2c0bd84SPaolo Bonzini { 1566d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1567d2c0bd84SPaolo Bonzini int i; 1568d2c0bd84SPaolo Bonzini 1569d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(s->clk); 1570d2c0bd84SPaolo Bonzini 1571d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) 1572d2c0bd84SPaolo Bonzini if (s->ch[i].active) 1573d2c0bd84SPaolo Bonzini soc_dma_set_request(s->ch[i].dma, on); 1574d2c0bd84SPaolo Bonzini } 1575d2c0bd84SPaolo Bonzini 1576d2c0bd84SPaolo Bonzini static void omap_dma_setcaps(struct omap_dma_s *s) 1577d2c0bd84SPaolo Bonzini { 1578d2c0bd84SPaolo Bonzini switch (s->model) { 1579d2c0bd84SPaolo Bonzini default: 1580d2c0bd84SPaolo Bonzini case omap_dma_3_1: 1581d2c0bd84SPaolo Bonzini break; 1582d2c0bd84SPaolo Bonzini case omap_dma_3_2: 1583d2c0bd84SPaolo Bonzini case omap_dma_4: 1584d2c0bd84SPaolo Bonzini /* XXX Only available for sDMA */ 1585d2c0bd84SPaolo Bonzini s->caps[0] = 1586d2c0bd84SPaolo Bonzini (1 << 19) | /* Constant Fill Capability */ 1587d2c0bd84SPaolo Bonzini (1 << 18); /* Transparent BLT Capability */ 1588d2c0bd84SPaolo Bonzini s->caps[1] = 1589d2c0bd84SPaolo Bonzini (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ 1590d2c0bd84SPaolo Bonzini s->caps[2] = 1591d2c0bd84SPaolo Bonzini (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ 1592d2c0bd84SPaolo Bonzini (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ 1593d2c0bd84SPaolo Bonzini (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ 1594d2c0bd84SPaolo Bonzini (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ 1595d2c0bd84SPaolo Bonzini (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ 1596d2c0bd84SPaolo Bonzini (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ 1597d2c0bd84SPaolo Bonzini (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ 1598d2c0bd84SPaolo Bonzini (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ 1599d2c0bd84SPaolo Bonzini (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ 1600d2c0bd84SPaolo Bonzini s->caps[3] = 1601d2c0bd84SPaolo Bonzini (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ 1602d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ 1603d2c0bd84SPaolo Bonzini (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ 1604d2c0bd84SPaolo Bonzini (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ 1605d2c0bd84SPaolo Bonzini (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ 1606d2c0bd84SPaolo Bonzini (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ 1607d2c0bd84SPaolo Bonzini (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ 1608d2c0bd84SPaolo Bonzini (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ 1609d2c0bd84SPaolo Bonzini s->caps[4] = 1610d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ 1611d2c0bd84SPaolo Bonzini (1 << 6) | /* SYNC_STATUS_CPBLTY */ 1612d2c0bd84SPaolo Bonzini (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ 1613d2c0bd84SPaolo Bonzini (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ 1614d2c0bd84SPaolo Bonzini (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ 1615d2c0bd84SPaolo Bonzini (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ 1616d2c0bd84SPaolo Bonzini (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ 1617d2c0bd84SPaolo Bonzini (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ 1618d2c0bd84SPaolo Bonzini break; 1619d2c0bd84SPaolo Bonzini } 1620d2c0bd84SPaolo Bonzini } 1621d2c0bd84SPaolo Bonzini 1622d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 1623d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 1624d2c0bd84SPaolo Bonzini qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 1625d2c0bd84SPaolo Bonzini enum omap_dma_model model) 1626d2c0bd84SPaolo Bonzini { 1627d2c0bd84SPaolo Bonzini int num_irqs, memsize, i; 1628d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) 1629d2c0bd84SPaolo Bonzini g_malloc0(sizeof(struct omap_dma_s)); 1630d2c0bd84SPaolo Bonzini 1631d2c0bd84SPaolo Bonzini if (model <= omap_dma_3_1) { 1632d2c0bd84SPaolo Bonzini num_irqs = 6; 1633d2c0bd84SPaolo Bonzini memsize = 0x800; 1634d2c0bd84SPaolo Bonzini } else { 1635d2c0bd84SPaolo Bonzini num_irqs = 16; 1636d2c0bd84SPaolo Bonzini memsize = 0xc00; 1637d2c0bd84SPaolo Bonzini } 1638d2c0bd84SPaolo Bonzini s->model = model; 1639d2c0bd84SPaolo Bonzini s->mpu = mpu; 1640d2c0bd84SPaolo Bonzini s->clk = clk; 1641d2c0bd84SPaolo Bonzini s->lcd_ch.irq = lcd_irq; 1642d2c0bd84SPaolo Bonzini s->lcd_ch.mpu = mpu; 1643d2c0bd84SPaolo Bonzini 1644d2c0bd84SPaolo Bonzini s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); 1645d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(clk); 1646d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 1647d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 1648d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32); 1649d2c0bd84SPaolo Bonzini s->dma->opaque = s; 1650d2c0bd84SPaolo Bonzini 1651d2c0bd84SPaolo Bonzini while (num_irqs --) 1652d2c0bd84SPaolo Bonzini s->ch[num_irqs].irq = irqs[num_irqs]; 1653d2c0bd84SPaolo Bonzini for (i = 0; i < 3; i ++) { 1654d2c0bd84SPaolo Bonzini s->ch[i].sibling = &s->ch[i + 6]; 1655d2c0bd84SPaolo Bonzini s->ch[i + 6].sibling = &s->ch[i]; 1656d2c0bd84SPaolo Bonzini } 1657d2c0bd84SPaolo Bonzini for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { 1658d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 1659d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 1660d2c0bd84SPaolo Bonzini } 1661d2c0bd84SPaolo Bonzini 1662d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 1663d2c0bd84SPaolo Bonzini omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); 1664d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1665d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, 1); 1666d2c0bd84SPaolo Bonzini 16672c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize); 1668d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 1669d2c0bd84SPaolo Bonzini 1670d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 1671d2c0bd84SPaolo Bonzini 1672d2c0bd84SPaolo Bonzini return s->dma; 1673d2c0bd84SPaolo Bonzini } 1674d2c0bd84SPaolo Bonzini 1675d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_4_update(struct omap_dma_s *s) 1676d2c0bd84SPaolo Bonzini { 1677d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 1678d2c0bd84SPaolo Bonzini uint32_t bmp, bit; 1679d2c0bd84SPaolo Bonzini 1680d2c0bd84SPaolo Bonzini for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) 1681d2c0bd84SPaolo Bonzini if (ch->status) { 1682d2c0bd84SPaolo Bonzini bmp |= bit; 1683d2c0bd84SPaolo Bonzini ch->cstatus |= ch->status; 1684d2c0bd84SPaolo Bonzini ch->status = 0; 1685d2c0bd84SPaolo Bonzini } 1686d2c0bd84SPaolo Bonzini if ((s->irqstat[0] |= s->irqen[0] & bmp)) 1687d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[0]); 1688d2c0bd84SPaolo Bonzini if ((s->irqstat[1] |= s->irqen[1] & bmp)) 1689d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[1]); 1690d2c0bd84SPaolo Bonzini if ((s->irqstat[2] |= s->irqen[2] & bmp)) 1691d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[2]); 1692d2c0bd84SPaolo Bonzini if ((s->irqstat[3] |= s->irqen[3] & bmp)) 1693d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[3]); 1694d2c0bd84SPaolo Bonzini } 1695d2c0bd84SPaolo Bonzini 1696d2c0bd84SPaolo Bonzini static uint64_t omap_dma4_read(void *opaque, hwaddr addr, 1697d2c0bd84SPaolo Bonzini unsigned size) 1698d2c0bd84SPaolo Bonzini { 1699d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1700d2c0bd84SPaolo Bonzini int irqn = 0, chnum; 1701d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1702d2c0bd84SPaolo Bonzini 1703d2c0bd84SPaolo Bonzini if (size == 1) { 1704d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1705d2c0bd84SPaolo Bonzini } 1706d2c0bd84SPaolo Bonzini 1707d2c0bd84SPaolo Bonzini switch (addr) { 1708d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1709d2c0bd84SPaolo Bonzini return 0x40; 1710d2c0bd84SPaolo Bonzini 1711d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1712d2c0bd84SPaolo Bonzini irqn ++; 1713d2c0bd84SPaolo Bonzini /* fall through */ 1714d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1715d2c0bd84SPaolo Bonzini irqn ++; 1716d2c0bd84SPaolo Bonzini /* fall through */ 1717d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1718d2c0bd84SPaolo Bonzini irqn ++; 1719d2c0bd84SPaolo Bonzini /* fall through */ 1720d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1721d2c0bd84SPaolo Bonzini return s->irqstat[irqn]; 1722d2c0bd84SPaolo Bonzini 1723d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1724d2c0bd84SPaolo Bonzini irqn ++; 1725d2c0bd84SPaolo Bonzini /* fall through */ 1726d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1727d2c0bd84SPaolo Bonzini irqn ++; 1728d2c0bd84SPaolo Bonzini /* fall through */ 1729d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1730d2c0bd84SPaolo Bonzini irqn ++; 1731d2c0bd84SPaolo Bonzini /* fall through */ 1732d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1733d2c0bd84SPaolo Bonzini return s->irqen[irqn]; 1734d2c0bd84SPaolo Bonzini 1735d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1736d2c0bd84SPaolo Bonzini return 1; /* RESETDONE */ 1737d2c0bd84SPaolo Bonzini 1738d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1739d2c0bd84SPaolo Bonzini return s->ocp; 1740d2c0bd84SPaolo Bonzini 1741d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1742d2c0bd84SPaolo Bonzini return s->caps[0]; 1743d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1744d2c0bd84SPaolo Bonzini return s->caps[2]; 1745d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1746d2c0bd84SPaolo Bonzini return s->caps[3]; 1747d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1748d2c0bd84SPaolo Bonzini return s->caps[4]; 1749d2c0bd84SPaolo Bonzini 1750d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1751d2c0bd84SPaolo Bonzini return s->gcr; 1752d2c0bd84SPaolo Bonzini 1753d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1754d2c0bd84SPaolo Bonzini addr -= 0x80; 1755d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1756d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1757d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1758d2c0bd84SPaolo Bonzini break; 1759d2c0bd84SPaolo Bonzini 1760d2c0bd84SPaolo Bonzini default: 1761d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1762d2c0bd84SPaolo Bonzini return 0; 1763d2c0bd84SPaolo Bonzini } 1764d2c0bd84SPaolo Bonzini 1765d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1766d2c0bd84SPaolo Bonzini switch (addr) { 1767d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1768d2c0bd84SPaolo Bonzini return (ch->buf_disable << 25) | 1769d2c0bd84SPaolo Bonzini (ch->src_sync << 24) | 1770d2c0bd84SPaolo Bonzini (ch->prefetch << 23) | 1771d2c0bd84SPaolo Bonzini ((ch->sync & 0x60) << 14) | 1772d2c0bd84SPaolo Bonzini (ch->bs << 18) | 1773d2c0bd84SPaolo Bonzini (ch->transparent_copy << 17) | 1774d2c0bd84SPaolo Bonzini (ch->constant_fill << 16) | 1775d2c0bd84SPaolo Bonzini (ch->mode[1] << 14) | 1776d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 1777d2c0bd84SPaolo Bonzini (0 << 10) | (0 << 9) | 1778d2c0bd84SPaolo Bonzini (ch->suspend << 8) | 1779d2c0bd84SPaolo Bonzini (ch->enable << 7) | 1780d2c0bd84SPaolo Bonzini (ch->priority << 6) | 1781d2c0bd84SPaolo Bonzini (ch->fs << 5) | (ch->sync & 0x1f); 1782d2c0bd84SPaolo Bonzini 1783d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1784d2c0bd84SPaolo Bonzini return (ch->link_enabled << 15) | ch->link_next_ch; 1785d2c0bd84SPaolo Bonzini 1786d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1787d2c0bd84SPaolo Bonzini return ch->interrupts; 1788d2c0bd84SPaolo Bonzini 1789d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1790d2c0bd84SPaolo Bonzini return ch->cstatus; 1791d2c0bd84SPaolo Bonzini 1792d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1793d2c0bd84SPaolo Bonzini return (ch->endian[0] << 21) | 1794d2c0bd84SPaolo Bonzini (ch->endian_lock[0] << 20) | 1795d2c0bd84SPaolo Bonzini (ch->endian[1] << 19) | 1796d2c0bd84SPaolo Bonzini (ch->endian_lock[1] << 18) | 1797d2c0bd84SPaolo Bonzini (ch->write_mode << 16) | 1798d2c0bd84SPaolo Bonzini (ch->burst[1] << 14) | 1799d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 1800d2c0bd84SPaolo Bonzini (ch->translate[1] << 9) | 1801d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 1802d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 1803d2c0bd84SPaolo Bonzini (ch->translate[0] << 2) | 1804d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 1805d2c0bd84SPaolo Bonzini 1806d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 1807d2c0bd84SPaolo Bonzini return ch->elements; 1808d2c0bd84SPaolo Bonzini 1809d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 1810d2c0bd84SPaolo Bonzini return ch->frames; 1811d2c0bd84SPaolo Bonzini 1812d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 1813d2c0bd84SPaolo Bonzini return ch->addr[0]; 1814d2c0bd84SPaolo Bonzini 1815d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 1816d2c0bd84SPaolo Bonzini return ch->addr[1]; 1817d2c0bd84SPaolo Bonzini 1818d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 1819d2c0bd84SPaolo Bonzini return ch->element_index[0]; 1820d2c0bd84SPaolo Bonzini 1821d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 1822d2c0bd84SPaolo Bonzini return ch->frame_index[0]; 1823d2c0bd84SPaolo Bonzini 1824d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 1825d2c0bd84SPaolo Bonzini return ch->element_index[1]; 1826d2c0bd84SPaolo Bonzini 1827d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 1828d2c0bd84SPaolo Bonzini return ch->frame_index[1]; 1829d2c0bd84SPaolo Bonzini 1830d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 1831d2c0bd84SPaolo Bonzini return ch->active_set.src & 0xffff; 1832d2c0bd84SPaolo Bonzini 1833d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 1834d2c0bd84SPaolo Bonzini return ch->active_set.dest & 0xffff; 1835d2c0bd84SPaolo Bonzini 1836d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 1837d2c0bd84SPaolo Bonzini return ch->active_set.element; 1838d2c0bd84SPaolo Bonzini 1839d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 1840d2c0bd84SPaolo Bonzini return ch->active_set.frame; 1841d2c0bd84SPaolo Bonzini 1842d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 1843d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 1844d2c0bd84SPaolo Bonzini return ch->color; 1845d2c0bd84SPaolo Bonzini 1846d2c0bd84SPaolo Bonzini default: 1847d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1848d2c0bd84SPaolo Bonzini return 0; 1849d2c0bd84SPaolo Bonzini } 1850d2c0bd84SPaolo Bonzini } 1851d2c0bd84SPaolo Bonzini 1852d2c0bd84SPaolo Bonzini static void omap_dma4_write(void *opaque, hwaddr addr, 1853d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1854d2c0bd84SPaolo Bonzini { 1855d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1856d2c0bd84SPaolo Bonzini int chnum, irqn = 0; 1857d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1858d2c0bd84SPaolo Bonzini 1859d2c0bd84SPaolo Bonzini if (size == 1) { 1860d2c0bd84SPaolo Bonzini return omap_badwidth_write16(opaque, addr, value); 1861d2c0bd84SPaolo Bonzini } 1862d2c0bd84SPaolo Bonzini 1863d2c0bd84SPaolo Bonzini switch (addr) { 1864d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1865d2c0bd84SPaolo Bonzini irqn ++; 1866d2c0bd84SPaolo Bonzini /* fall through */ 1867d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1868d2c0bd84SPaolo Bonzini irqn ++; 1869d2c0bd84SPaolo Bonzini /* fall through */ 1870d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1871d2c0bd84SPaolo Bonzini irqn ++; 1872d2c0bd84SPaolo Bonzini /* fall through */ 1873d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1874d2c0bd84SPaolo Bonzini s->irqstat[irqn] &= ~value; 1875d2c0bd84SPaolo Bonzini if (!s->irqstat[irqn]) 1876d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq[irqn]); 1877d2c0bd84SPaolo Bonzini return; 1878d2c0bd84SPaolo Bonzini 1879d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1880d2c0bd84SPaolo Bonzini irqn ++; 1881d2c0bd84SPaolo Bonzini /* fall through */ 1882d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1883d2c0bd84SPaolo Bonzini irqn ++; 1884d2c0bd84SPaolo Bonzini /* fall through */ 1885d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1886d2c0bd84SPaolo Bonzini irqn ++; 1887d2c0bd84SPaolo Bonzini /* fall through */ 1888d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1889d2c0bd84SPaolo Bonzini s->irqen[irqn] = value; 1890d2c0bd84SPaolo Bonzini return; 1891d2c0bd84SPaolo Bonzini 1892d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1893d2c0bd84SPaolo Bonzini if (value & 2) /* SOFTRESET */ 1894d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1895d2c0bd84SPaolo Bonzini s->ocp = value & 0x3321; 1896d2c0bd84SPaolo Bonzini if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ 1897d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); 1898d2c0bd84SPaolo Bonzini return; 1899d2c0bd84SPaolo Bonzini 1900d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1901d2c0bd84SPaolo Bonzini s->gcr = value & 0x00ff00ff; 1902d2c0bd84SPaolo Bonzini if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ 1903d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); 1904d2c0bd84SPaolo Bonzini return; 1905d2c0bd84SPaolo Bonzini 1906d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1907d2c0bd84SPaolo Bonzini addr -= 0x80; 1908d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1909d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1910d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1911d2c0bd84SPaolo Bonzini break; 1912d2c0bd84SPaolo Bonzini 1913d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1914d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1915d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1916d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1917d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1918d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1919d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 1920d2c0bd84SPaolo Bonzini return; 1921d2c0bd84SPaolo Bonzini 1922d2c0bd84SPaolo Bonzini default: 1923d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1924d2c0bd84SPaolo Bonzini return; 1925d2c0bd84SPaolo Bonzini } 1926d2c0bd84SPaolo Bonzini 1927d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1928d2c0bd84SPaolo Bonzini switch (addr) { 1929d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1930d2c0bd84SPaolo Bonzini ch->buf_disable = (value >> 25) & 1; 1931d2c0bd84SPaolo Bonzini ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ 1932d2c0bd84SPaolo Bonzini if (ch->buf_disable && !ch->src_sync) 1933d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: Buffering disable is not allowed in " 1934d2c0bd84SPaolo Bonzini "destination synchronised mode\n", __FUNCTION__); 1935d2c0bd84SPaolo Bonzini ch->prefetch = (value >> 23) & 1; 1936d2c0bd84SPaolo Bonzini ch->bs = (value >> 18) & 1; 1937d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 17) & 1; 1938d2c0bd84SPaolo Bonzini ch->constant_fill = (value >> 16) & 1; 1939d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 1940d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 1941d2c0bd84SPaolo Bonzini ch->suspend = (value & 0x0100) >> 8; 1942d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 1943d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 1944d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) 1945d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: For a packet transfer at least one port " 1946d2c0bd84SPaolo Bonzini "must be constant-addressed\n", __FUNCTION__); 1947d2c0bd84SPaolo Bonzini ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); 1948d2c0bd84SPaolo Bonzini /* XXX must be 0x01 for CamDMA */ 1949d2c0bd84SPaolo Bonzini 1950d2c0bd84SPaolo Bonzini if (value & 0x0080) 1951d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 1952d2c0bd84SPaolo Bonzini else 1953d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 1954d2c0bd84SPaolo Bonzini 1955d2c0bd84SPaolo Bonzini break; 1956d2c0bd84SPaolo Bonzini 1957d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1958d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 1959d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 1960d2c0bd84SPaolo Bonzini break; 1961d2c0bd84SPaolo Bonzini 1962d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1963d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x09be; 1964d2c0bd84SPaolo Bonzini break; 1965d2c0bd84SPaolo Bonzini 1966d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1967d2c0bd84SPaolo Bonzini ch->cstatus &= ~value; 1968d2c0bd84SPaolo Bonzini break; 1969d2c0bd84SPaolo Bonzini 1970d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1971d2c0bd84SPaolo Bonzini ch->endian[0] =(value >> 21) & 1; 1972d2c0bd84SPaolo Bonzini ch->endian_lock[0] =(value >> 20) & 1; 1973d2c0bd84SPaolo Bonzini ch->endian[1] =(value >> 19) & 1; 1974d2c0bd84SPaolo Bonzini ch->endian_lock[1] =(value >> 18) & 1; 1975d2c0bd84SPaolo Bonzini if (ch->endian[0] != ch->endian[1]) 1976d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n", 1977d2c0bd84SPaolo Bonzini __FUNCTION__); 1978d2c0bd84SPaolo Bonzini ch->write_mode = (value >> 16) & 3; 1979d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 1980d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 1981d2c0bd84SPaolo Bonzini ch->translate[1] = (value & 0x1e00) >> 9; 1982d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 1983d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 1984d2c0bd84SPaolo Bonzini ch->translate[0] = (value & 0x003c) >> 2; 1985d2c0bd84SPaolo Bonzini if (ch->translate[0] | ch->translate[1]) 1986d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", 1987d2c0bd84SPaolo Bonzini __FUNCTION__); 1988d2c0bd84SPaolo Bonzini ch->data_type = 1 << (value & 3); 1989d2c0bd84SPaolo Bonzini if ((value & 3) == 3) 1990d2c0bd84SPaolo Bonzini printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 1991d2c0bd84SPaolo Bonzini break; 1992d2c0bd84SPaolo Bonzini 1993d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 1994d2c0bd84SPaolo Bonzini ch->set_update = 1; 1995d2c0bd84SPaolo Bonzini ch->elements = value & 0xffffff; 1996d2c0bd84SPaolo Bonzini break; 1997d2c0bd84SPaolo Bonzini 1998d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 1999d2c0bd84SPaolo Bonzini ch->frames = value & 0xffff; 2000d2c0bd84SPaolo Bonzini ch->set_update = 1; 2001d2c0bd84SPaolo Bonzini break; 2002d2c0bd84SPaolo Bonzini 2003d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 2004d2c0bd84SPaolo Bonzini ch->addr[0] = (hwaddr) (uint32_t) value; 2005d2c0bd84SPaolo Bonzini ch->set_update = 1; 2006d2c0bd84SPaolo Bonzini break; 2007d2c0bd84SPaolo Bonzini 2008d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 2009d2c0bd84SPaolo Bonzini ch->addr[1] = (hwaddr) (uint32_t) value; 2010d2c0bd84SPaolo Bonzini ch->set_update = 1; 2011d2c0bd84SPaolo Bonzini break; 2012d2c0bd84SPaolo Bonzini 2013d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 2014d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 2015d2c0bd84SPaolo Bonzini ch->set_update = 1; 2016d2c0bd84SPaolo Bonzini break; 2017d2c0bd84SPaolo Bonzini 2018d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 2019d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int32_t) value; 2020d2c0bd84SPaolo Bonzini ch->set_update = 1; 2021d2c0bd84SPaolo Bonzini break; 2022d2c0bd84SPaolo Bonzini 2023d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 2024d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 2025d2c0bd84SPaolo Bonzini ch->set_update = 1; 2026d2c0bd84SPaolo Bonzini break; 2027d2c0bd84SPaolo Bonzini 2028d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 2029d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int32_t) value; 2030d2c0bd84SPaolo Bonzini ch->set_update = 1; 2031d2c0bd84SPaolo Bonzini break; 2032d2c0bd84SPaolo Bonzini 2033d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 2034d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 2035d2c0bd84SPaolo Bonzini ch->color = value; 2036d2c0bd84SPaolo Bonzini break; 2037d2c0bd84SPaolo Bonzini 2038d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 2039d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 2040d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 2041d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 2042d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 2043d2c0bd84SPaolo Bonzini break; 2044d2c0bd84SPaolo Bonzini 2045d2c0bd84SPaolo Bonzini default: 2046d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 2047d2c0bd84SPaolo Bonzini } 2048d2c0bd84SPaolo Bonzini } 2049d2c0bd84SPaolo Bonzini 2050d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma4_ops = { 2051d2c0bd84SPaolo Bonzini .read = omap_dma4_read, 2052d2c0bd84SPaolo Bonzini .write = omap_dma4_write, 2053d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 2054d2c0bd84SPaolo Bonzini }; 2055d2c0bd84SPaolo Bonzini 2056d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 2057d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 2058d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu, int fifo, 2059d2c0bd84SPaolo Bonzini int chans, omap_clk iclk, omap_clk fclk) 2060d2c0bd84SPaolo Bonzini { 2061d2c0bd84SPaolo Bonzini int i; 2062d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) 2063d2c0bd84SPaolo Bonzini g_malloc0(sizeof(struct omap_dma_s)); 2064d2c0bd84SPaolo Bonzini 2065d2c0bd84SPaolo Bonzini s->model = omap_dma_4; 2066d2c0bd84SPaolo Bonzini s->chans = chans; 2067d2c0bd84SPaolo Bonzini s->mpu = mpu; 2068d2c0bd84SPaolo Bonzini s->clk = fclk; 2069d2c0bd84SPaolo Bonzini 2070d2c0bd84SPaolo Bonzini s->dma = soc_dma_init(s->chans); 2071d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(fclk); 2072d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 2073d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 2074d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64); 2075d2c0bd84SPaolo Bonzini s->dma->opaque = s; 2076d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 2077d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 2078d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 2079d2c0bd84SPaolo Bonzini } 2080d2c0bd84SPaolo Bonzini 2081d2c0bd84SPaolo Bonzini memcpy(&s->irq, irqs, sizeof(s->irq)); 2082d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_4_update; 2083d2c0bd84SPaolo Bonzini 2084d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 2085d2c0bd84SPaolo Bonzini omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); 2086d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 2087d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, !!s->dma->freq); 2088d2c0bd84SPaolo Bonzini 20892c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000); 2090d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 2091d2c0bd84SPaolo Bonzini 2092d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 2093d2c0bd84SPaolo Bonzini 2094d2c0bd84SPaolo Bonzini return s->dma; 2095d2c0bd84SPaolo Bonzini } 2096d2c0bd84SPaolo Bonzini 2097d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) 2098d2c0bd84SPaolo Bonzini { 2099d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 2100d2c0bd84SPaolo Bonzini 2101d2c0bd84SPaolo Bonzini return &s->lcd_ch; 2102d2c0bd84SPaolo Bonzini } 2103