1d2c0bd84SPaolo Bonzini /* 2d2c0bd84SPaolo Bonzini * TI OMAP DMA gigacell. 3d2c0bd84SPaolo Bonzini * 4d2c0bd84SPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5d2c0bd84SPaolo Bonzini * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br> 6d2c0bd84SPaolo Bonzini * 7d2c0bd84SPaolo Bonzini * This program is free software; you can redistribute it and/or 8d2c0bd84SPaolo Bonzini * modify it under the terms of the GNU General Public License as 9d2c0bd84SPaolo Bonzini * published by the Free Software Foundation; either version 2 of 10d2c0bd84SPaolo Bonzini * the License, or (at your option) any later version. 11d2c0bd84SPaolo Bonzini * 12d2c0bd84SPaolo Bonzini * This program is distributed in the hope that it will be useful, 13d2c0bd84SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d2c0bd84SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d2c0bd84SPaolo Bonzini * GNU General Public License for more details. 16d2c0bd84SPaolo Bonzini * 17d2c0bd84SPaolo Bonzini * You should have received a copy of the GNU General Public License along 18d2c0bd84SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 19d2c0bd84SPaolo Bonzini */ 2017b7f2dbSPeter Maydell #include "qemu/osdep.h" 21f3724bf5SPhilippe Mathieu-Daudé #include "qemu/log.h" 22d2c0bd84SPaolo Bonzini #include "qemu/timer.h" 23d2c0bd84SPaolo Bonzini #include "hw/arm/omap.h" 24d2c0bd84SPaolo Bonzini #include "hw/irq.h" 25d2c0bd84SPaolo Bonzini #include "hw/arm/soc_dma.h" 26d2c0bd84SPaolo Bonzini 27d2c0bd84SPaolo Bonzini struct omap_dma_channel_s { 28d2c0bd84SPaolo Bonzini /* transfer data */ 29d2c0bd84SPaolo Bonzini int burst[2]; 30d2c0bd84SPaolo Bonzini int pack[2]; 31d2c0bd84SPaolo Bonzini int endian[2]; 32d2c0bd84SPaolo Bonzini int endian_lock[2]; 33d2c0bd84SPaolo Bonzini int translate[2]; 34d2c0bd84SPaolo Bonzini enum omap_dma_port port[2]; 35d2c0bd84SPaolo Bonzini hwaddr addr[2]; 36d2c0bd84SPaolo Bonzini omap_dma_addressing_t mode[2]; 37d2c0bd84SPaolo Bonzini uint32_t elements; 38d2c0bd84SPaolo Bonzini uint16_t frames; 39d2c0bd84SPaolo Bonzini int32_t frame_index[2]; 40d2c0bd84SPaolo Bonzini int16_t element_index[2]; 41d2c0bd84SPaolo Bonzini int data_type; 42d2c0bd84SPaolo Bonzini 43d2c0bd84SPaolo Bonzini /* transfer type */ 44d2c0bd84SPaolo Bonzini int transparent_copy; 45d2c0bd84SPaolo Bonzini int constant_fill; 46d2c0bd84SPaolo Bonzini uint32_t color; 47d2c0bd84SPaolo Bonzini int prefetch; 48d2c0bd84SPaolo Bonzini 49d2c0bd84SPaolo Bonzini /* auto init and linked channel data */ 50d2c0bd84SPaolo Bonzini int end_prog; 51d2c0bd84SPaolo Bonzini int repeat; 52d2c0bd84SPaolo Bonzini int auto_init; 53d2c0bd84SPaolo Bonzini int link_enabled; 54d2c0bd84SPaolo Bonzini int link_next_ch; 55d2c0bd84SPaolo Bonzini 56d2c0bd84SPaolo Bonzini /* interruption data */ 57d2c0bd84SPaolo Bonzini int interrupts; 58d2c0bd84SPaolo Bonzini int status; 59d2c0bd84SPaolo Bonzini int cstatus; 60d2c0bd84SPaolo Bonzini 61d2c0bd84SPaolo Bonzini /* state data */ 62d2c0bd84SPaolo Bonzini int active; 63d2c0bd84SPaolo Bonzini int enable; 64d2c0bd84SPaolo Bonzini int sync; 65d2c0bd84SPaolo Bonzini int src_sync; 66d2c0bd84SPaolo Bonzini int pending_request; 67d2c0bd84SPaolo Bonzini int waiting_end_prog; 68d2c0bd84SPaolo Bonzini uint16_t cpc; 69d2c0bd84SPaolo Bonzini int set_update; 70d2c0bd84SPaolo Bonzini 71d2c0bd84SPaolo Bonzini /* sync type */ 72d2c0bd84SPaolo Bonzini int fs; 73d2c0bd84SPaolo Bonzini int bs; 74d2c0bd84SPaolo Bonzini 75d2c0bd84SPaolo Bonzini /* compatibility */ 76d2c0bd84SPaolo Bonzini int omap_3_1_compatible_disable; 77d2c0bd84SPaolo Bonzini 78d2c0bd84SPaolo Bonzini qemu_irq irq; 79d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *sibling; 80d2c0bd84SPaolo Bonzini 81d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s { 82d2c0bd84SPaolo Bonzini hwaddr src, dest; 83d2c0bd84SPaolo Bonzini int frame; 84d2c0bd84SPaolo Bonzini int element; 85d2c0bd84SPaolo Bonzini int pck_element; 86d2c0bd84SPaolo Bonzini int frame_delta[2]; 87d2c0bd84SPaolo Bonzini int elem_delta[2]; 88d2c0bd84SPaolo Bonzini int frames; 89d2c0bd84SPaolo Bonzini int elements; 90d2c0bd84SPaolo Bonzini int pck_elements; 91d2c0bd84SPaolo Bonzini } active_set; 92d2c0bd84SPaolo Bonzini 93d2c0bd84SPaolo Bonzini struct soc_dma_ch_s *dma; 94d2c0bd84SPaolo Bonzini 95d2c0bd84SPaolo Bonzini /* unused parameters */ 96d2c0bd84SPaolo Bonzini int write_mode; 97d2c0bd84SPaolo Bonzini int priority; 98d2c0bd84SPaolo Bonzini int interleave_disabled; 99d2c0bd84SPaolo Bonzini int type; 100d2c0bd84SPaolo Bonzini int suspend; 101d2c0bd84SPaolo Bonzini int buf_disable; 102d2c0bd84SPaolo Bonzini }; 103d2c0bd84SPaolo Bonzini 104d2c0bd84SPaolo Bonzini struct omap_dma_s { 105d2c0bd84SPaolo Bonzini struct soc_dma_s *dma; 106d2c0bd84SPaolo Bonzini MemoryRegion iomem; 107d2c0bd84SPaolo Bonzini 108d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu; 109d2c0bd84SPaolo Bonzini omap_clk clk; 110d2c0bd84SPaolo Bonzini qemu_irq irq[4]; 111d2c0bd84SPaolo Bonzini void (*intr_update)(struct omap_dma_s *s); 112d2c0bd84SPaolo Bonzini enum omap_dma_model model; 113d2c0bd84SPaolo Bonzini int omap_3_1_mapping_disabled; 114d2c0bd84SPaolo Bonzini 115d2c0bd84SPaolo Bonzini uint32_t gcr; 116d2c0bd84SPaolo Bonzini uint32_t ocp; 117d2c0bd84SPaolo Bonzini uint32_t caps[5]; 118d2c0bd84SPaolo Bonzini uint32_t irqen[4]; 119d2c0bd84SPaolo Bonzini uint32_t irqstat[4]; 120d2c0bd84SPaolo Bonzini 121d2c0bd84SPaolo Bonzini int chans; 122d2c0bd84SPaolo Bonzini struct omap_dma_channel_s ch[32]; 123d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s lcd_ch; 124d2c0bd84SPaolo Bonzini }; 125d2c0bd84SPaolo Bonzini 126d2c0bd84SPaolo Bonzini /* Interrupts */ 127d2c0bd84SPaolo Bonzini #define TIMEOUT_INTR (1 << 0) 128d2c0bd84SPaolo Bonzini #define EVENT_DROP_INTR (1 << 1) 129d2c0bd84SPaolo Bonzini #define HALF_FRAME_INTR (1 << 2) 130d2c0bd84SPaolo Bonzini #define END_FRAME_INTR (1 << 3) 131d2c0bd84SPaolo Bonzini #define LAST_FRAME_INTR (1 << 4) 132d2c0bd84SPaolo Bonzini #define END_BLOCK_INTR (1 << 5) 133d2c0bd84SPaolo Bonzini #define SYNC (1 << 6) 134d2c0bd84SPaolo Bonzini #define END_PKT_INTR (1 << 7) 135d2c0bd84SPaolo Bonzini #define TRANS_ERR_INTR (1 << 8) 136d2c0bd84SPaolo Bonzini #define MISALIGN_INTR (1 << 11) 137d2c0bd84SPaolo Bonzini 138d2c0bd84SPaolo Bonzini static inline void omap_dma_interrupts_update(struct omap_dma_s *s) 139d2c0bd84SPaolo Bonzini { 14077a8257eSStefan Weil s->intr_update(s); 141d2c0bd84SPaolo Bonzini } 142d2c0bd84SPaolo Bonzini 143d2c0bd84SPaolo Bonzini static void omap_dma_channel_load(struct omap_dma_channel_s *ch) 144d2c0bd84SPaolo Bonzini { 145d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 146d2c0bd84SPaolo Bonzini int i, normal; 147d2c0bd84SPaolo Bonzini int omap_3_1 = !ch->omap_3_1_compatible_disable; 148d2c0bd84SPaolo Bonzini 149d2c0bd84SPaolo Bonzini /* 150d2c0bd84SPaolo Bonzini * TODO: verify address ranges and alignment 151d2c0bd84SPaolo Bonzini * TODO: port endianness 152d2c0bd84SPaolo Bonzini */ 153d2c0bd84SPaolo Bonzini 154d2c0bd84SPaolo Bonzini a->src = ch->addr[0]; 155d2c0bd84SPaolo Bonzini a->dest = ch->addr[1]; 156d2c0bd84SPaolo Bonzini a->frames = ch->frames; 157d2c0bd84SPaolo Bonzini a->elements = ch->elements; 158d2c0bd84SPaolo Bonzini a->pck_elements = ch->frame_index[!ch->src_sync]; 159d2c0bd84SPaolo Bonzini a->frame = 0; 160d2c0bd84SPaolo Bonzini a->element = 0; 161d2c0bd84SPaolo Bonzini a->pck_element = 0; 162d2c0bd84SPaolo Bonzini 163d2c0bd84SPaolo Bonzini if (unlikely(!ch->elements || !ch->frames)) { 164a89f364aSAlistair Francis printf("%s: bad DMA request\n", __func__); 165d2c0bd84SPaolo Bonzini return; 166d2c0bd84SPaolo Bonzini } 167d2c0bd84SPaolo Bonzini 168d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) 169d2c0bd84SPaolo Bonzini switch (ch->mode[i]) { 170d2c0bd84SPaolo Bonzini case constant: 171d2c0bd84SPaolo Bonzini a->elem_delta[i] = 0; 172d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 173d2c0bd84SPaolo Bonzini break; 174d2c0bd84SPaolo Bonzini case post_incremented: 175d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type; 176d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 177d2c0bd84SPaolo Bonzini break; 178d2c0bd84SPaolo Bonzini case single_index: 179d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 180d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 181d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 182d2c0bd84SPaolo Bonzini break; 183d2c0bd84SPaolo Bonzini case double_index: 184d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 185d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 186d2c0bd84SPaolo Bonzini a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - 187d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i]; 188d2c0bd84SPaolo Bonzini break; 189d2c0bd84SPaolo Bonzini default: 190d2c0bd84SPaolo Bonzini break; 191d2c0bd84SPaolo Bonzini } 192d2c0bd84SPaolo Bonzini 193d2c0bd84SPaolo Bonzini normal = !ch->transparent_copy && !ch->constant_fill && 194d2c0bd84SPaolo Bonzini /* FIFO is big-endian so either (ch->endian[n] == 1) OR 195d2c0bd84SPaolo Bonzini * (ch->endian_lock[n] == 1) mean no endianism conversion. */ 196d2c0bd84SPaolo Bonzini (ch->endian[0] | ch->endian_lock[0]) == 197d2c0bd84SPaolo Bonzini (ch->endian[1] | ch->endian_lock[1]); 198d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) { 199d2c0bd84SPaolo Bonzini /* TODO: for a->frame_delta[i] > 0 still use the fast path, just 200d2c0bd84SPaolo Bonzini * limit min_elems in omap_dma_transfer_setup to the nearest frame 201d2c0bd84SPaolo Bonzini * end. */ 202d2c0bd84SPaolo Bonzini if (!a->elem_delta[i] && normal && 203d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 204d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_const; 205d2c0bd84SPaolo Bonzini else if (a->elem_delta[i] == ch->data_type && normal && 206d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 207d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_linear; 208d2c0bd84SPaolo Bonzini else 209d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_other; 210d2c0bd84SPaolo Bonzini 211d2c0bd84SPaolo Bonzini ch->dma->vaddr[i] = ch->addr[i]; 212d2c0bd84SPaolo Bonzini } 213d2c0bd84SPaolo Bonzini soc_dma_ch_update(ch->dma); 214d2c0bd84SPaolo Bonzini } 215d2c0bd84SPaolo Bonzini 216d2c0bd84SPaolo Bonzini static void omap_dma_activate_channel(struct omap_dma_s *s, 217d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 218d2c0bd84SPaolo Bonzini { 219d2c0bd84SPaolo Bonzini if (!ch->active) { 220d2c0bd84SPaolo Bonzini if (ch->set_update) { 221d2c0bd84SPaolo Bonzini /* It's not clear when the active set is supposed to be 222d2c0bd84SPaolo Bonzini * loaded from registers. We're already loading it when the 223d2c0bd84SPaolo Bonzini * channel is enabled, and for some guests this is not enough 224d2c0bd84SPaolo Bonzini * but that may be also because of a race condition (no 225d2c0bd84SPaolo Bonzini * delays in qemu) in the guest code, which we're just 226d2c0bd84SPaolo Bonzini * working around here. */ 227d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 228d2c0bd84SPaolo Bonzini ch->set_update = 0; 229d2c0bd84SPaolo Bonzini } 230d2c0bd84SPaolo Bonzini 231d2c0bd84SPaolo Bonzini ch->active = 1; 232d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 1); 233d2c0bd84SPaolo Bonzini if (ch->sync) 234d2c0bd84SPaolo Bonzini ch->status |= SYNC; 235d2c0bd84SPaolo Bonzini } 236d2c0bd84SPaolo Bonzini } 237d2c0bd84SPaolo Bonzini 238d2c0bd84SPaolo Bonzini static void omap_dma_deactivate_channel(struct omap_dma_s *s, 239d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 240d2c0bd84SPaolo Bonzini { 241d2c0bd84SPaolo Bonzini /* Update cpc */ 242d2c0bd84SPaolo Bonzini ch->cpc = ch->active_set.dest & 0xffff; 243d2c0bd84SPaolo Bonzini 244d2c0bd84SPaolo Bonzini if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { 245d2c0bd84SPaolo Bonzini /* Don't deactivate the channel */ 246d2c0bd84SPaolo Bonzini ch->pending_request = 0; 247d2c0bd84SPaolo Bonzini return; 248d2c0bd84SPaolo Bonzini } 249d2c0bd84SPaolo Bonzini 250d2c0bd84SPaolo Bonzini /* Don't deactive the channel if it is synchronized and the DMA request is 251d2c0bd84SPaolo Bonzini active */ 25276486736SPeter Maydell if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) 253d2c0bd84SPaolo Bonzini return; 254d2c0bd84SPaolo Bonzini 255d2c0bd84SPaolo Bonzini if (ch->active) { 256d2c0bd84SPaolo Bonzini ch->active = 0; 257d2c0bd84SPaolo Bonzini ch->status &= ~SYNC; 258d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 0); 259d2c0bd84SPaolo Bonzini } 260d2c0bd84SPaolo Bonzini } 261d2c0bd84SPaolo Bonzini 262d2c0bd84SPaolo Bonzini static void omap_dma_enable_channel(struct omap_dma_s *s, 263d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 264d2c0bd84SPaolo Bonzini { 265d2c0bd84SPaolo Bonzini if (!ch->enable) { 266d2c0bd84SPaolo Bonzini ch->enable = 1; 267d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 268d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 269d2c0bd84SPaolo Bonzini /* TODO: theoretically if ch->sync && ch->prefetch && 270d2c0bd84SPaolo Bonzini * !s->dma->drqbmp[ch->sync], we should also activate and fetch 271d2c0bd84SPaolo Bonzini * from source and then stall until signalled. */ 27276486736SPeter Maydell if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { 273d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 274d2c0bd84SPaolo Bonzini } 275d2c0bd84SPaolo Bonzini } 27676486736SPeter Maydell } 277d2c0bd84SPaolo Bonzini 278d2c0bd84SPaolo Bonzini static void omap_dma_disable_channel(struct omap_dma_s *s, 279d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 280d2c0bd84SPaolo Bonzini { 281d2c0bd84SPaolo Bonzini if (ch->enable) { 282d2c0bd84SPaolo Bonzini ch->enable = 0; 283d2c0bd84SPaolo Bonzini /* Discard any pending request */ 284d2c0bd84SPaolo Bonzini ch->pending_request = 0; 285d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 286d2c0bd84SPaolo Bonzini } 287d2c0bd84SPaolo Bonzini } 288d2c0bd84SPaolo Bonzini 289d2c0bd84SPaolo Bonzini static void omap_dma_channel_end_prog(struct omap_dma_s *s, 290d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 291d2c0bd84SPaolo Bonzini { 292d2c0bd84SPaolo Bonzini if (ch->waiting_end_prog) { 293d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 294d2c0bd84SPaolo Bonzini if (!ch->sync || ch->pending_request) { 295d2c0bd84SPaolo Bonzini ch->pending_request = 0; 296d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 297d2c0bd84SPaolo Bonzini } 298d2c0bd84SPaolo Bonzini } 299d2c0bd84SPaolo Bonzini } 300d2c0bd84SPaolo Bonzini 301d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) 302d2c0bd84SPaolo Bonzini { 303d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 304d2c0bd84SPaolo Bonzini 305d2c0bd84SPaolo Bonzini /* First three interrupts are shared between two channels each. */ 306d2c0bd84SPaolo Bonzini if (ch[0].status | ch[6].status) 307d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[0].irq); 308d2c0bd84SPaolo Bonzini if (ch[1].status | ch[7].status) 309d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[1].irq); 310d2c0bd84SPaolo Bonzini if (ch[2].status | ch[8].status) 311d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[2].irq); 312d2c0bd84SPaolo Bonzini if (ch[3].status) 313d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[3].irq); 314d2c0bd84SPaolo Bonzini if (ch[4].status) 315d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[4].irq); 316d2c0bd84SPaolo Bonzini if (ch[5].status) 317d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[5].irq); 318d2c0bd84SPaolo Bonzini } 319d2c0bd84SPaolo Bonzini 320d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) 321d2c0bd84SPaolo Bonzini { 322d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 323d2c0bd84SPaolo Bonzini int i; 324d2c0bd84SPaolo Bonzini 325d2c0bd84SPaolo Bonzini for (i = s->chans; i; ch ++, i --) 326d2c0bd84SPaolo Bonzini if (ch->status) 327d2c0bd84SPaolo Bonzini qemu_irq_raise(ch->irq); 328d2c0bd84SPaolo Bonzini } 329d2c0bd84SPaolo Bonzini 330d2c0bd84SPaolo Bonzini static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) 331d2c0bd84SPaolo Bonzini { 332d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 0; 333d2c0bd84SPaolo Bonzini s->chans = 9; 334d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_1_update; 335d2c0bd84SPaolo Bonzini } 336d2c0bd84SPaolo Bonzini 337d2c0bd84SPaolo Bonzini static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) 338d2c0bd84SPaolo Bonzini { 339d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 1; 340d2c0bd84SPaolo Bonzini s->chans = 16; 341d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_2_update; 342d2c0bd84SPaolo Bonzini } 343d2c0bd84SPaolo Bonzini 344d2c0bd84SPaolo Bonzini static void omap_dma_process_request(struct omap_dma_s *s, int request) 345d2c0bd84SPaolo Bonzini { 346d2c0bd84SPaolo Bonzini int channel; 347d2c0bd84SPaolo Bonzini int drop_event = 0; 348d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 349d2c0bd84SPaolo Bonzini 350d2c0bd84SPaolo Bonzini for (channel = 0; channel < s->chans; channel ++, ch ++) { 351d2c0bd84SPaolo Bonzini if (ch->enable && ch->sync == request) { 352d2c0bd84SPaolo Bonzini if (!ch->active) 353d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 354d2c0bd84SPaolo Bonzini else if (!ch->pending_request) 355d2c0bd84SPaolo Bonzini ch->pending_request = 1; 356d2c0bd84SPaolo Bonzini else { 357d2c0bd84SPaolo Bonzini /* Request collision */ 358d2c0bd84SPaolo Bonzini /* Second request received while processing other request */ 359d2c0bd84SPaolo Bonzini ch->status |= EVENT_DROP_INTR; 360d2c0bd84SPaolo Bonzini drop_event = 1; 361d2c0bd84SPaolo Bonzini } 362d2c0bd84SPaolo Bonzini } 363d2c0bd84SPaolo Bonzini } 364d2c0bd84SPaolo Bonzini 365d2c0bd84SPaolo Bonzini if (drop_event) 366d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 367d2c0bd84SPaolo Bonzini } 368d2c0bd84SPaolo Bonzini 369d2c0bd84SPaolo Bonzini static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) 370d2c0bd84SPaolo Bonzini { 371d2c0bd84SPaolo Bonzini uint8_t value[4]; 372d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 373d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 374d2c0bd84SPaolo Bonzini int bytes = dma->bytes; 375d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 376d2c0bd84SPaolo Bonzini uint16_t status = ch->status; 377d2c0bd84SPaolo Bonzini #endif 378d2c0bd84SPaolo Bonzini 379d2c0bd84SPaolo Bonzini do { 380d2c0bd84SPaolo Bonzini /* Transfer a single element */ 381d2c0bd84SPaolo Bonzini /* FIXME: check the endianness */ 382d2c0bd84SPaolo Bonzini if (!ch->constant_fill) 383d2c0bd84SPaolo Bonzini cpu_physical_memory_read(a->src, value, ch->data_type); 384d2c0bd84SPaolo Bonzini else 385d2c0bd84SPaolo Bonzini *(uint32_t *) value = ch->color; 386d2c0bd84SPaolo Bonzini 387d2c0bd84SPaolo Bonzini if (!ch->transparent_copy || *(uint32_t *) value != ch->color) 388d2c0bd84SPaolo Bonzini cpu_physical_memory_write(a->dest, value, ch->data_type); 389d2c0bd84SPaolo Bonzini 390d2c0bd84SPaolo Bonzini a->src += a->elem_delta[0]; 391d2c0bd84SPaolo Bonzini a->dest += a->elem_delta[1]; 392d2c0bd84SPaolo Bonzini a->element ++; 393d2c0bd84SPaolo Bonzini 394d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 395d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 396d2c0bd84SPaolo Bonzini /* End of Frame */ 397d2c0bd84SPaolo Bonzini a->element = 0; 398d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 399d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 400d2c0bd84SPaolo Bonzini a->frame ++; 401d2c0bd84SPaolo Bonzini 402d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 403d2c0bd84SPaolo Bonzini if (!ch->sync) 404d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 405d2c0bd84SPaolo Bonzini } 406d2c0bd84SPaolo Bonzini } while ((bytes -= ch->data_type)); 407d2c0bd84SPaolo Bonzini #else 408d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 409d2c0bd84SPaolo Bonzini if (ch->sync && !ch->fs && !ch->bs) 410d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 411d2c0bd84SPaolo Bonzini 412d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 413d2c0bd84SPaolo Bonzini if (a->element == 1 && a->frame == a->frames - 1) 414d2c0bd84SPaolo Bonzini if (ch->interrupts & LAST_FRAME_INTR) 415d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 416d2c0bd84SPaolo Bonzini 417d2c0bd84SPaolo Bonzini /* If the half of the frame was reached, set the HALF_FRAME 418d2c0bd84SPaolo Bonzini interrupt */ 419d2c0bd84SPaolo Bonzini if (a->element == (a->elements >> 1)) 420d2c0bd84SPaolo Bonzini if (ch->interrupts & HALF_FRAME_INTR) 421d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 422d2c0bd84SPaolo Bonzini 423d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 424d2c0bd84SPaolo Bonzini a->pck_element ++; 425d2c0bd84SPaolo Bonzini /* Check if a full packet has beed transferred. */ 426d2c0bd84SPaolo Bonzini if (a->pck_element == a->pck_elements) { 427d2c0bd84SPaolo Bonzini a->pck_element = 0; 428d2c0bd84SPaolo Bonzini 429d2c0bd84SPaolo Bonzini /* Set the END_PKT interrupt */ 430d2c0bd84SPaolo Bonzini if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) 431d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 432d2c0bd84SPaolo Bonzini 433d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 434d2c0bd84SPaolo Bonzini if (ch->sync) 435d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 436d2c0bd84SPaolo Bonzini } 437d2c0bd84SPaolo Bonzini } 438d2c0bd84SPaolo Bonzini 439d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 440d2c0bd84SPaolo Bonzini /* End of Frame */ 441d2c0bd84SPaolo Bonzini a->element = 0; 442d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 443d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 444d2c0bd84SPaolo Bonzini a->frame ++; 445d2c0bd84SPaolo Bonzini 446d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 447d2c0bd84SPaolo Bonzini if (ch->sync && ch->fs && !ch->bs) 448d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 449d2c0bd84SPaolo Bonzini 450d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 451d2c0bd84SPaolo Bonzini if (!ch->sync) 452d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 453d2c0bd84SPaolo Bonzini 454d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 455d2c0bd84SPaolo Bonzini if (ch->interrupts & END_FRAME_INTR) 456d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 457d2c0bd84SPaolo Bonzini 458d2c0bd84SPaolo Bonzini if (a->frame == a->frames) { 459d2c0bd84SPaolo Bonzini /* End of Block */ 460d2c0bd84SPaolo Bonzini /* Disable the channel */ 461d2c0bd84SPaolo Bonzini 462d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 463d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 464d2c0bd84SPaolo Bonzini if (ch->link_enabled) 465d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, 466d2c0bd84SPaolo Bonzini &s->ch[ch->link_next_ch]); 467d2c0bd84SPaolo Bonzini } else { 468d2c0bd84SPaolo Bonzini if (!ch->auto_init) 469d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 470d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 471d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 472d2c0bd84SPaolo Bonzini else { 473d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 474d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 475d2c0bd84SPaolo Bonzini } 476d2c0bd84SPaolo Bonzini } 477d2c0bd84SPaolo Bonzini 478d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 479d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 480d2c0bd84SPaolo Bonzini } 481d2c0bd84SPaolo Bonzini } 482d2c0bd84SPaolo Bonzini } while (status == ch->status && ch->active); 483d2c0bd84SPaolo Bonzini 484d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 485d2c0bd84SPaolo Bonzini #endif 486d2c0bd84SPaolo Bonzini } 487d2c0bd84SPaolo Bonzini 488d2c0bd84SPaolo Bonzini enum { 489d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 490d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 491d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 492d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 493d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 494d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 495d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 496d2c0bd84SPaolo Bonzini omap_dma_intr_block, 497d2c0bd84SPaolo Bonzini __omap_dma_intr_last, 498d2c0bd84SPaolo Bonzini }; 499d2c0bd84SPaolo Bonzini 500d2c0bd84SPaolo Bonzini static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) 501d2c0bd84SPaolo Bonzini { 502d2c0bd84SPaolo Bonzini struct omap_dma_port_if_s *src_p, *dest_p; 503d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a; 504d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 505d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->dma->opaque; 506d2c0bd84SPaolo Bonzini int frames, min_elems, elements[__omap_dma_intr_last]; 507d2c0bd84SPaolo Bonzini 508d2c0bd84SPaolo Bonzini a = &ch->active_set; 509d2c0bd84SPaolo Bonzini 510d2c0bd84SPaolo Bonzini src_p = &s->mpu->port[ch->port[0]]; 511d2c0bd84SPaolo Bonzini dest_p = &s->mpu->port[ch->port[1]]; 512d2c0bd84SPaolo Bonzini if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || 513d2c0bd84SPaolo Bonzini (!dest_p->addr_valid(s->mpu, a->dest))) { 514d2c0bd84SPaolo Bonzini #if 0 515d2c0bd84SPaolo Bonzini /* Bus time-out */ 516d2c0bd84SPaolo Bonzini if (ch->interrupts & TIMEOUT_INTR) 517d2c0bd84SPaolo Bonzini ch->status |= TIMEOUT_INTR; 518d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 519d2c0bd84SPaolo Bonzini continue; 520d2c0bd84SPaolo Bonzini #endif 521d2c0bd84SPaolo Bonzini printf("%s: Bus time-out in DMA%i operation\n", 522a89f364aSAlistair Francis __func__, dma->num); 523d2c0bd84SPaolo Bonzini } 524d2c0bd84SPaolo Bonzini 525d2c0bd84SPaolo Bonzini min_elems = INT_MAX; 526d2c0bd84SPaolo Bonzini 527d2c0bd84SPaolo Bonzini /* Check all the conditions that terminate the transfer starting 528d2c0bd84SPaolo Bonzini * with those that can occur the soonest. */ 529d2c0bd84SPaolo Bonzini #define INTR_CHECK(cond, id, nelements) \ 530d2c0bd84SPaolo Bonzini if (cond) { \ 531d2c0bd84SPaolo Bonzini elements[id] = nelements; \ 532d2c0bd84SPaolo Bonzini if (elements[id] < min_elems) \ 533d2c0bd84SPaolo Bonzini min_elems = elements[id]; \ 534d2c0bd84SPaolo Bonzini } else \ 535d2c0bd84SPaolo Bonzini elements[id] = INT_MAX; 536d2c0bd84SPaolo Bonzini 537d2c0bd84SPaolo Bonzini /* Elements */ 538d2c0bd84SPaolo Bonzini INTR_CHECK( 539d2c0bd84SPaolo Bonzini ch->sync && !ch->fs && !ch->bs, 540d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 541d2c0bd84SPaolo Bonzini 1) 542d2c0bd84SPaolo Bonzini 543d2c0bd84SPaolo Bonzini /* Frames */ 544d2c0bd84SPaolo Bonzini /* TODO: for transfers where entire frames can be read and written 545d2c0bd84SPaolo Bonzini * using memcpy() but a->frame_delta is non-zero, try to still do 546d2c0bd84SPaolo Bonzini * transfers using soc_dma but limit min_elems to a->elements - ... 547d2c0bd84SPaolo Bonzini * See also the TODO in omap_dma_channel_load. */ 548d2c0bd84SPaolo Bonzini INTR_CHECK( 549d2c0bd84SPaolo Bonzini (ch->interrupts & LAST_FRAME_INTR) && 550d2c0bd84SPaolo Bonzini ((a->frame < a->frames - 1) || !a->element), 551d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 552d2c0bd84SPaolo Bonzini (a->frames - a->frame - 2) * a->elements + 553d2c0bd84SPaolo Bonzini (a->elements - a->element + 1)) 554d2c0bd84SPaolo Bonzini INTR_CHECK( 555d2c0bd84SPaolo Bonzini ch->interrupts & HALF_FRAME_INTR, 556d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 557d2c0bd84SPaolo Bonzini (a->elements >> 1) + 558d2c0bd84SPaolo Bonzini (a->element >= (a->elements >> 1) ? a->elements : 0) - 559d2c0bd84SPaolo Bonzini a->element) 560d2c0bd84SPaolo Bonzini INTR_CHECK( 561d2c0bd84SPaolo Bonzini ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), 562d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 563d2c0bd84SPaolo Bonzini a->elements - a->element) 564d2c0bd84SPaolo Bonzini INTR_CHECK( 565d2c0bd84SPaolo Bonzini ch->sync && ch->fs && !ch->bs, 566d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 567d2c0bd84SPaolo Bonzini a->elements - a->element) 568d2c0bd84SPaolo Bonzini 569d2c0bd84SPaolo Bonzini /* Packets */ 570d2c0bd84SPaolo Bonzini INTR_CHECK( 571d2c0bd84SPaolo Bonzini ch->fs && ch->bs && 572d2c0bd84SPaolo Bonzini (ch->interrupts & END_PKT_INTR) && !ch->src_sync, 573d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 574d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 575d2c0bd84SPaolo Bonzini INTR_CHECK( 576d2c0bd84SPaolo Bonzini ch->fs && ch->bs && ch->sync, 577d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 578d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 579d2c0bd84SPaolo Bonzini 580d2c0bd84SPaolo Bonzini /* Blocks */ 581d2c0bd84SPaolo Bonzini INTR_CHECK( 582d2c0bd84SPaolo Bonzini 1, 583d2c0bd84SPaolo Bonzini omap_dma_intr_block, 584d2c0bd84SPaolo Bonzini (a->frames - a->frame - 1) * a->elements + 585d2c0bd84SPaolo Bonzini (a->elements - a->element)) 586d2c0bd84SPaolo Bonzini 587d2c0bd84SPaolo Bonzini dma->bytes = min_elems * ch->data_type; 588d2c0bd84SPaolo Bonzini 589d2c0bd84SPaolo Bonzini /* Set appropriate interrupts and/or deactivate channels */ 590d2c0bd84SPaolo Bonzini 591d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 592d2c0bd84SPaolo Bonzini /* TODO: should all of this only be done if dma->update, and otherwise 593d2c0bd84SPaolo Bonzini * inside omap_dma_transfer_generic below - check what's faster. */ 594d2c0bd84SPaolo Bonzini if (dma->update) { 595d2c0bd84SPaolo Bonzini #endif 596d2c0bd84SPaolo Bonzini 597d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 598d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_element_sync]) 599d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 600d2c0bd84SPaolo Bonzini 601d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 602d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_last_frame]) 603d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 604d2c0bd84SPaolo Bonzini 605d2c0bd84SPaolo Bonzini /* If exactly half of the frame was reached, set the HALF_FRAME 606d2c0bd84SPaolo Bonzini interrupt */ 607d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_half_frame]) 608d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 609d2c0bd84SPaolo Bonzini 610d2c0bd84SPaolo Bonzini /* If a full packet has been transferred, set the END_PKT interrupt */ 611d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet]) 612d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 613d2c0bd84SPaolo Bonzini 614d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 615d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet_sync]) 616d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 617d2c0bd84SPaolo Bonzini 618d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 619d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame_sync]) 620d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 621d2c0bd84SPaolo Bonzini 622d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 623d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame]) 624d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 625d2c0bd84SPaolo Bonzini 626d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_block]) { 627d2c0bd84SPaolo Bonzini /* End of Block */ 628d2c0bd84SPaolo Bonzini /* Disable the channel */ 629d2c0bd84SPaolo Bonzini 630d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 631d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 632d2c0bd84SPaolo Bonzini if (ch->link_enabled) 633d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); 634d2c0bd84SPaolo Bonzini } else { 635d2c0bd84SPaolo Bonzini if (!ch->auto_init) 636d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 637d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 638d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 639d2c0bd84SPaolo Bonzini else { 640d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 641d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 642d2c0bd84SPaolo Bonzini } 643d2c0bd84SPaolo Bonzini } 644d2c0bd84SPaolo Bonzini 645d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 646d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 647d2c0bd84SPaolo Bonzini } 648d2c0bd84SPaolo Bonzini 649d2c0bd84SPaolo Bonzini /* Update packet number */ 650d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 651d2c0bd84SPaolo Bonzini a->pck_element += min_elems; 652d2c0bd84SPaolo Bonzini a->pck_element %= a->pck_elements; 653d2c0bd84SPaolo Bonzini } 654d2c0bd84SPaolo Bonzini 655d2c0bd84SPaolo Bonzini /* TODO: check if we really need to update anything here or perhaps we 656d2c0bd84SPaolo Bonzini * can skip part of this. */ 657d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 658d2c0bd84SPaolo Bonzini if (dma->update) { 659d2c0bd84SPaolo Bonzini #endif 660d2c0bd84SPaolo Bonzini a->element += min_elems; 661d2c0bd84SPaolo Bonzini 662d2c0bd84SPaolo Bonzini frames = a->element / a->elements; 663d2c0bd84SPaolo Bonzini a->element = a->element % a->elements; 664d2c0bd84SPaolo Bonzini a->frame += frames; 665d2c0bd84SPaolo Bonzini a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; 666d2c0bd84SPaolo Bonzini a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; 667d2c0bd84SPaolo Bonzini 668d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 669d2c0bd84SPaolo Bonzini if (!ch->sync && frames) 670d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 671d2c0bd84SPaolo Bonzini 672d2c0bd84SPaolo Bonzini /* TODO: if the destination port is IMIF or EMIFF, set the dirty 673d2c0bd84SPaolo Bonzini * bits on it. */ 674d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 675d2c0bd84SPaolo Bonzini } 676d2c0bd84SPaolo Bonzini #else 677d2c0bd84SPaolo Bonzini } 678d2c0bd84SPaolo Bonzini #endif 679d2c0bd84SPaolo Bonzini 680d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 681d2c0bd84SPaolo Bonzini } 682d2c0bd84SPaolo Bonzini 683d2c0bd84SPaolo Bonzini void omap_dma_reset(struct soc_dma_s *dma) 684d2c0bd84SPaolo Bonzini { 685d2c0bd84SPaolo Bonzini int i; 686d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 687d2c0bd84SPaolo Bonzini 688d2c0bd84SPaolo Bonzini soc_dma_reset(s->dma); 689d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 690d2c0bd84SPaolo Bonzini s->gcr = 0x0004; 691d2c0bd84SPaolo Bonzini else 692d2c0bd84SPaolo Bonzini s->gcr = 0x00010010; 693d2c0bd84SPaolo Bonzini s->ocp = 0x00000000; 694d2c0bd84SPaolo Bonzini memset(&s->irqstat, 0, sizeof(s->irqstat)); 695d2c0bd84SPaolo Bonzini memset(&s->irqen, 0, sizeof(s->irqen)); 696d2c0bd84SPaolo Bonzini s->lcd_ch.src = emiff; 697d2c0bd84SPaolo Bonzini s->lcd_ch.condition = 0; 698d2c0bd84SPaolo Bonzini s->lcd_ch.interrupts = 0; 699d2c0bd84SPaolo Bonzini s->lcd_ch.dual = 0; 700d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 701d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 702d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 703d2c0bd84SPaolo Bonzini s->ch[i].suspend = 0; 704d2c0bd84SPaolo Bonzini s->ch[i].prefetch = 0; 705d2c0bd84SPaolo Bonzini s->ch[i].buf_disable = 0; 706d2c0bd84SPaolo Bonzini s->ch[i].src_sync = 0; 707d2c0bd84SPaolo Bonzini memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); 708d2c0bd84SPaolo Bonzini memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); 709d2c0bd84SPaolo Bonzini memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); 710d2c0bd84SPaolo Bonzini memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); 711d2c0bd84SPaolo Bonzini memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); 712d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); 713d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); 714d2c0bd84SPaolo Bonzini memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); 715d2c0bd84SPaolo Bonzini s->ch[i].write_mode = 0; 716d2c0bd84SPaolo Bonzini s->ch[i].data_type = 0; 717d2c0bd84SPaolo Bonzini s->ch[i].transparent_copy = 0; 718d2c0bd84SPaolo Bonzini s->ch[i].constant_fill = 0; 719d2c0bd84SPaolo Bonzini s->ch[i].color = 0x00000000; 720d2c0bd84SPaolo Bonzini s->ch[i].end_prog = 0; 721d2c0bd84SPaolo Bonzini s->ch[i].repeat = 0; 722d2c0bd84SPaolo Bonzini s->ch[i].auto_init = 0; 723d2c0bd84SPaolo Bonzini s->ch[i].link_enabled = 0; 724d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 725d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0003; 726d2c0bd84SPaolo Bonzini else 727d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0000; 728d2c0bd84SPaolo Bonzini s->ch[i].status = 0; 729d2c0bd84SPaolo Bonzini s->ch[i].cstatus = 0; 730d2c0bd84SPaolo Bonzini s->ch[i].active = 0; 731d2c0bd84SPaolo Bonzini s->ch[i].enable = 0; 732d2c0bd84SPaolo Bonzini s->ch[i].sync = 0; 733d2c0bd84SPaolo Bonzini s->ch[i].pending_request = 0; 734d2c0bd84SPaolo Bonzini s->ch[i].waiting_end_prog = 0; 735d2c0bd84SPaolo Bonzini s->ch[i].cpc = 0x0000; 736d2c0bd84SPaolo Bonzini s->ch[i].fs = 0; 737d2c0bd84SPaolo Bonzini s->ch[i].bs = 0; 738d2c0bd84SPaolo Bonzini s->ch[i].omap_3_1_compatible_disable = 0; 739d2c0bd84SPaolo Bonzini memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); 740d2c0bd84SPaolo Bonzini s->ch[i].priority = 0; 741d2c0bd84SPaolo Bonzini s->ch[i].interleave_disabled = 0; 742d2c0bd84SPaolo Bonzini s->ch[i].type = 0; 743d2c0bd84SPaolo Bonzini } 744d2c0bd84SPaolo Bonzini } 745d2c0bd84SPaolo Bonzini 746d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_read(struct omap_dma_s *s, 747d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t *value) 748d2c0bd84SPaolo Bonzini { 749d2c0bd84SPaolo Bonzini switch (reg) { 750d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 751d2c0bd84SPaolo Bonzini *value = (ch->burst[1] << 14) | 752d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 753d2c0bd84SPaolo Bonzini (ch->port[1] << 9) | 754d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 755d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 756d2c0bd84SPaolo Bonzini (ch->port[0] << 2) | 757d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 758d2c0bd84SPaolo Bonzini break; 759d2c0bd84SPaolo Bonzini 760d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 761d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 762d2c0bd84SPaolo Bonzini *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ 763d2c0bd84SPaolo Bonzini else 764d2c0bd84SPaolo Bonzini *value = ch->omap_3_1_compatible_disable << 10; 765d2c0bd84SPaolo Bonzini *value |= (ch->mode[1] << 14) | 766d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 767d2c0bd84SPaolo Bonzini (ch->end_prog << 11) | 768d2c0bd84SPaolo Bonzini (ch->repeat << 9) | 769d2c0bd84SPaolo Bonzini (ch->auto_init << 8) | 770d2c0bd84SPaolo Bonzini (ch->enable << 7) | 771d2c0bd84SPaolo Bonzini (ch->priority << 6) | 772d2c0bd84SPaolo Bonzini (ch->fs << 5) | ch->sync; 773d2c0bd84SPaolo Bonzini break; 774d2c0bd84SPaolo Bonzini 775d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 776d2c0bd84SPaolo Bonzini *value = ch->interrupts; 777d2c0bd84SPaolo Bonzini break; 778d2c0bd84SPaolo Bonzini 779d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 780d2c0bd84SPaolo Bonzini *value = ch->status; 781d2c0bd84SPaolo Bonzini ch->status &= SYNC; 782d2c0bd84SPaolo Bonzini if (!ch->omap_3_1_compatible_disable && ch->sibling) { 783d2c0bd84SPaolo Bonzini *value |= (ch->sibling->status & 0x3f) << 6; 784d2c0bd84SPaolo Bonzini ch->sibling->status &= SYNC; 785d2c0bd84SPaolo Bonzini } 786d2c0bd84SPaolo Bonzini qemu_irq_lower(ch->irq); 787d2c0bd84SPaolo Bonzini break; 788d2c0bd84SPaolo Bonzini 789d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 790d2c0bd84SPaolo Bonzini *value = ch->addr[0] & 0x0000ffff; 791d2c0bd84SPaolo Bonzini break; 792d2c0bd84SPaolo Bonzini 793d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 794d2c0bd84SPaolo Bonzini *value = ch->addr[0] >> 16; 795d2c0bd84SPaolo Bonzini break; 796d2c0bd84SPaolo Bonzini 797d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 798d2c0bd84SPaolo Bonzini *value = ch->addr[1] & 0x0000ffff; 799d2c0bd84SPaolo Bonzini break; 800d2c0bd84SPaolo Bonzini 801d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 802d2c0bd84SPaolo Bonzini *value = ch->addr[1] >> 16; 803d2c0bd84SPaolo Bonzini break; 804d2c0bd84SPaolo Bonzini 805d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 806d2c0bd84SPaolo Bonzini *value = ch->elements; 807d2c0bd84SPaolo Bonzini break; 808d2c0bd84SPaolo Bonzini 809d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 810d2c0bd84SPaolo Bonzini *value = ch->frames; 811d2c0bd84SPaolo Bonzini break; 812d2c0bd84SPaolo Bonzini 813d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 814d2c0bd84SPaolo Bonzini *value = ch->frame_index[0]; 815d2c0bd84SPaolo Bonzini break; 816d2c0bd84SPaolo Bonzini 817d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 818d2c0bd84SPaolo Bonzini *value = ch->element_index[0]; 819d2c0bd84SPaolo Bonzini break; 820d2c0bd84SPaolo Bonzini 821d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 822d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) 823d2c0bd84SPaolo Bonzini *value = ch->active_set.src & 0xffff; /* CSAC */ 824d2c0bd84SPaolo Bonzini else 825d2c0bd84SPaolo Bonzini *value = ch->cpc; 826d2c0bd84SPaolo Bonzini break; 827d2c0bd84SPaolo Bonzini 828d2c0bd84SPaolo Bonzini case 0x1a: /* DMA_CDAC */ 829d2c0bd84SPaolo Bonzini *value = ch->active_set.dest & 0xffff; /* CDAC */ 830d2c0bd84SPaolo Bonzini break; 831d2c0bd84SPaolo Bonzini 832d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 833d2c0bd84SPaolo Bonzini *value = ch->element_index[1]; 834d2c0bd84SPaolo Bonzini break; 835d2c0bd84SPaolo Bonzini 836d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 837d2c0bd84SPaolo Bonzini *value = ch->frame_index[1]; 838d2c0bd84SPaolo Bonzini break; 839d2c0bd84SPaolo Bonzini 840d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 841d2c0bd84SPaolo Bonzini *value = ch->color & 0xffff; 842d2c0bd84SPaolo Bonzini break; 843d2c0bd84SPaolo Bonzini 844d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 845d2c0bd84SPaolo Bonzini *value = ch->color >> 16; 846d2c0bd84SPaolo Bonzini break; 847d2c0bd84SPaolo Bonzini 848d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 849d2c0bd84SPaolo Bonzini *value = (ch->bs << 2) | 850d2c0bd84SPaolo Bonzini (ch->transparent_copy << 1) | 851d2c0bd84SPaolo Bonzini ch->constant_fill; 852d2c0bd84SPaolo Bonzini break; 853d2c0bd84SPaolo Bonzini 854d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 855d2c0bd84SPaolo Bonzini *value = (ch->link_enabled << 15) | 856d2c0bd84SPaolo Bonzini (ch->link_next_ch & 0xf); 857d2c0bd84SPaolo Bonzini break; 858d2c0bd84SPaolo Bonzini 859d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 860d2c0bd84SPaolo Bonzini *value = (ch->interleave_disabled << 15) | 861d2c0bd84SPaolo Bonzini ch->type; 862d2c0bd84SPaolo Bonzini break; 863d2c0bd84SPaolo Bonzini 864d2c0bd84SPaolo Bonzini default: 865d2c0bd84SPaolo Bonzini return 1; 866d2c0bd84SPaolo Bonzini } 867d2c0bd84SPaolo Bonzini return 0; 868d2c0bd84SPaolo Bonzini } 869d2c0bd84SPaolo Bonzini 870d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_write(struct omap_dma_s *s, 871d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t value) 872d2c0bd84SPaolo Bonzini { 873d2c0bd84SPaolo Bonzini switch (reg) { 874d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 875d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 876d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 877d2c0bd84SPaolo Bonzini ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); 878d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 879d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 880d2c0bd84SPaolo Bonzini ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); 881e26745d5SPhilippe Mathieu-Daudé if (ch->port[0] >= __omap_dma_port_last) { 882e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n", 883e26745d5SPhilippe Mathieu-Daudé __func__, ch->port[0]); 884e26745d5SPhilippe Mathieu-Daudé } 885e26745d5SPhilippe Mathieu-Daudé if (ch->port[1] >= __omap_dma_port_last) { 886e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n", 887e26745d5SPhilippe Mathieu-Daudé __func__, ch->port[1]); 888e26745d5SPhilippe Mathieu-Daudé } 889146871c3SPrasad J Pandit ch->data_type = 1 << (value & 3); 890146871c3SPrasad J Pandit if ((value & 3) == 3) { 891e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 892e26745d5SPhilippe Mathieu-Daudé "%s: bad data_type for DMA channel\n", __func__); 893146871c3SPrasad J Pandit ch->data_type >>= 1; 894146871c3SPrasad J Pandit } 895d2c0bd84SPaolo Bonzini break; 896d2c0bd84SPaolo Bonzini 897d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 898d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 899d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 900d2c0bd84SPaolo Bonzini ch->end_prog = (value & 0x0800) >> 11; 901d2c0bd84SPaolo Bonzini if (s->model >= omap_dma_3_2) 902d2c0bd84SPaolo Bonzini ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; 903d2c0bd84SPaolo Bonzini ch->repeat = (value & 0x0200) >> 9; 904d2c0bd84SPaolo Bonzini ch->auto_init = (value & 0x0100) >> 8; 905d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 906d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 907d2c0bd84SPaolo Bonzini ch->sync = value & 0x001f; 908d2c0bd84SPaolo Bonzini 909d2c0bd84SPaolo Bonzini if (value & 0x0080) 910d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 911d2c0bd84SPaolo Bonzini else 912d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 913d2c0bd84SPaolo Bonzini 914d2c0bd84SPaolo Bonzini if (ch->end_prog) 915d2c0bd84SPaolo Bonzini omap_dma_channel_end_prog(s, ch); 916d2c0bd84SPaolo Bonzini 917d2c0bd84SPaolo Bonzini break; 918d2c0bd84SPaolo Bonzini 919d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 920d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x3f; 921d2c0bd84SPaolo Bonzini break; 922d2c0bd84SPaolo Bonzini 923d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 924d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 925d2c0bd84SPaolo Bonzini break; 926d2c0bd84SPaolo Bonzini 927d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 928d2c0bd84SPaolo Bonzini ch->addr[0] &= 0xffff0000; 929d2c0bd84SPaolo Bonzini ch->addr[0] |= value; 930d2c0bd84SPaolo Bonzini break; 931d2c0bd84SPaolo Bonzini 932d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 933d2c0bd84SPaolo Bonzini ch->addr[0] &= 0x0000ffff; 934d2c0bd84SPaolo Bonzini ch->addr[0] |= (uint32_t) value << 16; 935d2c0bd84SPaolo Bonzini break; 936d2c0bd84SPaolo Bonzini 937d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 938d2c0bd84SPaolo Bonzini ch->addr[1] &= 0xffff0000; 939d2c0bd84SPaolo Bonzini ch->addr[1] |= value; 940d2c0bd84SPaolo Bonzini break; 941d2c0bd84SPaolo Bonzini 942d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 943d2c0bd84SPaolo Bonzini ch->addr[1] &= 0x0000ffff; 944d2c0bd84SPaolo Bonzini ch->addr[1] |= (uint32_t) value << 16; 945d2c0bd84SPaolo Bonzini break; 946d2c0bd84SPaolo Bonzini 947d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 948d2c0bd84SPaolo Bonzini ch->elements = value; 949d2c0bd84SPaolo Bonzini break; 950d2c0bd84SPaolo Bonzini 951d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 952d2c0bd84SPaolo Bonzini ch->frames = value; 953d2c0bd84SPaolo Bonzini break; 954d2c0bd84SPaolo Bonzini 955d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 956d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int16_t) value; 957d2c0bd84SPaolo Bonzini break; 958d2c0bd84SPaolo Bonzini 959d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 960d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 961d2c0bd84SPaolo Bonzini break; 962d2c0bd84SPaolo Bonzini 963d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 964d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 965d2c0bd84SPaolo Bonzini break; 966d2c0bd84SPaolo Bonzini 967d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 968d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 969d2c0bd84SPaolo Bonzini break; 970d2c0bd84SPaolo Bonzini 971d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 972d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int16_t) value; 973d2c0bd84SPaolo Bonzini break; 974d2c0bd84SPaolo Bonzini 975d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 976d2c0bd84SPaolo Bonzini ch->color &= 0xffff0000; 977d2c0bd84SPaolo Bonzini ch->color |= value; 978d2c0bd84SPaolo Bonzini break; 979d2c0bd84SPaolo Bonzini 980d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 981d2c0bd84SPaolo Bonzini ch->color &= 0xffff; 9822a41c928SPeter Maydell ch->color |= (uint32_t)value << 16; 983d2c0bd84SPaolo Bonzini break; 984d2c0bd84SPaolo Bonzini 985d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 986d2c0bd84SPaolo Bonzini ch->bs = (value >> 2) & 0x1; 987d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 1) & 0x1; 988d2c0bd84SPaolo Bonzini ch->constant_fill = value & 0x1; 989d2c0bd84SPaolo Bonzini break; 990d2c0bd84SPaolo Bonzini 991d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 992d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 993d2c0bd84SPaolo Bonzini if (value & (1 << 14)) { /* Stop_Lnk */ 994d2c0bd84SPaolo Bonzini ch->link_enabled = 0; 995d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 996d2c0bd84SPaolo Bonzini } 997d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 998d2c0bd84SPaolo Bonzini break; 999d2c0bd84SPaolo Bonzini 1000d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 1001d2c0bd84SPaolo Bonzini ch->interleave_disabled = (value >> 15) & 0x1; 1002d2c0bd84SPaolo Bonzini ch->type = value & 0xf; 1003d2c0bd84SPaolo Bonzini break; 1004d2c0bd84SPaolo Bonzini 1005d2c0bd84SPaolo Bonzini default: 1006d2c0bd84SPaolo Bonzini return 1; 1007d2c0bd84SPaolo Bonzini } 1008d2c0bd84SPaolo Bonzini return 0; 1009d2c0bd84SPaolo Bonzini } 1010d2c0bd84SPaolo Bonzini 1011d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1012d2c0bd84SPaolo Bonzini uint16_t value) 1013d2c0bd84SPaolo Bonzini { 1014d2c0bd84SPaolo Bonzini switch (offset) { 1015d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1016d2c0bd84SPaolo Bonzini s->brust_f2 = (value >> 14) & 0x3; 1017d2c0bd84SPaolo Bonzini s->pack_f2 = (value >> 13) & 0x1; 1018d2c0bd84SPaolo Bonzini s->data_type_f2 = (1 << ((value >> 11) & 0x3)); 1019d2c0bd84SPaolo Bonzini s->brust_f1 = (value >> 7) & 0x3; 1020d2c0bd84SPaolo Bonzini s->pack_f1 = (value >> 6) & 0x1; 1021d2c0bd84SPaolo Bonzini s->data_type_f1 = (1 << ((value >> 0) & 0x3)); 1022d2c0bd84SPaolo Bonzini break; 1023d2c0bd84SPaolo Bonzini 1024d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1025d2c0bd84SPaolo Bonzini s->mode_f2 = (value >> 14) & 0x3; 1026d2c0bd84SPaolo Bonzini s->mode_f1 = (value >> 12) & 0x3; 1027d2c0bd84SPaolo Bonzini s->end_prog = (value >> 11) & 0x1; 1028d2c0bd84SPaolo Bonzini s->omap_3_1_compatible_disable = (value >> 10) & 0x1; 1029d2c0bd84SPaolo Bonzini s->repeat = (value >> 9) & 0x1; 1030d2c0bd84SPaolo Bonzini s->auto_init = (value >> 8) & 0x1; 1031d2c0bd84SPaolo Bonzini s->running = (value >> 7) & 0x1; 1032d2c0bd84SPaolo Bonzini s->priority = (value >> 6) & 0x1; 1033d2c0bd84SPaolo Bonzini s->bs = (value >> 4) & 0x1; 1034d2c0bd84SPaolo Bonzini break; 1035d2c0bd84SPaolo Bonzini 1036d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1037d2c0bd84SPaolo Bonzini s->dst = (value >> 8) & 0x1; 1038d2c0bd84SPaolo Bonzini s->src = ((value >> 6) & 0x3) << 1; 1039d2c0bd84SPaolo Bonzini s->condition = 0; 1040d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1041d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1042d2c0bd84SPaolo Bonzini s->dual = value & 1; 1043d2c0bd84SPaolo Bonzini break; 1044d2c0bd84SPaolo Bonzini 1045d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1046d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1047d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1048d2c0bd84SPaolo Bonzini break; 1049d2c0bd84SPaolo Bonzini 1050d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1051d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 10522a41c928SPeter Maydell s->src_f1_top |= (uint32_t)value << 16; 1053d2c0bd84SPaolo Bonzini break; 1054d2c0bd84SPaolo Bonzini 1055d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1056d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1057d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1058d2c0bd84SPaolo Bonzini break; 1059d2c0bd84SPaolo Bonzini 1060d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1061d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 1062d2c0bd84SPaolo Bonzini s->src_f1_bottom |= (uint32_t) value << 16; 1063d2c0bd84SPaolo Bonzini break; 1064d2c0bd84SPaolo Bonzini 1065d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1066d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1067d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1068d2c0bd84SPaolo Bonzini break; 1069d2c0bd84SPaolo Bonzini 1070d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1071d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 1072d2c0bd84SPaolo Bonzini s->src_f2_top |= (uint32_t) value << 16; 1073d2c0bd84SPaolo Bonzini break; 1074d2c0bd84SPaolo Bonzini 1075d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1076d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1077d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1078d2c0bd84SPaolo Bonzini break; 1079d2c0bd84SPaolo Bonzini 1080d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1081d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 1082d2c0bd84SPaolo Bonzini s->src_f2_bottom |= (uint32_t) value << 16; 1083d2c0bd84SPaolo Bonzini break; 1084d2c0bd84SPaolo Bonzini 1085d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1086d2c0bd84SPaolo Bonzini s->element_index_f1 = value; 1087d2c0bd84SPaolo Bonzini break; 1088d2c0bd84SPaolo Bonzini 1089d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1090d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0xffff0000; 1091d2c0bd84SPaolo Bonzini s->frame_index_f1 |= 0x0000ffff & value; 1092d2c0bd84SPaolo Bonzini break; 1093d2c0bd84SPaolo Bonzini 1094d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1095d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0x0000ffff; 1096d2c0bd84SPaolo Bonzini s->frame_index_f1 |= (uint32_t) value << 16; 1097d2c0bd84SPaolo Bonzini break; 1098d2c0bd84SPaolo Bonzini 1099d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1100d2c0bd84SPaolo Bonzini s->element_index_f2 = value; 1101d2c0bd84SPaolo Bonzini break; 1102d2c0bd84SPaolo Bonzini 1103d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1104d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0xffff0000; 1105d2c0bd84SPaolo Bonzini s->frame_index_f2 |= 0x0000ffff & value; 1106d2c0bd84SPaolo Bonzini break; 1107d2c0bd84SPaolo Bonzini 1108d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1109d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0x0000ffff; 1110d2c0bd84SPaolo Bonzini s->frame_index_f2 |= (uint32_t) value << 16; 1111d2c0bd84SPaolo Bonzini break; 1112d2c0bd84SPaolo Bonzini 1113d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1114d2c0bd84SPaolo Bonzini s->elements_f1 = value; 1115d2c0bd84SPaolo Bonzini break; 1116d2c0bd84SPaolo Bonzini 1117d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1118d2c0bd84SPaolo Bonzini s->frames_f1 = value; 1119d2c0bd84SPaolo Bonzini break; 1120d2c0bd84SPaolo Bonzini 1121d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1122d2c0bd84SPaolo Bonzini s->elements_f2 = value; 1123d2c0bd84SPaolo Bonzini break; 1124d2c0bd84SPaolo Bonzini 1125d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1126d2c0bd84SPaolo Bonzini s->frames_f2 = value; 1127d2c0bd84SPaolo Bonzini break; 1128d2c0bd84SPaolo Bonzini 1129d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1130d2c0bd84SPaolo Bonzini s->lch_type = value & 0xf; 1131d2c0bd84SPaolo Bonzini break; 1132d2c0bd84SPaolo Bonzini 1133d2c0bd84SPaolo Bonzini default: 1134d2c0bd84SPaolo Bonzini return 1; 1135d2c0bd84SPaolo Bonzini } 1136d2c0bd84SPaolo Bonzini return 0; 1137d2c0bd84SPaolo Bonzini } 1138d2c0bd84SPaolo Bonzini 1139d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1140d2c0bd84SPaolo Bonzini uint16_t *ret) 1141d2c0bd84SPaolo Bonzini { 1142d2c0bd84SPaolo Bonzini switch (offset) { 1143d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1144d2c0bd84SPaolo Bonzini *ret = (s->brust_f2 << 14) | 1145d2c0bd84SPaolo Bonzini (s->pack_f2 << 13) | 1146d2c0bd84SPaolo Bonzini ((s->data_type_f2 >> 1) << 11) | 1147d2c0bd84SPaolo Bonzini (s->brust_f1 << 7) | 1148d2c0bd84SPaolo Bonzini (s->pack_f1 << 6) | 1149d2c0bd84SPaolo Bonzini ((s->data_type_f1 >> 1) << 0); 1150d2c0bd84SPaolo Bonzini break; 1151d2c0bd84SPaolo Bonzini 1152d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1153d2c0bd84SPaolo Bonzini *ret = (s->mode_f2 << 14) | 1154d2c0bd84SPaolo Bonzini (s->mode_f1 << 12) | 1155d2c0bd84SPaolo Bonzini (s->end_prog << 11) | 1156d2c0bd84SPaolo Bonzini (s->omap_3_1_compatible_disable << 10) | 1157d2c0bd84SPaolo Bonzini (s->repeat << 9) | 1158d2c0bd84SPaolo Bonzini (s->auto_init << 8) | 1159d2c0bd84SPaolo Bonzini (s->running << 7) | 1160d2c0bd84SPaolo Bonzini (s->priority << 6) | 1161d2c0bd84SPaolo Bonzini (s->bs << 4); 1162d2c0bd84SPaolo Bonzini break; 1163d2c0bd84SPaolo Bonzini 1164d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1165d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1166d2c0bd84SPaolo Bonzini *ret = (s->dst << 8) | 1167d2c0bd84SPaolo Bonzini ((s->src & 0x6) << 5) | 1168d2c0bd84SPaolo Bonzini (s->condition << 3) | 1169d2c0bd84SPaolo Bonzini (s->interrupts << 1) | 1170d2c0bd84SPaolo Bonzini s->dual; 1171d2c0bd84SPaolo Bonzini break; 1172d2c0bd84SPaolo Bonzini 1173d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1174d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1175d2c0bd84SPaolo Bonzini break; 1176d2c0bd84SPaolo Bonzini 1177d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1178d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1179d2c0bd84SPaolo Bonzini break; 1180d2c0bd84SPaolo Bonzini 1181d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1182d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1183d2c0bd84SPaolo Bonzini break; 1184d2c0bd84SPaolo Bonzini 1185d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1186d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1187d2c0bd84SPaolo Bonzini break; 1188d2c0bd84SPaolo Bonzini 1189d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1190d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1191d2c0bd84SPaolo Bonzini break; 1192d2c0bd84SPaolo Bonzini 1193d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1194d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1195d2c0bd84SPaolo Bonzini break; 1196d2c0bd84SPaolo Bonzini 1197d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1198d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1199d2c0bd84SPaolo Bonzini break; 1200d2c0bd84SPaolo Bonzini 1201d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1202d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1203d2c0bd84SPaolo Bonzini break; 1204d2c0bd84SPaolo Bonzini 1205d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1206d2c0bd84SPaolo Bonzini *ret = s->element_index_f1; 1207d2c0bd84SPaolo Bonzini break; 1208d2c0bd84SPaolo Bonzini 1209d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1210d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 & 0xffff; 1211d2c0bd84SPaolo Bonzini break; 1212d2c0bd84SPaolo Bonzini 1213d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1214d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 >> 16; 1215d2c0bd84SPaolo Bonzini break; 1216d2c0bd84SPaolo Bonzini 1217d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1218d2c0bd84SPaolo Bonzini *ret = s->element_index_f2; 1219d2c0bd84SPaolo Bonzini break; 1220d2c0bd84SPaolo Bonzini 1221d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1222d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 & 0xffff; 1223d2c0bd84SPaolo Bonzini break; 1224d2c0bd84SPaolo Bonzini 1225d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1226d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 >> 16; 1227d2c0bd84SPaolo Bonzini break; 1228d2c0bd84SPaolo Bonzini 1229d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1230d2c0bd84SPaolo Bonzini *ret = s->elements_f1; 1231d2c0bd84SPaolo Bonzini break; 1232d2c0bd84SPaolo Bonzini 1233d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1234d2c0bd84SPaolo Bonzini *ret = s->frames_f1; 1235d2c0bd84SPaolo Bonzini break; 1236d2c0bd84SPaolo Bonzini 1237d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1238d2c0bd84SPaolo Bonzini *ret = s->elements_f2; 1239d2c0bd84SPaolo Bonzini break; 1240d2c0bd84SPaolo Bonzini 1241d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1242d2c0bd84SPaolo Bonzini *ret = s->frames_f2; 1243d2c0bd84SPaolo Bonzini break; 1244d2c0bd84SPaolo Bonzini 1245d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1246d2c0bd84SPaolo Bonzini *ret = s->lch_type; 1247d2c0bd84SPaolo Bonzini break; 1248d2c0bd84SPaolo Bonzini 1249d2c0bd84SPaolo Bonzini default: 1250d2c0bd84SPaolo Bonzini return 1; 1251d2c0bd84SPaolo Bonzini } 1252d2c0bd84SPaolo Bonzini return 0; 1253d2c0bd84SPaolo Bonzini } 1254d2c0bd84SPaolo Bonzini 1255d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1256d2c0bd84SPaolo Bonzini uint16_t value) 1257d2c0bd84SPaolo Bonzini { 1258d2c0bd84SPaolo Bonzini switch (offset) { 1259d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1260d2c0bd84SPaolo Bonzini s->src = (value & 0x40) ? imif : emiff; 1261d2c0bd84SPaolo Bonzini s->condition = 0; 1262d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1263d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1264d2c0bd84SPaolo Bonzini s->dual = value & 1; 1265d2c0bd84SPaolo Bonzini break; 1266d2c0bd84SPaolo Bonzini 1267d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1268d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1269d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1270d2c0bd84SPaolo Bonzini break; 1271d2c0bd84SPaolo Bonzini 1272d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1273d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 12742a41c928SPeter Maydell s->src_f1_top |= (uint32_t)value << 16; 1275d2c0bd84SPaolo Bonzini break; 1276d2c0bd84SPaolo Bonzini 1277d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1278d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1279d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1280d2c0bd84SPaolo Bonzini break; 1281d2c0bd84SPaolo Bonzini 1282d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1283d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 12842a41c928SPeter Maydell s->src_f1_bottom |= (uint32_t)value << 16; 1285d2c0bd84SPaolo Bonzini break; 1286d2c0bd84SPaolo Bonzini 1287d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1288d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1289d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1290d2c0bd84SPaolo Bonzini break; 1291d2c0bd84SPaolo Bonzini 1292d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1293d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 12942a41c928SPeter Maydell s->src_f2_top |= (uint32_t)value << 16; 1295d2c0bd84SPaolo Bonzini break; 1296d2c0bd84SPaolo Bonzini 1297d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1298d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1299d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1300d2c0bd84SPaolo Bonzini break; 1301d2c0bd84SPaolo Bonzini 1302d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1303d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 13042a41c928SPeter Maydell s->src_f2_bottom |= (uint32_t)value << 16; 1305d2c0bd84SPaolo Bonzini break; 1306d2c0bd84SPaolo Bonzini 1307d2c0bd84SPaolo Bonzini default: 1308d2c0bd84SPaolo Bonzini return 1; 1309d2c0bd84SPaolo Bonzini } 1310d2c0bd84SPaolo Bonzini return 0; 1311d2c0bd84SPaolo Bonzini } 1312d2c0bd84SPaolo Bonzini 1313d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1314d2c0bd84SPaolo Bonzini uint16_t *ret) 1315d2c0bd84SPaolo Bonzini { 1316d2c0bd84SPaolo Bonzini int i; 1317d2c0bd84SPaolo Bonzini 1318d2c0bd84SPaolo Bonzini switch (offset) { 1319d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1320d2c0bd84SPaolo Bonzini i = s->condition; 1321d2c0bd84SPaolo Bonzini s->condition = 0; 1322d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1323d2c0bd84SPaolo Bonzini *ret = ((s->src == imif) << 6) | (i << 3) | 1324d2c0bd84SPaolo Bonzini (s->interrupts << 1) | s->dual; 1325d2c0bd84SPaolo Bonzini break; 1326d2c0bd84SPaolo Bonzini 1327d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1328d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1329d2c0bd84SPaolo Bonzini break; 1330d2c0bd84SPaolo Bonzini 1331d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1332d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1333d2c0bd84SPaolo Bonzini break; 1334d2c0bd84SPaolo Bonzini 1335d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1336d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1337d2c0bd84SPaolo Bonzini break; 1338d2c0bd84SPaolo Bonzini 1339d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1340d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1341d2c0bd84SPaolo Bonzini break; 1342d2c0bd84SPaolo Bonzini 1343d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1344d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1345d2c0bd84SPaolo Bonzini break; 1346d2c0bd84SPaolo Bonzini 1347d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1348d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1349d2c0bd84SPaolo Bonzini break; 1350d2c0bd84SPaolo Bonzini 1351d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1352d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1353d2c0bd84SPaolo Bonzini break; 1354d2c0bd84SPaolo Bonzini 1355d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1356d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1357d2c0bd84SPaolo Bonzini break; 1358d2c0bd84SPaolo Bonzini 1359d2c0bd84SPaolo Bonzini default: 1360d2c0bd84SPaolo Bonzini return 1; 1361d2c0bd84SPaolo Bonzini } 1362d2c0bd84SPaolo Bonzini return 0; 1363d2c0bd84SPaolo Bonzini } 1364d2c0bd84SPaolo Bonzini 1365d2c0bd84SPaolo Bonzini static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) 1366d2c0bd84SPaolo Bonzini { 1367d2c0bd84SPaolo Bonzini switch (offset) { 1368d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1369d2c0bd84SPaolo Bonzini s->gcr = value; 1370d2c0bd84SPaolo Bonzini break; 1371d2c0bd84SPaolo Bonzini 1372d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1373d2c0bd84SPaolo Bonzini if (value & 0x8) 1374d2c0bd84SPaolo Bonzini omap_dma_disable_3_1_mapping(s); 1375d2c0bd84SPaolo Bonzini else 1376d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 1377d2c0bd84SPaolo Bonzini break; 1378d2c0bd84SPaolo Bonzini 1379d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1380d2c0bd84SPaolo Bonzini if (value & 0x1) 1381d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1382d2c0bd84SPaolo Bonzini break; 1383d2c0bd84SPaolo Bonzini 1384d2c0bd84SPaolo Bonzini default: 1385d2c0bd84SPaolo Bonzini return 1; 1386d2c0bd84SPaolo Bonzini } 1387d2c0bd84SPaolo Bonzini return 0; 1388d2c0bd84SPaolo Bonzini } 1389d2c0bd84SPaolo Bonzini 1390d2c0bd84SPaolo Bonzini static int omap_dma_sys_read(struct omap_dma_s *s, int offset, 1391d2c0bd84SPaolo Bonzini uint16_t *ret) 1392d2c0bd84SPaolo Bonzini { 1393d2c0bd84SPaolo Bonzini switch (offset) { 1394d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1395d2c0bd84SPaolo Bonzini *ret = s->gcr; 1396d2c0bd84SPaolo Bonzini break; 1397d2c0bd84SPaolo Bonzini 1398d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1399d2c0bd84SPaolo Bonzini *ret = s->omap_3_1_mapping_disabled << 3; 1400d2c0bd84SPaolo Bonzini break; 1401d2c0bd84SPaolo Bonzini 1402d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1403d2c0bd84SPaolo Bonzini *ret = 0; 1404d2c0bd84SPaolo Bonzini break; 1405d2c0bd84SPaolo Bonzini 1406d2c0bd84SPaolo Bonzini case 0x442: /* DMA_HW_ID */ 1407d2c0bd84SPaolo Bonzini case 0x444: /* DMA_PCh2_ID */ 1408d2c0bd84SPaolo Bonzini case 0x446: /* DMA_PCh0_ID */ 1409d2c0bd84SPaolo Bonzini case 0x448: /* DMA_PCh1_ID */ 1410d2c0bd84SPaolo Bonzini case 0x44a: /* DMA_PChG_ID */ 1411d2c0bd84SPaolo Bonzini case 0x44c: /* DMA_PChD_ID */ 1412d2c0bd84SPaolo Bonzini *ret = 1; 1413d2c0bd84SPaolo Bonzini break; 1414d2c0bd84SPaolo Bonzini 1415d2c0bd84SPaolo Bonzini case 0x44e: /* DMA_CAPS_0_U */ 1416d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 16) & 0xffff; 1417d2c0bd84SPaolo Bonzini break; 1418d2c0bd84SPaolo Bonzini case 0x450: /* DMA_CAPS_0_L */ 1419d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 0) & 0xffff; 1420d2c0bd84SPaolo Bonzini break; 1421d2c0bd84SPaolo Bonzini 1422d2c0bd84SPaolo Bonzini case 0x452: /* DMA_CAPS_1_U */ 1423d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 16) & 0xffff; 1424d2c0bd84SPaolo Bonzini break; 1425d2c0bd84SPaolo Bonzini case 0x454: /* DMA_CAPS_1_L */ 1426d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 0) & 0xffff; 1427d2c0bd84SPaolo Bonzini break; 1428d2c0bd84SPaolo Bonzini 1429d2c0bd84SPaolo Bonzini case 0x456: /* DMA_CAPS_2 */ 1430d2c0bd84SPaolo Bonzini *ret = s->caps[2]; 1431d2c0bd84SPaolo Bonzini break; 1432d2c0bd84SPaolo Bonzini 1433d2c0bd84SPaolo Bonzini case 0x458: /* DMA_CAPS_3 */ 1434d2c0bd84SPaolo Bonzini *ret = s->caps[3]; 1435d2c0bd84SPaolo Bonzini break; 1436d2c0bd84SPaolo Bonzini 1437d2c0bd84SPaolo Bonzini case 0x45a: /* DMA_CAPS_4 */ 1438d2c0bd84SPaolo Bonzini *ret = s->caps[4]; 1439d2c0bd84SPaolo Bonzini break; 1440d2c0bd84SPaolo Bonzini 1441d2c0bd84SPaolo Bonzini case 0x460: /* DMA_PCh2_SR */ 1442d2c0bd84SPaolo Bonzini case 0x480: /* DMA_PCh0_SR */ 1443d2c0bd84SPaolo Bonzini case 0x482: /* DMA_PCh1_SR */ 1444d2c0bd84SPaolo Bonzini case 0x4c0: /* DMA_PChD_SR_0 */ 1445f3724bf5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, 1446f3724bf5SPhilippe Mathieu-Daudé "%s: Physical Channel Status Registers not implemented\n", 1447a89f364aSAlistair Francis __func__); 1448d2c0bd84SPaolo Bonzini *ret = 0xff; 1449d2c0bd84SPaolo Bonzini break; 1450d2c0bd84SPaolo Bonzini 1451d2c0bd84SPaolo Bonzini default: 1452d2c0bd84SPaolo Bonzini return 1; 1453d2c0bd84SPaolo Bonzini } 1454d2c0bd84SPaolo Bonzini return 0; 1455d2c0bd84SPaolo Bonzini } 1456d2c0bd84SPaolo Bonzini 1457*a75ed3c4SPhilippe Mathieu-Daudé static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size) 1458d2c0bd84SPaolo Bonzini { 1459*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1460d2c0bd84SPaolo Bonzini int reg, ch; 1461d2c0bd84SPaolo Bonzini uint16_t ret; 1462d2c0bd84SPaolo Bonzini 1463d2c0bd84SPaolo Bonzini if (size != 2) { 1464d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1465d2c0bd84SPaolo Bonzini } 1466d2c0bd84SPaolo Bonzini 1467d2c0bd84SPaolo Bonzini switch (addr) { 1468d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1469d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1470d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) 1471d2c0bd84SPaolo Bonzini break; 1472d2c0bd84SPaolo Bonzini return ret; 1473d2c0bd84SPaolo Bonzini } 1474d2c0bd84SPaolo Bonzini /* Fall through. */ 1475d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1476d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1477d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1478d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) 1479d2c0bd84SPaolo Bonzini break; 1480d2c0bd84SPaolo Bonzini return ret; 1481d2c0bd84SPaolo Bonzini 1482d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1483d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1484d2c0bd84SPaolo Bonzini break; 1485d2c0bd84SPaolo Bonzini /* Fall through. */ 1486d2c0bd84SPaolo Bonzini case 0x400: 1487d2c0bd84SPaolo Bonzini if (omap_dma_sys_read(s, addr, &ret)) 1488d2c0bd84SPaolo Bonzini break; 1489d2c0bd84SPaolo Bonzini return ret; 1490d2c0bd84SPaolo Bonzini 1491d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1492d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1493d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret)) 1494d2c0bd84SPaolo Bonzini break; 1495d2c0bd84SPaolo Bonzini return ret; 1496d2c0bd84SPaolo Bonzini } 1497d2c0bd84SPaolo Bonzini break; 1498d2c0bd84SPaolo Bonzini } 1499d2c0bd84SPaolo Bonzini 1500d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1501d2c0bd84SPaolo Bonzini return 0; 1502d2c0bd84SPaolo Bonzini } 1503d2c0bd84SPaolo Bonzini 1504d2c0bd84SPaolo Bonzini static void omap_dma_write(void *opaque, hwaddr addr, 1505d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1506d2c0bd84SPaolo Bonzini { 1507*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1508d2c0bd84SPaolo Bonzini int reg, ch; 1509d2c0bd84SPaolo Bonzini 1510d2c0bd84SPaolo Bonzini if (size != 2) { 151177a8257eSStefan Weil omap_badwidth_write16(opaque, addr, value); 151277a8257eSStefan Weil return; 1513d2c0bd84SPaolo Bonzini } 1514d2c0bd84SPaolo Bonzini 1515d2c0bd84SPaolo Bonzini switch (addr) { 1516d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1517d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1518d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) 1519d2c0bd84SPaolo Bonzini break; 1520d2c0bd84SPaolo Bonzini return; 1521d2c0bd84SPaolo Bonzini } 1522d2c0bd84SPaolo Bonzini /* Fall through. */ 1523d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1524d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1525d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1526d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) 1527d2c0bd84SPaolo Bonzini break; 1528d2c0bd84SPaolo Bonzini return; 1529d2c0bd84SPaolo Bonzini 1530d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1531d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1532d2c0bd84SPaolo Bonzini break; 153345a9eaceSPhilippe Mathieu-Daudé /* fall through */ 1534d2c0bd84SPaolo Bonzini case 0x400: 1535d2c0bd84SPaolo Bonzini if (omap_dma_sys_write(s, addr, value)) 1536d2c0bd84SPaolo Bonzini break; 1537d2c0bd84SPaolo Bonzini return; 1538d2c0bd84SPaolo Bonzini 1539d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1540d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1541d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value)) 1542d2c0bd84SPaolo Bonzini break; 1543d2c0bd84SPaolo Bonzini return; 1544d2c0bd84SPaolo Bonzini } 1545d2c0bd84SPaolo Bonzini break; 1546d2c0bd84SPaolo Bonzini } 1547d2c0bd84SPaolo Bonzini 1548d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1549d2c0bd84SPaolo Bonzini } 1550d2c0bd84SPaolo Bonzini 1551d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma_ops = { 1552d2c0bd84SPaolo Bonzini .read = omap_dma_read, 1553d2c0bd84SPaolo Bonzini .write = omap_dma_write, 1554d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1555d2c0bd84SPaolo Bonzini }; 1556d2c0bd84SPaolo Bonzini 1557d2c0bd84SPaolo Bonzini static void omap_dma_request(void *opaque, int drq, int req) 1558d2c0bd84SPaolo Bonzini { 1559*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1560d2c0bd84SPaolo Bonzini /* The request pins are level triggered in QEMU. */ 1561d2c0bd84SPaolo Bonzini if (req) { 156276486736SPeter Maydell if (~s->dma->drqbmp & (1ULL << drq)) { 156376486736SPeter Maydell s->dma->drqbmp |= 1ULL << drq; 1564d2c0bd84SPaolo Bonzini omap_dma_process_request(s, drq); 1565d2c0bd84SPaolo Bonzini } 1566d2c0bd84SPaolo Bonzini } else 156776486736SPeter Maydell s->dma->drqbmp &= ~(1ULL << drq); 1568d2c0bd84SPaolo Bonzini } 1569d2c0bd84SPaolo Bonzini 1570d2c0bd84SPaolo Bonzini /* XXX: this won't be needed once soc_dma knows about clocks. */ 1571d2c0bd84SPaolo Bonzini static void omap_dma_clk_update(void *opaque, int line, int on) 1572d2c0bd84SPaolo Bonzini { 1573*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1574d2c0bd84SPaolo Bonzini int i; 1575d2c0bd84SPaolo Bonzini 1576d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(s->clk); 1577d2c0bd84SPaolo Bonzini 1578d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) 1579d2c0bd84SPaolo Bonzini if (s->ch[i].active) 1580d2c0bd84SPaolo Bonzini soc_dma_set_request(s->ch[i].dma, on); 1581d2c0bd84SPaolo Bonzini } 1582d2c0bd84SPaolo Bonzini 1583d2c0bd84SPaolo Bonzini static void omap_dma_setcaps(struct omap_dma_s *s) 1584d2c0bd84SPaolo Bonzini { 1585d2c0bd84SPaolo Bonzini switch (s->model) { 1586d2c0bd84SPaolo Bonzini default: 1587d2c0bd84SPaolo Bonzini case omap_dma_3_1: 1588d2c0bd84SPaolo Bonzini break; 1589d2c0bd84SPaolo Bonzini case omap_dma_3_2: 1590d2c0bd84SPaolo Bonzini case omap_dma_4: 1591d2c0bd84SPaolo Bonzini /* XXX Only available for sDMA */ 1592d2c0bd84SPaolo Bonzini s->caps[0] = 1593d2c0bd84SPaolo Bonzini (1 << 19) | /* Constant Fill Capability */ 1594d2c0bd84SPaolo Bonzini (1 << 18); /* Transparent BLT Capability */ 1595d2c0bd84SPaolo Bonzini s->caps[1] = 1596d2c0bd84SPaolo Bonzini (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ 1597d2c0bd84SPaolo Bonzini s->caps[2] = 1598d2c0bd84SPaolo Bonzini (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ 1599d2c0bd84SPaolo Bonzini (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ 1600d2c0bd84SPaolo Bonzini (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ 1601d2c0bd84SPaolo Bonzini (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ 1602d2c0bd84SPaolo Bonzini (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ 1603d2c0bd84SPaolo Bonzini (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ 1604d2c0bd84SPaolo Bonzini (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ 1605d2c0bd84SPaolo Bonzini (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ 1606d2c0bd84SPaolo Bonzini (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ 1607d2c0bd84SPaolo Bonzini s->caps[3] = 1608d2c0bd84SPaolo Bonzini (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ 1609d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ 1610d2c0bd84SPaolo Bonzini (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ 1611d2c0bd84SPaolo Bonzini (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ 1612d2c0bd84SPaolo Bonzini (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ 1613d2c0bd84SPaolo Bonzini (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ 1614d2c0bd84SPaolo Bonzini (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ 1615d2c0bd84SPaolo Bonzini (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ 1616d2c0bd84SPaolo Bonzini s->caps[4] = 1617d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ 1618d2c0bd84SPaolo Bonzini (1 << 6) | /* SYNC_STATUS_CPBLTY */ 1619d2c0bd84SPaolo Bonzini (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ 1620d2c0bd84SPaolo Bonzini (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ 1621d2c0bd84SPaolo Bonzini (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ 1622d2c0bd84SPaolo Bonzini (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ 1623d2c0bd84SPaolo Bonzini (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ 1624d2c0bd84SPaolo Bonzini (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ 1625d2c0bd84SPaolo Bonzini break; 1626d2c0bd84SPaolo Bonzini } 1627d2c0bd84SPaolo Bonzini } 1628d2c0bd84SPaolo Bonzini 1629d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 1630d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 1631d2c0bd84SPaolo Bonzini qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 1632d2c0bd84SPaolo Bonzini enum omap_dma_model model) 1633d2c0bd84SPaolo Bonzini { 1634d2c0bd84SPaolo Bonzini int num_irqs, memsize, i; 1635b45c03f5SMarkus Armbruster struct omap_dma_s *s = g_new0(struct omap_dma_s, 1); 1636d2c0bd84SPaolo Bonzini 1637d2c0bd84SPaolo Bonzini if (model <= omap_dma_3_1) { 1638d2c0bd84SPaolo Bonzini num_irqs = 6; 1639d2c0bd84SPaolo Bonzini memsize = 0x800; 1640d2c0bd84SPaolo Bonzini } else { 1641d2c0bd84SPaolo Bonzini num_irqs = 16; 1642d2c0bd84SPaolo Bonzini memsize = 0xc00; 1643d2c0bd84SPaolo Bonzini } 1644d2c0bd84SPaolo Bonzini s->model = model; 1645d2c0bd84SPaolo Bonzini s->mpu = mpu; 1646d2c0bd84SPaolo Bonzini s->clk = clk; 1647d2c0bd84SPaolo Bonzini s->lcd_ch.irq = lcd_irq; 1648d2c0bd84SPaolo Bonzini s->lcd_ch.mpu = mpu; 1649d2c0bd84SPaolo Bonzini 1650d2c0bd84SPaolo Bonzini s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); 1651d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(clk); 1652d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 1653d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 1654d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32); 1655d2c0bd84SPaolo Bonzini s->dma->opaque = s; 1656d2c0bd84SPaolo Bonzini 1657d2c0bd84SPaolo Bonzini while (num_irqs --) 1658d2c0bd84SPaolo Bonzini s->ch[num_irqs].irq = irqs[num_irqs]; 1659d2c0bd84SPaolo Bonzini for (i = 0; i < 3; i ++) { 1660d2c0bd84SPaolo Bonzini s->ch[i].sibling = &s->ch[i + 6]; 1661d2c0bd84SPaolo Bonzini s->ch[i + 6].sibling = &s->ch[i]; 1662d2c0bd84SPaolo Bonzini } 1663d2c0bd84SPaolo Bonzini for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { 1664d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 1665d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 1666d2c0bd84SPaolo Bonzini } 1667d2c0bd84SPaolo Bonzini 1668d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 1669f3c7d038SAndreas Färber omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0)); 1670d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1671d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, 1); 1672d2c0bd84SPaolo Bonzini 16732c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize); 1674d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 1675d2c0bd84SPaolo Bonzini 1676d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 1677d2c0bd84SPaolo Bonzini 1678d2c0bd84SPaolo Bonzini return s->dma; 1679d2c0bd84SPaolo Bonzini } 1680d2c0bd84SPaolo Bonzini 1681d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_4_update(struct omap_dma_s *s) 1682d2c0bd84SPaolo Bonzini { 1683d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 1684d2c0bd84SPaolo Bonzini uint32_t bmp, bit; 1685d2c0bd84SPaolo Bonzini 1686d2c0bd84SPaolo Bonzini for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) 1687d2c0bd84SPaolo Bonzini if (ch->status) { 1688d2c0bd84SPaolo Bonzini bmp |= bit; 1689d2c0bd84SPaolo Bonzini ch->cstatus |= ch->status; 1690d2c0bd84SPaolo Bonzini ch->status = 0; 1691d2c0bd84SPaolo Bonzini } 1692d2c0bd84SPaolo Bonzini if ((s->irqstat[0] |= s->irqen[0] & bmp)) 1693d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[0]); 1694d2c0bd84SPaolo Bonzini if ((s->irqstat[1] |= s->irqen[1] & bmp)) 1695d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[1]); 1696d2c0bd84SPaolo Bonzini if ((s->irqstat[2] |= s->irqen[2] & bmp)) 1697d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[2]); 1698d2c0bd84SPaolo Bonzini if ((s->irqstat[3] |= s->irqen[3] & bmp)) 1699d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[3]); 1700d2c0bd84SPaolo Bonzini } 1701d2c0bd84SPaolo Bonzini 1702d2c0bd84SPaolo Bonzini static uint64_t omap_dma4_read(void *opaque, hwaddr addr, 1703d2c0bd84SPaolo Bonzini unsigned size) 1704d2c0bd84SPaolo Bonzini { 1705*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1706d2c0bd84SPaolo Bonzini int irqn = 0, chnum; 1707d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1708d2c0bd84SPaolo Bonzini 1709d2c0bd84SPaolo Bonzini if (size == 1) { 1710d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1711d2c0bd84SPaolo Bonzini } 1712d2c0bd84SPaolo Bonzini 1713d2c0bd84SPaolo Bonzini switch (addr) { 1714d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1715d2c0bd84SPaolo Bonzini return 0x40; 1716d2c0bd84SPaolo Bonzini 1717d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1718d2c0bd84SPaolo Bonzini irqn ++; 1719d2c0bd84SPaolo Bonzini /* fall through */ 1720d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1721d2c0bd84SPaolo Bonzini irqn ++; 1722d2c0bd84SPaolo Bonzini /* fall through */ 1723d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1724d2c0bd84SPaolo Bonzini irqn ++; 1725d2c0bd84SPaolo Bonzini /* fall through */ 1726d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1727d2c0bd84SPaolo Bonzini return s->irqstat[irqn]; 1728d2c0bd84SPaolo Bonzini 1729d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1730d2c0bd84SPaolo Bonzini irqn ++; 1731d2c0bd84SPaolo Bonzini /* fall through */ 1732d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1733d2c0bd84SPaolo Bonzini irqn ++; 1734d2c0bd84SPaolo Bonzini /* fall through */ 1735d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1736d2c0bd84SPaolo Bonzini irqn ++; 1737d2c0bd84SPaolo Bonzini /* fall through */ 1738d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1739d2c0bd84SPaolo Bonzini return s->irqen[irqn]; 1740d2c0bd84SPaolo Bonzini 1741d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1742d2c0bd84SPaolo Bonzini return 1; /* RESETDONE */ 1743d2c0bd84SPaolo Bonzini 1744d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1745d2c0bd84SPaolo Bonzini return s->ocp; 1746d2c0bd84SPaolo Bonzini 1747d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1748d2c0bd84SPaolo Bonzini return s->caps[0]; 1749d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1750d2c0bd84SPaolo Bonzini return s->caps[2]; 1751d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1752d2c0bd84SPaolo Bonzini return s->caps[3]; 1753d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1754d2c0bd84SPaolo Bonzini return s->caps[4]; 1755d2c0bd84SPaolo Bonzini 1756d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1757d2c0bd84SPaolo Bonzini return s->gcr; 1758d2c0bd84SPaolo Bonzini 1759d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1760d2c0bd84SPaolo Bonzini addr -= 0x80; 1761d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1762d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1763d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1764d2c0bd84SPaolo Bonzini break; 1765d2c0bd84SPaolo Bonzini 1766d2c0bd84SPaolo Bonzini default: 1767d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1768d2c0bd84SPaolo Bonzini return 0; 1769d2c0bd84SPaolo Bonzini } 1770d2c0bd84SPaolo Bonzini 1771d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1772d2c0bd84SPaolo Bonzini switch (addr) { 1773d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1774d2c0bd84SPaolo Bonzini return (ch->buf_disable << 25) | 1775d2c0bd84SPaolo Bonzini (ch->src_sync << 24) | 1776d2c0bd84SPaolo Bonzini (ch->prefetch << 23) | 1777d2c0bd84SPaolo Bonzini ((ch->sync & 0x60) << 14) | 1778d2c0bd84SPaolo Bonzini (ch->bs << 18) | 1779d2c0bd84SPaolo Bonzini (ch->transparent_copy << 17) | 1780d2c0bd84SPaolo Bonzini (ch->constant_fill << 16) | 1781d2c0bd84SPaolo Bonzini (ch->mode[1] << 14) | 1782d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 1783d2c0bd84SPaolo Bonzini (0 << 10) | (0 << 9) | 1784d2c0bd84SPaolo Bonzini (ch->suspend << 8) | 1785d2c0bd84SPaolo Bonzini (ch->enable << 7) | 1786d2c0bd84SPaolo Bonzini (ch->priority << 6) | 1787d2c0bd84SPaolo Bonzini (ch->fs << 5) | (ch->sync & 0x1f); 1788d2c0bd84SPaolo Bonzini 1789d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1790d2c0bd84SPaolo Bonzini return (ch->link_enabled << 15) | ch->link_next_ch; 1791d2c0bd84SPaolo Bonzini 1792d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1793d2c0bd84SPaolo Bonzini return ch->interrupts; 1794d2c0bd84SPaolo Bonzini 1795d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1796d2c0bd84SPaolo Bonzini return ch->cstatus; 1797d2c0bd84SPaolo Bonzini 1798d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1799d2c0bd84SPaolo Bonzini return (ch->endian[0] << 21) | 1800d2c0bd84SPaolo Bonzini (ch->endian_lock[0] << 20) | 1801d2c0bd84SPaolo Bonzini (ch->endian[1] << 19) | 1802d2c0bd84SPaolo Bonzini (ch->endian_lock[1] << 18) | 1803d2c0bd84SPaolo Bonzini (ch->write_mode << 16) | 1804d2c0bd84SPaolo Bonzini (ch->burst[1] << 14) | 1805d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 1806d2c0bd84SPaolo Bonzini (ch->translate[1] << 9) | 1807d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 1808d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 1809d2c0bd84SPaolo Bonzini (ch->translate[0] << 2) | 1810d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 1811d2c0bd84SPaolo Bonzini 1812d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 1813d2c0bd84SPaolo Bonzini return ch->elements; 1814d2c0bd84SPaolo Bonzini 1815d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 1816d2c0bd84SPaolo Bonzini return ch->frames; 1817d2c0bd84SPaolo Bonzini 1818d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 1819d2c0bd84SPaolo Bonzini return ch->addr[0]; 1820d2c0bd84SPaolo Bonzini 1821d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 1822d2c0bd84SPaolo Bonzini return ch->addr[1]; 1823d2c0bd84SPaolo Bonzini 1824d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 1825d2c0bd84SPaolo Bonzini return ch->element_index[0]; 1826d2c0bd84SPaolo Bonzini 1827d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 1828d2c0bd84SPaolo Bonzini return ch->frame_index[0]; 1829d2c0bd84SPaolo Bonzini 1830d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 1831d2c0bd84SPaolo Bonzini return ch->element_index[1]; 1832d2c0bd84SPaolo Bonzini 1833d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 1834d2c0bd84SPaolo Bonzini return ch->frame_index[1]; 1835d2c0bd84SPaolo Bonzini 1836d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 1837d2c0bd84SPaolo Bonzini return ch->active_set.src & 0xffff; 1838d2c0bd84SPaolo Bonzini 1839d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 1840d2c0bd84SPaolo Bonzini return ch->active_set.dest & 0xffff; 1841d2c0bd84SPaolo Bonzini 1842d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 1843d2c0bd84SPaolo Bonzini return ch->active_set.element; 1844d2c0bd84SPaolo Bonzini 1845d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 1846d2c0bd84SPaolo Bonzini return ch->active_set.frame; 1847d2c0bd84SPaolo Bonzini 1848d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 1849d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 1850d2c0bd84SPaolo Bonzini return ch->color; 1851d2c0bd84SPaolo Bonzini 1852d2c0bd84SPaolo Bonzini default: 1853d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1854d2c0bd84SPaolo Bonzini return 0; 1855d2c0bd84SPaolo Bonzini } 1856d2c0bd84SPaolo Bonzini } 1857d2c0bd84SPaolo Bonzini 1858d2c0bd84SPaolo Bonzini static void omap_dma4_write(void *opaque, hwaddr addr, 1859d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1860d2c0bd84SPaolo Bonzini { 1861*a75ed3c4SPhilippe Mathieu-Daudé struct omap_dma_s *s = opaque; 1862d2c0bd84SPaolo Bonzini int chnum, irqn = 0; 1863d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1864d2c0bd84SPaolo Bonzini 1865d2c0bd84SPaolo Bonzini if (size == 1) { 186677a8257eSStefan Weil omap_badwidth_write16(opaque, addr, value); 186777a8257eSStefan Weil return; 1868d2c0bd84SPaolo Bonzini } 1869d2c0bd84SPaolo Bonzini 1870d2c0bd84SPaolo Bonzini switch (addr) { 1871d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1872d2c0bd84SPaolo Bonzini irqn ++; 1873d2c0bd84SPaolo Bonzini /* fall through */ 1874d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1875d2c0bd84SPaolo Bonzini irqn ++; 1876d2c0bd84SPaolo Bonzini /* fall through */ 1877d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1878d2c0bd84SPaolo Bonzini irqn ++; 1879d2c0bd84SPaolo Bonzini /* fall through */ 1880d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1881d2c0bd84SPaolo Bonzini s->irqstat[irqn] &= ~value; 1882d2c0bd84SPaolo Bonzini if (!s->irqstat[irqn]) 1883d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq[irqn]); 1884d2c0bd84SPaolo Bonzini return; 1885d2c0bd84SPaolo Bonzini 1886d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1887d2c0bd84SPaolo Bonzini irqn ++; 1888d2c0bd84SPaolo Bonzini /* fall through */ 1889d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1890d2c0bd84SPaolo Bonzini irqn ++; 1891d2c0bd84SPaolo Bonzini /* fall through */ 1892d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1893d2c0bd84SPaolo Bonzini irqn ++; 1894d2c0bd84SPaolo Bonzini /* fall through */ 1895d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1896d2c0bd84SPaolo Bonzini s->irqen[irqn] = value; 1897d2c0bd84SPaolo Bonzini return; 1898d2c0bd84SPaolo Bonzini 1899d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1900d2c0bd84SPaolo Bonzini if (value & 2) /* SOFTRESET */ 1901d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1902d2c0bd84SPaolo Bonzini s->ocp = value & 0x3321; 1903e26745d5SPhilippe Mathieu-Daudé if (((s->ocp >> 12) & 3) == 3) { /* MIDLEMODE */ 1904e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n", 1905e26745d5SPhilippe Mathieu-Daudé __func__); 1906e26745d5SPhilippe Mathieu-Daudé } 1907d2c0bd84SPaolo Bonzini return; 1908d2c0bd84SPaolo Bonzini 1909d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1910d2c0bd84SPaolo Bonzini s->gcr = value & 0x00ff00ff; 1911e26745d5SPhilippe Mathieu-Daudé if ((value & 0xff) == 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */ 1912e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n", 1913e26745d5SPhilippe Mathieu-Daudé __func__); 1914e26745d5SPhilippe Mathieu-Daudé } 1915d2c0bd84SPaolo Bonzini return; 1916d2c0bd84SPaolo Bonzini 1917d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1918d2c0bd84SPaolo Bonzini addr -= 0x80; 1919d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1920d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1921d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1922d2c0bd84SPaolo Bonzini break; 1923d2c0bd84SPaolo Bonzini 1924d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1925d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1926d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1927d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1928d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1929d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1930d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 1931d2c0bd84SPaolo Bonzini return; 1932d2c0bd84SPaolo Bonzini 1933d2c0bd84SPaolo Bonzini default: 1934d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1935d2c0bd84SPaolo Bonzini return; 1936d2c0bd84SPaolo Bonzini } 1937d2c0bd84SPaolo Bonzini 1938d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1939d2c0bd84SPaolo Bonzini switch (addr) { 1940d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1941d2c0bd84SPaolo Bonzini ch->buf_disable = (value >> 25) & 1; 1942d2c0bd84SPaolo Bonzini ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ 1943e26745d5SPhilippe Mathieu-Daudé if (ch->buf_disable && !ch->src_sync) { 1944e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 1945e26745d5SPhilippe Mathieu-Daudé "%s: Buffering disable is not allowed in " 1946a89f364aSAlistair Francis "destination synchronised mode\n", __func__); 1947e26745d5SPhilippe Mathieu-Daudé } 1948d2c0bd84SPaolo Bonzini ch->prefetch = (value >> 23) & 1; 1949d2c0bd84SPaolo Bonzini ch->bs = (value >> 18) & 1; 1950d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 17) & 1; 1951d2c0bd84SPaolo Bonzini ch->constant_fill = (value >> 16) & 1; 1952d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 1953d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 1954d2c0bd84SPaolo Bonzini ch->suspend = (value & 0x0100) >> 8; 1955d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 1956d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 1957e26745d5SPhilippe Mathieu-Daudé if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) { 1958e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 1959e26745d5SPhilippe Mathieu-Daudé "%s: For a packet transfer at least one port " 1960a89f364aSAlistair Francis "must be constant-addressed\n", __func__); 1961e26745d5SPhilippe Mathieu-Daudé } 1962d2c0bd84SPaolo Bonzini ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); 1963d2c0bd84SPaolo Bonzini /* XXX must be 0x01 for CamDMA */ 1964d2c0bd84SPaolo Bonzini 1965d2c0bd84SPaolo Bonzini if (value & 0x0080) 1966d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 1967d2c0bd84SPaolo Bonzini else 1968d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 1969d2c0bd84SPaolo Bonzini 1970d2c0bd84SPaolo Bonzini break; 1971d2c0bd84SPaolo Bonzini 1972d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1973d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 1974d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 1975d2c0bd84SPaolo Bonzini break; 1976d2c0bd84SPaolo Bonzini 1977d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1978d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x09be; 1979d2c0bd84SPaolo Bonzini break; 1980d2c0bd84SPaolo Bonzini 1981d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1982d2c0bd84SPaolo Bonzini ch->cstatus &= ~value; 1983d2c0bd84SPaolo Bonzini break; 1984d2c0bd84SPaolo Bonzini 1985d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1986d2c0bd84SPaolo Bonzini ch->endian[0] =(value >> 21) & 1; 1987d2c0bd84SPaolo Bonzini ch->endian_lock[0] =(value >> 20) & 1; 1988d2c0bd84SPaolo Bonzini ch->endian[1] =(value >> 19) & 1; 1989d2c0bd84SPaolo Bonzini ch->endian_lock[1] =(value >> 18) & 1; 1990e26745d5SPhilippe Mathieu-Daudé if (ch->endian[0] != ch->endian[1]) { 1991e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 1992e26745d5SPhilippe Mathieu-Daudé "%s: DMA endianness conversion enable attempt\n", 1993a89f364aSAlistair Francis __func__); 1994e26745d5SPhilippe Mathieu-Daudé } 1995d2c0bd84SPaolo Bonzini ch->write_mode = (value >> 16) & 3; 1996d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 1997d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 1998d2c0bd84SPaolo Bonzini ch->translate[1] = (value & 0x1e00) >> 9; 1999d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 2000d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 2001d2c0bd84SPaolo Bonzini ch->translate[0] = (value & 0x003c) >> 2; 2002e26745d5SPhilippe Mathieu-Daudé if (ch->translate[0] | ch->translate[1]) { 2003e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 2004e26745d5SPhilippe Mathieu-Daudé "%s: bad MReqAddressTranslate sideband signal\n", 2005a89f364aSAlistair Francis __func__); 2006e26745d5SPhilippe Mathieu-Daudé } 2007d2c0bd84SPaolo Bonzini ch->data_type = 1 << (value & 3); 2008146871c3SPrasad J Pandit if ((value & 3) == 3) { 2009e26745d5SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, 2010e26745d5SPhilippe Mathieu-Daudé "%s: bad data_type for DMA channel\n", __func__); 2011146871c3SPrasad J Pandit ch->data_type >>= 1; 2012146871c3SPrasad J Pandit } 2013d2c0bd84SPaolo Bonzini break; 2014d2c0bd84SPaolo Bonzini 2015d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 2016d2c0bd84SPaolo Bonzini ch->set_update = 1; 2017d2c0bd84SPaolo Bonzini ch->elements = value & 0xffffff; 2018d2c0bd84SPaolo Bonzini break; 2019d2c0bd84SPaolo Bonzini 2020d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 2021d2c0bd84SPaolo Bonzini ch->frames = value & 0xffff; 2022d2c0bd84SPaolo Bonzini ch->set_update = 1; 2023d2c0bd84SPaolo Bonzini break; 2024d2c0bd84SPaolo Bonzini 2025d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 2026d2c0bd84SPaolo Bonzini ch->addr[0] = (hwaddr) (uint32_t) value; 2027d2c0bd84SPaolo Bonzini ch->set_update = 1; 2028d2c0bd84SPaolo Bonzini break; 2029d2c0bd84SPaolo Bonzini 2030d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 2031d2c0bd84SPaolo Bonzini ch->addr[1] = (hwaddr) (uint32_t) value; 2032d2c0bd84SPaolo Bonzini ch->set_update = 1; 2033d2c0bd84SPaolo Bonzini break; 2034d2c0bd84SPaolo Bonzini 2035d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 2036d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 2037d2c0bd84SPaolo Bonzini ch->set_update = 1; 2038d2c0bd84SPaolo Bonzini break; 2039d2c0bd84SPaolo Bonzini 2040d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 2041d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int32_t) value; 2042d2c0bd84SPaolo Bonzini ch->set_update = 1; 2043d2c0bd84SPaolo Bonzini break; 2044d2c0bd84SPaolo Bonzini 2045d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 2046d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 2047d2c0bd84SPaolo Bonzini ch->set_update = 1; 2048d2c0bd84SPaolo Bonzini break; 2049d2c0bd84SPaolo Bonzini 2050d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 2051d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int32_t) value; 2052d2c0bd84SPaolo Bonzini ch->set_update = 1; 2053d2c0bd84SPaolo Bonzini break; 2054d2c0bd84SPaolo Bonzini 2055d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 2056d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 2057d2c0bd84SPaolo Bonzini ch->color = value; 2058d2c0bd84SPaolo Bonzini break; 2059d2c0bd84SPaolo Bonzini 2060d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 2061d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 2062d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 2063d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 2064d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 2065d2c0bd84SPaolo Bonzini break; 2066d2c0bd84SPaolo Bonzini 2067d2c0bd84SPaolo Bonzini default: 2068d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 2069d2c0bd84SPaolo Bonzini } 2070d2c0bd84SPaolo Bonzini } 2071d2c0bd84SPaolo Bonzini 2072d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma4_ops = { 2073d2c0bd84SPaolo Bonzini .read = omap_dma4_read, 2074d2c0bd84SPaolo Bonzini .write = omap_dma4_write, 2075d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 2076d2c0bd84SPaolo Bonzini }; 2077d2c0bd84SPaolo Bonzini 2078d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 2079d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 2080d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu, int fifo, 2081d2c0bd84SPaolo Bonzini int chans, omap_clk iclk, omap_clk fclk) 2082d2c0bd84SPaolo Bonzini { 2083d2c0bd84SPaolo Bonzini int i; 2084b45c03f5SMarkus Armbruster struct omap_dma_s *s = g_new0(struct omap_dma_s, 1); 2085d2c0bd84SPaolo Bonzini 2086d2c0bd84SPaolo Bonzini s->model = omap_dma_4; 2087d2c0bd84SPaolo Bonzini s->chans = chans; 2088d2c0bd84SPaolo Bonzini s->mpu = mpu; 2089d2c0bd84SPaolo Bonzini s->clk = fclk; 2090d2c0bd84SPaolo Bonzini 2091d2c0bd84SPaolo Bonzini s->dma = soc_dma_init(s->chans); 2092d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(fclk); 2093d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 2094d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 2095d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64); 2096d2c0bd84SPaolo Bonzini s->dma->opaque = s; 2097d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 2098d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 2099d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 2100d2c0bd84SPaolo Bonzini } 2101d2c0bd84SPaolo Bonzini 2102d2c0bd84SPaolo Bonzini memcpy(&s->irq, irqs, sizeof(s->irq)); 2103d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_4_update; 2104d2c0bd84SPaolo Bonzini 2105d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 2106f3c7d038SAndreas Färber omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0)); 2107d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 2108d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, !!s->dma->freq); 2109d2c0bd84SPaolo Bonzini 21102c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000); 2111d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 2112d2c0bd84SPaolo Bonzini 2113d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 2114d2c0bd84SPaolo Bonzini 2115d2c0bd84SPaolo Bonzini return s->dma; 2116d2c0bd84SPaolo Bonzini } 2117d2c0bd84SPaolo Bonzini 2118d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) 2119d2c0bd84SPaolo Bonzini { 2120d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 2121d2c0bd84SPaolo Bonzini 2122d2c0bd84SPaolo Bonzini return &s->lcd_ch; 2123d2c0bd84SPaolo Bonzini } 2124