1*d2c0bd84SPaolo Bonzini /* 2*d2c0bd84SPaolo Bonzini * TI OMAP DMA gigacell. 3*d2c0bd84SPaolo Bonzini * 4*d2c0bd84SPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5*d2c0bd84SPaolo Bonzini * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br> 6*d2c0bd84SPaolo Bonzini * 7*d2c0bd84SPaolo Bonzini * This program is free software; you can redistribute it and/or 8*d2c0bd84SPaolo Bonzini * modify it under the terms of the GNU General Public License as 9*d2c0bd84SPaolo Bonzini * published by the Free Software Foundation; either version 2 of 10*d2c0bd84SPaolo Bonzini * the License, or (at your option) any later version. 11*d2c0bd84SPaolo Bonzini * 12*d2c0bd84SPaolo Bonzini * This program is distributed in the hope that it will be useful, 13*d2c0bd84SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*d2c0bd84SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*d2c0bd84SPaolo Bonzini * GNU General Public License for more details. 16*d2c0bd84SPaolo Bonzini * 17*d2c0bd84SPaolo Bonzini * You should have received a copy of the GNU General Public License along 18*d2c0bd84SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 19*d2c0bd84SPaolo Bonzini */ 20*d2c0bd84SPaolo Bonzini #include "qemu-common.h" 21*d2c0bd84SPaolo Bonzini #include "qemu/timer.h" 22*d2c0bd84SPaolo Bonzini #include "hw/arm/omap.h" 23*d2c0bd84SPaolo Bonzini #include "hw/irq.h" 24*d2c0bd84SPaolo Bonzini #include "hw/arm/soc_dma.h" 25*d2c0bd84SPaolo Bonzini 26*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s { 27*d2c0bd84SPaolo Bonzini /* transfer data */ 28*d2c0bd84SPaolo Bonzini int burst[2]; 29*d2c0bd84SPaolo Bonzini int pack[2]; 30*d2c0bd84SPaolo Bonzini int endian[2]; 31*d2c0bd84SPaolo Bonzini int endian_lock[2]; 32*d2c0bd84SPaolo Bonzini int translate[2]; 33*d2c0bd84SPaolo Bonzini enum omap_dma_port port[2]; 34*d2c0bd84SPaolo Bonzini hwaddr addr[2]; 35*d2c0bd84SPaolo Bonzini omap_dma_addressing_t mode[2]; 36*d2c0bd84SPaolo Bonzini uint32_t elements; 37*d2c0bd84SPaolo Bonzini uint16_t frames; 38*d2c0bd84SPaolo Bonzini int32_t frame_index[2]; 39*d2c0bd84SPaolo Bonzini int16_t element_index[2]; 40*d2c0bd84SPaolo Bonzini int data_type; 41*d2c0bd84SPaolo Bonzini 42*d2c0bd84SPaolo Bonzini /* transfer type */ 43*d2c0bd84SPaolo Bonzini int transparent_copy; 44*d2c0bd84SPaolo Bonzini int constant_fill; 45*d2c0bd84SPaolo Bonzini uint32_t color; 46*d2c0bd84SPaolo Bonzini int prefetch; 47*d2c0bd84SPaolo Bonzini 48*d2c0bd84SPaolo Bonzini /* auto init and linked channel data */ 49*d2c0bd84SPaolo Bonzini int end_prog; 50*d2c0bd84SPaolo Bonzini int repeat; 51*d2c0bd84SPaolo Bonzini int auto_init; 52*d2c0bd84SPaolo Bonzini int link_enabled; 53*d2c0bd84SPaolo Bonzini int link_next_ch; 54*d2c0bd84SPaolo Bonzini 55*d2c0bd84SPaolo Bonzini /* interruption data */ 56*d2c0bd84SPaolo Bonzini int interrupts; 57*d2c0bd84SPaolo Bonzini int status; 58*d2c0bd84SPaolo Bonzini int cstatus; 59*d2c0bd84SPaolo Bonzini 60*d2c0bd84SPaolo Bonzini /* state data */ 61*d2c0bd84SPaolo Bonzini int active; 62*d2c0bd84SPaolo Bonzini int enable; 63*d2c0bd84SPaolo Bonzini int sync; 64*d2c0bd84SPaolo Bonzini int src_sync; 65*d2c0bd84SPaolo Bonzini int pending_request; 66*d2c0bd84SPaolo Bonzini int waiting_end_prog; 67*d2c0bd84SPaolo Bonzini uint16_t cpc; 68*d2c0bd84SPaolo Bonzini int set_update; 69*d2c0bd84SPaolo Bonzini 70*d2c0bd84SPaolo Bonzini /* sync type */ 71*d2c0bd84SPaolo Bonzini int fs; 72*d2c0bd84SPaolo Bonzini int bs; 73*d2c0bd84SPaolo Bonzini 74*d2c0bd84SPaolo Bonzini /* compatibility */ 75*d2c0bd84SPaolo Bonzini int omap_3_1_compatible_disable; 76*d2c0bd84SPaolo Bonzini 77*d2c0bd84SPaolo Bonzini qemu_irq irq; 78*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *sibling; 79*d2c0bd84SPaolo Bonzini 80*d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s { 81*d2c0bd84SPaolo Bonzini hwaddr src, dest; 82*d2c0bd84SPaolo Bonzini int frame; 83*d2c0bd84SPaolo Bonzini int element; 84*d2c0bd84SPaolo Bonzini int pck_element; 85*d2c0bd84SPaolo Bonzini int frame_delta[2]; 86*d2c0bd84SPaolo Bonzini int elem_delta[2]; 87*d2c0bd84SPaolo Bonzini int frames; 88*d2c0bd84SPaolo Bonzini int elements; 89*d2c0bd84SPaolo Bonzini int pck_elements; 90*d2c0bd84SPaolo Bonzini } active_set; 91*d2c0bd84SPaolo Bonzini 92*d2c0bd84SPaolo Bonzini struct soc_dma_ch_s *dma; 93*d2c0bd84SPaolo Bonzini 94*d2c0bd84SPaolo Bonzini /* unused parameters */ 95*d2c0bd84SPaolo Bonzini int write_mode; 96*d2c0bd84SPaolo Bonzini int priority; 97*d2c0bd84SPaolo Bonzini int interleave_disabled; 98*d2c0bd84SPaolo Bonzini int type; 99*d2c0bd84SPaolo Bonzini int suspend; 100*d2c0bd84SPaolo Bonzini int buf_disable; 101*d2c0bd84SPaolo Bonzini }; 102*d2c0bd84SPaolo Bonzini 103*d2c0bd84SPaolo Bonzini struct omap_dma_s { 104*d2c0bd84SPaolo Bonzini struct soc_dma_s *dma; 105*d2c0bd84SPaolo Bonzini MemoryRegion iomem; 106*d2c0bd84SPaolo Bonzini 107*d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu; 108*d2c0bd84SPaolo Bonzini omap_clk clk; 109*d2c0bd84SPaolo Bonzini qemu_irq irq[4]; 110*d2c0bd84SPaolo Bonzini void (*intr_update)(struct omap_dma_s *s); 111*d2c0bd84SPaolo Bonzini enum omap_dma_model model; 112*d2c0bd84SPaolo Bonzini int omap_3_1_mapping_disabled; 113*d2c0bd84SPaolo Bonzini 114*d2c0bd84SPaolo Bonzini uint32_t gcr; 115*d2c0bd84SPaolo Bonzini uint32_t ocp; 116*d2c0bd84SPaolo Bonzini uint32_t caps[5]; 117*d2c0bd84SPaolo Bonzini uint32_t irqen[4]; 118*d2c0bd84SPaolo Bonzini uint32_t irqstat[4]; 119*d2c0bd84SPaolo Bonzini 120*d2c0bd84SPaolo Bonzini int chans; 121*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s ch[32]; 122*d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s lcd_ch; 123*d2c0bd84SPaolo Bonzini }; 124*d2c0bd84SPaolo Bonzini 125*d2c0bd84SPaolo Bonzini /* Interrupts */ 126*d2c0bd84SPaolo Bonzini #define TIMEOUT_INTR (1 << 0) 127*d2c0bd84SPaolo Bonzini #define EVENT_DROP_INTR (1 << 1) 128*d2c0bd84SPaolo Bonzini #define HALF_FRAME_INTR (1 << 2) 129*d2c0bd84SPaolo Bonzini #define END_FRAME_INTR (1 << 3) 130*d2c0bd84SPaolo Bonzini #define LAST_FRAME_INTR (1 << 4) 131*d2c0bd84SPaolo Bonzini #define END_BLOCK_INTR (1 << 5) 132*d2c0bd84SPaolo Bonzini #define SYNC (1 << 6) 133*d2c0bd84SPaolo Bonzini #define END_PKT_INTR (1 << 7) 134*d2c0bd84SPaolo Bonzini #define TRANS_ERR_INTR (1 << 8) 135*d2c0bd84SPaolo Bonzini #define MISALIGN_INTR (1 << 11) 136*d2c0bd84SPaolo Bonzini 137*d2c0bd84SPaolo Bonzini static inline void omap_dma_interrupts_update(struct omap_dma_s *s) 138*d2c0bd84SPaolo Bonzini { 139*d2c0bd84SPaolo Bonzini return s->intr_update(s); 140*d2c0bd84SPaolo Bonzini } 141*d2c0bd84SPaolo Bonzini 142*d2c0bd84SPaolo Bonzini static void omap_dma_channel_load(struct omap_dma_channel_s *ch) 143*d2c0bd84SPaolo Bonzini { 144*d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 145*d2c0bd84SPaolo Bonzini int i, normal; 146*d2c0bd84SPaolo Bonzini int omap_3_1 = !ch->omap_3_1_compatible_disable; 147*d2c0bd84SPaolo Bonzini 148*d2c0bd84SPaolo Bonzini /* 149*d2c0bd84SPaolo Bonzini * TODO: verify address ranges and alignment 150*d2c0bd84SPaolo Bonzini * TODO: port endianness 151*d2c0bd84SPaolo Bonzini */ 152*d2c0bd84SPaolo Bonzini 153*d2c0bd84SPaolo Bonzini a->src = ch->addr[0]; 154*d2c0bd84SPaolo Bonzini a->dest = ch->addr[1]; 155*d2c0bd84SPaolo Bonzini a->frames = ch->frames; 156*d2c0bd84SPaolo Bonzini a->elements = ch->elements; 157*d2c0bd84SPaolo Bonzini a->pck_elements = ch->frame_index[!ch->src_sync]; 158*d2c0bd84SPaolo Bonzini a->frame = 0; 159*d2c0bd84SPaolo Bonzini a->element = 0; 160*d2c0bd84SPaolo Bonzini a->pck_element = 0; 161*d2c0bd84SPaolo Bonzini 162*d2c0bd84SPaolo Bonzini if (unlikely(!ch->elements || !ch->frames)) { 163*d2c0bd84SPaolo Bonzini printf("%s: bad DMA request\n", __FUNCTION__); 164*d2c0bd84SPaolo Bonzini return; 165*d2c0bd84SPaolo Bonzini } 166*d2c0bd84SPaolo Bonzini 167*d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) 168*d2c0bd84SPaolo Bonzini switch (ch->mode[i]) { 169*d2c0bd84SPaolo Bonzini case constant: 170*d2c0bd84SPaolo Bonzini a->elem_delta[i] = 0; 171*d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 172*d2c0bd84SPaolo Bonzini break; 173*d2c0bd84SPaolo Bonzini case post_incremented: 174*d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type; 175*d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 176*d2c0bd84SPaolo Bonzini break; 177*d2c0bd84SPaolo Bonzini case single_index: 178*d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 179*d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 180*d2c0bd84SPaolo Bonzini a->frame_delta[i] = 0; 181*d2c0bd84SPaolo Bonzini break; 182*d2c0bd84SPaolo Bonzini case double_index: 183*d2c0bd84SPaolo Bonzini a->elem_delta[i] = ch->data_type + 184*d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i] - 1; 185*d2c0bd84SPaolo Bonzini a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - 186*d2c0bd84SPaolo Bonzini ch->element_index[omap_3_1 ? 0 : i]; 187*d2c0bd84SPaolo Bonzini break; 188*d2c0bd84SPaolo Bonzini default: 189*d2c0bd84SPaolo Bonzini break; 190*d2c0bd84SPaolo Bonzini } 191*d2c0bd84SPaolo Bonzini 192*d2c0bd84SPaolo Bonzini normal = !ch->transparent_copy && !ch->constant_fill && 193*d2c0bd84SPaolo Bonzini /* FIFO is big-endian so either (ch->endian[n] == 1) OR 194*d2c0bd84SPaolo Bonzini * (ch->endian_lock[n] == 1) mean no endianism conversion. */ 195*d2c0bd84SPaolo Bonzini (ch->endian[0] | ch->endian_lock[0]) == 196*d2c0bd84SPaolo Bonzini (ch->endian[1] | ch->endian_lock[1]); 197*d2c0bd84SPaolo Bonzini for (i = 0; i < 2; i ++) { 198*d2c0bd84SPaolo Bonzini /* TODO: for a->frame_delta[i] > 0 still use the fast path, just 199*d2c0bd84SPaolo Bonzini * limit min_elems in omap_dma_transfer_setup to the nearest frame 200*d2c0bd84SPaolo Bonzini * end. */ 201*d2c0bd84SPaolo Bonzini if (!a->elem_delta[i] && normal && 202*d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 203*d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_const; 204*d2c0bd84SPaolo Bonzini else if (a->elem_delta[i] == ch->data_type && normal && 205*d2c0bd84SPaolo Bonzini (a->frames == 1 || !a->frame_delta[i])) 206*d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_linear; 207*d2c0bd84SPaolo Bonzini else 208*d2c0bd84SPaolo Bonzini ch->dma->type[i] = soc_dma_access_other; 209*d2c0bd84SPaolo Bonzini 210*d2c0bd84SPaolo Bonzini ch->dma->vaddr[i] = ch->addr[i]; 211*d2c0bd84SPaolo Bonzini } 212*d2c0bd84SPaolo Bonzini soc_dma_ch_update(ch->dma); 213*d2c0bd84SPaolo Bonzini } 214*d2c0bd84SPaolo Bonzini 215*d2c0bd84SPaolo Bonzini static void omap_dma_activate_channel(struct omap_dma_s *s, 216*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 217*d2c0bd84SPaolo Bonzini { 218*d2c0bd84SPaolo Bonzini if (!ch->active) { 219*d2c0bd84SPaolo Bonzini if (ch->set_update) { 220*d2c0bd84SPaolo Bonzini /* It's not clear when the active set is supposed to be 221*d2c0bd84SPaolo Bonzini * loaded from registers. We're already loading it when the 222*d2c0bd84SPaolo Bonzini * channel is enabled, and for some guests this is not enough 223*d2c0bd84SPaolo Bonzini * but that may be also because of a race condition (no 224*d2c0bd84SPaolo Bonzini * delays in qemu) in the guest code, which we're just 225*d2c0bd84SPaolo Bonzini * working around here. */ 226*d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 227*d2c0bd84SPaolo Bonzini ch->set_update = 0; 228*d2c0bd84SPaolo Bonzini } 229*d2c0bd84SPaolo Bonzini 230*d2c0bd84SPaolo Bonzini ch->active = 1; 231*d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 1); 232*d2c0bd84SPaolo Bonzini if (ch->sync) 233*d2c0bd84SPaolo Bonzini ch->status |= SYNC; 234*d2c0bd84SPaolo Bonzini } 235*d2c0bd84SPaolo Bonzini } 236*d2c0bd84SPaolo Bonzini 237*d2c0bd84SPaolo Bonzini static void omap_dma_deactivate_channel(struct omap_dma_s *s, 238*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 239*d2c0bd84SPaolo Bonzini { 240*d2c0bd84SPaolo Bonzini /* Update cpc */ 241*d2c0bd84SPaolo Bonzini ch->cpc = ch->active_set.dest & 0xffff; 242*d2c0bd84SPaolo Bonzini 243*d2c0bd84SPaolo Bonzini if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { 244*d2c0bd84SPaolo Bonzini /* Don't deactivate the channel */ 245*d2c0bd84SPaolo Bonzini ch->pending_request = 0; 246*d2c0bd84SPaolo Bonzini return; 247*d2c0bd84SPaolo Bonzini } 248*d2c0bd84SPaolo Bonzini 249*d2c0bd84SPaolo Bonzini /* Don't deactive the channel if it is synchronized and the DMA request is 250*d2c0bd84SPaolo Bonzini active */ 251*d2c0bd84SPaolo Bonzini if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync))) 252*d2c0bd84SPaolo Bonzini return; 253*d2c0bd84SPaolo Bonzini 254*d2c0bd84SPaolo Bonzini if (ch->active) { 255*d2c0bd84SPaolo Bonzini ch->active = 0; 256*d2c0bd84SPaolo Bonzini ch->status &= ~SYNC; 257*d2c0bd84SPaolo Bonzini soc_dma_set_request(ch->dma, 0); 258*d2c0bd84SPaolo Bonzini } 259*d2c0bd84SPaolo Bonzini } 260*d2c0bd84SPaolo Bonzini 261*d2c0bd84SPaolo Bonzini static void omap_dma_enable_channel(struct omap_dma_s *s, 262*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 263*d2c0bd84SPaolo Bonzini { 264*d2c0bd84SPaolo Bonzini if (!ch->enable) { 265*d2c0bd84SPaolo Bonzini ch->enable = 1; 266*d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 267*d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 268*d2c0bd84SPaolo Bonzini /* TODO: theoretically if ch->sync && ch->prefetch && 269*d2c0bd84SPaolo Bonzini * !s->dma->drqbmp[ch->sync], we should also activate and fetch 270*d2c0bd84SPaolo Bonzini * from source and then stall until signalled. */ 271*d2c0bd84SPaolo Bonzini if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync))) 272*d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 273*d2c0bd84SPaolo Bonzini } 274*d2c0bd84SPaolo Bonzini } 275*d2c0bd84SPaolo Bonzini 276*d2c0bd84SPaolo Bonzini static void omap_dma_disable_channel(struct omap_dma_s *s, 277*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 278*d2c0bd84SPaolo Bonzini { 279*d2c0bd84SPaolo Bonzini if (ch->enable) { 280*d2c0bd84SPaolo Bonzini ch->enable = 0; 281*d2c0bd84SPaolo Bonzini /* Discard any pending request */ 282*d2c0bd84SPaolo Bonzini ch->pending_request = 0; 283*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 284*d2c0bd84SPaolo Bonzini } 285*d2c0bd84SPaolo Bonzini } 286*d2c0bd84SPaolo Bonzini 287*d2c0bd84SPaolo Bonzini static void omap_dma_channel_end_prog(struct omap_dma_s *s, 288*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch) 289*d2c0bd84SPaolo Bonzini { 290*d2c0bd84SPaolo Bonzini if (ch->waiting_end_prog) { 291*d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 0; 292*d2c0bd84SPaolo Bonzini if (!ch->sync || ch->pending_request) { 293*d2c0bd84SPaolo Bonzini ch->pending_request = 0; 294*d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 295*d2c0bd84SPaolo Bonzini } 296*d2c0bd84SPaolo Bonzini } 297*d2c0bd84SPaolo Bonzini } 298*d2c0bd84SPaolo Bonzini 299*d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) 300*d2c0bd84SPaolo Bonzini { 301*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 302*d2c0bd84SPaolo Bonzini 303*d2c0bd84SPaolo Bonzini /* First three interrupts are shared between two channels each. */ 304*d2c0bd84SPaolo Bonzini if (ch[0].status | ch[6].status) 305*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[0].irq); 306*d2c0bd84SPaolo Bonzini if (ch[1].status | ch[7].status) 307*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[1].irq); 308*d2c0bd84SPaolo Bonzini if (ch[2].status | ch[8].status) 309*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[2].irq); 310*d2c0bd84SPaolo Bonzini if (ch[3].status) 311*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[3].irq); 312*d2c0bd84SPaolo Bonzini if (ch[4].status) 313*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[4].irq); 314*d2c0bd84SPaolo Bonzini if (ch[5].status) 315*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch[5].irq); 316*d2c0bd84SPaolo Bonzini } 317*d2c0bd84SPaolo Bonzini 318*d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) 319*d2c0bd84SPaolo Bonzini { 320*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 321*d2c0bd84SPaolo Bonzini int i; 322*d2c0bd84SPaolo Bonzini 323*d2c0bd84SPaolo Bonzini for (i = s->chans; i; ch ++, i --) 324*d2c0bd84SPaolo Bonzini if (ch->status) 325*d2c0bd84SPaolo Bonzini qemu_irq_raise(ch->irq); 326*d2c0bd84SPaolo Bonzini } 327*d2c0bd84SPaolo Bonzini 328*d2c0bd84SPaolo Bonzini static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) 329*d2c0bd84SPaolo Bonzini { 330*d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 0; 331*d2c0bd84SPaolo Bonzini s->chans = 9; 332*d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_1_update; 333*d2c0bd84SPaolo Bonzini } 334*d2c0bd84SPaolo Bonzini 335*d2c0bd84SPaolo Bonzini static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) 336*d2c0bd84SPaolo Bonzini { 337*d2c0bd84SPaolo Bonzini s->omap_3_1_mapping_disabled = 1; 338*d2c0bd84SPaolo Bonzini s->chans = 16; 339*d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_3_2_update; 340*d2c0bd84SPaolo Bonzini } 341*d2c0bd84SPaolo Bonzini 342*d2c0bd84SPaolo Bonzini static void omap_dma_process_request(struct omap_dma_s *s, int request) 343*d2c0bd84SPaolo Bonzini { 344*d2c0bd84SPaolo Bonzini int channel; 345*d2c0bd84SPaolo Bonzini int drop_event = 0; 346*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 347*d2c0bd84SPaolo Bonzini 348*d2c0bd84SPaolo Bonzini for (channel = 0; channel < s->chans; channel ++, ch ++) { 349*d2c0bd84SPaolo Bonzini if (ch->enable && ch->sync == request) { 350*d2c0bd84SPaolo Bonzini if (!ch->active) 351*d2c0bd84SPaolo Bonzini omap_dma_activate_channel(s, ch); 352*d2c0bd84SPaolo Bonzini else if (!ch->pending_request) 353*d2c0bd84SPaolo Bonzini ch->pending_request = 1; 354*d2c0bd84SPaolo Bonzini else { 355*d2c0bd84SPaolo Bonzini /* Request collision */ 356*d2c0bd84SPaolo Bonzini /* Second request received while processing other request */ 357*d2c0bd84SPaolo Bonzini ch->status |= EVENT_DROP_INTR; 358*d2c0bd84SPaolo Bonzini drop_event = 1; 359*d2c0bd84SPaolo Bonzini } 360*d2c0bd84SPaolo Bonzini } 361*d2c0bd84SPaolo Bonzini } 362*d2c0bd84SPaolo Bonzini 363*d2c0bd84SPaolo Bonzini if (drop_event) 364*d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 365*d2c0bd84SPaolo Bonzini } 366*d2c0bd84SPaolo Bonzini 367*d2c0bd84SPaolo Bonzini static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) 368*d2c0bd84SPaolo Bonzini { 369*d2c0bd84SPaolo Bonzini uint8_t value[4]; 370*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 371*d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a = &ch->active_set; 372*d2c0bd84SPaolo Bonzini int bytes = dma->bytes; 373*d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 374*d2c0bd84SPaolo Bonzini uint16_t status = ch->status; 375*d2c0bd84SPaolo Bonzini #endif 376*d2c0bd84SPaolo Bonzini 377*d2c0bd84SPaolo Bonzini do { 378*d2c0bd84SPaolo Bonzini /* Transfer a single element */ 379*d2c0bd84SPaolo Bonzini /* FIXME: check the endianness */ 380*d2c0bd84SPaolo Bonzini if (!ch->constant_fill) 381*d2c0bd84SPaolo Bonzini cpu_physical_memory_read(a->src, value, ch->data_type); 382*d2c0bd84SPaolo Bonzini else 383*d2c0bd84SPaolo Bonzini *(uint32_t *) value = ch->color; 384*d2c0bd84SPaolo Bonzini 385*d2c0bd84SPaolo Bonzini if (!ch->transparent_copy || *(uint32_t *) value != ch->color) 386*d2c0bd84SPaolo Bonzini cpu_physical_memory_write(a->dest, value, ch->data_type); 387*d2c0bd84SPaolo Bonzini 388*d2c0bd84SPaolo Bonzini a->src += a->elem_delta[0]; 389*d2c0bd84SPaolo Bonzini a->dest += a->elem_delta[1]; 390*d2c0bd84SPaolo Bonzini a->element ++; 391*d2c0bd84SPaolo Bonzini 392*d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 393*d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 394*d2c0bd84SPaolo Bonzini /* End of Frame */ 395*d2c0bd84SPaolo Bonzini a->element = 0; 396*d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 397*d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 398*d2c0bd84SPaolo Bonzini a->frame ++; 399*d2c0bd84SPaolo Bonzini 400*d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 401*d2c0bd84SPaolo Bonzini if (!ch->sync) 402*d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 403*d2c0bd84SPaolo Bonzini } 404*d2c0bd84SPaolo Bonzini } while ((bytes -= ch->data_type)); 405*d2c0bd84SPaolo Bonzini #else 406*d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 407*d2c0bd84SPaolo Bonzini if (ch->sync && !ch->fs && !ch->bs) 408*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 409*d2c0bd84SPaolo Bonzini 410*d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 411*d2c0bd84SPaolo Bonzini if (a->element == 1 && a->frame == a->frames - 1) 412*d2c0bd84SPaolo Bonzini if (ch->interrupts & LAST_FRAME_INTR) 413*d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 414*d2c0bd84SPaolo Bonzini 415*d2c0bd84SPaolo Bonzini /* If the half of the frame was reached, set the HALF_FRAME 416*d2c0bd84SPaolo Bonzini interrupt */ 417*d2c0bd84SPaolo Bonzini if (a->element == (a->elements >> 1)) 418*d2c0bd84SPaolo Bonzini if (ch->interrupts & HALF_FRAME_INTR) 419*d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 420*d2c0bd84SPaolo Bonzini 421*d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 422*d2c0bd84SPaolo Bonzini a->pck_element ++; 423*d2c0bd84SPaolo Bonzini /* Check if a full packet has beed transferred. */ 424*d2c0bd84SPaolo Bonzini if (a->pck_element == a->pck_elements) { 425*d2c0bd84SPaolo Bonzini a->pck_element = 0; 426*d2c0bd84SPaolo Bonzini 427*d2c0bd84SPaolo Bonzini /* Set the END_PKT interrupt */ 428*d2c0bd84SPaolo Bonzini if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) 429*d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 430*d2c0bd84SPaolo Bonzini 431*d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 432*d2c0bd84SPaolo Bonzini if (ch->sync) 433*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 434*d2c0bd84SPaolo Bonzini } 435*d2c0bd84SPaolo Bonzini } 436*d2c0bd84SPaolo Bonzini 437*d2c0bd84SPaolo Bonzini if (a->element == a->elements) { 438*d2c0bd84SPaolo Bonzini /* End of Frame */ 439*d2c0bd84SPaolo Bonzini a->element = 0; 440*d2c0bd84SPaolo Bonzini a->src += a->frame_delta[0]; 441*d2c0bd84SPaolo Bonzini a->dest += a->frame_delta[1]; 442*d2c0bd84SPaolo Bonzini a->frame ++; 443*d2c0bd84SPaolo Bonzini 444*d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 445*d2c0bd84SPaolo Bonzini if (ch->sync && ch->fs && !ch->bs) 446*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 447*d2c0bd84SPaolo Bonzini 448*d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 449*d2c0bd84SPaolo Bonzini if (!ch->sync) 450*d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 451*d2c0bd84SPaolo Bonzini 452*d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 453*d2c0bd84SPaolo Bonzini if (ch->interrupts & END_FRAME_INTR) 454*d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 455*d2c0bd84SPaolo Bonzini 456*d2c0bd84SPaolo Bonzini if (a->frame == a->frames) { 457*d2c0bd84SPaolo Bonzini /* End of Block */ 458*d2c0bd84SPaolo Bonzini /* Disable the channel */ 459*d2c0bd84SPaolo Bonzini 460*d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 461*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 462*d2c0bd84SPaolo Bonzini if (ch->link_enabled) 463*d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, 464*d2c0bd84SPaolo Bonzini &s->ch[ch->link_next_ch]); 465*d2c0bd84SPaolo Bonzini } else { 466*d2c0bd84SPaolo Bonzini if (!ch->auto_init) 467*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 468*d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 469*d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 470*d2c0bd84SPaolo Bonzini else { 471*d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 472*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 473*d2c0bd84SPaolo Bonzini } 474*d2c0bd84SPaolo Bonzini } 475*d2c0bd84SPaolo Bonzini 476*d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 477*d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 478*d2c0bd84SPaolo Bonzini } 479*d2c0bd84SPaolo Bonzini } 480*d2c0bd84SPaolo Bonzini } while (status == ch->status && ch->active); 481*d2c0bd84SPaolo Bonzini 482*d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 483*d2c0bd84SPaolo Bonzini #endif 484*d2c0bd84SPaolo Bonzini } 485*d2c0bd84SPaolo Bonzini 486*d2c0bd84SPaolo Bonzini enum { 487*d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 488*d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 489*d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 490*d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 491*d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 492*d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 493*d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 494*d2c0bd84SPaolo Bonzini omap_dma_intr_block, 495*d2c0bd84SPaolo Bonzini __omap_dma_intr_last, 496*d2c0bd84SPaolo Bonzini }; 497*d2c0bd84SPaolo Bonzini 498*d2c0bd84SPaolo Bonzini static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) 499*d2c0bd84SPaolo Bonzini { 500*d2c0bd84SPaolo Bonzini struct omap_dma_port_if_s *src_p, *dest_p; 501*d2c0bd84SPaolo Bonzini struct omap_dma_reg_set_s *a; 502*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = dma->opaque; 503*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->dma->opaque; 504*d2c0bd84SPaolo Bonzini int frames, min_elems, elements[__omap_dma_intr_last]; 505*d2c0bd84SPaolo Bonzini 506*d2c0bd84SPaolo Bonzini a = &ch->active_set; 507*d2c0bd84SPaolo Bonzini 508*d2c0bd84SPaolo Bonzini src_p = &s->mpu->port[ch->port[0]]; 509*d2c0bd84SPaolo Bonzini dest_p = &s->mpu->port[ch->port[1]]; 510*d2c0bd84SPaolo Bonzini if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || 511*d2c0bd84SPaolo Bonzini (!dest_p->addr_valid(s->mpu, a->dest))) { 512*d2c0bd84SPaolo Bonzini #if 0 513*d2c0bd84SPaolo Bonzini /* Bus time-out */ 514*d2c0bd84SPaolo Bonzini if (ch->interrupts & TIMEOUT_INTR) 515*d2c0bd84SPaolo Bonzini ch->status |= TIMEOUT_INTR; 516*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 517*d2c0bd84SPaolo Bonzini continue; 518*d2c0bd84SPaolo Bonzini #endif 519*d2c0bd84SPaolo Bonzini printf("%s: Bus time-out in DMA%i operation\n", 520*d2c0bd84SPaolo Bonzini __FUNCTION__, dma->num); 521*d2c0bd84SPaolo Bonzini } 522*d2c0bd84SPaolo Bonzini 523*d2c0bd84SPaolo Bonzini min_elems = INT_MAX; 524*d2c0bd84SPaolo Bonzini 525*d2c0bd84SPaolo Bonzini /* Check all the conditions that terminate the transfer starting 526*d2c0bd84SPaolo Bonzini * with those that can occur the soonest. */ 527*d2c0bd84SPaolo Bonzini #define INTR_CHECK(cond, id, nelements) \ 528*d2c0bd84SPaolo Bonzini if (cond) { \ 529*d2c0bd84SPaolo Bonzini elements[id] = nelements; \ 530*d2c0bd84SPaolo Bonzini if (elements[id] < min_elems) \ 531*d2c0bd84SPaolo Bonzini min_elems = elements[id]; \ 532*d2c0bd84SPaolo Bonzini } else \ 533*d2c0bd84SPaolo Bonzini elements[id] = INT_MAX; 534*d2c0bd84SPaolo Bonzini 535*d2c0bd84SPaolo Bonzini /* Elements */ 536*d2c0bd84SPaolo Bonzini INTR_CHECK( 537*d2c0bd84SPaolo Bonzini ch->sync && !ch->fs && !ch->bs, 538*d2c0bd84SPaolo Bonzini omap_dma_intr_element_sync, 539*d2c0bd84SPaolo Bonzini 1) 540*d2c0bd84SPaolo Bonzini 541*d2c0bd84SPaolo Bonzini /* Frames */ 542*d2c0bd84SPaolo Bonzini /* TODO: for transfers where entire frames can be read and written 543*d2c0bd84SPaolo Bonzini * using memcpy() but a->frame_delta is non-zero, try to still do 544*d2c0bd84SPaolo Bonzini * transfers using soc_dma but limit min_elems to a->elements - ... 545*d2c0bd84SPaolo Bonzini * See also the TODO in omap_dma_channel_load. */ 546*d2c0bd84SPaolo Bonzini INTR_CHECK( 547*d2c0bd84SPaolo Bonzini (ch->interrupts & LAST_FRAME_INTR) && 548*d2c0bd84SPaolo Bonzini ((a->frame < a->frames - 1) || !a->element), 549*d2c0bd84SPaolo Bonzini omap_dma_intr_last_frame, 550*d2c0bd84SPaolo Bonzini (a->frames - a->frame - 2) * a->elements + 551*d2c0bd84SPaolo Bonzini (a->elements - a->element + 1)) 552*d2c0bd84SPaolo Bonzini INTR_CHECK( 553*d2c0bd84SPaolo Bonzini ch->interrupts & HALF_FRAME_INTR, 554*d2c0bd84SPaolo Bonzini omap_dma_intr_half_frame, 555*d2c0bd84SPaolo Bonzini (a->elements >> 1) + 556*d2c0bd84SPaolo Bonzini (a->element >= (a->elements >> 1) ? a->elements : 0) - 557*d2c0bd84SPaolo Bonzini a->element) 558*d2c0bd84SPaolo Bonzini INTR_CHECK( 559*d2c0bd84SPaolo Bonzini ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), 560*d2c0bd84SPaolo Bonzini omap_dma_intr_frame, 561*d2c0bd84SPaolo Bonzini a->elements - a->element) 562*d2c0bd84SPaolo Bonzini INTR_CHECK( 563*d2c0bd84SPaolo Bonzini ch->sync && ch->fs && !ch->bs, 564*d2c0bd84SPaolo Bonzini omap_dma_intr_frame_sync, 565*d2c0bd84SPaolo Bonzini a->elements - a->element) 566*d2c0bd84SPaolo Bonzini 567*d2c0bd84SPaolo Bonzini /* Packets */ 568*d2c0bd84SPaolo Bonzini INTR_CHECK( 569*d2c0bd84SPaolo Bonzini ch->fs && ch->bs && 570*d2c0bd84SPaolo Bonzini (ch->interrupts & END_PKT_INTR) && !ch->src_sync, 571*d2c0bd84SPaolo Bonzini omap_dma_intr_packet, 572*d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 573*d2c0bd84SPaolo Bonzini INTR_CHECK( 574*d2c0bd84SPaolo Bonzini ch->fs && ch->bs && ch->sync, 575*d2c0bd84SPaolo Bonzini omap_dma_intr_packet_sync, 576*d2c0bd84SPaolo Bonzini a->pck_elements - a->pck_element) 577*d2c0bd84SPaolo Bonzini 578*d2c0bd84SPaolo Bonzini /* Blocks */ 579*d2c0bd84SPaolo Bonzini INTR_CHECK( 580*d2c0bd84SPaolo Bonzini 1, 581*d2c0bd84SPaolo Bonzini omap_dma_intr_block, 582*d2c0bd84SPaolo Bonzini (a->frames - a->frame - 1) * a->elements + 583*d2c0bd84SPaolo Bonzini (a->elements - a->element)) 584*d2c0bd84SPaolo Bonzini 585*d2c0bd84SPaolo Bonzini dma->bytes = min_elems * ch->data_type; 586*d2c0bd84SPaolo Bonzini 587*d2c0bd84SPaolo Bonzini /* Set appropriate interrupts and/or deactivate channels */ 588*d2c0bd84SPaolo Bonzini 589*d2c0bd84SPaolo Bonzini #ifdef MULTI_REQ 590*d2c0bd84SPaolo Bonzini /* TODO: should all of this only be done if dma->update, and otherwise 591*d2c0bd84SPaolo Bonzini * inside omap_dma_transfer_generic below - check what's faster. */ 592*d2c0bd84SPaolo Bonzini if (dma->update) { 593*d2c0bd84SPaolo Bonzini #endif 594*d2c0bd84SPaolo Bonzini 595*d2c0bd84SPaolo Bonzini /* If the channel is element synchronized, deactivate it */ 596*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_element_sync]) 597*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 598*d2c0bd84SPaolo Bonzini 599*d2c0bd84SPaolo Bonzini /* If it is the last frame, set the LAST_FRAME interrupt */ 600*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_last_frame]) 601*d2c0bd84SPaolo Bonzini ch->status |= LAST_FRAME_INTR; 602*d2c0bd84SPaolo Bonzini 603*d2c0bd84SPaolo Bonzini /* If exactly half of the frame was reached, set the HALF_FRAME 604*d2c0bd84SPaolo Bonzini interrupt */ 605*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_half_frame]) 606*d2c0bd84SPaolo Bonzini ch->status |= HALF_FRAME_INTR; 607*d2c0bd84SPaolo Bonzini 608*d2c0bd84SPaolo Bonzini /* If a full packet has been transferred, set the END_PKT interrupt */ 609*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet]) 610*d2c0bd84SPaolo Bonzini ch->status |= END_PKT_INTR; 611*d2c0bd84SPaolo Bonzini 612*d2c0bd84SPaolo Bonzini /* If the channel is packet-synchronized, deactivate it */ 613*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_packet_sync]) 614*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 615*d2c0bd84SPaolo Bonzini 616*d2c0bd84SPaolo Bonzini /* If the channel is frame synchronized, deactivate it */ 617*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame_sync]) 618*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 619*d2c0bd84SPaolo Bonzini 620*d2c0bd84SPaolo Bonzini /* Set the END_FRAME interrupt */ 621*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_frame]) 622*d2c0bd84SPaolo Bonzini ch->status |= END_FRAME_INTR; 623*d2c0bd84SPaolo Bonzini 624*d2c0bd84SPaolo Bonzini if (min_elems == elements[omap_dma_intr_block]) { 625*d2c0bd84SPaolo Bonzini /* End of Block */ 626*d2c0bd84SPaolo Bonzini /* Disable the channel */ 627*d2c0bd84SPaolo Bonzini 628*d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) { 629*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 630*d2c0bd84SPaolo Bonzini if (ch->link_enabled) 631*d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); 632*d2c0bd84SPaolo Bonzini } else { 633*d2c0bd84SPaolo Bonzini if (!ch->auto_init) 634*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 635*d2c0bd84SPaolo Bonzini else if (ch->repeat || ch->end_prog) 636*d2c0bd84SPaolo Bonzini omap_dma_channel_load(ch); 637*d2c0bd84SPaolo Bonzini else { 638*d2c0bd84SPaolo Bonzini ch->waiting_end_prog = 1; 639*d2c0bd84SPaolo Bonzini omap_dma_deactivate_channel(s, ch); 640*d2c0bd84SPaolo Bonzini } 641*d2c0bd84SPaolo Bonzini } 642*d2c0bd84SPaolo Bonzini 643*d2c0bd84SPaolo Bonzini if (ch->interrupts & END_BLOCK_INTR) 644*d2c0bd84SPaolo Bonzini ch->status |= END_BLOCK_INTR; 645*d2c0bd84SPaolo Bonzini } 646*d2c0bd84SPaolo Bonzini 647*d2c0bd84SPaolo Bonzini /* Update packet number */ 648*d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs) { 649*d2c0bd84SPaolo Bonzini a->pck_element += min_elems; 650*d2c0bd84SPaolo Bonzini a->pck_element %= a->pck_elements; 651*d2c0bd84SPaolo Bonzini } 652*d2c0bd84SPaolo Bonzini 653*d2c0bd84SPaolo Bonzini /* TODO: check if we really need to update anything here or perhaps we 654*d2c0bd84SPaolo Bonzini * can skip part of this. */ 655*d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 656*d2c0bd84SPaolo Bonzini if (dma->update) { 657*d2c0bd84SPaolo Bonzini #endif 658*d2c0bd84SPaolo Bonzini a->element += min_elems; 659*d2c0bd84SPaolo Bonzini 660*d2c0bd84SPaolo Bonzini frames = a->element / a->elements; 661*d2c0bd84SPaolo Bonzini a->element = a->element % a->elements; 662*d2c0bd84SPaolo Bonzini a->frame += frames; 663*d2c0bd84SPaolo Bonzini a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; 664*d2c0bd84SPaolo Bonzini a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; 665*d2c0bd84SPaolo Bonzini 666*d2c0bd84SPaolo Bonzini /* If the channel is async, update cpc */ 667*d2c0bd84SPaolo Bonzini if (!ch->sync && frames) 668*d2c0bd84SPaolo Bonzini ch->cpc = a->dest & 0xffff; 669*d2c0bd84SPaolo Bonzini 670*d2c0bd84SPaolo Bonzini /* TODO: if the destination port is IMIF or EMIFF, set the dirty 671*d2c0bd84SPaolo Bonzini * bits on it. */ 672*d2c0bd84SPaolo Bonzini #ifndef MULTI_REQ 673*d2c0bd84SPaolo Bonzini } 674*d2c0bd84SPaolo Bonzini #else 675*d2c0bd84SPaolo Bonzini } 676*d2c0bd84SPaolo Bonzini #endif 677*d2c0bd84SPaolo Bonzini 678*d2c0bd84SPaolo Bonzini omap_dma_interrupts_update(s); 679*d2c0bd84SPaolo Bonzini } 680*d2c0bd84SPaolo Bonzini 681*d2c0bd84SPaolo Bonzini void omap_dma_reset(struct soc_dma_s *dma) 682*d2c0bd84SPaolo Bonzini { 683*d2c0bd84SPaolo Bonzini int i; 684*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 685*d2c0bd84SPaolo Bonzini 686*d2c0bd84SPaolo Bonzini soc_dma_reset(s->dma); 687*d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 688*d2c0bd84SPaolo Bonzini s->gcr = 0x0004; 689*d2c0bd84SPaolo Bonzini else 690*d2c0bd84SPaolo Bonzini s->gcr = 0x00010010; 691*d2c0bd84SPaolo Bonzini s->ocp = 0x00000000; 692*d2c0bd84SPaolo Bonzini memset(&s->irqstat, 0, sizeof(s->irqstat)); 693*d2c0bd84SPaolo Bonzini memset(&s->irqen, 0, sizeof(s->irqen)); 694*d2c0bd84SPaolo Bonzini s->lcd_ch.src = emiff; 695*d2c0bd84SPaolo Bonzini s->lcd_ch.condition = 0; 696*d2c0bd84SPaolo Bonzini s->lcd_ch.interrupts = 0; 697*d2c0bd84SPaolo Bonzini s->lcd_ch.dual = 0; 698*d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 699*d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 700*d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 701*d2c0bd84SPaolo Bonzini s->ch[i].suspend = 0; 702*d2c0bd84SPaolo Bonzini s->ch[i].prefetch = 0; 703*d2c0bd84SPaolo Bonzini s->ch[i].buf_disable = 0; 704*d2c0bd84SPaolo Bonzini s->ch[i].src_sync = 0; 705*d2c0bd84SPaolo Bonzini memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); 706*d2c0bd84SPaolo Bonzini memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); 707*d2c0bd84SPaolo Bonzini memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); 708*d2c0bd84SPaolo Bonzini memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); 709*d2c0bd84SPaolo Bonzini memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); 710*d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); 711*d2c0bd84SPaolo Bonzini memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); 712*d2c0bd84SPaolo Bonzini memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); 713*d2c0bd84SPaolo Bonzini s->ch[i].write_mode = 0; 714*d2c0bd84SPaolo Bonzini s->ch[i].data_type = 0; 715*d2c0bd84SPaolo Bonzini s->ch[i].transparent_copy = 0; 716*d2c0bd84SPaolo Bonzini s->ch[i].constant_fill = 0; 717*d2c0bd84SPaolo Bonzini s->ch[i].color = 0x00000000; 718*d2c0bd84SPaolo Bonzini s->ch[i].end_prog = 0; 719*d2c0bd84SPaolo Bonzini s->ch[i].repeat = 0; 720*d2c0bd84SPaolo Bonzini s->ch[i].auto_init = 0; 721*d2c0bd84SPaolo Bonzini s->ch[i].link_enabled = 0; 722*d2c0bd84SPaolo Bonzini if (s->model < omap_dma_4) 723*d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0003; 724*d2c0bd84SPaolo Bonzini else 725*d2c0bd84SPaolo Bonzini s->ch[i].interrupts = 0x0000; 726*d2c0bd84SPaolo Bonzini s->ch[i].status = 0; 727*d2c0bd84SPaolo Bonzini s->ch[i].cstatus = 0; 728*d2c0bd84SPaolo Bonzini s->ch[i].active = 0; 729*d2c0bd84SPaolo Bonzini s->ch[i].enable = 0; 730*d2c0bd84SPaolo Bonzini s->ch[i].sync = 0; 731*d2c0bd84SPaolo Bonzini s->ch[i].pending_request = 0; 732*d2c0bd84SPaolo Bonzini s->ch[i].waiting_end_prog = 0; 733*d2c0bd84SPaolo Bonzini s->ch[i].cpc = 0x0000; 734*d2c0bd84SPaolo Bonzini s->ch[i].fs = 0; 735*d2c0bd84SPaolo Bonzini s->ch[i].bs = 0; 736*d2c0bd84SPaolo Bonzini s->ch[i].omap_3_1_compatible_disable = 0; 737*d2c0bd84SPaolo Bonzini memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); 738*d2c0bd84SPaolo Bonzini s->ch[i].priority = 0; 739*d2c0bd84SPaolo Bonzini s->ch[i].interleave_disabled = 0; 740*d2c0bd84SPaolo Bonzini s->ch[i].type = 0; 741*d2c0bd84SPaolo Bonzini } 742*d2c0bd84SPaolo Bonzini } 743*d2c0bd84SPaolo Bonzini 744*d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_read(struct omap_dma_s *s, 745*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t *value) 746*d2c0bd84SPaolo Bonzini { 747*d2c0bd84SPaolo Bonzini switch (reg) { 748*d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 749*d2c0bd84SPaolo Bonzini *value = (ch->burst[1] << 14) | 750*d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 751*d2c0bd84SPaolo Bonzini (ch->port[1] << 9) | 752*d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 753*d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 754*d2c0bd84SPaolo Bonzini (ch->port[0] << 2) | 755*d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 756*d2c0bd84SPaolo Bonzini break; 757*d2c0bd84SPaolo Bonzini 758*d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 759*d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 760*d2c0bd84SPaolo Bonzini *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ 761*d2c0bd84SPaolo Bonzini else 762*d2c0bd84SPaolo Bonzini *value = ch->omap_3_1_compatible_disable << 10; 763*d2c0bd84SPaolo Bonzini *value |= (ch->mode[1] << 14) | 764*d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 765*d2c0bd84SPaolo Bonzini (ch->end_prog << 11) | 766*d2c0bd84SPaolo Bonzini (ch->repeat << 9) | 767*d2c0bd84SPaolo Bonzini (ch->auto_init << 8) | 768*d2c0bd84SPaolo Bonzini (ch->enable << 7) | 769*d2c0bd84SPaolo Bonzini (ch->priority << 6) | 770*d2c0bd84SPaolo Bonzini (ch->fs << 5) | ch->sync; 771*d2c0bd84SPaolo Bonzini break; 772*d2c0bd84SPaolo Bonzini 773*d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 774*d2c0bd84SPaolo Bonzini *value = ch->interrupts; 775*d2c0bd84SPaolo Bonzini break; 776*d2c0bd84SPaolo Bonzini 777*d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 778*d2c0bd84SPaolo Bonzini *value = ch->status; 779*d2c0bd84SPaolo Bonzini ch->status &= SYNC; 780*d2c0bd84SPaolo Bonzini if (!ch->omap_3_1_compatible_disable && ch->sibling) { 781*d2c0bd84SPaolo Bonzini *value |= (ch->sibling->status & 0x3f) << 6; 782*d2c0bd84SPaolo Bonzini ch->sibling->status &= SYNC; 783*d2c0bd84SPaolo Bonzini } 784*d2c0bd84SPaolo Bonzini qemu_irq_lower(ch->irq); 785*d2c0bd84SPaolo Bonzini break; 786*d2c0bd84SPaolo Bonzini 787*d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 788*d2c0bd84SPaolo Bonzini *value = ch->addr[0] & 0x0000ffff; 789*d2c0bd84SPaolo Bonzini break; 790*d2c0bd84SPaolo Bonzini 791*d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 792*d2c0bd84SPaolo Bonzini *value = ch->addr[0] >> 16; 793*d2c0bd84SPaolo Bonzini break; 794*d2c0bd84SPaolo Bonzini 795*d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 796*d2c0bd84SPaolo Bonzini *value = ch->addr[1] & 0x0000ffff; 797*d2c0bd84SPaolo Bonzini break; 798*d2c0bd84SPaolo Bonzini 799*d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 800*d2c0bd84SPaolo Bonzini *value = ch->addr[1] >> 16; 801*d2c0bd84SPaolo Bonzini break; 802*d2c0bd84SPaolo Bonzini 803*d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 804*d2c0bd84SPaolo Bonzini *value = ch->elements; 805*d2c0bd84SPaolo Bonzini break; 806*d2c0bd84SPaolo Bonzini 807*d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 808*d2c0bd84SPaolo Bonzini *value = ch->frames; 809*d2c0bd84SPaolo Bonzini break; 810*d2c0bd84SPaolo Bonzini 811*d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 812*d2c0bd84SPaolo Bonzini *value = ch->frame_index[0]; 813*d2c0bd84SPaolo Bonzini break; 814*d2c0bd84SPaolo Bonzini 815*d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 816*d2c0bd84SPaolo Bonzini *value = ch->element_index[0]; 817*d2c0bd84SPaolo Bonzini break; 818*d2c0bd84SPaolo Bonzini 819*d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 820*d2c0bd84SPaolo Bonzini if (ch->omap_3_1_compatible_disable) 821*d2c0bd84SPaolo Bonzini *value = ch->active_set.src & 0xffff; /* CSAC */ 822*d2c0bd84SPaolo Bonzini else 823*d2c0bd84SPaolo Bonzini *value = ch->cpc; 824*d2c0bd84SPaolo Bonzini break; 825*d2c0bd84SPaolo Bonzini 826*d2c0bd84SPaolo Bonzini case 0x1a: /* DMA_CDAC */ 827*d2c0bd84SPaolo Bonzini *value = ch->active_set.dest & 0xffff; /* CDAC */ 828*d2c0bd84SPaolo Bonzini break; 829*d2c0bd84SPaolo Bonzini 830*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 831*d2c0bd84SPaolo Bonzini *value = ch->element_index[1]; 832*d2c0bd84SPaolo Bonzini break; 833*d2c0bd84SPaolo Bonzini 834*d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 835*d2c0bd84SPaolo Bonzini *value = ch->frame_index[1]; 836*d2c0bd84SPaolo Bonzini break; 837*d2c0bd84SPaolo Bonzini 838*d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 839*d2c0bd84SPaolo Bonzini *value = ch->color & 0xffff; 840*d2c0bd84SPaolo Bonzini break; 841*d2c0bd84SPaolo Bonzini 842*d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 843*d2c0bd84SPaolo Bonzini *value = ch->color >> 16; 844*d2c0bd84SPaolo Bonzini break; 845*d2c0bd84SPaolo Bonzini 846*d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 847*d2c0bd84SPaolo Bonzini *value = (ch->bs << 2) | 848*d2c0bd84SPaolo Bonzini (ch->transparent_copy << 1) | 849*d2c0bd84SPaolo Bonzini ch->constant_fill; 850*d2c0bd84SPaolo Bonzini break; 851*d2c0bd84SPaolo Bonzini 852*d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 853*d2c0bd84SPaolo Bonzini *value = (ch->link_enabled << 15) | 854*d2c0bd84SPaolo Bonzini (ch->link_next_ch & 0xf); 855*d2c0bd84SPaolo Bonzini break; 856*d2c0bd84SPaolo Bonzini 857*d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 858*d2c0bd84SPaolo Bonzini *value = (ch->interleave_disabled << 15) | 859*d2c0bd84SPaolo Bonzini ch->type; 860*d2c0bd84SPaolo Bonzini break; 861*d2c0bd84SPaolo Bonzini 862*d2c0bd84SPaolo Bonzini default: 863*d2c0bd84SPaolo Bonzini return 1; 864*d2c0bd84SPaolo Bonzini } 865*d2c0bd84SPaolo Bonzini return 0; 866*d2c0bd84SPaolo Bonzini } 867*d2c0bd84SPaolo Bonzini 868*d2c0bd84SPaolo Bonzini static int omap_dma_ch_reg_write(struct omap_dma_s *s, 869*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch, int reg, uint16_t value) 870*d2c0bd84SPaolo Bonzini { 871*d2c0bd84SPaolo Bonzini switch (reg) { 872*d2c0bd84SPaolo Bonzini case 0x00: /* SYS_DMA_CSDP_CH0 */ 873*d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 874*d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 875*d2c0bd84SPaolo Bonzini ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); 876*d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 877*d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 878*d2c0bd84SPaolo Bonzini ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); 879*d2c0bd84SPaolo Bonzini ch->data_type = 1 << (value & 3); 880*d2c0bd84SPaolo Bonzini if (ch->port[0] >= __omap_dma_port_last) 881*d2c0bd84SPaolo Bonzini printf("%s: invalid DMA port %i\n", __FUNCTION__, 882*d2c0bd84SPaolo Bonzini ch->port[0]); 883*d2c0bd84SPaolo Bonzini if (ch->port[1] >= __omap_dma_port_last) 884*d2c0bd84SPaolo Bonzini printf("%s: invalid DMA port %i\n", __FUNCTION__, 885*d2c0bd84SPaolo Bonzini ch->port[1]); 886*d2c0bd84SPaolo Bonzini if ((value & 3) == 3) 887*d2c0bd84SPaolo Bonzini printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 888*d2c0bd84SPaolo Bonzini break; 889*d2c0bd84SPaolo Bonzini 890*d2c0bd84SPaolo Bonzini case 0x02: /* SYS_DMA_CCR_CH0 */ 891*d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 892*d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 893*d2c0bd84SPaolo Bonzini ch->end_prog = (value & 0x0800) >> 11; 894*d2c0bd84SPaolo Bonzini if (s->model >= omap_dma_3_2) 895*d2c0bd84SPaolo Bonzini ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; 896*d2c0bd84SPaolo Bonzini ch->repeat = (value & 0x0200) >> 9; 897*d2c0bd84SPaolo Bonzini ch->auto_init = (value & 0x0100) >> 8; 898*d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 899*d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 900*d2c0bd84SPaolo Bonzini ch->sync = value & 0x001f; 901*d2c0bd84SPaolo Bonzini 902*d2c0bd84SPaolo Bonzini if (value & 0x0080) 903*d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 904*d2c0bd84SPaolo Bonzini else 905*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 906*d2c0bd84SPaolo Bonzini 907*d2c0bd84SPaolo Bonzini if (ch->end_prog) 908*d2c0bd84SPaolo Bonzini omap_dma_channel_end_prog(s, ch); 909*d2c0bd84SPaolo Bonzini 910*d2c0bd84SPaolo Bonzini break; 911*d2c0bd84SPaolo Bonzini 912*d2c0bd84SPaolo Bonzini case 0x04: /* SYS_DMA_CICR_CH0 */ 913*d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x3f; 914*d2c0bd84SPaolo Bonzini break; 915*d2c0bd84SPaolo Bonzini 916*d2c0bd84SPaolo Bonzini case 0x06: /* SYS_DMA_CSR_CH0 */ 917*d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 918*d2c0bd84SPaolo Bonzini break; 919*d2c0bd84SPaolo Bonzini 920*d2c0bd84SPaolo Bonzini case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 921*d2c0bd84SPaolo Bonzini ch->addr[0] &= 0xffff0000; 922*d2c0bd84SPaolo Bonzini ch->addr[0] |= value; 923*d2c0bd84SPaolo Bonzini break; 924*d2c0bd84SPaolo Bonzini 925*d2c0bd84SPaolo Bonzini case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 926*d2c0bd84SPaolo Bonzini ch->addr[0] &= 0x0000ffff; 927*d2c0bd84SPaolo Bonzini ch->addr[0] |= (uint32_t) value << 16; 928*d2c0bd84SPaolo Bonzini break; 929*d2c0bd84SPaolo Bonzini 930*d2c0bd84SPaolo Bonzini case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 931*d2c0bd84SPaolo Bonzini ch->addr[1] &= 0xffff0000; 932*d2c0bd84SPaolo Bonzini ch->addr[1] |= value; 933*d2c0bd84SPaolo Bonzini break; 934*d2c0bd84SPaolo Bonzini 935*d2c0bd84SPaolo Bonzini case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 936*d2c0bd84SPaolo Bonzini ch->addr[1] &= 0x0000ffff; 937*d2c0bd84SPaolo Bonzini ch->addr[1] |= (uint32_t) value << 16; 938*d2c0bd84SPaolo Bonzini break; 939*d2c0bd84SPaolo Bonzini 940*d2c0bd84SPaolo Bonzini case 0x10: /* SYS_DMA_CEN_CH0 */ 941*d2c0bd84SPaolo Bonzini ch->elements = value; 942*d2c0bd84SPaolo Bonzini break; 943*d2c0bd84SPaolo Bonzini 944*d2c0bd84SPaolo Bonzini case 0x12: /* SYS_DMA_CFN_CH0 */ 945*d2c0bd84SPaolo Bonzini ch->frames = value; 946*d2c0bd84SPaolo Bonzini break; 947*d2c0bd84SPaolo Bonzini 948*d2c0bd84SPaolo Bonzini case 0x14: /* SYS_DMA_CFI_CH0 */ 949*d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int16_t) value; 950*d2c0bd84SPaolo Bonzini break; 951*d2c0bd84SPaolo Bonzini 952*d2c0bd84SPaolo Bonzini case 0x16: /* SYS_DMA_CEI_CH0 */ 953*d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 954*d2c0bd84SPaolo Bonzini break; 955*d2c0bd84SPaolo Bonzini 956*d2c0bd84SPaolo Bonzini case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 957*d2c0bd84SPaolo Bonzini OMAP_RO_REG((hwaddr) reg); 958*d2c0bd84SPaolo Bonzini break; 959*d2c0bd84SPaolo Bonzini 960*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA_CDEI */ 961*d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 962*d2c0bd84SPaolo Bonzini break; 963*d2c0bd84SPaolo Bonzini 964*d2c0bd84SPaolo Bonzini case 0x1e: /* DMA_CDFI */ 965*d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int16_t) value; 966*d2c0bd84SPaolo Bonzini break; 967*d2c0bd84SPaolo Bonzini 968*d2c0bd84SPaolo Bonzini case 0x20: /* DMA_COLOR_L */ 969*d2c0bd84SPaolo Bonzini ch->color &= 0xffff0000; 970*d2c0bd84SPaolo Bonzini ch->color |= value; 971*d2c0bd84SPaolo Bonzini break; 972*d2c0bd84SPaolo Bonzini 973*d2c0bd84SPaolo Bonzini case 0x22: /* DMA_COLOR_U */ 974*d2c0bd84SPaolo Bonzini ch->color &= 0xffff; 975*d2c0bd84SPaolo Bonzini ch->color |= value << 16; 976*d2c0bd84SPaolo Bonzini break; 977*d2c0bd84SPaolo Bonzini 978*d2c0bd84SPaolo Bonzini case 0x24: /* DMA_CCR2 */ 979*d2c0bd84SPaolo Bonzini ch->bs = (value >> 2) & 0x1; 980*d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 1) & 0x1; 981*d2c0bd84SPaolo Bonzini ch->constant_fill = value & 0x1; 982*d2c0bd84SPaolo Bonzini break; 983*d2c0bd84SPaolo Bonzini 984*d2c0bd84SPaolo Bonzini case 0x28: /* DMA_CLNK_CTRL */ 985*d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 986*d2c0bd84SPaolo Bonzini if (value & (1 << 14)) { /* Stop_Lnk */ 987*d2c0bd84SPaolo Bonzini ch->link_enabled = 0; 988*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 989*d2c0bd84SPaolo Bonzini } 990*d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 991*d2c0bd84SPaolo Bonzini break; 992*d2c0bd84SPaolo Bonzini 993*d2c0bd84SPaolo Bonzini case 0x2a: /* DMA_LCH_CTRL */ 994*d2c0bd84SPaolo Bonzini ch->interleave_disabled = (value >> 15) & 0x1; 995*d2c0bd84SPaolo Bonzini ch->type = value & 0xf; 996*d2c0bd84SPaolo Bonzini break; 997*d2c0bd84SPaolo Bonzini 998*d2c0bd84SPaolo Bonzini default: 999*d2c0bd84SPaolo Bonzini return 1; 1000*d2c0bd84SPaolo Bonzini } 1001*d2c0bd84SPaolo Bonzini return 0; 1002*d2c0bd84SPaolo Bonzini } 1003*d2c0bd84SPaolo Bonzini 1004*d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1005*d2c0bd84SPaolo Bonzini uint16_t value) 1006*d2c0bd84SPaolo Bonzini { 1007*d2c0bd84SPaolo Bonzini switch (offset) { 1008*d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1009*d2c0bd84SPaolo Bonzini s->brust_f2 = (value >> 14) & 0x3; 1010*d2c0bd84SPaolo Bonzini s->pack_f2 = (value >> 13) & 0x1; 1011*d2c0bd84SPaolo Bonzini s->data_type_f2 = (1 << ((value >> 11) & 0x3)); 1012*d2c0bd84SPaolo Bonzini s->brust_f1 = (value >> 7) & 0x3; 1013*d2c0bd84SPaolo Bonzini s->pack_f1 = (value >> 6) & 0x1; 1014*d2c0bd84SPaolo Bonzini s->data_type_f1 = (1 << ((value >> 0) & 0x3)); 1015*d2c0bd84SPaolo Bonzini break; 1016*d2c0bd84SPaolo Bonzini 1017*d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1018*d2c0bd84SPaolo Bonzini s->mode_f2 = (value >> 14) & 0x3; 1019*d2c0bd84SPaolo Bonzini s->mode_f1 = (value >> 12) & 0x3; 1020*d2c0bd84SPaolo Bonzini s->end_prog = (value >> 11) & 0x1; 1021*d2c0bd84SPaolo Bonzini s->omap_3_1_compatible_disable = (value >> 10) & 0x1; 1022*d2c0bd84SPaolo Bonzini s->repeat = (value >> 9) & 0x1; 1023*d2c0bd84SPaolo Bonzini s->auto_init = (value >> 8) & 0x1; 1024*d2c0bd84SPaolo Bonzini s->running = (value >> 7) & 0x1; 1025*d2c0bd84SPaolo Bonzini s->priority = (value >> 6) & 0x1; 1026*d2c0bd84SPaolo Bonzini s->bs = (value >> 4) & 0x1; 1027*d2c0bd84SPaolo Bonzini break; 1028*d2c0bd84SPaolo Bonzini 1029*d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1030*d2c0bd84SPaolo Bonzini s->dst = (value >> 8) & 0x1; 1031*d2c0bd84SPaolo Bonzini s->src = ((value >> 6) & 0x3) << 1; 1032*d2c0bd84SPaolo Bonzini s->condition = 0; 1033*d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1034*d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1035*d2c0bd84SPaolo Bonzini s->dual = value & 1; 1036*d2c0bd84SPaolo Bonzini break; 1037*d2c0bd84SPaolo Bonzini 1038*d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1039*d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1040*d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1041*d2c0bd84SPaolo Bonzini break; 1042*d2c0bd84SPaolo Bonzini 1043*d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1044*d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 1045*d2c0bd84SPaolo Bonzini s->src_f1_top |= value << 16; 1046*d2c0bd84SPaolo Bonzini break; 1047*d2c0bd84SPaolo Bonzini 1048*d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1049*d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1050*d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1051*d2c0bd84SPaolo Bonzini break; 1052*d2c0bd84SPaolo Bonzini 1053*d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1054*d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 1055*d2c0bd84SPaolo Bonzini s->src_f1_bottom |= (uint32_t) value << 16; 1056*d2c0bd84SPaolo Bonzini break; 1057*d2c0bd84SPaolo Bonzini 1058*d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1059*d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1060*d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1061*d2c0bd84SPaolo Bonzini break; 1062*d2c0bd84SPaolo Bonzini 1063*d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1064*d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 1065*d2c0bd84SPaolo Bonzini s->src_f2_top |= (uint32_t) value << 16; 1066*d2c0bd84SPaolo Bonzini break; 1067*d2c0bd84SPaolo Bonzini 1068*d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1069*d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1070*d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1071*d2c0bd84SPaolo Bonzini break; 1072*d2c0bd84SPaolo Bonzini 1073*d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1074*d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 1075*d2c0bd84SPaolo Bonzini s->src_f2_bottom |= (uint32_t) value << 16; 1076*d2c0bd84SPaolo Bonzini break; 1077*d2c0bd84SPaolo Bonzini 1078*d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1079*d2c0bd84SPaolo Bonzini s->element_index_f1 = value; 1080*d2c0bd84SPaolo Bonzini break; 1081*d2c0bd84SPaolo Bonzini 1082*d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1083*d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0xffff0000; 1084*d2c0bd84SPaolo Bonzini s->frame_index_f1 |= 0x0000ffff & value; 1085*d2c0bd84SPaolo Bonzini break; 1086*d2c0bd84SPaolo Bonzini 1087*d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1088*d2c0bd84SPaolo Bonzini s->frame_index_f1 &= 0x0000ffff; 1089*d2c0bd84SPaolo Bonzini s->frame_index_f1 |= (uint32_t) value << 16; 1090*d2c0bd84SPaolo Bonzini break; 1091*d2c0bd84SPaolo Bonzini 1092*d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1093*d2c0bd84SPaolo Bonzini s->element_index_f2 = value; 1094*d2c0bd84SPaolo Bonzini break; 1095*d2c0bd84SPaolo Bonzini 1096*d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1097*d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0xffff0000; 1098*d2c0bd84SPaolo Bonzini s->frame_index_f2 |= 0x0000ffff & value; 1099*d2c0bd84SPaolo Bonzini break; 1100*d2c0bd84SPaolo Bonzini 1101*d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1102*d2c0bd84SPaolo Bonzini s->frame_index_f2 &= 0x0000ffff; 1103*d2c0bd84SPaolo Bonzini s->frame_index_f2 |= (uint32_t) value << 16; 1104*d2c0bd84SPaolo Bonzini break; 1105*d2c0bd84SPaolo Bonzini 1106*d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1107*d2c0bd84SPaolo Bonzini s->elements_f1 = value; 1108*d2c0bd84SPaolo Bonzini break; 1109*d2c0bd84SPaolo Bonzini 1110*d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1111*d2c0bd84SPaolo Bonzini s->frames_f1 = value; 1112*d2c0bd84SPaolo Bonzini break; 1113*d2c0bd84SPaolo Bonzini 1114*d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1115*d2c0bd84SPaolo Bonzini s->elements_f2 = value; 1116*d2c0bd84SPaolo Bonzini break; 1117*d2c0bd84SPaolo Bonzini 1118*d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1119*d2c0bd84SPaolo Bonzini s->frames_f2 = value; 1120*d2c0bd84SPaolo Bonzini break; 1121*d2c0bd84SPaolo Bonzini 1122*d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1123*d2c0bd84SPaolo Bonzini s->lch_type = value & 0xf; 1124*d2c0bd84SPaolo Bonzini break; 1125*d2c0bd84SPaolo Bonzini 1126*d2c0bd84SPaolo Bonzini default: 1127*d2c0bd84SPaolo Bonzini return 1; 1128*d2c0bd84SPaolo Bonzini } 1129*d2c0bd84SPaolo Bonzini return 0; 1130*d2c0bd84SPaolo Bonzini } 1131*d2c0bd84SPaolo Bonzini 1132*d2c0bd84SPaolo Bonzini static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1133*d2c0bd84SPaolo Bonzini uint16_t *ret) 1134*d2c0bd84SPaolo Bonzini { 1135*d2c0bd84SPaolo Bonzini switch (offset) { 1136*d2c0bd84SPaolo Bonzini case 0xbc0: /* DMA_LCD_CSDP */ 1137*d2c0bd84SPaolo Bonzini *ret = (s->brust_f2 << 14) | 1138*d2c0bd84SPaolo Bonzini (s->pack_f2 << 13) | 1139*d2c0bd84SPaolo Bonzini ((s->data_type_f2 >> 1) << 11) | 1140*d2c0bd84SPaolo Bonzini (s->brust_f1 << 7) | 1141*d2c0bd84SPaolo Bonzini (s->pack_f1 << 6) | 1142*d2c0bd84SPaolo Bonzini ((s->data_type_f1 >> 1) << 0); 1143*d2c0bd84SPaolo Bonzini break; 1144*d2c0bd84SPaolo Bonzini 1145*d2c0bd84SPaolo Bonzini case 0xbc2: /* DMA_LCD_CCR */ 1146*d2c0bd84SPaolo Bonzini *ret = (s->mode_f2 << 14) | 1147*d2c0bd84SPaolo Bonzini (s->mode_f1 << 12) | 1148*d2c0bd84SPaolo Bonzini (s->end_prog << 11) | 1149*d2c0bd84SPaolo Bonzini (s->omap_3_1_compatible_disable << 10) | 1150*d2c0bd84SPaolo Bonzini (s->repeat << 9) | 1151*d2c0bd84SPaolo Bonzini (s->auto_init << 8) | 1152*d2c0bd84SPaolo Bonzini (s->running << 7) | 1153*d2c0bd84SPaolo Bonzini (s->priority << 6) | 1154*d2c0bd84SPaolo Bonzini (s->bs << 4); 1155*d2c0bd84SPaolo Bonzini break; 1156*d2c0bd84SPaolo Bonzini 1157*d2c0bd84SPaolo Bonzini case 0xbc4: /* DMA_LCD_CTRL */ 1158*d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1159*d2c0bd84SPaolo Bonzini *ret = (s->dst << 8) | 1160*d2c0bd84SPaolo Bonzini ((s->src & 0x6) << 5) | 1161*d2c0bd84SPaolo Bonzini (s->condition << 3) | 1162*d2c0bd84SPaolo Bonzini (s->interrupts << 1) | 1163*d2c0bd84SPaolo Bonzini s->dual; 1164*d2c0bd84SPaolo Bonzini break; 1165*d2c0bd84SPaolo Bonzini 1166*d2c0bd84SPaolo Bonzini case 0xbc8: /* TOP_B1_L */ 1167*d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1168*d2c0bd84SPaolo Bonzini break; 1169*d2c0bd84SPaolo Bonzini 1170*d2c0bd84SPaolo Bonzini case 0xbca: /* TOP_B1_U */ 1171*d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1172*d2c0bd84SPaolo Bonzini break; 1173*d2c0bd84SPaolo Bonzini 1174*d2c0bd84SPaolo Bonzini case 0xbcc: /* BOT_B1_L */ 1175*d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1176*d2c0bd84SPaolo Bonzini break; 1177*d2c0bd84SPaolo Bonzini 1178*d2c0bd84SPaolo Bonzini case 0xbce: /* BOT_B1_U */ 1179*d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1180*d2c0bd84SPaolo Bonzini break; 1181*d2c0bd84SPaolo Bonzini 1182*d2c0bd84SPaolo Bonzini case 0xbd0: /* TOP_B2_L */ 1183*d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1184*d2c0bd84SPaolo Bonzini break; 1185*d2c0bd84SPaolo Bonzini 1186*d2c0bd84SPaolo Bonzini case 0xbd2: /* TOP_B2_U */ 1187*d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1188*d2c0bd84SPaolo Bonzini break; 1189*d2c0bd84SPaolo Bonzini 1190*d2c0bd84SPaolo Bonzini case 0xbd4: /* BOT_B2_L */ 1191*d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1192*d2c0bd84SPaolo Bonzini break; 1193*d2c0bd84SPaolo Bonzini 1194*d2c0bd84SPaolo Bonzini case 0xbd6: /* BOT_B2_U */ 1195*d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1196*d2c0bd84SPaolo Bonzini break; 1197*d2c0bd84SPaolo Bonzini 1198*d2c0bd84SPaolo Bonzini case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1199*d2c0bd84SPaolo Bonzini *ret = s->element_index_f1; 1200*d2c0bd84SPaolo Bonzini break; 1201*d2c0bd84SPaolo Bonzini 1202*d2c0bd84SPaolo Bonzini case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1203*d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 & 0xffff; 1204*d2c0bd84SPaolo Bonzini break; 1205*d2c0bd84SPaolo Bonzini 1206*d2c0bd84SPaolo Bonzini case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1207*d2c0bd84SPaolo Bonzini *ret = s->frame_index_f1 >> 16; 1208*d2c0bd84SPaolo Bonzini break; 1209*d2c0bd84SPaolo Bonzini 1210*d2c0bd84SPaolo Bonzini case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1211*d2c0bd84SPaolo Bonzini *ret = s->element_index_f2; 1212*d2c0bd84SPaolo Bonzini break; 1213*d2c0bd84SPaolo Bonzini 1214*d2c0bd84SPaolo Bonzini case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1215*d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 & 0xffff; 1216*d2c0bd84SPaolo Bonzini break; 1217*d2c0bd84SPaolo Bonzini 1218*d2c0bd84SPaolo Bonzini case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1219*d2c0bd84SPaolo Bonzini *ret = s->frame_index_f2 >> 16; 1220*d2c0bd84SPaolo Bonzini break; 1221*d2c0bd84SPaolo Bonzini 1222*d2c0bd84SPaolo Bonzini case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1223*d2c0bd84SPaolo Bonzini *ret = s->elements_f1; 1224*d2c0bd84SPaolo Bonzini break; 1225*d2c0bd84SPaolo Bonzini 1226*d2c0bd84SPaolo Bonzini case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1227*d2c0bd84SPaolo Bonzini *ret = s->frames_f1; 1228*d2c0bd84SPaolo Bonzini break; 1229*d2c0bd84SPaolo Bonzini 1230*d2c0bd84SPaolo Bonzini case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1231*d2c0bd84SPaolo Bonzini *ret = s->elements_f2; 1232*d2c0bd84SPaolo Bonzini break; 1233*d2c0bd84SPaolo Bonzini 1234*d2c0bd84SPaolo Bonzini case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1235*d2c0bd84SPaolo Bonzini *ret = s->frames_f2; 1236*d2c0bd84SPaolo Bonzini break; 1237*d2c0bd84SPaolo Bonzini 1238*d2c0bd84SPaolo Bonzini case 0xbea: /* DMA_LCD_LCH_CTRL */ 1239*d2c0bd84SPaolo Bonzini *ret = s->lch_type; 1240*d2c0bd84SPaolo Bonzini break; 1241*d2c0bd84SPaolo Bonzini 1242*d2c0bd84SPaolo Bonzini default: 1243*d2c0bd84SPaolo Bonzini return 1; 1244*d2c0bd84SPaolo Bonzini } 1245*d2c0bd84SPaolo Bonzini return 0; 1246*d2c0bd84SPaolo Bonzini } 1247*d2c0bd84SPaolo Bonzini 1248*d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, 1249*d2c0bd84SPaolo Bonzini uint16_t value) 1250*d2c0bd84SPaolo Bonzini { 1251*d2c0bd84SPaolo Bonzini switch (offset) { 1252*d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1253*d2c0bd84SPaolo Bonzini s->src = (value & 0x40) ? imif : emiff; 1254*d2c0bd84SPaolo Bonzini s->condition = 0; 1255*d2c0bd84SPaolo Bonzini /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1256*d2c0bd84SPaolo Bonzini s->interrupts = (value >> 1) & 1; 1257*d2c0bd84SPaolo Bonzini s->dual = value & 1; 1258*d2c0bd84SPaolo Bonzini break; 1259*d2c0bd84SPaolo Bonzini 1260*d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1261*d2c0bd84SPaolo Bonzini s->src_f1_top &= 0xffff0000; 1262*d2c0bd84SPaolo Bonzini s->src_f1_top |= 0x0000ffff & value; 1263*d2c0bd84SPaolo Bonzini break; 1264*d2c0bd84SPaolo Bonzini 1265*d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1266*d2c0bd84SPaolo Bonzini s->src_f1_top &= 0x0000ffff; 1267*d2c0bd84SPaolo Bonzini s->src_f1_top |= value << 16; 1268*d2c0bd84SPaolo Bonzini break; 1269*d2c0bd84SPaolo Bonzini 1270*d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1271*d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0xffff0000; 1272*d2c0bd84SPaolo Bonzini s->src_f1_bottom |= 0x0000ffff & value; 1273*d2c0bd84SPaolo Bonzini break; 1274*d2c0bd84SPaolo Bonzini 1275*d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1276*d2c0bd84SPaolo Bonzini s->src_f1_bottom &= 0x0000ffff; 1277*d2c0bd84SPaolo Bonzini s->src_f1_bottom |= value << 16; 1278*d2c0bd84SPaolo Bonzini break; 1279*d2c0bd84SPaolo Bonzini 1280*d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1281*d2c0bd84SPaolo Bonzini s->src_f2_top &= 0xffff0000; 1282*d2c0bd84SPaolo Bonzini s->src_f2_top |= 0x0000ffff & value; 1283*d2c0bd84SPaolo Bonzini break; 1284*d2c0bd84SPaolo Bonzini 1285*d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1286*d2c0bd84SPaolo Bonzini s->src_f2_top &= 0x0000ffff; 1287*d2c0bd84SPaolo Bonzini s->src_f2_top |= value << 16; 1288*d2c0bd84SPaolo Bonzini break; 1289*d2c0bd84SPaolo Bonzini 1290*d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1291*d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0xffff0000; 1292*d2c0bd84SPaolo Bonzini s->src_f2_bottom |= 0x0000ffff & value; 1293*d2c0bd84SPaolo Bonzini break; 1294*d2c0bd84SPaolo Bonzini 1295*d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1296*d2c0bd84SPaolo Bonzini s->src_f2_bottom &= 0x0000ffff; 1297*d2c0bd84SPaolo Bonzini s->src_f2_bottom |= value << 16; 1298*d2c0bd84SPaolo Bonzini break; 1299*d2c0bd84SPaolo Bonzini 1300*d2c0bd84SPaolo Bonzini default: 1301*d2c0bd84SPaolo Bonzini return 1; 1302*d2c0bd84SPaolo Bonzini } 1303*d2c0bd84SPaolo Bonzini return 0; 1304*d2c0bd84SPaolo Bonzini } 1305*d2c0bd84SPaolo Bonzini 1306*d2c0bd84SPaolo Bonzini static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, 1307*d2c0bd84SPaolo Bonzini uint16_t *ret) 1308*d2c0bd84SPaolo Bonzini { 1309*d2c0bd84SPaolo Bonzini int i; 1310*d2c0bd84SPaolo Bonzini 1311*d2c0bd84SPaolo Bonzini switch (offset) { 1312*d2c0bd84SPaolo Bonzini case 0x300: /* SYS_DMA_LCD_CTRL */ 1313*d2c0bd84SPaolo Bonzini i = s->condition; 1314*d2c0bd84SPaolo Bonzini s->condition = 0; 1315*d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq); 1316*d2c0bd84SPaolo Bonzini *ret = ((s->src == imif) << 6) | (i << 3) | 1317*d2c0bd84SPaolo Bonzini (s->interrupts << 1) | s->dual; 1318*d2c0bd84SPaolo Bonzini break; 1319*d2c0bd84SPaolo Bonzini 1320*d2c0bd84SPaolo Bonzini case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1321*d2c0bd84SPaolo Bonzini *ret = s->src_f1_top & 0xffff; 1322*d2c0bd84SPaolo Bonzini break; 1323*d2c0bd84SPaolo Bonzini 1324*d2c0bd84SPaolo Bonzini case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1325*d2c0bd84SPaolo Bonzini *ret = s->src_f1_top >> 16; 1326*d2c0bd84SPaolo Bonzini break; 1327*d2c0bd84SPaolo Bonzini 1328*d2c0bd84SPaolo Bonzini case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1329*d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom & 0xffff; 1330*d2c0bd84SPaolo Bonzini break; 1331*d2c0bd84SPaolo Bonzini 1332*d2c0bd84SPaolo Bonzini case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1333*d2c0bd84SPaolo Bonzini *ret = s->src_f1_bottom >> 16; 1334*d2c0bd84SPaolo Bonzini break; 1335*d2c0bd84SPaolo Bonzini 1336*d2c0bd84SPaolo Bonzini case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1337*d2c0bd84SPaolo Bonzini *ret = s->src_f2_top & 0xffff; 1338*d2c0bd84SPaolo Bonzini break; 1339*d2c0bd84SPaolo Bonzini 1340*d2c0bd84SPaolo Bonzini case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1341*d2c0bd84SPaolo Bonzini *ret = s->src_f2_top >> 16; 1342*d2c0bd84SPaolo Bonzini break; 1343*d2c0bd84SPaolo Bonzini 1344*d2c0bd84SPaolo Bonzini case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1345*d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom & 0xffff; 1346*d2c0bd84SPaolo Bonzini break; 1347*d2c0bd84SPaolo Bonzini 1348*d2c0bd84SPaolo Bonzini case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1349*d2c0bd84SPaolo Bonzini *ret = s->src_f2_bottom >> 16; 1350*d2c0bd84SPaolo Bonzini break; 1351*d2c0bd84SPaolo Bonzini 1352*d2c0bd84SPaolo Bonzini default: 1353*d2c0bd84SPaolo Bonzini return 1; 1354*d2c0bd84SPaolo Bonzini } 1355*d2c0bd84SPaolo Bonzini return 0; 1356*d2c0bd84SPaolo Bonzini } 1357*d2c0bd84SPaolo Bonzini 1358*d2c0bd84SPaolo Bonzini static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) 1359*d2c0bd84SPaolo Bonzini { 1360*d2c0bd84SPaolo Bonzini switch (offset) { 1361*d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1362*d2c0bd84SPaolo Bonzini s->gcr = value; 1363*d2c0bd84SPaolo Bonzini break; 1364*d2c0bd84SPaolo Bonzini 1365*d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1366*d2c0bd84SPaolo Bonzini if (value & 0x8) 1367*d2c0bd84SPaolo Bonzini omap_dma_disable_3_1_mapping(s); 1368*d2c0bd84SPaolo Bonzini else 1369*d2c0bd84SPaolo Bonzini omap_dma_enable_3_1_mapping(s); 1370*d2c0bd84SPaolo Bonzini break; 1371*d2c0bd84SPaolo Bonzini 1372*d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1373*d2c0bd84SPaolo Bonzini if (value & 0x1) 1374*d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1375*d2c0bd84SPaolo Bonzini break; 1376*d2c0bd84SPaolo Bonzini 1377*d2c0bd84SPaolo Bonzini default: 1378*d2c0bd84SPaolo Bonzini return 1; 1379*d2c0bd84SPaolo Bonzini } 1380*d2c0bd84SPaolo Bonzini return 0; 1381*d2c0bd84SPaolo Bonzini } 1382*d2c0bd84SPaolo Bonzini 1383*d2c0bd84SPaolo Bonzini static int omap_dma_sys_read(struct omap_dma_s *s, int offset, 1384*d2c0bd84SPaolo Bonzini uint16_t *ret) 1385*d2c0bd84SPaolo Bonzini { 1386*d2c0bd84SPaolo Bonzini switch (offset) { 1387*d2c0bd84SPaolo Bonzini case 0x400: /* SYS_DMA_GCR */ 1388*d2c0bd84SPaolo Bonzini *ret = s->gcr; 1389*d2c0bd84SPaolo Bonzini break; 1390*d2c0bd84SPaolo Bonzini 1391*d2c0bd84SPaolo Bonzini case 0x404: /* DMA_GSCR */ 1392*d2c0bd84SPaolo Bonzini *ret = s->omap_3_1_mapping_disabled << 3; 1393*d2c0bd84SPaolo Bonzini break; 1394*d2c0bd84SPaolo Bonzini 1395*d2c0bd84SPaolo Bonzini case 0x408: /* DMA_GRST */ 1396*d2c0bd84SPaolo Bonzini *ret = 0; 1397*d2c0bd84SPaolo Bonzini break; 1398*d2c0bd84SPaolo Bonzini 1399*d2c0bd84SPaolo Bonzini case 0x442: /* DMA_HW_ID */ 1400*d2c0bd84SPaolo Bonzini case 0x444: /* DMA_PCh2_ID */ 1401*d2c0bd84SPaolo Bonzini case 0x446: /* DMA_PCh0_ID */ 1402*d2c0bd84SPaolo Bonzini case 0x448: /* DMA_PCh1_ID */ 1403*d2c0bd84SPaolo Bonzini case 0x44a: /* DMA_PChG_ID */ 1404*d2c0bd84SPaolo Bonzini case 0x44c: /* DMA_PChD_ID */ 1405*d2c0bd84SPaolo Bonzini *ret = 1; 1406*d2c0bd84SPaolo Bonzini break; 1407*d2c0bd84SPaolo Bonzini 1408*d2c0bd84SPaolo Bonzini case 0x44e: /* DMA_CAPS_0_U */ 1409*d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 16) & 0xffff; 1410*d2c0bd84SPaolo Bonzini break; 1411*d2c0bd84SPaolo Bonzini case 0x450: /* DMA_CAPS_0_L */ 1412*d2c0bd84SPaolo Bonzini *ret = (s->caps[0] >> 0) & 0xffff; 1413*d2c0bd84SPaolo Bonzini break; 1414*d2c0bd84SPaolo Bonzini 1415*d2c0bd84SPaolo Bonzini case 0x452: /* DMA_CAPS_1_U */ 1416*d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 16) & 0xffff; 1417*d2c0bd84SPaolo Bonzini break; 1418*d2c0bd84SPaolo Bonzini case 0x454: /* DMA_CAPS_1_L */ 1419*d2c0bd84SPaolo Bonzini *ret = (s->caps[1] >> 0) & 0xffff; 1420*d2c0bd84SPaolo Bonzini break; 1421*d2c0bd84SPaolo Bonzini 1422*d2c0bd84SPaolo Bonzini case 0x456: /* DMA_CAPS_2 */ 1423*d2c0bd84SPaolo Bonzini *ret = s->caps[2]; 1424*d2c0bd84SPaolo Bonzini break; 1425*d2c0bd84SPaolo Bonzini 1426*d2c0bd84SPaolo Bonzini case 0x458: /* DMA_CAPS_3 */ 1427*d2c0bd84SPaolo Bonzini *ret = s->caps[3]; 1428*d2c0bd84SPaolo Bonzini break; 1429*d2c0bd84SPaolo Bonzini 1430*d2c0bd84SPaolo Bonzini case 0x45a: /* DMA_CAPS_4 */ 1431*d2c0bd84SPaolo Bonzini *ret = s->caps[4]; 1432*d2c0bd84SPaolo Bonzini break; 1433*d2c0bd84SPaolo Bonzini 1434*d2c0bd84SPaolo Bonzini case 0x460: /* DMA_PCh2_SR */ 1435*d2c0bd84SPaolo Bonzini case 0x480: /* DMA_PCh0_SR */ 1436*d2c0bd84SPaolo Bonzini case 0x482: /* DMA_PCh1_SR */ 1437*d2c0bd84SPaolo Bonzini case 0x4c0: /* DMA_PChD_SR_0 */ 1438*d2c0bd84SPaolo Bonzini printf("%s: Physical Channel Status Registers not implemented.\n", 1439*d2c0bd84SPaolo Bonzini __FUNCTION__); 1440*d2c0bd84SPaolo Bonzini *ret = 0xff; 1441*d2c0bd84SPaolo Bonzini break; 1442*d2c0bd84SPaolo Bonzini 1443*d2c0bd84SPaolo Bonzini default: 1444*d2c0bd84SPaolo Bonzini return 1; 1445*d2c0bd84SPaolo Bonzini } 1446*d2c0bd84SPaolo Bonzini return 0; 1447*d2c0bd84SPaolo Bonzini } 1448*d2c0bd84SPaolo Bonzini 1449*d2c0bd84SPaolo Bonzini static uint64_t omap_dma_read(void *opaque, hwaddr addr, 1450*d2c0bd84SPaolo Bonzini unsigned size) 1451*d2c0bd84SPaolo Bonzini { 1452*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1453*d2c0bd84SPaolo Bonzini int reg, ch; 1454*d2c0bd84SPaolo Bonzini uint16_t ret; 1455*d2c0bd84SPaolo Bonzini 1456*d2c0bd84SPaolo Bonzini if (size != 2) { 1457*d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1458*d2c0bd84SPaolo Bonzini } 1459*d2c0bd84SPaolo Bonzini 1460*d2c0bd84SPaolo Bonzini switch (addr) { 1461*d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1462*d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1463*d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) 1464*d2c0bd84SPaolo Bonzini break; 1465*d2c0bd84SPaolo Bonzini return ret; 1466*d2c0bd84SPaolo Bonzini } 1467*d2c0bd84SPaolo Bonzini /* Fall through. */ 1468*d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1469*d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1470*d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1471*d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) 1472*d2c0bd84SPaolo Bonzini break; 1473*d2c0bd84SPaolo Bonzini return ret; 1474*d2c0bd84SPaolo Bonzini 1475*d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1476*d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1477*d2c0bd84SPaolo Bonzini break; 1478*d2c0bd84SPaolo Bonzini /* Fall through. */ 1479*d2c0bd84SPaolo Bonzini case 0x400: 1480*d2c0bd84SPaolo Bonzini if (omap_dma_sys_read(s, addr, &ret)) 1481*d2c0bd84SPaolo Bonzini break; 1482*d2c0bd84SPaolo Bonzini return ret; 1483*d2c0bd84SPaolo Bonzini 1484*d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1485*d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1486*d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret)) 1487*d2c0bd84SPaolo Bonzini break; 1488*d2c0bd84SPaolo Bonzini return ret; 1489*d2c0bd84SPaolo Bonzini } 1490*d2c0bd84SPaolo Bonzini break; 1491*d2c0bd84SPaolo Bonzini } 1492*d2c0bd84SPaolo Bonzini 1493*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1494*d2c0bd84SPaolo Bonzini return 0; 1495*d2c0bd84SPaolo Bonzini } 1496*d2c0bd84SPaolo Bonzini 1497*d2c0bd84SPaolo Bonzini static void omap_dma_write(void *opaque, hwaddr addr, 1498*d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1499*d2c0bd84SPaolo Bonzini { 1500*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1501*d2c0bd84SPaolo Bonzini int reg, ch; 1502*d2c0bd84SPaolo Bonzini 1503*d2c0bd84SPaolo Bonzini if (size != 2) { 1504*d2c0bd84SPaolo Bonzini return omap_badwidth_write16(opaque, addr, value); 1505*d2c0bd84SPaolo Bonzini } 1506*d2c0bd84SPaolo Bonzini 1507*d2c0bd84SPaolo Bonzini switch (addr) { 1508*d2c0bd84SPaolo Bonzini case 0x300 ... 0x3fe: 1509*d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1510*d2c0bd84SPaolo Bonzini if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) 1511*d2c0bd84SPaolo Bonzini break; 1512*d2c0bd84SPaolo Bonzini return; 1513*d2c0bd84SPaolo Bonzini } 1514*d2c0bd84SPaolo Bonzini /* Fall through. */ 1515*d2c0bd84SPaolo Bonzini case 0x000 ... 0x2fe: 1516*d2c0bd84SPaolo Bonzini reg = addr & 0x3f; 1517*d2c0bd84SPaolo Bonzini ch = (addr >> 6) & 0x0f; 1518*d2c0bd84SPaolo Bonzini if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) 1519*d2c0bd84SPaolo Bonzini break; 1520*d2c0bd84SPaolo Bonzini return; 1521*d2c0bd84SPaolo Bonzini 1522*d2c0bd84SPaolo Bonzini case 0x404 ... 0x4fe: 1523*d2c0bd84SPaolo Bonzini if (s->model <= omap_dma_3_1) 1524*d2c0bd84SPaolo Bonzini break; 1525*d2c0bd84SPaolo Bonzini case 0x400: 1526*d2c0bd84SPaolo Bonzini /* Fall through. */ 1527*d2c0bd84SPaolo Bonzini if (omap_dma_sys_write(s, addr, value)) 1528*d2c0bd84SPaolo Bonzini break; 1529*d2c0bd84SPaolo Bonzini return; 1530*d2c0bd84SPaolo Bonzini 1531*d2c0bd84SPaolo Bonzini case 0xb00 ... 0xbfe: 1532*d2c0bd84SPaolo Bonzini if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1533*d2c0bd84SPaolo Bonzini if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value)) 1534*d2c0bd84SPaolo Bonzini break; 1535*d2c0bd84SPaolo Bonzini return; 1536*d2c0bd84SPaolo Bonzini } 1537*d2c0bd84SPaolo Bonzini break; 1538*d2c0bd84SPaolo Bonzini } 1539*d2c0bd84SPaolo Bonzini 1540*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1541*d2c0bd84SPaolo Bonzini } 1542*d2c0bd84SPaolo Bonzini 1543*d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma_ops = { 1544*d2c0bd84SPaolo Bonzini .read = omap_dma_read, 1545*d2c0bd84SPaolo Bonzini .write = omap_dma_write, 1546*d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1547*d2c0bd84SPaolo Bonzini }; 1548*d2c0bd84SPaolo Bonzini 1549*d2c0bd84SPaolo Bonzini static void omap_dma_request(void *opaque, int drq, int req) 1550*d2c0bd84SPaolo Bonzini { 1551*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1552*d2c0bd84SPaolo Bonzini /* The request pins are level triggered in QEMU. */ 1553*d2c0bd84SPaolo Bonzini if (req) { 1554*d2c0bd84SPaolo Bonzini if (~s->dma->drqbmp & (1 << drq)) { 1555*d2c0bd84SPaolo Bonzini s->dma->drqbmp |= 1 << drq; 1556*d2c0bd84SPaolo Bonzini omap_dma_process_request(s, drq); 1557*d2c0bd84SPaolo Bonzini } 1558*d2c0bd84SPaolo Bonzini } else 1559*d2c0bd84SPaolo Bonzini s->dma->drqbmp &= ~(1 << drq); 1560*d2c0bd84SPaolo Bonzini } 1561*d2c0bd84SPaolo Bonzini 1562*d2c0bd84SPaolo Bonzini /* XXX: this won't be needed once soc_dma knows about clocks. */ 1563*d2c0bd84SPaolo Bonzini static void omap_dma_clk_update(void *opaque, int line, int on) 1564*d2c0bd84SPaolo Bonzini { 1565*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1566*d2c0bd84SPaolo Bonzini int i; 1567*d2c0bd84SPaolo Bonzini 1568*d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(s->clk); 1569*d2c0bd84SPaolo Bonzini 1570*d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) 1571*d2c0bd84SPaolo Bonzini if (s->ch[i].active) 1572*d2c0bd84SPaolo Bonzini soc_dma_set_request(s->ch[i].dma, on); 1573*d2c0bd84SPaolo Bonzini } 1574*d2c0bd84SPaolo Bonzini 1575*d2c0bd84SPaolo Bonzini static void omap_dma_setcaps(struct omap_dma_s *s) 1576*d2c0bd84SPaolo Bonzini { 1577*d2c0bd84SPaolo Bonzini switch (s->model) { 1578*d2c0bd84SPaolo Bonzini default: 1579*d2c0bd84SPaolo Bonzini case omap_dma_3_1: 1580*d2c0bd84SPaolo Bonzini break; 1581*d2c0bd84SPaolo Bonzini case omap_dma_3_2: 1582*d2c0bd84SPaolo Bonzini case omap_dma_4: 1583*d2c0bd84SPaolo Bonzini /* XXX Only available for sDMA */ 1584*d2c0bd84SPaolo Bonzini s->caps[0] = 1585*d2c0bd84SPaolo Bonzini (1 << 19) | /* Constant Fill Capability */ 1586*d2c0bd84SPaolo Bonzini (1 << 18); /* Transparent BLT Capability */ 1587*d2c0bd84SPaolo Bonzini s->caps[1] = 1588*d2c0bd84SPaolo Bonzini (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ 1589*d2c0bd84SPaolo Bonzini s->caps[2] = 1590*d2c0bd84SPaolo Bonzini (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ 1591*d2c0bd84SPaolo Bonzini (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ 1592*d2c0bd84SPaolo Bonzini (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ 1593*d2c0bd84SPaolo Bonzini (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ 1594*d2c0bd84SPaolo Bonzini (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ 1595*d2c0bd84SPaolo Bonzini (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ 1596*d2c0bd84SPaolo Bonzini (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ 1597*d2c0bd84SPaolo Bonzini (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ 1598*d2c0bd84SPaolo Bonzini (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ 1599*d2c0bd84SPaolo Bonzini s->caps[3] = 1600*d2c0bd84SPaolo Bonzini (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ 1601*d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ 1602*d2c0bd84SPaolo Bonzini (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ 1603*d2c0bd84SPaolo Bonzini (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ 1604*d2c0bd84SPaolo Bonzini (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ 1605*d2c0bd84SPaolo Bonzini (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ 1606*d2c0bd84SPaolo Bonzini (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ 1607*d2c0bd84SPaolo Bonzini (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ 1608*d2c0bd84SPaolo Bonzini s->caps[4] = 1609*d2c0bd84SPaolo Bonzini (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ 1610*d2c0bd84SPaolo Bonzini (1 << 6) | /* SYNC_STATUS_CPBLTY */ 1611*d2c0bd84SPaolo Bonzini (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ 1612*d2c0bd84SPaolo Bonzini (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ 1613*d2c0bd84SPaolo Bonzini (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ 1614*d2c0bd84SPaolo Bonzini (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ 1615*d2c0bd84SPaolo Bonzini (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ 1616*d2c0bd84SPaolo Bonzini (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ 1617*d2c0bd84SPaolo Bonzini break; 1618*d2c0bd84SPaolo Bonzini } 1619*d2c0bd84SPaolo Bonzini } 1620*d2c0bd84SPaolo Bonzini 1621*d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 1622*d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 1623*d2c0bd84SPaolo Bonzini qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 1624*d2c0bd84SPaolo Bonzini enum omap_dma_model model) 1625*d2c0bd84SPaolo Bonzini { 1626*d2c0bd84SPaolo Bonzini int num_irqs, memsize, i; 1627*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) 1628*d2c0bd84SPaolo Bonzini g_malloc0(sizeof(struct omap_dma_s)); 1629*d2c0bd84SPaolo Bonzini 1630*d2c0bd84SPaolo Bonzini if (model <= omap_dma_3_1) { 1631*d2c0bd84SPaolo Bonzini num_irqs = 6; 1632*d2c0bd84SPaolo Bonzini memsize = 0x800; 1633*d2c0bd84SPaolo Bonzini } else { 1634*d2c0bd84SPaolo Bonzini num_irqs = 16; 1635*d2c0bd84SPaolo Bonzini memsize = 0xc00; 1636*d2c0bd84SPaolo Bonzini } 1637*d2c0bd84SPaolo Bonzini s->model = model; 1638*d2c0bd84SPaolo Bonzini s->mpu = mpu; 1639*d2c0bd84SPaolo Bonzini s->clk = clk; 1640*d2c0bd84SPaolo Bonzini s->lcd_ch.irq = lcd_irq; 1641*d2c0bd84SPaolo Bonzini s->lcd_ch.mpu = mpu; 1642*d2c0bd84SPaolo Bonzini 1643*d2c0bd84SPaolo Bonzini s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); 1644*d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(clk); 1645*d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 1646*d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 1647*d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32); 1648*d2c0bd84SPaolo Bonzini s->dma->opaque = s; 1649*d2c0bd84SPaolo Bonzini 1650*d2c0bd84SPaolo Bonzini while (num_irqs --) 1651*d2c0bd84SPaolo Bonzini s->ch[num_irqs].irq = irqs[num_irqs]; 1652*d2c0bd84SPaolo Bonzini for (i = 0; i < 3; i ++) { 1653*d2c0bd84SPaolo Bonzini s->ch[i].sibling = &s->ch[i + 6]; 1654*d2c0bd84SPaolo Bonzini s->ch[i + 6].sibling = &s->ch[i]; 1655*d2c0bd84SPaolo Bonzini } 1656*d2c0bd84SPaolo Bonzini for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { 1657*d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 1658*d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 1659*d2c0bd84SPaolo Bonzini } 1660*d2c0bd84SPaolo Bonzini 1661*d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 1662*d2c0bd84SPaolo Bonzini omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); 1663*d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1664*d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, 1); 1665*d2c0bd84SPaolo Bonzini 1666*d2c0bd84SPaolo Bonzini memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize); 1667*d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 1668*d2c0bd84SPaolo Bonzini 1669*d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 1670*d2c0bd84SPaolo Bonzini 1671*d2c0bd84SPaolo Bonzini return s->dma; 1672*d2c0bd84SPaolo Bonzini } 1673*d2c0bd84SPaolo Bonzini 1674*d2c0bd84SPaolo Bonzini static void omap_dma_interrupts_4_update(struct omap_dma_s *s) 1675*d2c0bd84SPaolo Bonzini { 1676*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch = s->ch; 1677*d2c0bd84SPaolo Bonzini uint32_t bmp, bit; 1678*d2c0bd84SPaolo Bonzini 1679*d2c0bd84SPaolo Bonzini for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) 1680*d2c0bd84SPaolo Bonzini if (ch->status) { 1681*d2c0bd84SPaolo Bonzini bmp |= bit; 1682*d2c0bd84SPaolo Bonzini ch->cstatus |= ch->status; 1683*d2c0bd84SPaolo Bonzini ch->status = 0; 1684*d2c0bd84SPaolo Bonzini } 1685*d2c0bd84SPaolo Bonzini if ((s->irqstat[0] |= s->irqen[0] & bmp)) 1686*d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[0]); 1687*d2c0bd84SPaolo Bonzini if ((s->irqstat[1] |= s->irqen[1] & bmp)) 1688*d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[1]); 1689*d2c0bd84SPaolo Bonzini if ((s->irqstat[2] |= s->irqen[2] & bmp)) 1690*d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[2]); 1691*d2c0bd84SPaolo Bonzini if ((s->irqstat[3] |= s->irqen[3] & bmp)) 1692*d2c0bd84SPaolo Bonzini qemu_irq_raise(s->irq[3]); 1693*d2c0bd84SPaolo Bonzini } 1694*d2c0bd84SPaolo Bonzini 1695*d2c0bd84SPaolo Bonzini static uint64_t omap_dma4_read(void *opaque, hwaddr addr, 1696*d2c0bd84SPaolo Bonzini unsigned size) 1697*d2c0bd84SPaolo Bonzini { 1698*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1699*d2c0bd84SPaolo Bonzini int irqn = 0, chnum; 1700*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1701*d2c0bd84SPaolo Bonzini 1702*d2c0bd84SPaolo Bonzini if (size == 1) { 1703*d2c0bd84SPaolo Bonzini return omap_badwidth_read16(opaque, addr); 1704*d2c0bd84SPaolo Bonzini } 1705*d2c0bd84SPaolo Bonzini 1706*d2c0bd84SPaolo Bonzini switch (addr) { 1707*d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1708*d2c0bd84SPaolo Bonzini return 0x40; 1709*d2c0bd84SPaolo Bonzini 1710*d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1711*d2c0bd84SPaolo Bonzini irqn ++; 1712*d2c0bd84SPaolo Bonzini /* fall through */ 1713*d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1714*d2c0bd84SPaolo Bonzini irqn ++; 1715*d2c0bd84SPaolo Bonzini /* fall through */ 1716*d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1717*d2c0bd84SPaolo Bonzini irqn ++; 1718*d2c0bd84SPaolo Bonzini /* fall through */ 1719*d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1720*d2c0bd84SPaolo Bonzini return s->irqstat[irqn]; 1721*d2c0bd84SPaolo Bonzini 1722*d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1723*d2c0bd84SPaolo Bonzini irqn ++; 1724*d2c0bd84SPaolo Bonzini /* fall through */ 1725*d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1726*d2c0bd84SPaolo Bonzini irqn ++; 1727*d2c0bd84SPaolo Bonzini /* fall through */ 1728*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1729*d2c0bd84SPaolo Bonzini irqn ++; 1730*d2c0bd84SPaolo Bonzini /* fall through */ 1731*d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1732*d2c0bd84SPaolo Bonzini return s->irqen[irqn]; 1733*d2c0bd84SPaolo Bonzini 1734*d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1735*d2c0bd84SPaolo Bonzini return 1; /* RESETDONE */ 1736*d2c0bd84SPaolo Bonzini 1737*d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1738*d2c0bd84SPaolo Bonzini return s->ocp; 1739*d2c0bd84SPaolo Bonzini 1740*d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1741*d2c0bd84SPaolo Bonzini return s->caps[0]; 1742*d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1743*d2c0bd84SPaolo Bonzini return s->caps[2]; 1744*d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1745*d2c0bd84SPaolo Bonzini return s->caps[3]; 1746*d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1747*d2c0bd84SPaolo Bonzini return s->caps[4]; 1748*d2c0bd84SPaolo Bonzini 1749*d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1750*d2c0bd84SPaolo Bonzini return s->gcr; 1751*d2c0bd84SPaolo Bonzini 1752*d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1753*d2c0bd84SPaolo Bonzini addr -= 0x80; 1754*d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1755*d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1756*d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1757*d2c0bd84SPaolo Bonzini break; 1758*d2c0bd84SPaolo Bonzini 1759*d2c0bd84SPaolo Bonzini default: 1760*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1761*d2c0bd84SPaolo Bonzini return 0; 1762*d2c0bd84SPaolo Bonzini } 1763*d2c0bd84SPaolo Bonzini 1764*d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1765*d2c0bd84SPaolo Bonzini switch (addr) { 1766*d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1767*d2c0bd84SPaolo Bonzini return (ch->buf_disable << 25) | 1768*d2c0bd84SPaolo Bonzini (ch->src_sync << 24) | 1769*d2c0bd84SPaolo Bonzini (ch->prefetch << 23) | 1770*d2c0bd84SPaolo Bonzini ((ch->sync & 0x60) << 14) | 1771*d2c0bd84SPaolo Bonzini (ch->bs << 18) | 1772*d2c0bd84SPaolo Bonzini (ch->transparent_copy << 17) | 1773*d2c0bd84SPaolo Bonzini (ch->constant_fill << 16) | 1774*d2c0bd84SPaolo Bonzini (ch->mode[1] << 14) | 1775*d2c0bd84SPaolo Bonzini (ch->mode[0] << 12) | 1776*d2c0bd84SPaolo Bonzini (0 << 10) | (0 << 9) | 1777*d2c0bd84SPaolo Bonzini (ch->suspend << 8) | 1778*d2c0bd84SPaolo Bonzini (ch->enable << 7) | 1779*d2c0bd84SPaolo Bonzini (ch->priority << 6) | 1780*d2c0bd84SPaolo Bonzini (ch->fs << 5) | (ch->sync & 0x1f); 1781*d2c0bd84SPaolo Bonzini 1782*d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1783*d2c0bd84SPaolo Bonzini return (ch->link_enabled << 15) | ch->link_next_ch; 1784*d2c0bd84SPaolo Bonzini 1785*d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1786*d2c0bd84SPaolo Bonzini return ch->interrupts; 1787*d2c0bd84SPaolo Bonzini 1788*d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1789*d2c0bd84SPaolo Bonzini return ch->cstatus; 1790*d2c0bd84SPaolo Bonzini 1791*d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1792*d2c0bd84SPaolo Bonzini return (ch->endian[0] << 21) | 1793*d2c0bd84SPaolo Bonzini (ch->endian_lock[0] << 20) | 1794*d2c0bd84SPaolo Bonzini (ch->endian[1] << 19) | 1795*d2c0bd84SPaolo Bonzini (ch->endian_lock[1] << 18) | 1796*d2c0bd84SPaolo Bonzini (ch->write_mode << 16) | 1797*d2c0bd84SPaolo Bonzini (ch->burst[1] << 14) | 1798*d2c0bd84SPaolo Bonzini (ch->pack[1] << 13) | 1799*d2c0bd84SPaolo Bonzini (ch->translate[1] << 9) | 1800*d2c0bd84SPaolo Bonzini (ch->burst[0] << 7) | 1801*d2c0bd84SPaolo Bonzini (ch->pack[0] << 6) | 1802*d2c0bd84SPaolo Bonzini (ch->translate[0] << 2) | 1803*d2c0bd84SPaolo Bonzini (ch->data_type >> 1); 1804*d2c0bd84SPaolo Bonzini 1805*d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 1806*d2c0bd84SPaolo Bonzini return ch->elements; 1807*d2c0bd84SPaolo Bonzini 1808*d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 1809*d2c0bd84SPaolo Bonzini return ch->frames; 1810*d2c0bd84SPaolo Bonzini 1811*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 1812*d2c0bd84SPaolo Bonzini return ch->addr[0]; 1813*d2c0bd84SPaolo Bonzini 1814*d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 1815*d2c0bd84SPaolo Bonzini return ch->addr[1]; 1816*d2c0bd84SPaolo Bonzini 1817*d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 1818*d2c0bd84SPaolo Bonzini return ch->element_index[0]; 1819*d2c0bd84SPaolo Bonzini 1820*d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 1821*d2c0bd84SPaolo Bonzini return ch->frame_index[0]; 1822*d2c0bd84SPaolo Bonzini 1823*d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 1824*d2c0bd84SPaolo Bonzini return ch->element_index[1]; 1825*d2c0bd84SPaolo Bonzini 1826*d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 1827*d2c0bd84SPaolo Bonzini return ch->frame_index[1]; 1828*d2c0bd84SPaolo Bonzini 1829*d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 1830*d2c0bd84SPaolo Bonzini return ch->active_set.src & 0xffff; 1831*d2c0bd84SPaolo Bonzini 1832*d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 1833*d2c0bd84SPaolo Bonzini return ch->active_set.dest & 0xffff; 1834*d2c0bd84SPaolo Bonzini 1835*d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 1836*d2c0bd84SPaolo Bonzini return ch->active_set.element; 1837*d2c0bd84SPaolo Bonzini 1838*d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 1839*d2c0bd84SPaolo Bonzini return ch->active_set.frame; 1840*d2c0bd84SPaolo Bonzini 1841*d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 1842*d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 1843*d2c0bd84SPaolo Bonzini return ch->color; 1844*d2c0bd84SPaolo Bonzini 1845*d2c0bd84SPaolo Bonzini default: 1846*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1847*d2c0bd84SPaolo Bonzini return 0; 1848*d2c0bd84SPaolo Bonzini } 1849*d2c0bd84SPaolo Bonzini } 1850*d2c0bd84SPaolo Bonzini 1851*d2c0bd84SPaolo Bonzini static void omap_dma4_write(void *opaque, hwaddr addr, 1852*d2c0bd84SPaolo Bonzini uint64_t value, unsigned size) 1853*d2c0bd84SPaolo Bonzini { 1854*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) opaque; 1855*d2c0bd84SPaolo Bonzini int chnum, irqn = 0; 1856*d2c0bd84SPaolo Bonzini struct omap_dma_channel_s *ch; 1857*d2c0bd84SPaolo Bonzini 1858*d2c0bd84SPaolo Bonzini if (size == 1) { 1859*d2c0bd84SPaolo Bonzini return omap_badwidth_write16(opaque, addr, value); 1860*d2c0bd84SPaolo Bonzini } 1861*d2c0bd84SPaolo Bonzini 1862*d2c0bd84SPaolo Bonzini switch (addr) { 1863*d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_IRQSTATUS_L3 */ 1864*d2c0bd84SPaolo Bonzini irqn ++; 1865*d2c0bd84SPaolo Bonzini /* fall through */ 1866*d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_IRQSTATUS_L2 */ 1867*d2c0bd84SPaolo Bonzini irqn ++; 1868*d2c0bd84SPaolo Bonzini /* fall through */ 1869*d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_IRQSTATUS_L1 */ 1870*d2c0bd84SPaolo Bonzini irqn ++; 1871*d2c0bd84SPaolo Bonzini /* fall through */ 1872*d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_IRQSTATUS_L0 */ 1873*d2c0bd84SPaolo Bonzini s->irqstat[irqn] &= ~value; 1874*d2c0bd84SPaolo Bonzini if (!s->irqstat[irqn]) 1875*d2c0bd84SPaolo Bonzini qemu_irq_lower(s->irq[irqn]); 1876*d2c0bd84SPaolo Bonzini return; 1877*d2c0bd84SPaolo Bonzini 1878*d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_IRQENABLE_L3 */ 1879*d2c0bd84SPaolo Bonzini irqn ++; 1880*d2c0bd84SPaolo Bonzini /* fall through */ 1881*d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_IRQENABLE_L2 */ 1882*d2c0bd84SPaolo Bonzini irqn ++; 1883*d2c0bd84SPaolo Bonzini /* fall through */ 1884*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_IRQENABLE_L1 */ 1885*d2c0bd84SPaolo Bonzini irqn ++; 1886*d2c0bd84SPaolo Bonzini /* fall through */ 1887*d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_IRQENABLE_L0 */ 1888*d2c0bd84SPaolo Bonzini s->irqen[irqn] = value; 1889*d2c0bd84SPaolo Bonzini return; 1890*d2c0bd84SPaolo Bonzini 1891*d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_OCP_SYSCONFIG */ 1892*d2c0bd84SPaolo Bonzini if (value & 2) /* SOFTRESET */ 1893*d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 1894*d2c0bd84SPaolo Bonzini s->ocp = value & 0x3321; 1895*d2c0bd84SPaolo Bonzini if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ 1896*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); 1897*d2c0bd84SPaolo Bonzini return; 1898*d2c0bd84SPaolo Bonzini 1899*d2c0bd84SPaolo Bonzini case 0x78: /* DMA4_GCR */ 1900*d2c0bd84SPaolo Bonzini s->gcr = value & 0x00ff00ff; 1901*d2c0bd84SPaolo Bonzini if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ 1902*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); 1903*d2c0bd84SPaolo Bonzini return; 1904*d2c0bd84SPaolo Bonzini 1905*d2c0bd84SPaolo Bonzini case 0x80 ... 0xfff: 1906*d2c0bd84SPaolo Bonzini addr -= 0x80; 1907*d2c0bd84SPaolo Bonzini chnum = addr / 0x60; 1908*d2c0bd84SPaolo Bonzini ch = s->ch + chnum; 1909*d2c0bd84SPaolo Bonzini addr -= chnum * 0x60; 1910*d2c0bd84SPaolo Bonzini break; 1911*d2c0bd84SPaolo Bonzini 1912*d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_REVISION */ 1913*d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_SYSSTATUS */ 1914*d2c0bd84SPaolo Bonzini case 0x64: /* DMA4_CAPS_0 */ 1915*d2c0bd84SPaolo Bonzini case 0x6c: /* DMA4_CAPS_2 */ 1916*d2c0bd84SPaolo Bonzini case 0x70: /* DMA4_CAPS_3 */ 1917*d2c0bd84SPaolo Bonzini case 0x74: /* DMA4_CAPS_4 */ 1918*d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 1919*d2c0bd84SPaolo Bonzini return; 1920*d2c0bd84SPaolo Bonzini 1921*d2c0bd84SPaolo Bonzini default: 1922*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 1923*d2c0bd84SPaolo Bonzini return; 1924*d2c0bd84SPaolo Bonzini } 1925*d2c0bd84SPaolo Bonzini 1926*d2c0bd84SPaolo Bonzini /* Per-channel registers */ 1927*d2c0bd84SPaolo Bonzini switch (addr) { 1928*d2c0bd84SPaolo Bonzini case 0x00: /* DMA4_CCR */ 1929*d2c0bd84SPaolo Bonzini ch->buf_disable = (value >> 25) & 1; 1930*d2c0bd84SPaolo Bonzini ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ 1931*d2c0bd84SPaolo Bonzini if (ch->buf_disable && !ch->src_sync) 1932*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: Buffering disable is not allowed in " 1933*d2c0bd84SPaolo Bonzini "destination synchronised mode\n", __FUNCTION__); 1934*d2c0bd84SPaolo Bonzini ch->prefetch = (value >> 23) & 1; 1935*d2c0bd84SPaolo Bonzini ch->bs = (value >> 18) & 1; 1936*d2c0bd84SPaolo Bonzini ch->transparent_copy = (value >> 17) & 1; 1937*d2c0bd84SPaolo Bonzini ch->constant_fill = (value >> 16) & 1; 1938*d2c0bd84SPaolo Bonzini ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); 1939*d2c0bd84SPaolo Bonzini ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); 1940*d2c0bd84SPaolo Bonzini ch->suspend = (value & 0x0100) >> 8; 1941*d2c0bd84SPaolo Bonzini ch->priority = (value & 0x0040) >> 6; 1942*d2c0bd84SPaolo Bonzini ch->fs = (value & 0x0020) >> 5; 1943*d2c0bd84SPaolo Bonzini if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) 1944*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: For a packet transfer at least one port " 1945*d2c0bd84SPaolo Bonzini "must be constant-addressed\n", __FUNCTION__); 1946*d2c0bd84SPaolo Bonzini ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); 1947*d2c0bd84SPaolo Bonzini /* XXX must be 0x01 for CamDMA */ 1948*d2c0bd84SPaolo Bonzini 1949*d2c0bd84SPaolo Bonzini if (value & 0x0080) 1950*d2c0bd84SPaolo Bonzini omap_dma_enable_channel(s, ch); 1951*d2c0bd84SPaolo Bonzini else 1952*d2c0bd84SPaolo Bonzini omap_dma_disable_channel(s, ch); 1953*d2c0bd84SPaolo Bonzini 1954*d2c0bd84SPaolo Bonzini break; 1955*d2c0bd84SPaolo Bonzini 1956*d2c0bd84SPaolo Bonzini case 0x04: /* DMA4_CLNK_CTRL */ 1957*d2c0bd84SPaolo Bonzini ch->link_enabled = (value >> 15) & 0x1; 1958*d2c0bd84SPaolo Bonzini ch->link_next_ch = value & 0x1f; 1959*d2c0bd84SPaolo Bonzini break; 1960*d2c0bd84SPaolo Bonzini 1961*d2c0bd84SPaolo Bonzini case 0x08: /* DMA4_CICR */ 1962*d2c0bd84SPaolo Bonzini ch->interrupts = value & 0x09be; 1963*d2c0bd84SPaolo Bonzini break; 1964*d2c0bd84SPaolo Bonzini 1965*d2c0bd84SPaolo Bonzini case 0x0c: /* DMA4_CSR */ 1966*d2c0bd84SPaolo Bonzini ch->cstatus &= ~value; 1967*d2c0bd84SPaolo Bonzini break; 1968*d2c0bd84SPaolo Bonzini 1969*d2c0bd84SPaolo Bonzini case 0x10: /* DMA4_CSDP */ 1970*d2c0bd84SPaolo Bonzini ch->endian[0] =(value >> 21) & 1; 1971*d2c0bd84SPaolo Bonzini ch->endian_lock[0] =(value >> 20) & 1; 1972*d2c0bd84SPaolo Bonzini ch->endian[1] =(value >> 19) & 1; 1973*d2c0bd84SPaolo Bonzini ch->endian_lock[1] =(value >> 18) & 1; 1974*d2c0bd84SPaolo Bonzini if (ch->endian[0] != ch->endian[1]) 1975*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n", 1976*d2c0bd84SPaolo Bonzini __FUNCTION__); 1977*d2c0bd84SPaolo Bonzini ch->write_mode = (value >> 16) & 3; 1978*d2c0bd84SPaolo Bonzini ch->burst[1] = (value & 0xc000) >> 14; 1979*d2c0bd84SPaolo Bonzini ch->pack[1] = (value & 0x2000) >> 13; 1980*d2c0bd84SPaolo Bonzini ch->translate[1] = (value & 0x1e00) >> 9; 1981*d2c0bd84SPaolo Bonzini ch->burst[0] = (value & 0x0180) >> 7; 1982*d2c0bd84SPaolo Bonzini ch->pack[0] = (value & 0x0040) >> 6; 1983*d2c0bd84SPaolo Bonzini ch->translate[0] = (value & 0x003c) >> 2; 1984*d2c0bd84SPaolo Bonzini if (ch->translate[0] | ch->translate[1]) 1985*d2c0bd84SPaolo Bonzini fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", 1986*d2c0bd84SPaolo Bonzini __FUNCTION__); 1987*d2c0bd84SPaolo Bonzini ch->data_type = 1 << (value & 3); 1988*d2c0bd84SPaolo Bonzini if ((value & 3) == 3) 1989*d2c0bd84SPaolo Bonzini printf("%s: bad data_type for DMA channel\n", __FUNCTION__); 1990*d2c0bd84SPaolo Bonzini break; 1991*d2c0bd84SPaolo Bonzini 1992*d2c0bd84SPaolo Bonzini case 0x14: /* DMA4_CEN */ 1993*d2c0bd84SPaolo Bonzini ch->set_update = 1; 1994*d2c0bd84SPaolo Bonzini ch->elements = value & 0xffffff; 1995*d2c0bd84SPaolo Bonzini break; 1996*d2c0bd84SPaolo Bonzini 1997*d2c0bd84SPaolo Bonzini case 0x18: /* DMA4_CFN */ 1998*d2c0bd84SPaolo Bonzini ch->frames = value & 0xffff; 1999*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2000*d2c0bd84SPaolo Bonzini break; 2001*d2c0bd84SPaolo Bonzini 2002*d2c0bd84SPaolo Bonzini case 0x1c: /* DMA4_CSSA */ 2003*d2c0bd84SPaolo Bonzini ch->addr[0] = (hwaddr) (uint32_t) value; 2004*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2005*d2c0bd84SPaolo Bonzini break; 2006*d2c0bd84SPaolo Bonzini 2007*d2c0bd84SPaolo Bonzini case 0x20: /* DMA4_CDSA */ 2008*d2c0bd84SPaolo Bonzini ch->addr[1] = (hwaddr) (uint32_t) value; 2009*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2010*d2c0bd84SPaolo Bonzini break; 2011*d2c0bd84SPaolo Bonzini 2012*d2c0bd84SPaolo Bonzini case 0x24: /* DMA4_CSEI */ 2013*d2c0bd84SPaolo Bonzini ch->element_index[0] = (int16_t) value; 2014*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2015*d2c0bd84SPaolo Bonzini break; 2016*d2c0bd84SPaolo Bonzini 2017*d2c0bd84SPaolo Bonzini case 0x28: /* DMA4_CSFI */ 2018*d2c0bd84SPaolo Bonzini ch->frame_index[0] = (int32_t) value; 2019*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2020*d2c0bd84SPaolo Bonzini break; 2021*d2c0bd84SPaolo Bonzini 2022*d2c0bd84SPaolo Bonzini case 0x2c: /* DMA4_CDEI */ 2023*d2c0bd84SPaolo Bonzini ch->element_index[1] = (int16_t) value; 2024*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2025*d2c0bd84SPaolo Bonzini break; 2026*d2c0bd84SPaolo Bonzini 2027*d2c0bd84SPaolo Bonzini case 0x30: /* DMA4_CDFI */ 2028*d2c0bd84SPaolo Bonzini ch->frame_index[1] = (int32_t) value; 2029*d2c0bd84SPaolo Bonzini ch->set_update = 1; 2030*d2c0bd84SPaolo Bonzini break; 2031*d2c0bd84SPaolo Bonzini 2032*d2c0bd84SPaolo Bonzini case 0x44: /* DMA4_COLOR */ 2033*d2c0bd84SPaolo Bonzini /* XXX only in sDMA */ 2034*d2c0bd84SPaolo Bonzini ch->color = value; 2035*d2c0bd84SPaolo Bonzini break; 2036*d2c0bd84SPaolo Bonzini 2037*d2c0bd84SPaolo Bonzini case 0x34: /* DMA4_CSAC */ 2038*d2c0bd84SPaolo Bonzini case 0x38: /* DMA4_CDAC */ 2039*d2c0bd84SPaolo Bonzini case 0x3c: /* DMA4_CCEN */ 2040*d2c0bd84SPaolo Bonzini case 0x40: /* DMA4_CCFN */ 2041*d2c0bd84SPaolo Bonzini OMAP_RO_REG(addr); 2042*d2c0bd84SPaolo Bonzini break; 2043*d2c0bd84SPaolo Bonzini 2044*d2c0bd84SPaolo Bonzini default: 2045*d2c0bd84SPaolo Bonzini OMAP_BAD_REG(addr); 2046*d2c0bd84SPaolo Bonzini } 2047*d2c0bd84SPaolo Bonzini } 2048*d2c0bd84SPaolo Bonzini 2049*d2c0bd84SPaolo Bonzini static const MemoryRegionOps omap_dma4_ops = { 2050*d2c0bd84SPaolo Bonzini .read = omap_dma4_read, 2051*d2c0bd84SPaolo Bonzini .write = omap_dma4_write, 2052*d2c0bd84SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 2053*d2c0bd84SPaolo Bonzini }; 2054*d2c0bd84SPaolo Bonzini 2055*d2c0bd84SPaolo Bonzini struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 2056*d2c0bd84SPaolo Bonzini MemoryRegion *sysmem, 2057*d2c0bd84SPaolo Bonzini struct omap_mpu_state_s *mpu, int fifo, 2058*d2c0bd84SPaolo Bonzini int chans, omap_clk iclk, omap_clk fclk) 2059*d2c0bd84SPaolo Bonzini { 2060*d2c0bd84SPaolo Bonzini int i; 2061*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = (struct omap_dma_s *) 2062*d2c0bd84SPaolo Bonzini g_malloc0(sizeof(struct omap_dma_s)); 2063*d2c0bd84SPaolo Bonzini 2064*d2c0bd84SPaolo Bonzini s->model = omap_dma_4; 2065*d2c0bd84SPaolo Bonzini s->chans = chans; 2066*d2c0bd84SPaolo Bonzini s->mpu = mpu; 2067*d2c0bd84SPaolo Bonzini s->clk = fclk; 2068*d2c0bd84SPaolo Bonzini 2069*d2c0bd84SPaolo Bonzini s->dma = soc_dma_init(s->chans); 2070*d2c0bd84SPaolo Bonzini s->dma->freq = omap_clk_getrate(fclk); 2071*d2c0bd84SPaolo Bonzini s->dma->transfer_fn = omap_dma_transfer_generic; 2072*d2c0bd84SPaolo Bonzini s->dma->setup_fn = omap_dma_transfer_setup; 2073*d2c0bd84SPaolo Bonzini s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64); 2074*d2c0bd84SPaolo Bonzini s->dma->opaque = s; 2075*d2c0bd84SPaolo Bonzini for (i = 0; i < s->chans; i ++) { 2076*d2c0bd84SPaolo Bonzini s->ch[i].dma = &s->dma->ch[i]; 2077*d2c0bd84SPaolo Bonzini s->dma->ch[i].opaque = &s->ch[i]; 2078*d2c0bd84SPaolo Bonzini } 2079*d2c0bd84SPaolo Bonzini 2080*d2c0bd84SPaolo Bonzini memcpy(&s->irq, irqs, sizeof(s->irq)); 2081*d2c0bd84SPaolo Bonzini s->intr_update = omap_dma_interrupts_4_update; 2082*d2c0bd84SPaolo Bonzini 2083*d2c0bd84SPaolo Bonzini omap_dma_setcaps(s); 2084*d2c0bd84SPaolo Bonzini omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); 2085*d2c0bd84SPaolo Bonzini omap_dma_reset(s->dma); 2086*d2c0bd84SPaolo Bonzini omap_dma_clk_update(s, 0, !!s->dma->freq); 2087*d2c0bd84SPaolo Bonzini 2088*d2c0bd84SPaolo Bonzini memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000); 2089*d2c0bd84SPaolo Bonzini memory_region_add_subregion(sysmem, base, &s->iomem); 2090*d2c0bd84SPaolo Bonzini 2091*d2c0bd84SPaolo Bonzini mpu->drq = s->dma->drq; 2092*d2c0bd84SPaolo Bonzini 2093*d2c0bd84SPaolo Bonzini return s->dma; 2094*d2c0bd84SPaolo Bonzini } 2095*d2c0bd84SPaolo Bonzini 2096*d2c0bd84SPaolo Bonzini struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) 2097*d2c0bd84SPaolo Bonzini { 2098*d2c0bd84SPaolo Bonzini struct omap_dma_s *s = dma->opaque; 2099*d2c0bd84SPaolo Bonzini 2100*d2c0bd84SPaolo Bonzini return &s->lcd_ch; 2101*d2c0bd84SPaolo Bonzini } 2102