1 /* 2 * QEMU JAZZ RC4030 chipset 3 * 4 * Copyright (c) 2007-2013 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/mips/mips.h" 29 #include "hw/sysbus.h" 30 #include "qemu/timer.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "exec/address-spaces.h" 34 #include "trace.h" 35 36 /********************************************************/ 37 /* rc4030 emulation */ 38 39 typedef struct dma_pagetable_entry { 40 int32_t frame; 41 int32_t owner; 42 } QEMU_PACKED dma_pagetable_entry; 43 44 #define DMA_PAGESIZE 4096 45 #define DMA_REG_ENABLE 1 46 #define DMA_REG_COUNT 2 47 #define DMA_REG_ADDRESS 3 48 49 #define DMA_FLAG_ENABLE 0x0001 50 #define DMA_FLAG_MEM_TO_DEV 0x0002 51 #define DMA_FLAG_TC_INTR 0x0100 52 #define DMA_FLAG_MEM_INTR 0x0200 53 #define DMA_FLAG_ADDR_INTR 0x0400 54 55 #define TYPE_RC4030 "rc4030" 56 #define RC4030(obj) \ 57 OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030) 58 59 #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region" 60 61 typedef struct rc4030State { 62 63 SysBusDevice parent; 64 65 uint32_t config; /* 0x0000: RC4030 config register */ 66 uint32_t revision; /* 0x0008: RC4030 Revision register */ 67 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */ 68 69 /* DMA */ 70 uint32_t dma_regs[8][4]; 71 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */ 72 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */ 73 74 /* cache */ 75 uint32_t cache_maint; /* 0x0030: Cache Maintenance */ 76 uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */ 77 uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */ 78 uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */ 79 uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */ 80 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ 81 82 uint32_t nmi_interrupt; /* 0x0200: interrupt source */ 83 uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */ 84 uint32_t nvram_protect; /* 0x0220: NV ram protect register */ 85 uint32_t rem_speed[16]; 86 uint32_t imr_jazz; /* Local bus int enable mask */ 87 uint32_t isr_jazz; /* Local bus int source */ 88 89 /* timer */ 90 QEMUTimer *periodic_timer; 91 uint32_t itr; /* Interval timer reload */ 92 93 qemu_irq timer_irq; 94 qemu_irq jazz_bus_irq; 95 96 /* whole DMA memory region, root of DMA address space */ 97 IOMMUMemoryRegion dma_mr; 98 AddressSpace dma_as; 99 100 MemoryRegion iomem_chipset; 101 MemoryRegion iomem_jazzio; 102 } rc4030State; 103 104 static void set_next_tick(rc4030State *s) 105 { 106 uint32_t tm_hz; 107 qemu_irq_lower(s->timer_irq); 108 109 tm_hz = 1000 / (s->itr + 1); 110 111 timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 112 NANOSECONDS_PER_SECOND / tm_hz); 113 } 114 115 /* called for accesses to rc4030 */ 116 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) 117 { 118 rc4030State *s = opaque; 119 uint32_t val; 120 121 addr &= 0x3fff; 122 switch (addr & ~0x3) { 123 /* Global config register */ 124 case 0x0000: 125 val = s->config; 126 break; 127 /* Revision register */ 128 case 0x0008: 129 val = s->revision; 130 break; 131 /* Invalid Address register */ 132 case 0x0010: 133 val = s->invalid_address_register; 134 break; 135 /* DMA transl. table base */ 136 case 0x0018: 137 val = s->dma_tl_base; 138 break; 139 /* DMA transl. table limit */ 140 case 0x0020: 141 val = s->dma_tl_limit; 142 break; 143 /* Remote Failed Address */ 144 case 0x0038: 145 val = s->remote_failed_address; 146 break; 147 /* Memory Failed Address */ 148 case 0x0040: 149 val = s->memory_failed_address; 150 break; 151 /* I/O Cache Byte Mask */ 152 case 0x0058: 153 val = s->cache_bmask; 154 /* HACK */ 155 if (s->cache_bmask == (uint32_t)-1) { 156 s->cache_bmask = 0; 157 } 158 break; 159 /* Remote Speed Registers */ 160 case 0x0070: 161 case 0x0078: 162 case 0x0080: 163 case 0x0088: 164 case 0x0090: 165 case 0x0098: 166 case 0x00a0: 167 case 0x00a8: 168 case 0x00b0: 169 case 0x00b8: 170 case 0x00c0: 171 case 0x00c8: 172 case 0x00d0: 173 case 0x00d8: 174 case 0x00e0: 175 case 0x00e8: 176 val = s->rem_speed[(addr - 0x0070) >> 3]; 177 break; 178 /* DMA channel base address */ 179 case 0x0100: 180 case 0x0108: 181 case 0x0110: 182 case 0x0118: 183 case 0x0120: 184 case 0x0128: 185 case 0x0130: 186 case 0x0138: 187 case 0x0140: 188 case 0x0148: 189 case 0x0150: 190 case 0x0158: 191 case 0x0160: 192 case 0x0168: 193 case 0x0170: 194 case 0x0178: 195 case 0x0180: 196 case 0x0188: 197 case 0x0190: 198 case 0x0198: 199 case 0x01a0: 200 case 0x01a8: 201 case 0x01b0: 202 case 0x01b8: 203 case 0x01c0: 204 case 0x01c8: 205 case 0x01d0: 206 case 0x01d8: 207 case 0x01e0: 208 case 0x01e8: 209 case 0x01f0: 210 case 0x01f8: 211 { 212 int entry = (addr - 0x0100) >> 5; 213 int idx = (addr & 0x1f) >> 3; 214 val = s->dma_regs[entry][idx]; 215 } 216 break; 217 /* Interrupt source */ 218 case 0x0200: 219 val = s->nmi_interrupt; 220 break; 221 /* Error type */ 222 case 0x0208: 223 val = 0; 224 break; 225 /* Memory refresh rate */ 226 case 0x0210: 227 val = s->memory_refresh_rate; 228 break; 229 /* NV ram protect register */ 230 case 0x0220: 231 val = s->nvram_protect; 232 break; 233 /* Interval timer count */ 234 case 0x0230: 235 val = 0; 236 qemu_irq_lower(s->timer_irq); 237 break; 238 /* EISA interrupt */ 239 case 0x0238: 240 val = 7; /* FIXME: should be read from EISA controller */ 241 break; 242 default: 243 qemu_log_mask(LOG_GUEST_ERROR, 244 "rc4030: invalid read at 0x%x", (int)addr); 245 val = 0; 246 break; 247 } 248 249 if ((addr & ~3) != 0x230) { 250 trace_rc4030_read(addr, val); 251 } 252 253 return val; 254 } 255 256 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data, 257 unsigned int size) 258 { 259 rc4030State *s = opaque; 260 uint32_t val = data; 261 addr &= 0x3fff; 262 263 trace_rc4030_write(addr, val); 264 265 switch (addr & ~0x3) { 266 /* Global config register */ 267 case 0x0000: 268 s->config = val; 269 break; 270 /* DMA transl. table base */ 271 case 0x0018: 272 s->dma_tl_base = val; 273 break; 274 /* DMA transl. table limit */ 275 case 0x0020: 276 s->dma_tl_limit = val; 277 break; 278 /* DMA transl. table invalidated */ 279 case 0x0028: 280 break; 281 /* Cache Maintenance */ 282 case 0x0030: 283 s->cache_maint = val; 284 break; 285 /* I/O Cache Physical Tag */ 286 case 0x0048: 287 s->cache_ptag = val; 288 break; 289 /* I/O Cache Logical Tag */ 290 case 0x0050: 291 s->cache_ltag = val; 292 break; 293 /* I/O Cache Byte Mask */ 294 case 0x0058: 295 s->cache_bmask |= val; /* HACK */ 296 break; 297 /* I/O Cache Buffer Window */ 298 case 0x0060: 299 /* HACK */ 300 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { 301 hwaddr dest = s->cache_ptag & ~0x1; 302 dest += (s->cache_maint & 0x3) << 3; 303 cpu_physical_memory_write(dest, &val, 4); 304 } 305 break; 306 /* Remote Speed Registers */ 307 case 0x0070: 308 case 0x0078: 309 case 0x0080: 310 case 0x0088: 311 case 0x0090: 312 case 0x0098: 313 case 0x00a0: 314 case 0x00a8: 315 case 0x00b0: 316 case 0x00b8: 317 case 0x00c0: 318 case 0x00c8: 319 case 0x00d0: 320 case 0x00d8: 321 case 0x00e0: 322 case 0x00e8: 323 s->rem_speed[(addr - 0x0070) >> 3] = val; 324 break; 325 /* DMA channel base address */ 326 case 0x0100: 327 case 0x0108: 328 case 0x0110: 329 case 0x0118: 330 case 0x0120: 331 case 0x0128: 332 case 0x0130: 333 case 0x0138: 334 case 0x0140: 335 case 0x0148: 336 case 0x0150: 337 case 0x0158: 338 case 0x0160: 339 case 0x0168: 340 case 0x0170: 341 case 0x0178: 342 case 0x0180: 343 case 0x0188: 344 case 0x0190: 345 case 0x0198: 346 case 0x01a0: 347 case 0x01a8: 348 case 0x01b0: 349 case 0x01b8: 350 case 0x01c0: 351 case 0x01c8: 352 case 0x01d0: 353 case 0x01d8: 354 case 0x01e0: 355 case 0x01e8: 356 case 0x01f0: 357 case 0x01f8: 358 { 359 int entry = (addr - 0x0100) >> 5; 360 int idx = (addr & 0x1f) >> 3; 361 s->dma_regs[entry][idx] = val; 362 } 363 break; 364 /* Memory refresh rate */ 365 case 0x0210: 366 s->memory_refresh_rate = val; 367 break; 368 /* Interval timer reload */ 369 case 0x0228: 370 s->itr = val & 0x01FF; 371 qemu_irq_lower(s->timer_irq); 372 set_next_tick(s); 373 break; 374 /* EISA interrupt */ 375 case 0x0238: 376 break; 377 default: 378 qemu_log_mask(LOG_GUEST_ERROR, 379 "rc4030: invalid write of 0x%02x at 0x%x", 380 val, (int)addr); 381 break; 382 } 383 } 384 385 static const MemoryRegionOps rc4030_ops = { 386 .read = rc4030_read, 387 .write = rc4030_write, 388 .impl.min_access_size = 4, 389 .impl.max_access_size = 4, 390 .endianness = DEVICE_NATIVE_ENDIAN, 391 }; 392 393 static void update_jazz_irq(rc4030State *s) 394 { 395 uint16_t pending; 396 397 pending = s->isr_jazz & s->imr_jazz; 398 399 if (pending != 0) 400 qemu_irq_raise(s->jazz_bus_irq); 401 else 402 qemu_irq_lower(s->jazz_bus_irq); 403 } 404 405 static void rc4030_irq_jazz_request(void *opaque, int irq, int level) 406 { 407 rc4030State *s = opaque; 408 409 if (level) { 410 s->isr_jazz |= 1 << irq; 411 } else { 412 s->isr_jazz &= ~(1 << irq); 413 } 414 415 update_jazz_irq(s); 416 } 417 418 static void rc4030_periodic_timer(void *opaque) 419 { 420 rc4030State *s = opaque; 421 422 set_next_tick(s); 423 qemu_irq_raise(s->timer_irq); 424 } 425 426 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size) 427 { 428 rc4030State *s = opaque; 429 uint32_t val; 430 uint32_t irq; 431 addr &= 0xfff; 432 433 switch (addr) { 434 /* Local bus int source */ 435 case 0x00: { 436 uint32_t pending = s->isr_jazz & s->imr_jazz; 437 val = 0; 438 irq = 0; 439 while (pending) { 440 if (pending & 1) { 441 val = (irq + 1) << 2; 442 break; 443 } 444 irq++; 445 pending >>= 1; 446 } 447 break; 448 } 449 /* Local bus int enable mask */ 450 case 0x02: 451 val = s->imr_jazz; 452 break; 453 default: 454 qemu_log_mask(LOG_GUEST_ERROR, 455 "rc4030/jazzio: invalid read at 0x%x", (int)addr); 456 val = 0; 457 break; 458 } 459 460 trace_jazzio_read(addr, val); 461 462 return val; 463 } 464 465 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data, 466 unsigned int size) 467 { 468 rc4030State *s = opaque; 469 uint32_t val = data; 470 addr &= 0xfff; 471 472 trace_jazzio_write(addr, val); 473 474 switch (addr) { 475 /* Local bus int enable mask */ 476 case 0x02: 477 s->imr_jazz = val; 478 update_jazz_irq(s); 479 break; 480 default: 481 qemu_log_mask(LOG_GUEST_ERROR, 482 "rc4030/jazzio: invalid write of 0x%02x at 0x%x", 483 val, (int)addr); 484 break; 485 } 486 } 487 488 static const MemoryRegionOps jazzio_ops = { 489 .read = jazzio_read, 490 .write = jazzio_write, 491 .impl.min_access_size = 2, 492 .impl.max_access_size = 2, 493 .endianness = DEVICE_NATIVE_ENDIAN, 494 }; 495 496 static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, 497 IOMMUAccessFlags flag, int iommu_idx) 498 { 499 rc4030State *s = container_of(iommu, rc4030State, dma_mr); 500 IOMMUTLBEntry ret = { 501 .target_as = &address_space_memory, 502 .iova = addr & ~(DMA_PAGESIZE - 1), 503 .translated_addr = 0, 504 .addr_mask = DMA_PAGESIZE - 1, 505 .perm = IOMMU_NONE, 506 }; 507 uint64_t i, entry_address; 508 dma_pagetable_entry entry; 509 510 i = addr / DMA_PAGESIZE; 511 if (i < s->dma_tl_limit / sizeof(entry)) { 512 entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); 513 if (address_space_read(ret.target_as, entry_address, 514 MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, 515 sizeof(entry)) == MEMTX_OK) { 516 ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); 517 ret.perm = IOMMU_RW; 518 } 519 } 520 521 return ret; 522 } 523 524 static void rc4030_reset(DeviceState *dev) 525 { 526 rc4030State *s = RC4030(dev); 527 int i; 528 529 s->config = 0x410; /* some boards seem to accept 0x104 too */ 530 s->revision = 1; 531 s->invalid_address_register = 0; 532 533 memset(s->dma_regs, 0, sizeof(s->dma_regs)); 534 535 s->remote_failed_address = s->memory_failed_address = 0; 536 s->cache_maint = 0; 537 s->cache_ptag = s->cache_ltag = 0; 538 s->cache_bmask = 0; 539 540 s->memory_refresh_rate = 0x18186; 541 s->nvram_protect = 7; 542 for (i = 0; i < 15; i++) { 543 s->rem_speed[i] = 7; 544 } 545 s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ 546 s->isr_jazz = 0; 547 548 s->itr = 0; 549 550 qemu_irq_lower(s->timer_irq); 551 qemu_irq_lower(s->jazz_bus_irq); 552 } 553 554 static int rc4030_post_load(void *opaque, int version_id) 555 { 556 rc4030State *s = opaque; 557 558 set_next_tick(s); 559 update_jazz_irq(s); 560 561 return 0; 562 } 563 564 static const VMStateDescription vmstate_rc4030 = { 565 .name = "rc4030", 566 .version_id = 3, 567 .post_load = rc4030_post_load, 568 .fields = (VMStateField []) { 569 VMSTATE_UINT32(config, rc4030State), 570 VMSTATE_UINT32(invalid_address_register, rc4030State), 571 VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4), 572 VMSTATE_UINT32(dma_tl_base, rc4030State), 573 VMSTATE_UINT32(dma_tl_limit, rc4030State), 574 VMSTATE_UINT32(cache_maint, rc4030State), 575 VMSTATE_UINT32(remote_failed_address, rc4030State), 576 VMSTATE_UINT32(memory_failed_address, rc4030State), 577 VMSTATE_UINT32(cache_ptag, rc4030State), 578 VMSTATE_UINT32(cache_ltag, rc4030State), 579 VMSTATE_UINT32(cache_bmask, rc4030State), 580 VMSTATE_UINT32(memory_refresh_rate, rc4030State), 581 VMSTATE_UINT32(nvram_protect, rc4030State), 582 VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16), 583 VMSTATE_UINT32(imr_jazz, rc4030State), 584 VMSTATE_UINT32(isr_jazz, rc4030State), 585 VMSTATE_UINT32(itr, rc4030State), 586 VMSTATE_END_OF_LIST() 587 } 588 }; 589 590 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) 591 { 592 rc4030State *s = opaque; 593 hwaddr dma_addr; 594 int dev_to_mem; 595 596 s->dma_regs[n][DMA_REG_ENABLE] &= 597 ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); 598 599 /* Check DMA channel consistency */ 600 dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; 601 if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || 602 (is_write != dev_to_mem)) { 603 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; 604 s->nmi_interrupt |= 1 << n; 605 return; 606 } 607 608 /* Get start address and len */ 609 if (len > s->dma_regs[n][DMA_REG_COUNT]) { 610 len = s->dma_regs[n][DMA_REG_COUNT]; 611 } 612 dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; 613 614 /* Read/write data at right place */ 615 address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED, 616 buf, len, is_write); 617 618 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; 619 s->dma_regs[n][DMA_REG_COUNT] -= len; 620 } 621 622 struct rc4030DMAState { 623 void *opaque; 624 int n; 625 }; 626 627 void rc4030_dma_read(void *dma, uint8_t *buf, int len) 628 { 629 rc4030_dma s = dma; 630 rc4030_do_dma(s->opaque, s->n, buf, len, 0); 631 } 632 633 void rc4030_dma_write(void *dma, uint8_t *buf, int len) 634 { 635 rc4030_dma s = dma; 636 rc4030_do_dma(s->opaque, s->n, buf, len, 1); 637 } 638 639 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) 640 { 641 rc4030_dma *s; 642 struct rc4030DMAState *p; 643 int i; 644 645 s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n); 646 p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n); 647 for (i = 0; i < n; i++) { 648 p->opaque = opaque; 649 p->n = i; 650 s[i] = p; 651 p++; 652 } 653 return s; 654 } 655 656 static void rc4030_initfn(Object *obj) 657 { 658 DeviceState *dev = DEVICE(obj); 659 rc4030State *s = RC4030(obj); 660 SysBusDevice *sysbus = SYS_BUS_DEVICE(obj); 661 662 qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16); 663 664 sysbus_init_irq(sysbus, &s->timer_irq); 665 sysbus_init_irq(sysbus, &s->jazz_bus_irq); 666 667 sysbus_init_mmio(sysbus, &s->iomem_chipset); 668 sysbus_init_mmio(sysbus, &s->iomem_jazzio); 669 } 670 671 static void rc4030_realize(DeviceState *dev, Error **errp) 672 { 673 rc4030State *s = RC4030(dev); 674 Object *o = OBJECT(dev); 675 676 s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 677 rc4030_periodic_timer, s); 678 679 memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s, 680 "rc4030.chipset", 0x300); 681 memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s, 682 "rc4030.jazzio", 0x00001000); 683 684 memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr), 685 TYPE_RC4030_IOMMU_MEMORY_REGION, 686 o, "rc4030.dma", 4 * GiB); 687 address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma"); 688 } 689 690 static void rc4030_unrealize(DeviceState *dev, Error **errp) 691 { 692 rc4030State *s = RC4030(dev); 693 694 timer_free(s->periodic_timer); 695 696 address_space_destroy(&s->dma_as); 697 object_unparent(OBJECT(&s->dma_mr)); 698 } 699 700 static void rc4030_class_init(ObjectClass *klass, void *class_data) 701 { 702 DeviceClass *dc = DEVICE_CLASS(klass); 703 704 dc->realize = rc4030_realize; 705 dc->unrealize = rc4030_unrealize; 706 dc->reset = rc4030_reset; 707 dc->vmsd = &vmstate_rc4030; 708 } 709 710 static const TypeInfo rc4030_info = { 711 .name = TYPE_RC4030, 712 .parent = TYPE_SYS_BUS_DEVICE, 713 .instance_size = sizeof(rc4030State), 714 .instance_init = rc4030_initfn, 715 .class_init = rc4030_class_init, 716 }; 717 718 static void rc4030_iommu_memory_region_class_init(ObjectClass *klass, 719 void *data) 720 { 721 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 722 723 imrc->translate = rc4030_dma_translate; 724 } 725 726 static const TypeInfo rc4030_iommu_memory_region_info = { 727 .parent = TYPE_IOMMU_MEMORY_REGION, 728 .name = TYPE_RC4030_IOMMU_MEMORY_REGION, 729 .class_init = rc4030_iommu_memory_region_class_init, 730 }; 731 732 static void rc4030_register_types(void) 733 { 734 type_register_static(&rc4030_info); 735 type_register_static(&rc4030_iommu_memory_region_info); 736 } 737 738 type_init(rc4030_register_types) 739 740 DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr) 741 { 742 DeviceState *dev; 743 744 dev = qdev_create(NULL, TYPE_RC4030); 745 qdev_init_nofail(dev); 746 747 *dmas = rc4030_allocate_dmas(dev, 4); 748 *dma_mr = &RC4030(dev)->dma_mr; 749 return dev; 750 } 751