1 /* 2 * nRF51 System-on-Chip general purpose input/output register definition 3 * 4 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf 5 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf 6 * 7 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 #include "hw/gpio/nrf51_gpio.h" 17 #include "hw/irq.h" 18 #include "trace.h" 19 20 /* 21 * Check if the output driver is connected to the direction switch 22 * given the current configuration and logic level. 23 * It is not differentiated between standard and "high"(-power) drive modes. 24 */ 25 static bool is_connected(uint32_t config, uint32_t level) 26 { 27 bool state; 28 uint32_t drive_config = extract32(config, 8, 3); 29 30 switch (drive_config) { 31 case 0 ... 3: 32 state = true; 33 break; 34 case 4 ... 5: 35 state = level != 0; 36 break; 37 case 6 ... 7: 38 state = level == 0; 39 break; 40 default: 41 g_assert_not_reached(); 42 break; 43 } 44 45 return state; 46 } 47 48 static int pull_value(uint32_t config) 49 { 50 int pull = extract32(config, 2, 2); 51 if (pull == NRF51_GPIO_PULLDOWN) { 52 return 0; 53 } else if (pull == NRF51_GPIO_PULLUP) { 54 return 1; 55 } 56 return -1; 57 } 58 59 static void update_output_irq(NRF51GPIOState *s, size_t i, 60 bool connected, bool level) 61 { 62 int64_t irq_level = connected ? level : -1; 63 bool old_connected = extract32(s->old_out_connected, i, 1); 64 bool old_level = extract32(s->old_out, i, 1); 65 66 if ((old_connected != connected) || (old_level != level)) { 67 qemu_set_irq(s->output[i], irq_level); 68 trace_nrf51_gpio_update_output_irq(i, irq_level); 69 } 70 71 s->old_out = deposit32(s->old_out, i, 1, level); 72 s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); 73 } 74 75 static void update_state(NRF51GPIOState *s) 76 { 77 int pull; 78 size_t i; 79 bool connected_out, dir, connected_in, out, in, input; 80 81 for (i = 0; i < NRF51_GPIO_PINS; i++) { 82 pull = pull_value(s->cnf[i]); 83 dir = extract32(s->cnf[i], 0, 1); 84 connected_in = extract32(s->in_mask, i, 1); 85 out = extract32(s->out, i, 1); 86 in = extract32(s->in, i, 1); 87 input = !extract32(s->cnf[i], 1, 1); 88 connected_out = is_connected(s->cnf[i], out) && dir; 89 90 if (!input) { 91 if (pull >= 0) { 92 /* Input buffer disconnected from external drives */ 93 s->in = deposit32(s->in, i, 1, pull); 94 } 95 } else { 96 if (connected_out && connected_in && out != in) { 97 /* Pin both driven externally and internally */ 98 qemu_log_mask(LOG_GUEST_ERROR, 99 "GPIO pin %zu short circuited\n", i); 100 } 101 if (!connected_in) { 102 /* 103 * Floating input: the output stimulates IN if connected, 104 * otherwise pull-up/pull-down resistors put a value on both 105 * IN and OUT. 106 */ 107 if (pull >= 0 && !connected_out) { 108 connected_out = true; 109 out = pull; 110 } 111 if (connected_out) { 112 s->in = deposit32(s->in, i, 1, out); 113 } 114 } 115 } 116 update_output_irq(s, i, connected_out, out); 117 } 118 } 119 120 /* 121 * Direction is exposed in both the DIR register and the DIR bit 122 * of each PINs CNF configuration register. Reflect bits for pins in DIR 123 * to individual pin configuration registers. 124 */ 125 static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) 126 { 127 size_t i; 128 129 uint32_t value = s->dir; 130 131 for (i = 0; i < NRF51_GPIO_PINS; i++) { 132 s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); 133 } 134 } 135 136 static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size) 137 { 138 NRF51GPIOState *s = NRF51_GPIO(opaque); 139 uint64_t r = 0; 140 size_t idx; 141 142 switch (offset) { 143 case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: 144 r = s->out; 145 break; 146 147 case NRF51_GPIO_REG_IN: 148 r = s->in; 149 break; 150 151 case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: 152 r = s->dir; 153 break; 154 155 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 156 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 157 r = s->cnf[idx]; 158 break; 159 160 default: 161 qemu_log_mask(LOG_GUEST_ERROR, 162 "%s: bad read offset 0x%" HWADDR_PRIx "\n", 163 __func__, offset); 164 } 165 166 trace_nrf51_gpio_read(offset, r); 167 168 return r; 169 } 170 171 static void nrf51_gpio_write(void *opaque, hwaddr offset, 172 uint64_t value, unsigned int size) 173 { 174 NRF51GPIOState *s = NRF51_GPIO(opaque); 175 size_t idx; 176 177 trace_nrf51_gpio_write(offset, value); 178 179 switch (offset) { 180 case NRF51_GPIO_REG_OUT: 181 s->out = value; 182 break; 183 184 case NRF51_GPIO_REG_OUTSET: 185 s->out |= value; 186 break; 187 188 case NRF51_GPIO_REG_OUTCLR: 189 s->out &= ~value; 190 break; 191 192 case NRF51_GPIO_REG_DIR: 193 s->dir = value; 194 reflect_dir_bit_in_cnf(s); 195 break; 196 197 case NRF51_GPIO_REG_DIRSET: 198 s->dir |= value; 199 reflect_dir_bit_in_cnf(s); 200 break; 201 202 case NRF51_GPIO_REG_DIRCLR: 203 s->dir &= ~value; 204 reflect_dir_bit_in_cnf(s); 205 break; 206 207 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 208 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 209 s->cnf[idx] = value; 210 /* 211 * direction is exposed in both the DIR register and the DIR bit 212 * of each PINs CNF configuration register. 213 */ 214 s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); 215 break; 216 217 default: 218 qemu_log_mask(LOG_GUEST_ERROR, 219 "%s: bad write offset 0x%" HWADDR_PRIx "\n", 220 __func__, offset); 221 } 222 223 update_state(s); 224 } 225 226 static const MemoryRegionOps gpio_ops = { 227 .read = nrf51_gpio_read, 228 .write = nrf51_gpio_write, 229 .endianness = DEVICE_LITTLE_ENDIAN, 230 .impl.min_access_size = 4, 231 .impl.max_access_size = 4, 232 }; 233 234 static void nrf51_gpio_set(void *opaque, int line, int value) 235 { 236 NRF51GPIOState *s = NRF51_GPIO(opaque); 237 238 trace_nrf51_gpio_set(line, value); 239 240 assert(line >= 0 && line < NRF51_GPIO_PINS); 241 242 s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); 243 if (value >= 0) { 244 s->in = deposit32(s->in, line, 1, value != 0); 245 } 246 247 update_state(s); 248 } 249 250 static void nrf51_gpio_reset(DeviceState *dev) 251 { 252 NRF51GPIOState *s = NRF51_GPIO(dev); 253 size_t i; 254 255 s->out = 0; 256 s->old_out = 0; 257 s->old_out_connected = 0; 258 s->in = 0; 259 s->in_mask = 0; 260 s->dir = 0; 261 262 for (i = 0; i < NRF51_GPIO_PINS; i++) { 263 s->cnf[i] = 0x00000002; 264 } 265 } 266 267 static const VMStateDescription vmstate_nrf51_gpio = { 268 .name = TYPE_NRF51_GPIO, 269 .version_id = 1, 270 .minimum_version_id = 1, 271 .fields = (VMStateField[]) { 272 VMSTATE_UINT32(out, NRF51GPIOState), 273 VMSTATE_UINT32(in, NRF51GPIOState), 274 VMSTATE_UINT32(in_mask, NRF51GPIOState), 275 VMSTATE_UINT32(dir, NRF51GPIOState), 276 VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), 277 VMSTATE_UINT32(old_out, NRF51GPIOState), 278 VMSTATE_UINT32(old_out_connected, NRF51GPIOState), 279 VMSTATE_END_OF_LIST() 280 } 281 }; 282 283 static void nrf51_gpio_init(Object *obj) 284 { 285 NRF51GPIOState *s = NRF51_GPIO(obj); 286 287 memory_region_init_io(&s->mmio, obj, &gpio_ops, s, 288 TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); 289 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 290 291 qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); 292 qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); 293 } 294 295 static void nrf51_gpio_class_init(ObjectClass *klass, void *data) 296 { 297 DeviceClass *dc = DEVICE_CLASS(klass); 298 299 dc->vmsd = &vmstate_nrf51_gpio; 300 dc->reset = nrf51_gpio_reset; 301 dc->desc = "nRF51 GPIO"; 302 } 303 304 static const TypeInfo nrf51_gpio_info = { 305 .name = TYPE_NRF51_GPIO, 306 .parent = TYPE_SYS_BUS_DEVICE, 307 .instance_size = sizeof(NRF51GPIOState), 308 .instance_init = nrf51_gpio_init, 309 .class_init = nrf51_gpio_class_init 310 }; 311 312 static void nrf51_gpio_register_types(void) 313 { 314 type_register_static(&nrf51_gpio_info); 315 } 316 317 type_init(nrf51_gpio_register_types) 318