1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/sysbus.h" 13 14 //#define DEBUG_PL061 1 15 16 #ifdef DEBUG_PL061 17 #define DPRINTF(fmt, ...) \ 18 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 19 #define BADF(fmt, ...) \ 20 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 21 #else 22 #define DPRINTF(fmt, ...) do {} while(0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 25 #endif 26 27 static const uint8_t pl061_id[12] = 28 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 29 static const uint8_t pl061_id_luminary[12] = 30 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 31 32 #define TYPE_PL061 "pl061" 33 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 34 35 typedef struct PL061State { 36 SysBusDevice parent_obj; 37 38 MemoryRegion iomem; 39 uint32_t locked; 40 uint32_t data; 41 uint32_t old_out_data; 42 uint32_t old_in_data; 43 uint32_t dir; 44 uint32_t isense; 45 uint32_t ibe; 46 uint32_t iev; 47 uint32_t im; 48 uint32_t istate; 49 uint32_t afsel; 50 uint32_t dr2r; 51 uint32_t dr4r; 52 uint32_t dr8r; 53 uint32_t odr; 54 uint32_t pur; 55 uint32_t pdr; 56 uint32_t slr; 57 uint32_t den; 58 uint32_t cr; 59 uint32_t float_high; 60 uint32_t amsel; 61 qemu_irq irq; 62 qemu_irq out[8]; 63 const unsigned char *id; 64 } PL061State; 65 66 static const VMStateDescription vmstate_pl061 = { 67 .name = "pl061", 68 .version_id = 3, 69 .minimum_version_id = 3, 70 .fields = (VMStateField[]) { 71 VMSTATE_UINT32(locked, PL061State), 72 VMSTATE_UINT32(data, PL061State), 73 VMSTATE_UINT32(old_out_data, PL061State), 74 VMSTATE_UINT32(old_in_data, PL061State), 75 VMSTATE_UINT32(dir, PL061State), 76 VMSTATE_UINT32(isense, PL061State), 77 VMSTATE_UINT32(ibe, PL061State), 78 VMSTATE_UINT32(iev, PL061State), 79 VMSTATE_UINT32(im, PL061State), 80 VMSTATE_UINT32(istate, PL061State), 81 VMSTATE_UINT32(afsel, PL061State), 82 VMSTATE_UINT32(dr2r, PL061State), 83 VMSTATE_UINT32(dr4r, PL061State), 84 VMSTATE_UINT32(dr8r, PL061State), 85 VMSTATE_UINT32(odr, PL061State), 86 VMSTATE_UINT32(pur, PL061State), 87 VMSTATE_UINT32(pdr, PL061State), 88 VMSTATE_UINT32(slr, PL061State), 89 VMSTATE_UINT32(den, PL061State), 90 VMSTATE_UINT32(cr, PL061State), 91 VMSTATE_UINT32(float_high, PL061State), 92 VMSTATE_UINT32_V(amsel, PL061State, 2), 93 VMSTATE_END_OF_LIST() 94 } 95 }; 96 97 static void pl061_update(PL061State *s) 98 { 99 uint8_t changed; 100 uint8_t mask; 101 uint8_t out; 102 int i; 103 104 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 105 106 /* Outputs float high. */ 107 /* FIXME: This is board dependent. */ 108 out = (s->data & s->dir) | ~s->dir; 109 changed = s->old_out_data ^ out; 110 if (changed) { 111 s->old_out_data = out; 112 for (i = 0; i < 8; i++) { 113 mask = 1 << i; 114 if (changed & mask) { 115 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 116 qemu_set_irq(s->out[i], (out & mask) != 0); 117 } 118 } 119 } 120 121 /* Inputs */ 122 changed = (s->old_in_data ^ s->data) & ~s->dir; 123 if (changed) { 124 s->old_in_data = s->data; 125 for (i = 0; i < 8; i++) { 126 mask = 1 << i; 127 if (changed & mask) { 128 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 129 130 if (!(s->isense & mask)) { 131 /* Edge interrupt */ 132 if (s->ibe & mask) { 133 /* Any edge triggers the interrupt */ 134 s->istate |= mask; 135 } else { 136 /* Edge is selected by IEV */ 137 s->istate |= ~(s->data ^ s->iev) & mask; 138 } 139 } 140 } 141 } 142 } 143 144 /* Level interrupt */ 145 s->istate |= ~(s->data ^ s->iev) & s->isense; 146 147 DPRINTF("istate = %02X\n", s->istate); 148 149 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 150 } 151 152 static uint64_t pl061_read(void *opaque, hwaddr offset, 153 unsigned size) 154 { 155 PL061State *s = (PL061State *)opaque; 156 157 if (offset >= 0xfd0 && offset < 0x1000) { 158 return s->id[(offset - 0xfd0) >> 2]; 159 } 160 if (offset < 0x400) { 161 return s->data & (offset >> 2); 162 } 163 switch (offset) { 164 case 0x400: /* Direction */ 165 return s->dir; 166 case 0x404: /* Interrupt sense */ 167 return s->isense; 168 case 0x408: /* Interrupt both edges */ 169 return s->ibe; 170 case 0x40c: /* Interrupt event */ 171 return s->iev; 172 case 0x410: /* Interrupt mask */ 173 return s->im; 174 case 0x414: /* Raw interrupt status */ 175 return s->istate; 176 case 0x418: /* Masked interrupt status */ 177 return s->istate & s->im; 178 case 0x420: /* Alternate function select */ 179 return s->afsel; 180 case 0x500: /* 2mA drive */ 181 return s->dr2r; 182 case 0x504: /* 4mA drive */ 183 return s->dr4r; 184 case 0x508: /* 8mA drive */ 185 return s->dr8r; 186 case 0x50c: /* Open drain */ 187 return s->odr; 188 case 0x510: /* Pull-up */ 189 return s->pur; 190 case 0x514: /* Pull-down */ 191 return s->pdr; 192 case 0x518: /* Slew rate control */ 193 return s->slr; 194 case 0x51c: /* Digital enable */ 195 return s->den; 196 case 0x520: /* Lock */ 197 return s->locked; 198 case 0x524: /* Commit */ 199 return s->cr; 200 case 0x528: /* Analog mode select */ 201 return s->amsel; 202 default: 203 qemu_log_mask(LOG_GUEST_ERROR, 204 "pl061_read: Bad offset %x\n", (int)offset); 205 return 0; 206 } 207 } 208 209 static void pl061_write(void *opaque, hwaddr offset, 210 uint64_t value, unsigned size) 211 { 212 PL061State *s = (PL061State *)opaque; 213 uint8_t mask; 214 215 if (offset < 0x400) { 216 mask = (offset >> 2) & s->dir; 217 s->data = (s->data & ~mask) | (value & mask); 218 pl061_update(s); 219 return; 220 } 221 switch (offset) { 222 case 0x400: /* Direction */ 223 s->dir = value & 0xff; 224 break; 225 case 0x404: /* Interrupt sense */ 226 s->isense = value & 0xff; 227 break; 228 case 0x408: /* Interrupt both edges */ 229 s->ibe = value & 0xff; 230 break; 231 case 0x40c: /* Interrupt event */ 232 s->iev = value & 0xff; 233 break; 234 case 0x410: /* Interrupt mask */ 235 s->im = value & 0xff; 236 break; 237 case 0x41c: /* Interrupt clear */ 238 s->istate &= ~value; 239 break; 240 case 0x420: /* Alternate function select */ 241 mask = s->cr; 242 s->afsel = (s->afsel & ~mask) | (value & mask); 243 break; 244 case 0x500: /* 2mA drive */ 245 s->dr2r = value & 0xff; 246 break; 247 case 0x504: /* 4mA drive */ 248 s->dr4r = value & 0xff; 249 break; 250 case 0x508: /* 8mA drive */ 251 s->dr8r = value & 0xff; 252 break; 253 case 0x50c: /* Open drain */ 254 s->odr = value & 0xff; 255 break; 256 case 0x510: /* Pull-up */ 257 s->pur = value & 0xff; 258 break; 259 case 0x514: /* Pull-down */ 260 s->pdr = value & 0xff; 261 break; 262 case 0x518: /* Slew rate control */ 263 s->slr = value & 0xff; 264 break; 265 case 0x51c: /* Digital enable */ 266 s->den = value & 0xff; 267 break; 268 case 0x520: /* Lock */ 269 s->locked = (value != 0xacce551); 270 break; 271 case 0x524: /* Commit */ 272 if (!s->locked) 273 s->cr = value & 0xff; 274 break; 275 case 0x528: 276 s->amsel = value & 0xff; 277 break; 278 default: 279 qemu_log_mask(LOG_GUEST_ERROR, 280 "pl061_write: Bad offset %x\n", (int)offset); 281 } 282 pl061_update(s); 283 } 284 285 static void pl061_reset(PL061State *s) 286 { 287 s->locked = 1; 288 s->cr = 0xff; 289 } 290 291 static void pl061_set_irq(void * opaque, int irq, int level) 292 { 293 PL061State *s = (PL061State *)opaque; 294 uint8_t mask; 295 296 mask = 1 << irq; 297 if ((s->dir & mask) == 0) { 298 s->data &= ~mask; 299 if (level) 300 s->data |= mask; 301 pl061_update(s); 302 } 303 } 304 305 static const MemoryRegionOps pl061_ops = { 306 .read = pl061_read, 307 .write = pl061_write, 308 .endianness = DEVICE_NATIVE_ENDIAN, 309 }; 310 311 static int pl061_initfn(SysBusDevice *sbd) 312 { 313 DeviceState *dev = DEVICE(sbd); 314 PL061State *s = PL061(dev); 315 316 memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000); 317 sysbus_init_mmio(sbd, &s->iomem); 318 sysbus_init_irq(sbd, &s->irq); 319 qdev_init_gpio_in(dev, pl061_set_irq, 8); 320 qdev_init_gpio_out(dev, s->out, 8); 321 pl061_reset(s); 322 return 0; 323 } 324 325 static void pl061_luminary_init(Object *obj) 326 { 327 PL061State *s = PL061(obj); 328 329 s->id = pl061_id_luminary; 330 } 331 332 static void pl061_init(Object *obj) 333 { 334 PL061State *s = PL061(obj); 335 336 s->id = pl061_id; 337 } 338 339 static void pl061_class_init(ObjectClass *klass, void *data) 340 { 341 DeviceClass *dc = DEVICE_CLASS(klass); 342 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 343 344 k->init = pl061_initfn; 345 dc->vmsd = &vmstate_pl061; 346 } 347 348 static const TypeInfo pl061_info = { 349 .name = TYPE_PL061, 350 .parent = TYPE_SYS_BUS_DEVICE, 351 .instance_size = sizeof(PL061State), 352 .instance_init = pl061_init, 353 .class_init = pl061_class_init, 354 }; 355 356 static const TypeInfo pl061_luminary_info = { 357 .name = "pl061_luminary", 358 .parent = TYPE_PL061, 359 .instance_init = pl061_luminary_init, 360 }; 361 362 static void pl061_register_types(void) 363 { 364 type_register_static(&pl061_info); 365 type_register_static(&pl061_luminary_info); 366 } 367 368 type_init(pl061_register_types) 369