1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "qom/object.h" 18 #include "trace.h" 19 20 static const uint8_t pl061_id[12] = 21 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 22 static const uint8_t pl061_id_luminary[12] = 23 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 24 25 #define TYPE_PL061 "pl061" 26 OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061) 27 28 #define N_GPIOS 8 29 30 struct PL061State { 31 SysBusDevice parent_obj; 32 33 MemoryRegion iomem; 34 uint32_t locked; 35 uint32_t data; 36 uint32_t old_out_data; 37 uint32_t old_in_data; 38 uint32_t dir; 39 uint32_t isense; 40 uint32_t ibe; 41 uint32_t iev; 42 uint32_t im; 43 uint32_t istate; 44 uint32_t afsel; 45 uint32_t dr2r; 46 uint32_t dr4r; 47 uint32_t dr8r; 48 uint32_t odr; 49 uint32_t pur; 50 uint32_t pdr; 51 uint32_t slr; 52 uint32_t den; 53 uint32_t cr; 54 uint32_t amsel; 55 qemu_irq irq; 56 qemu_irq out[N_GPIOS]; 57 const unsigned char *id; 58 }; 59 60 static const VMStateDescription vmstate_pl061 = { 61 .name = "pl061", 62 .version_id = 4, 63 .minimum_version_id = 4, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT32(locked, PL061State), 66 VMSTATE_UINT32(data, PL061State), 67 VMSTATE_UINT32(old_out_data, PL061State), 68 VMSTATE_UINT32(old_in_data, PL061State), 69 VMSTATE_UINT32(dir, PL061State), 70 VMSTATE_UINT32(isense, PL061State), 71 VMSTATE_UINT32(ibe, PL061State), 72 VMSTATE_UINT32(iev, PL061State), 73 VMSTATE_UINT32(im, PL061State), 74 VMSTATE_UINT32(istate, PL061State), 75 VMSTATE_UINT32(afsel, PL061State), 76 VMSTATE_UINT32(dr2r, PL061State), 77 VMSTATE_UINT32(dr4r, PL061State), 78 VMSTATE_UINT32(dr8r, PL061State), 79 VMSTATE_UINT32(odr, PL061State), 80 VMSTATE_UINT32(pur, PL061State), 81 VMSTATE_UINT32(pdr, PL061State), 82 VMSTATE_UINT32(slr, PL061State), 83 VMSTATE_UINT32(den, PL061State), 84 VMSTATE_UINT32(cr, PL061State), 85 VMSTATE_UINT32_V(amsel, PL061State, 2), 86 VMSTATE_END_OF_LIST() 87 } 88 }; 89 90 static void pl061_update(PL061State *s) 91 { 92 uint8_t changed; 93 uint8_t mask; 94 uint8_t out; 95 int i; 96 97 trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); 98 99 /* Outputs float high. */ 100 /* FIXME: This is board dependent. */ 101 out = (s->data & s->dir) | ~s->dir; 102 changed = s->old_out_data ^ out; 103 if (changed) { 104 s->old_out_data = out; 105 for (i = 0; i < N_GPIOS; i++) { 106 mask = 1 << i; 107 if (changed & mask) { 108 int level = (out & mask) != 0; 109 trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); 110 qemu_set_irq(s->out[i], level); 111 } 112 } 113 } 114 115 /* Inputs */ 116 changed = (s->old_in_data ^ s->data) & ~s->dir; 117 if (changed) { 118 s->old_in_data = s->data; 119 for (i = 0; i < N_GPIOS; i++) { 120 mask = 1 << i; 121 if (changed & mask) { 122 trace_pl061_input_change(DEVICE(s)->canonical_path, i, 123 (s->data & mask) != 0); 124 125 if (!(s->isense & mask)) { 126 /* Edge interrupt */ 127 if (s->ibe & mask) { 128 /* Any edge triggers the interrupt */ 129 s->istate |= mask; 130 } else { 131 /* Edge is selected by IEV */ 132 s->istate |= ~(s->data ^ s->iev) & mask; 133 } 134 } 135 } 136 } 137 } 138 139 /* Level interrupt */ 140 s->istate |= ~(s->data ^ s->iev) & s->isense; 141 142 trace_pl061_update_istate(DEVICE(s)->canonical_path, 143 s->istate, s->im, (s->istate & s->im) != 0); 144 145 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 146 } 147 148 static uint64_t pl061_read(void *opaque, hwaddr offset, 149 unsigned size) 150 { 151 PL061State *s = (PL061State *)opaque; 152 153 switch (offset) { 154 case 0x0 ... 0x3ff: /* Data */ 155 return s->data & (offset >> 2); 156 case 0x400: /* Direction */ 157 return s->dir; 158 case 0x404: /* Interrupt sense */ 159 return s->isense; 160 case 0x408: /* Interrupt both edges */ 161 return s->ibe; 162 case 0x40c: /* Interrupt event */ 163 return s->iev; 164 case 0x410: /* Interrupt mask */ 165 return s->im; 166 case 0x414: /* Raw interrupt status */ 167 return s->istate; 168 case 0x418: /* Masked interrupt status */ 169 return s->istate & s->im; 170 case 0x420: /* Alternate function select */ 171 return s->afsel; 172 case 0x500: /* 2mA drive */ 173 if (s->id != pl061_id_luminary) { 174 goto bad_offset; 175 } 176 return s->dr2r; 177 case 0x504: /* 4mA drive */ 178 if (s->id != pl061_id_luminary) { 179 goto bad_offset; 180 } 181 return s->dr4r; 182 case 0x508: /* 8mA drive */ 183 if (s->id != pl061_id_luminary) { 184 goto bad_offset; 185 } 186 return s->dr8r; 187 case 0x50c: /* Open drain */ 188 if (s->id != pl061_id_luminary) { 189 goto bad_offset; 190 } 191 return s->odr; 192 case 0x510: /* Pull-up */ 193 if (s->id != pl061_id_luminary) { 194 goto bad_offset; 195 } 196 return s->pur; 197 case 0x514: /* Pull-down */ 198 if (s->id != pl061_id_luminary) { 199 goto bad_offset; 200 } 201 return s->pdr; 202 case 0x518: /* Slew rate control */ 203 if (s->id != pl061_id_luminary) { 204 goto bad_offset; 205 } 206 return s->slr; 207 case 0x51c: /* Digital enable */ 208 if (s->id != pl061_id_luminary) { 209 goto bad_offset; 210 } 211 return s->den; 212 case 0x520: /* Lock */ 213 if (s->id != pl061_id_luminary) { 214 goto bad_offset; 215 } 216 return s->locked; 217 case 0x524: /* Commit */ 218 if (s->id != pl061_id_luminary) { 219 goto bad_offset; 220 } 221 return s->cr; 222 case 0x528: /* Analog mode select */ 223 if (s->id != pl061_id_luminary) { 224 goto bad_offset; 225 } 226 return s->amsel; 227 case 0xfd0 ... 0xfff: /* ID registers */ 228 return s->id[(offset - 0xfd0) >> 2]; 229 default: 230 bad_offset: 231 qemu_log_mask(LOG_GUEST_ERROR, 232 "pl061_read: Bad offset %x\n", (int)offset); 233 break; 234 } 235 return 0; 236 } 237 238 static void pl061_write(void *opaque, hwaddr offset, 239 uint64_t value, unsigned size) 240 { 241 PL061State *s = (PL061State *)opaque; 242 uint8_t mask; 243 244 switch (offset) { 245 case 0 ... 0x3ff: 246 mask = (offset >> 2) & s->dir; 247 s->data = (s->data & ~mask) | (value & mask); 248 pl061_update(s); 249 return; 250 case 0x400: /* Direction */ 251 s->dir = value & 0xff; 252 break; 253 case 0x404: /* Interrupt sense */ 254 s->isense = value & 0xff; 255 break; 256 case 0x408: /* Interrupt both edges */ 257 s->ibe = value & 0xff; 258 break; 259 case 0x40c: /* Interrupt event */ 260 s->iev = value & 0xff; 261 break; 262 case 0x410: /* Interrupt mask */ 263 s->im = value & 0xff; 264 break; 265 case 0x41c: /* Interrupt clear */ 266 s->istate &= ~value; 267 break; 268 case 0x420: /* Alternate function select */ 269 mask = s->cr; 270 s->afsel = (s->afsel & ~mask) | (value & mask); 271 break; 272 case 0x500: /* 2mA drive */ 273 if (s->id != pl061_id_luminary) { 274 goto bad_offset; 275 } 276 s->dr2r = value & 0xff; 277 break; 278 case 0x504: /* 4mA drive */ 279 if (s->id != pl061_id_luminary) { 280 goto bad_offset; 281 } 282 s->dr4r = value & 0xff; 283 break; 284 case 0x508: /* 8mA drive */ 285 if (s->id != pl061_id_luminary) { 286 goto bad_offset; 287 } 288 s->dr8r = value & 0xff; 289 break; 290 case 0x50c: /* Open drain */ 291 if (s->id != pl061_id_luminary) { 292 goto bad_offset; 293 } 294 s->odr = value & 0xff; 295 break; 296 case 0x510: /* Pull-up */ 297 if (s->id != pl061_id_luminary) { 298 goto bad_offset; 299 } 300 s->pur = value & 0xff; 301 break; 302 case 0x514: /* Pull-down */ 303 if (s->id != pl061_id_luminary) { 304 goto bad_offset; 305 } 306 s->pdr = value & 0xff; 307 break; 308 case 0x518: /* Slew rate control */ 309 if (s->id != pl061_id_luminary) { 310 goto bad_offset; 311 } 312 s->slr = value & 0xff; 313 break; 314 case 0x51c: /* Digital enable */ 315 if (s->id != pl061_id_luminary) { 316 goto bad_offset; 317 } 318 s->den = value & 0xff; 319 break; 320 case 0x520: /* Lock */ 321 if (s->id != pl061_id_luminary) { 322 goto bad_offset; 323 } 324 s->locked = (value != 0xacce551); 325 break; 326 case 0x524: /* Commit */ 327 if (s->id != pl061_id_luminary) { 328 goto bad_offset; 329 } 330 if (!s->locked) 331 s->cr = value & 0xff; 332 break; 333 case 0x528: 334 if (s->id != pl061_id_luminary) { 335 goto bad_offset; 336 } 337 s->amsel = value & 0xff; 338 break; 339 default: 340 bad_offset: 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "pl061_write: Bad offset %x\n", (int)offset); 343 return; 344 } 345 pl061_update(s); 346 return; 347 } 348 349 static void pl061_reset(DeviceState *dev) 350 { 351 PL061State *s = PL061(dev); 352 353 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 354 s->data = 0; 355 s->old_out_data = 0; 356 s->old_in_data = 0; 357 s->dir = 0; 358 s->isense = 0; 359 s->ibe = 0; 360 s->iev = 0; 361 s->im = 0; 362 s->istate = 0; 363 s->afsel = 0; 364 s->dr2r = 0xff; 365 s->dr4r = 0; 366 s->dr8r = 0; 367 s->odr = 0; 368 s->pur = 0; 369 s->pdr = 0; 370 s->slr = 0; 371 s->den = 0; 372 s->locked = 1; 373 s->cr = 0xff; 374 s->amsel = 0; 375 } 376 377 static void pl061_set_irq(void * opaque, int irq, int level) 378 { 379 PL061State *s = (PL061State *)opaque; 380 uint8_t mask; 381 382 mask = 1 << irq; 383 if ((s->dir & mask) == 0) { 384 s->data &= ~mask; 385 if (level) 386 s->data |= mask; 387 pl061_update(s); 388 } 389 } 390 391 static const MemoryRegionOps pl061_ops = { 392 .read = pl061_read, 393 .write = pl061_write, 394 .endianness = DEVICE_NATIVE_ENDIAN, 395 }; 396 397 static void pl061_luminary_init(Object *obj) 398 { 399 PL061State *s = PL061(obj); 400 401 s->id = pl061_id_luminary; 402 } 403 404 static void pl061_init(Object *obj) 405 { 406 PL061State *s = PL061(obj); 407 DeviceState *dev = DEVICE(obj); 408 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 409 410 s->id = pl061_id; 411 412 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 413 sysbus_init_mmio(sbd, &s->iomem); 414 sysbus_init_irq(sbd, &s->irq); 415 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS); 416 qdev_init_gpio_out(dev, s->out, N_GPIOS); 417 } 418 419 static void pl061_class_init(ObjectClass *klass, void *data) 420 { 421 DeviceClass *dc = DEVICE_CLASS(klass); 422 423 dc->vmsd = &vmstate_pl061; 424 dc->reset = &pl061_reset; 425 } 426 427 static const TypeInfo pl061_info = { 428 .name = TYPE_PL061, 429 .parent = TYPE_SYS_BUS_DEVICE, 430 .instance_size = sizeof(PL061State), 431 .instance_init = pl061_init, 432 .class_init = pl061_class_init, 433 }; 434 435 static const TypeInfo pl061_luminary_info = { 436 .name = "pl061_luminary", 437 .parent = TYPE_PL061, 438 .instance_init = pl061_luminary_init, 439 }; 440 441 static void pl061_register_types(void) 442 { 443 type_register_static(&pl061_info); 444 type_register_static(&pl061_luminary_info); 445 } 446 447 type_init(pl061_register_types) 448