1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "acpi-build.h" 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "hw/i386/pc.h" 32 #include "target/i386/cpu.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/timer/mc146818rtc_regs.h" 48 #include "sysemu/numa.h" 49 50 /* Supported chipsets: */ 51 #include "hw/acpi/piix4.h" 52 #include "hw/acpi/pcihp.h" 53 #include "hw/i386/ich9.h" 54 #include "hw/pci/pci_bus.h" 55 #include "hw/pci-host/q35.h" 56 #include "hw/i386/x86-iommu.h" 57 58 #include "hw/acpi/aml-build.h" 59 60 #include "qom/qom-qobject.h" 61 #include "hw/i386/amd_iommu.h" 62 #include "hw/i386/intel_iommu.h" 63 64 #include "hw/acpi/ipmi.h" 65 66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 68 * a little bit, there should be plenty of free space since the DSDT 69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 70 */ 71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 72 #define ACPI_BUILD_ALIGN_SIZE 0x1000 73 74 #define ACPI_BUILD_TABLE_SIZE 0x20000 75 76 /* #define DEBUG_ACPI_BUILD */ 77 #ifdef DEBUG_ACPI_BUILD 78 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 80 #else 81 #define ACPI_BUILD_DPRINTF(fmt, ...) 82 #endif 83 84 /* Default IOAPIC ID */ 85 #define ACPI_BUILD_IOAPIC_ID 0x0 86 87 typedef struct AcpiMcfgInfo { 88 uint64_t mcfg_base; 89 uint32_t mcfg_size; 90 } AcpiMcfgInfo; 91 92 typedef struct AcpiPmInfo { 93 bool s3_disabled; 94 bool s4_disabled; 95 bool pcihp_bridge_en; 96 uint8_t s4_val; 97 uint16_t sci_int; 98 uint8_t acpi_enable_cmd; 99 uint8_t acpi_disable_cmd; 100 uint32_t gpe0_blk; 101 uint32_t gpe0_blk_len; 102 uint32_t io_base; 103 uint16_t cpu_hp_io_base; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool is_piix4; 110 bool has_hpet; 111 TPMVersion tpm_version; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 static void acpi_get_pm_info(AcpiPmInfo *pm) 126 { 127 Object *piix = piix4_pm_find(); 128 Object *lpc = ich9_lpc_find(); 129 Object *obj = NULL; 130 QObject *o; 131 132 pm->cpu_hp_io_base = 0; 133 pm->pcihp_io_base = 0; 134 pm->pcihp_io_len = 0; 135 if (piix) { 136 obj = piix; 137 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 138 pm->pcihp_io_base = 139 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 140 pm->pcihp_io_len = 141 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 142 } 143 if (lpc) { 144 obj = lpc; 145 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 146 } 147 assert(obj); 148 149 /* Fill in optional s3/s4 related properties */ 150 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 151 if (o) { 152 pm->s3_disabled = qnum_get_uint(qobject_to_qnum(o)); 153 } else { 154 pm->s3_disabled = false; 155 } 156 qobject_decref(o); 157 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 158 if (o) { 159 pm->s4_disabled = qnum_get_uint(qobject_to_qnum(o)); 160 } else { 161 pm->s4_disabled = false; 162 } 163 qobject_decref(o); 164 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 165 if (o) { 166 pm->s4_val = qnum_get_uint(qobject_to_qnum(o)); 167 } else { 168 pm->s4_val = false; 169 } 170 qobject_decref(o); 171 172 /* Fill in mandatory properties */ 173 pm->sci_int = object_property_get_uint(obj, ACPI_PM_PROP_SCI_INT, NULL); 174 175 pm->acpi_enable_cmd = object_property_get_uint(obj, 176 ACPI_PM_PROP_ACPI_ENABLE_CMD, 177 NULL); 178 pm->acpi_disable_cmd = 179 object_property_get_uint(obj, 180 ACPI_PM_PROP_ACPI_DISABLE_CMD, 181 NULL); 182 pm->io_base = object_property_get_uint(obj, ACPI_PM_PROP_PM_IO_BASE, 183 NULL); 184 pm->gpe0_blk = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK, 185 NULL); 186 pm->gpe0_blk_len = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 187 NULL); 188 pm->pcihp_bridge_en = 189 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 190 NULL); 191 } 192 193 static void acpi_get_misc_info(AcpiMiscInfo *info) 194 { 195 Object *piix = piix4_pm_find(); 196 Object *lpc = ich9_lpc_find(); 197 assert(!!piix != !!lpc); 198 199 if (piix) { 200 info->is_piix4 = true; 201 } 202 if (lpc) { 203 info->is_piix4 = false; 204 } 205 206 info->has_hpet = hpet_find(); 207 info->tpm_version = tpm_get_version(); 208 info->pvpanic_port = pvpanic_port(); 209 info->applesmc_io_base = applesmc_port(); 210 } 211 212 /* 213 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 214 * On i386 arch we only have two pci hosts, so we can look only for them. 215 */ 216 static Object *acpi_get_i386_pci_host(void) 217 { 218 PCIHostState *host; 219 220 host = OBJECT_CHECK(PCIHostState, 221 object_resolve_path("/machine/i440fx", NULL), 222 TYPE_PCI_HOST_BRIDGE); 223 if (!host) { 224 host = OBJECT_CHECK(PCIHostState, 225 object_resolve_path("/machine/q35", NULL), 226 TYPE_PCI_HOST_BRIDGE); 227 } 228 229 return OBJECT(host); 230 } 231 232 static void acpi_get_pci_holes(Range *hole, Range *hole64) 233 { 234 Object *pci_host; 235 236 pci_host = acpi_get_i386_pci_host(); 237 g_assert(pci_host); 238 239 range_set_bounds1(hole, 240 object_property_get_uint(pci_host, 241 PCI_HOST_PROP_PCI_HOLE_START, 242 NULL), 243 object_property_get_uint(pci_host, 244 PCI_HOST_PROP_PCI_HOLE_END, 245 NULL)); 246 range_set_bounds1(hole64, 247 object_property_get_uint(pci_host, 248 PCI_HOST_PROP_PCI_HOLE64_START, 249 NULL), 250 object_property_get_uint(pci_host, 251 PCI_HOST_PROP_PCI_HOLE64_END, 252 NULL)); 253 } 254 255 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 256 257 static void acpi_align_size(GArray *blob, unsigned align) 258 { 259 /* Align size to multiple of given size. This reduces the chance 260 * we need to change size in the future (breaking cross version migration). 261 */ 262 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 263 } 264 265 /* FACS */ 266 static void 267 build_facs(GArray *table_data, BIOSLinker *linker) 268 { 269 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 270 memcpy(&facs->signature, "FACS", 4); 271 facs->length = cpu_to_le32(sizeof(*facs)); 272 } 273 274 /* Load chipset information in FADT */ 275 static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm) 276 { 277 fadt->model = 1; 278 fadt->reserved1 = 0; 279 fadt->sci_int = cpu_to_le16(pm->sci_int); 280 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 281 fadt->acpi_enable = pm->acpi_enable_cmd; 282 fadt->acpi_disable = pm->acpi_disable_cmd; 283 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 284 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 285 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 286 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 287 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 288 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 289 fadt->pm1_evt_len = 4; 290 fadt->pm1_cnt_len = 2; 291 fadt->pm_tmr_len = 4; 292 fadt->gpe0_blk_len = pm->gpe0_blk_len; 293 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 294 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 295 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 296 (1 << ACPI_FADT_F_PROC_C1) | 297 (1 << ACPI_FADT_F_SLP_BUTTON) | 298 (1 << ACPI_FADT_F_RTC_S4)); 299 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 300 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 301 * For more than 8 CPUs, "Clustered Logical" mode has to be used 302 */ 303 if (max_cpus > 8) { 304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 305 } 306 fadt->century = RTC_CENTURY; 307 308 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP); 309 fadt->reset_value = 0xf; 310 fadt->reset_register.space_id = AML_SYSTEM_IO; 311 fadt->reset_register.bit_width = 8; 312 fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT); 313 /* The above need not be conditional on machine type because the reset port 314 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 315 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 316 317 fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO; 318 fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8; 319 fadt->xpm1a_event_block.address = cpu_to_le64(pm->io_base); 320 321 fadt->xpm1a_control_block.space_id = AML_SYSTEM_IO; 322 fadt->xpm1a_control_block.bit_width = fadt->pm1_cnt_len * 8; 323 fadt->xpm1a_control_block.address = cpu_to_le64(pm->io_base + 0x4); 324 325 fadt->xpm_timer_block.space_id = AML_SYSTEM_IO; 326 fadt->xpm_timer_block.bit_width = fadt->pm_tmr_len * 8; 327 fadt->xpm_timer_block.address = cpu_to_le64(pm->io_base + 0x8); 328 329 fadt->xgpe0_block.space_id = AML_SYSTEM_IO; 330 fadt->xgpe0_block.bit_width = pm->gpe0_blk_len * 8; 331 fadt->xgpe0_block.address = cpu_to_le64(pm->gpe0_blk); 332 } 333 334 335 /* FADT */ 336 static void 337 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, 338 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset, 339 const char *oem_id, const char *oem_table_id) 340 { 341 AcpiFadtDescriptorRev3 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 342 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data; 343 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data; 344 unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data; 345 346 /* FACS address to be filled by Guest linker */ 347 bios_linker_loader_add_pointer(linker, 348 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl), 349 ACPI_BUILD_TABLE_FILE, facs_tbl_offset); 350 351 /* DSDT address to be filled by Guest linker */ 352 fadt_setup(fadt, pm); 353 bios_linker_loader_add_pointer(linker, 354 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt), 355 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); 356 bios_linker_loader_add_pointer(linker, 357 ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt), 358 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); 359 360 build_header(linker, table_data, 361 (void *)fadt, "FACP", sizeof(*fadt), 3, oem_id, oem_table_id); 362 } 363 364 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 365 const CPUArchIdList *apic_ids, GArray *entry) 366 { 367 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 368 369 /* ACPI spec says that LAPIC entry for non present 370 * CPU may be omitted from MADT or it must be marked 371 * as disabled. However omitting non present CPU from 372 * MADT breaks hotplug on linux. So possible CPUs 373 * should be put in MADT but kept disabled. 374 */ 375 if (apic_id < 255) { 376 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 377 378 apic->type = ACPI_APIC_PROCESSOR; 379 apic->length = sizeof(*apic); 380 apic->processor_id = uid; 381 apic->local_apic_id = apic_id; 382 if (apic_ids->cpus[uid].cpu != NULL) { 383 apic->flags = cpu_to_le32(1); 384 } else { 385 apic->flags = cpu_to_le32(0); 386 } 387 } else { 388 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 389 390 apic->type = ACPI_APIC_LOCAL_X2APIC; 391 apic->length = sizeof(*apic); 392 apic->uid = cpu_to_le32(uid); 393 apic->x2apic_id = cpu_to_le32(apic_id); 394 if (apic_ids->cpus[uid].cpu != NULL) { 395 apic->flags = cpu_to_le32(1); 396 } else { 397 apic->flags = cpu_to_le32(0); 398 } 399 } 400 } 401 402 static void 403 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 404 { 405 MachineClass *mc = MACHINE_GET_CLASS(pcms); 406 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 407 int madt_start = table_data->len; 408 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 409 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 410 bool x2apic_mode = false; 411 412 AcpiMultipleApicTable *madt; 413 AcpiMadtIoApic *io_apic; 414 AcpiMadtIntsrcovr *intsrcovr; 415 int i; 416 417 madt = acpi_data_push(table_data, sizeof *madt); 418 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 419 madt->flags = cpu_to_le32(1); 420 421 for (i = 0; i < apic_ids->len; i++) { 422 adevc->madt_cpu(adev, i, apic_ids, table_data); 423 if (apic_ids->cpus[i].arch_id > 254) { 424 x2apic_mode = true; 425 } 426 } 427 428 io_apic = acpi_data_push(table_data, sizeof *io_apic); 429 io_apic->type = ACPI_APIC_IO; 430 io_apic->length = sizeof(*io_apic); 431 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 432 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 433 io_apic->interrupt = cpu_to_le32(0); 434 435 if (pcms->apic_xrupt_override) { 436 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 437 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 438 intsrcovr->length = sizeof(*intsrcovr); 439 intsrcovr->source = 0; 440 intsrcovr->gsi = cpu_to_le32(2); 441 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 442 } 443 for (i = 1; i < 16; i++) { 444 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 445 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 446 /* No need for a INT source override structure. */ 447 continue; 448 } 449 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 450 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 451 intsrcovr->length = sizeof(*intsrcovr); 452 intsrcovr->source = i; 453 intsrcovr->gsi = cpu_to_le32(i); 454 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 455 } 456 457 if (x2apic_mode) { 458 AcpiMadtLocalX2ApicNmi *local_nmi; 459 460 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 461 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 462 local_nmi->length = sizeof(*local_nmi); 463 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 464 local_nmi->flags = cpu_to_le16(0); 465 local_nmi->lint = 1; /* ACPI_LINT1 */ 466 } else { 467 AcpiMadtLocalNmi *local_nmi; 468 469 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 470 local_nmi->type = ACPI_APIC_LOCAL_NMI; 471 local_nmi->length = sizeof(*local_nmi); 472 local_nmi->processor_id = 0xff; /* all processors */ 473 local_nmi->flags = cpu_to_le16(0); 474 local_nmi->lint = 1; /* ACPI_LINT1 */ 475 } 476 477 build_header(linker, table_data, 478 (void *)(table_data->data + madt_start), "APIC", 479 table_data->len - madt_start, 1, NULL, NULL); 480 } 481 482 /* Assign BSEL property to all buses. In the future, this can be changed 483 * to only assign to buses that support hotplug. 484 */ 485 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 486 { 487 unsigned *bsel_alloc = opaque; 488 unsigned *bus_bsel; 489 490 if (qbus_is_hotpluggable(BUS(bus))) { 491 bus_bsel = g_malloc(sizeof *bus_bsel); 492 493 *bus_bsel = (*bsel_alloc)++; 494 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 495 bus_bsel, &error_abort); 496 } 497 498 return bsel_alloc; 499 } 500 501 static void acpi_set_pci_info(void) 502 { 503 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 504 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT; 505 506 if (bus) { 507 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 508 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 509 } 510 } 511 512 static void build_append_pcihp_notify_entry(Aml *method, int slot) 513 { 514 Aml *if_ctx; 515 int32_t devfn = PCI_DEVFN(slot, 0); 516 517 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 518 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 519 aml_append(method, if_ctx); 520 } 521 522 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 523 bool pcihp_bridge_en) 524 { 525 Aml *dev, *notify_method, *method; 526 QObject *bsel; 527 PCIBus *sec; 528 int i; 529 530 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 531 if (bsel) { 532 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel)); 533 534 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 535 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 536 } 537 538 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 539 DeviceClass *dc; 540 PCIDeviceClass *pc; 541 PCIDevice *pdev = bus->devices[i]; 542 int slot = PCI_SLOT(i); 543 bool hotplug_enabled_dev; 544 bool bridge_in_acpi; 545 546 if (!pdev) { 547 if (bsel) { /* add hotplug slots for non present devices */ 548 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 549 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 550 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 551 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 552 aml_append(method, 553 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 554 ); 555 aml_append(dev, method); 556 aml_append(parent_scope, dev); 557 558 build_append_pcihp_notify_entry(notify_method, slot); 559 } 560 continue; 561 } 562 563 pc = PCI_DEVICE_GET_CLASS(pdev); 564 dc = DEVICE_GET_CLASS(pdev); 565 566 /* When hotplug for bridges is enabled, bridges are 567 * described in ACPI separately (see build_pci_bus_end). 568 * In this case they aren't themselves hot-pluggable. 569 * Hotplugged bridges *are* hot-pluggable. 570 */ 571 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 572 !DEVICE(pdev)->hotplugged; 573 574 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 575 576 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 577 continue; 578 } 579 580 /* start to compose PCI slot descriptor */ 581 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 582 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 583 584 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 585 /* add VGA specific AML methods */ 586 int s3d; 587 588 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 589 s3d = 3; 590 } else { 591 s3d = 0; 592 } 593 594 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 595 aml_append(method, aml_return(aml_int(0))); 596 aml_append(dev, method); 597 598 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 599 aml_append(method, aml_return(aml_int(0))); 600 aml_append(dev, method); 601 602 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 603 aml_append(method, aml_return(aml_int(s3d))); 604 aml_append(dev, method); 605 } else if (hotplug_enabled_dev) { 606 /* add _SUN/_EJ0 to make slot hotpluggable */ 607 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 608 609 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 610 aml_append(method, 611 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 612 ); 613 aml_append(dev, method); 614 615 if (bsel) { 616 build_append_pcihp_notify_entry(notify_method, slot); 617 } 618 } else if (bridge_in_acpi) { 619 /* 620 * device is coldplugged bridge, 621 * add child device descriptions into its scope 622 */ 623 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 624 625 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 626 } 627 /* slot descriptor has been composed, add it into parent context */ 628 aml_append(parent_scope, dev); 629 } 630 631 if (bsel) { 632 aml_append(parent_scope, notify_method); 633 } 634 635 /* Append PCNT method to notify about events on local and child buses. 636 * Add unconditionally for root since DSDT expects it. 637 */ 638 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 639 640 /* If bus supports hotplug select it and notify about local events */ 641 if (bsel) { 642 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel)); 643 644 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 645 aml_append(method, 646 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 647 ); 648 aml_append(method, 649 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 650 ); 651 } 652 653 /* Notify about child bus events in any case */ 654 if (pcihp_bridge_en) { 655 QLIST_FOREACH(sec, &bus->child, sibling) { 656 int32_t devfn = sec->parent_dev->devfn; 657 658 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 659 continue; 660 } 661 662 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 663 } 664 } 665 aml_append(parent_scope, method); 666 qobject_decref(bsel); 667 } 668 669 /** 670 * build_prt_entry: 671 * @link_name: link name for PCI route entry 672 * 673 * build AML package containing a PCI route entry for @link_name 674 */ 675 static Aml *build_prt_entry(const char *link_name) 676 { 677 Aml *a_zero = aml_int(0); 678 Aml *pkg = aml_package(4); 679 aml_append(pkg, a_zero); 680 aml_append(pkg, a_zero); 681 aml_append(pkg, aml_name("%s", link_name)); 682 aml_append(pkg, a_zero); 683 return pkg; 684 } 685 686 /* 687 * initialize_route - Initialize the interrupt routing rule 688 * through a specific LINK: 689 * if (lnk_idx == idx) 690 * route using link 'link_name' 691 */ 692 static Aml *initialize_route(Aml *route, const char *link_name, 693 Aml *lnk_idx, int idx) 694 { 695 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 696 Aml *pkg = build_prt_entry(link_name); 697 698 aml_append(if_ctx, aml_store(pkg, route)); 699 700 return if_ctx; 701 } 702 703 /* 704 * build_prt - Define interrupt rounting rules 705 * 706 * Returns an array of 128 routes, one for each device, 707 * based on device location. 708 * The main goal is to equaly distribute the interrupts 709 * over the 4 existing ACPI links (works only for i440fx). 710 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 711 * 712 */ 713 static Aml *build_prt(bool is_pci0_prt) 714 { 715 Aml *method, *while_ctx, *pin, *res; 716 717 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 718 res = aml_local(0); 719 pin = aml_local(1); 720 aml_append(method, aml_store(aml_package(128), res)); 721 aml_append(method, aml_store(aml_int(0), pin)); 722 723 /* while (pin < 128) */ 724 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 725 { 726 Aml *slot = aml_local(2); 727 Aml *lnk_idx = aml_local(3); 728 Aml *route = aml_local(4); 729 730 /* slot = pin >> 2 */ 731 aml_append(while_ctx, 732 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 733 /* lnk_idx = (slot + pin) & 3 */ 734 aml_append(while_ctx, 735 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 736 lnk_idx)); 737 738 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 739 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 740 if (is_pci0_prt) { 741 Aml *if_device_1, *if_pin_4, *else_pin_4; 742 743 /* device 1 is the power-management device, needs SCI */ 744 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 745 { 746 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 747 { 748 aml_append(if_pin_4, 749 aml_store(build_prt_entry("LNKS"), route)); 750 } 751 aml_append(if_device_1, if_pin_4); 752 else_pin_4 = aml_else(); 753 { 754 aml_append(else_pin_4, 755 aml_store(build_prt_entry("LNKA"), route)); 756 } 757 aml_append(if_device_1, else_pin_4); 758 } 759 aml_append(while_ctx, if_device_1); 760 } else { 761 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 762 } 763 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 764 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 765 766 /* route[0] = 0x[slot]FFFF */ 767 aml_append(while_ctx, 768 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 769 NULL), 770 aml_index(route, aml_int(0)))); 771 /* route[1] = pin & 3 */ 772 aml_append(while_ctx, 773 aml_store(aml_and(pin, aml_int(3), NULL), 774 aml_index(route, aml_int(1)))); 775 /* res[pin] = route */ 776 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 777 /* pin++ */ 778 aml_append(while_ctx, aml_increment(pin)); 779 } 780 aml_append(method, while_ctx); 781 /* return res*/ 782 aml_append(method, aml_return(res)); 783 784 return method; 785 } 786 787 typedef struct CrsRangeEntry { 788 uint64_t base; 789 uint64_t limit; 790 } CrsRangeEntry; 791 792 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 793 { 794 CrsRangeEntry *entry; 795 796 entry = g_malloc(sizeof(*entry)); 797 entry->base = base; 798 entry->limit = limit; 799 800 g_ptr_array_add(ranges, entry); 801 } 802 803 static void crs_range_free(gpointer data) 804 { 805 CrsRangeEntry *entry = (CrsRangeEntry *)data; 806 g_free(entry); 807 } 808 809 typedef struct CrsRangeSet { 810 GPtrArray *io_ranges; 811 GPtrArray *mem_ranges; 812 GPtrArray *mem_64bit_ranges; 813 } CrsRangeSet; 814 815 static void crs_range_set_init(CrsRangeSet *range_set) 816 { 817 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 818 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 819 range_set->mem_64bit_ranges = 820 g_ptr_array_new_with_free_func(crs_range_free); 821 } 822 823 static void crs_range_set_free(CrsRangeSet *range_set) 824 { 825 g_ptr_array_free(range_set->io_ranges, true); 826 g_ptr_array_free(range_set->mem_ranges, true); 827 g_ptr_array_free(range_set->mem_64bit_ranges, true); 828 } 829 830 static gint crs_range_compare(gconstpointer a, gconstpointer b) 831 { 832 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 833 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 834 835 return (int64_t)entry_a->base - (int64_t)entry_b->base; 836 } 837 838 /* 839 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 840 * interval, computes the 'free' ranges from the same interval. 841 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 842 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 843 */ 844 static void crs_replace_with_free_ranges(GPtrArray *ranges, 845 uint64_t start, uint64_t end) 846 { 847 GPtrArray *free_ranges = g_ptr_array_new(); 848 uint64_t free_base = start; 849 int i; 850 851 g_ptr_array_sort(ranges, crs_range_compare); 852 for (i = 0; i < ranges->len; i++) { 853 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 854 855 if (free_base < used->base) { 856 crs_range_insert(free_ranges, free_base, used->base - 1); 857 } 858 859 free_base = used->limit + 1; 860 } 861 862 if (free_base < end) { 863 crs_range_insert(free_ranges, free_base, end); 864 } 865 866 g_ptr_array_set_size(ranges, 0); 867 for (i = 0; i < free_ranges->len; i++) { 868 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 869 } 870 871 g_ptr_array_free(free_ranges, true); 872 } 873 874 /* 875 * crs_range_merge - merges adjacent ranges in the given array. 876 * Array elements are deleted and replaced with the merged ranges. 877 */ 878 static void crs_range_merge(GPtrArray *range) 879 { 880 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 881 CrsRangeEntry *entry; 882 uint64_t range_base, range_limit; 883 int i; 884 885 if (!range->len) { 886 return; 887 } 888 889 g_ptr_array_sort(range, crs_range_compare); 890 891 entry = g_ptr_array_index(range, 0); 892 range_base = entry->base; 893 range_limit = entry->limit; 894 for (i = 1; i < range->len; i++) { 895 entry = g_ptr_array_index(range, i); 896 if (entry->base - 1 == range_limit) { 897 range_limit = entry->limit; 898 } else { 899 crs_range_insert(tmp, range_base, range_limit); 900 range_base = entry->base; 901 range_limit = entry->limit; 902 } 903 } 904 crs_range_insert(tmp, range_base, range_limit); 905 906 g_ptr_array_set_size(range, 0); 907 for (i = 0; i < tmp->len; i++) { 908 entry = g_ptr_array_index(tmp, i); 909 crs_range_insert(range, entry->base, entry->limit); 910 } 911 g_ptr_array_free(tmp, true); 912 } 913 914 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 915 { 916 Aml *crs = aml_resource_template(); 917 CrsRangeSet temp_range_set; 918 CrsRangeEntry *entry; 919 uint8_t max_bus = pci_bus_num(host->bus); 920 uint8_t type; 921 int devfn; 922 int i; 923 924 crs_range_set_init(&temp_range_set); 925 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 926 uint64_t range_base, range_limit; 927 PCIDevice *dev = host->bus->devices[devfn]; 928 929 if (!dev) { 930 continue; 931 } 932 933 for (i = 0; i < PCI_NUM_REGIONS; i++) { 934 PCIIORegion *r = &dev->io_regions[i]; 935 936 range_base = r->addr; 937 range_limit = r->addr + r->size - 1; 938 939 /* 940 * Work-around for old bioses 941 * that do not support multiple root buses 942 */ 943 if (!range_base || range_base > range_limit) { 944 continue; 945 } 946 947 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 948 crs_range_insert(temp_range_set.io_ranges, 949 range_base, range_limit); 950 } else { /* "memory" */ 951 crs_range_insert(temp_range_set.mem_ranges, 952 range_base, range_limit); 953 } 954 } 955 956 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 957 if (type == PCI_HEADER_TYPE_BRIDGE) { 958 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 959 if (subordinate > max_bus) { 960 max_bus = subordinate; 961 } 962 963 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 964 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 965 966 /* 967 * Work-around for old bioses 968 * that do not support multiple root buses 969 */ 970 if (range_base && range_base <= range_limit) { 971 crs_range_insert(temp_range_set.io_ranges, 972 range_base, range_limit); 973 } 974 975 range_base = 976 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 977 range_limit = 978 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 979 980 /* 981 * Work-around for old bioses 982 * that do not support multiple root buses 983 */ 984 if (range_base && range_base <= range_limit) { 985 uint64_t length = range_limit - range_base + 1; 986 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 987 crs_range_insert(temp_range_set.mem_ranges, 988 range_base, range_limit); 989 } else { 990 crs_range_insert(temp_range_set.mem_64bit_ranges, 991 range_base, range_limit); 992 } 993 } 994 995 range_base = 996 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 997 range_limit = 998 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 999 1000 /* 1001 * Work-around for old bioses 1002 * that do not support multiple root buses 1003 */ 1004 if (range_base && range_base <= range_limit) { 1005 uint64_t length = range_limit - range_base + 1; 1006 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 1007 crs_range_insert(temp_range_set.mem_ranges, 1008 range_base, range_limit); 1009 } else { 1010 crs_range_insert(temp_range_set.mem_64bit_ranges, 1011 range_base, range_limit); 1012 } 1013 } 1014 } 1015 } 1016 1017 crs_range_merge(temp_range_set.io_ranges); 1018 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 1019 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 1020 aml_append(crs, 1021 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1022 AML_POS_DECODE, AML_ENTIRE_RANGE, 1023 0, entry->base, entry->limit, 0, 1024 entry->limit - entry->base + 1)); 1025 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 1026 } 1027 1028 crs_range_merge(temp_range_set.mem_ranges); 1029 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 1030 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 1031 aml_append(crs, 1032 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1033 AML_MAX_FIXED, AML_NON_CACHEABLE, 1034 AML_READ_WRITE, 1035 0, entry->base, entry->limit, 0, 1036 entry->limit - entry->base + 1)); 1037 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 1038 } 1039 1040 crs_range_merge(temp_range_set.mem_64bit_ranges); 1041 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 1042 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 1043 aml_append(crs, 1044 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1045 AML_MAX_FIXED, AML_NON_CACHEABLE, 1046 AML_READ_WRITE, 1047 0, entry->base, entry->limit, 0, 1048 entry->limit - entry->base + 1)); 1049 crs_range_insert(range_set->mem_64bit_ranges, 1050 entry->base, entry->limit); 1051 } 1052 1053 crs_range_set_free(&temp_range_set); 1054 1055 aml_append(crs, 1056 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1057 0, 1058 pci_bus_num(host->bus), 1059 max_bus, 1060 0, 1061 max_bus - pci_bus_num(host->bus) + 1)); 1062 1063 return crs; 1064 } 1065 1066 static void build_hpet_aml(Aml *table) 1067 { 1068 Aml *crs; 1069 Aml *field; 1070 Aml *method; 1071 Aml *if_ctx; 1072 Aml *scope = aml_scope("_SB"); 1073 Aml *dev = aml_device("HPET"); 1074 Aml *zero = aml_int(0); 1075 Aml *id = aml_local(0); 1076 Aml *period = aml_local(1); 1077 1078 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1079 aml_append(dev, aml_name_decl("_UID", zero)); 1080 1081 aml_append(dev, 1082 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1083 HPET_LEN)); 1084 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1085 aml_append(field, aml_named_field("VEND", 32)); 1086 aml_append(field, aml_named_field("PRD", 32)); 1087 aml_append(dev, field); 1088 1089 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1090 aml_append(method, aml_store(aml_name("VEND"), id)); 1091 aml_append(method, aml_store(aml_name("PRD"), period)); 1092 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1093 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1094 aml_equal(id, aml_int(0xffff)))); 1095 { 1096 aml_append(if_ctx, aml_return(zero)); 1097 } 1098 aml_append(method, if_ctx); 1099 1100 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1101 aml_lgreater(period, aml_int(100000000)))); 1102 { 1103 aml_append(if_ctx, aml_return(zero)); 1104 } 1105 aml_append(method, if_ctx); 1106 1107 aml_append(method, aml_return(aml_int(0x0F))); 1108 aml_append(dev, method); 1109 1110 crs = aml_resource_template(); 1111 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1112 aml_append(dev, aml_name_decl("_CRS", crs)); 1113 1114 aml_append(scope, dev); 1115 aml_append(table, scope); 1116 } 1117 1118 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1119 { 1120 Aml *dev, *fdi; 1121 uint8_t maxc, maxh, maxs; 1122 1123 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1124 1125 dev = aml_device("FLP%c", 'A' + idx); 1126 1127 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1128 1129 fdi = aml_package(16); 1130 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1131 aml_append(fdi, 1132 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1133 /* 1134 * the values below are the limits of the drive, and are thus independent 1135 * of the inserted media 1136 */ 1137 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1138 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1139 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1140 /* 1141 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1142 * the drive type, so shall we 1143 */ 1144 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1145 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1146 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1147 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1148 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1149 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1150 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1151 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1152 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1153 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1154 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1155 1156 aml_append(dev, aml_name_decl("_FDI", fdi)); 1157 return dev; 1158 } 1159 1160 static Aml *build_fdc_device_aml(ISADevice *fdc) 1161 { 1162 int i; 1163 Aml *dev; 1164 Aml *crs; 1165 1166 #define ACPI_FDE_MAX_FD 4 1167 uint32_t fde_buf[5] = { 1168 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1169 cpu_to_le32(2) /* tape presence (2 == never present) */ 1170 }; 1171 1172 dev = aml_device("FDC0"); 1173 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1174 1175 crs = aml_resource_template(); 1176 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1177 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1178 aml_append(crs, aml_irq_no_flags(6)); 1179 aml_append(crs, 1180 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1181 aml_append(dev, aml_name_decl("_CRS", crs)); 1182 1183 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1184 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1185 1186 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1187 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1188 aml_append(dev, build_fdinfo_aml(i, type)); 1189 } 1190 } 1191 aml_append(dev, aml_name_decl("_FDE", 1192 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1193 1194 return dev; 1195 } 1196 1197 static Aml *build_rtc_device_aml(void) 1198 { 1199 Aml *dev; 1200 Aml *crs; 1201 1202 dev = aml_device("RTC"); 1203 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1204 crs = aml_resource_template(); 1205 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1206 aml_append(crs, aml_irq_no_flags(8)); 1207 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1208 aml_append(dev, aml_name_decl("_CRS", crs)); 1209 1210 return dev; 1211 } 1212 1213 static Aml *build_kbd_device_aml(void) 1214 { 1215 Aml *dev; 1216 Aml *crs; 1217 Aml *method; 1218 1219 dev = aml_device("KBD"); 1220 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1221 1222 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1223 aml_append(method, aml_return(aml_int(0x0f))); 1224 aml_append(dev, method); 1225 1226 crs = aml_resource_template(); 1227 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1228 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1229 aml_append(crs, aml_irq_no_flags(1)); 1230 aml_append(dev, aml_name_decl("_CRS", crs)); 1231 1232 return dev; 1233 } 1234 1235 static Aml *build_mouse_device_aml(void) 1236 { 1237 Aml *dev; 1238 Aml *crs; 1239 Aml *method; 1240 1241 dev = aml_device("MOU"); 1242 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1243 1244 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1245 aml_append(method, aml_return(aml_int(0x0f))); 1246 aml_append(dev, method); 1247 1248 crs = aml_resource_template(); 1249 aml_append(crs, aml_irq_no_flags(12)); 1250 aml_append(dev, aml_name_decl("_CRS", crs)); 1251 1252 return dev; 1253 } 1254 1255 static Aml *build_lpt_device_aml(void) 1256 { 1257 Aml *dev; 1258 Aml *crs; 1259 Aml *method; 1260 Aml *if_ctx; 1261 Aml *else_ctx; 1262 Aml *zero = aml_int(0); 1263 Aml *is_present = aml_local(0); 1264 1265 dev = aml_device("LPT"); 1266 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1267 1268 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1269 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1270 if_ctx = aml_if(aml_equal(is_present, zero)); 1271 { 1272 aml_append(if_ctx, aml_return(aml_int(0x00))); 1273 } 1274 aml_append(method, if_ctx); 1275 else_ctx = aml_else(); 1276 { 1277 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1278 } 1279 aml_append(method, else_ctx); 1280 aml_append(dev, method); 1281 1282 crs = aml_resource_template(); 1283 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1284 aml_append(crs, aml_irq_no_flags(7)); 1285 aml_append(dev, aml_name_decl("_CRS", crs)); 1286 1287 return dev; 1288 } 1289 1290 static Aml *build_com_device_aml(uint8_t uid) 1291 { 1292 Aml *dev; 1293 Aml *crs; 1294 Aml *method; 1295 Aml *if_ctx; 1296 Aml *else_ctx; 1297 Aml *zero = aml_int(0); 1298 Aml *is_present = aml_local(0); 1299 const char *enabled_field = "CAEN"; 1300 uint8_t irq = 4; 1301 uint16_t io_port = 0x03F8; 1302 1303 assert(uid == 1 || uid == 2); 1304 if (uid == 2) { 1305 enabled_field = "CBEN"; 1306 irq = 3; 1307 io_port = 0x02F8; 1308 } 1309 1310 dev = aml_device("COM%d", uid); 1311 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1312 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1313 1314 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1315 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1316 if_ctx = aml_if(aml_equal(is_present, zero)); 1317 { 1318 aml_append(if_ctx, aml_return(aml_int(0x00))); 1319 } 1320 aml_append(method, if_ctx); 1321 else_ctx = aml_else(); 1322 { 1323 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1324 } 1325 aml_append(method, else_ctx); 1326 aml_append(dev, method); 1327 1328 crs = aml_resource_template(); 1329 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1330 aml_append(crs, aml_irq_no_flags(irq)); 1331 aml_append(dev, aml_name_decl("_CRS", crs)); 1332 1333 return dev; 1334 } 1335 1336 static void build_isa_devices_aml(Aml *table) 1337 { 1338 ISADevice *fdc = pc_find_fdc0(); 1339 bool ambiguous; 1340 1341 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1342 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1343 1344 aml_append(scope, build_rtc_device_aml()); 1345 aml_append(scope, build_kbd_device_aml()); 1346 aml_append(scope, build_mouse_device_aml()); 1347 if (fdc) { 1348 aml_append(scope, build_fdc_device_aml(fdc)); 1349 } 1350 aml_append(scope, build_lpt_device_aml()); 1351 aml_append(scope, build_com_device_aml(1)); 1352 aml_append(scope, build_com_device_aml(2)); 1353 1354 if (ambiguous) { 1355 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1356 } else if (!obj) { 1357 error_report("No ISA bus, unable to define IPMI ACPI data"); 1358 } else { 1359 build_acpi_ipmi_devices(scope, BUS(obj)); 1360 } 1361 1362 aml_append(table, scope); 1363 } 1364 1365 static void build_dbg_aml(Aml *table) 1366 { 1367 Aml *field; 1368 Aml *method; 1369 Aml *while_ctx; 1370 Aml *scope = aml_scope("\\"); 1371 Aml *buf = aml_local(0); 1372 Aml *len = aml_local(1); 1373 Aml *idx = aml_local(2); 1374 1375 aml_append(scope, 1376 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1377 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1378 aml_append(field, aml_named_field("DBGB", 8)); 1379 aml_append(scope, field); 1380 1381 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1382 1383 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1384 aml_append(method, aml_to_buffer(buf, buf)); 1385 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1386 aml_append(method, aml_store(aml_int(0), idx)); 1387 1388 while_ctx = aml_while(aml_lless(idx, len)); 1389 aml_append(while_ctx, 1390 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1391 aml_append(while_ctx, aml_increment(idx)); 1392 aml_append(method, while_ctx); 1393 1394 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1395 aml_append(scope, method); 1396 1397 aml_append(table, scope); 1398 } 1399 1400 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1401 { 1402 Aml *dev; 1403 Aml *crs; 1404 Aml *method; 1405 uint32_t irqs[] = {5, 10, 11}; 1406 1407 dev = aml_device("%s", name); 1408 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1409 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1410 1411 crs = aml_resource_template(); 1412 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1413 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1414 aml_append(dev, aml_name_decl("_PRS", crs)); 1415 1416 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1417 aml_append(method, aml_return(aml_call1("IQST", reg))); 1418 aml_append(dev, method); 1419 1420 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1421 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1422 aml_append(dev, method); 1423 1424 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1425 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1426 aml_append(dev, method); 1427 1428 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1429 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1430 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1431 aml_append(dev, method); 1432 1433 return dev; 1434 } 1435 1436 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1437 { 1438 Aml *dev; 1439 Aml *crs; 1440 Aml *method; 1441 uint32_t irqs; 1442 1443 dev = aml_device("%s", name); 1444 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1445 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1446 1447 crs = aml_resource_template(); 1448 irqs = gsi; 1449 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1450 AML_SHARED, &irqs, 1)); 1451 aml_append(dev, aml_name_decl("_PRS", crs)); 1452 1453 aml_append(dev, aml_name_decl("_CRS", crs)); 1454 1455 /* 1456 * _DIS can be no-op because the interrupt cannot be disabled. 1457 */ 1458 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1459 aml_append(dev, method); 1460 1461 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1462 aml_append(dev, method); 1463 1464 return dev; 1465 } 1466 1467 /* _CRS method - get current settings */ 1468 static Aml *build_iqcr_method(bool is_piix4) 1469 { 1470 Aml *if_ctx; 1471 uint32_t irqs; 1472 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1473 Aml *crs = aml_resource_template(); 1474 1475 irqs = 0; 1476 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1477 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1478 aml_append(method, aml_name_decl("PRR0", crs)); 1479 1480 aml_append(method, 1481 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1482 1483 if (is_piix4) { 1484 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1485 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1486 aml_append(method, if_ctx); 1487 } else { 1488 aml_append(method, 1489 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1490 aml_name("PRRI"))); 1491 } 1492 1493 aml_append(method, aml_return(aml_name("PRR0"))); 1494 return method; 1495 } 1496 1497 /* _STA method - get status */ 1498 static Aml *build_irq_status_method(void) 1499 { 1500 Aml *if_ctx; 1501 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1502 1503 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1504 aml_append(if_ctx, aml_return(aml_int(0x09))); 1505 aml_append(method, if_ctx); 1506 aml_append(method, aml_return(aml_int(0x0B))); 1507 return method; 1508 } 1509 1510 static void build_piix4_pci0_int(Aml *table) 1511 { 1512 Aml *dev; 1513 Aml *crs; 1514 Aml *field; 1515 Aml *method; 1516 uint32_t irqs; 1517 Aml *sb_scope = aml_scope("_SB"); 1518 Aml *pci0_scope = aml_scope("PCI0"); 1519 1520 aml_append(pci0_scope, build_prt(true)); 1521 aml_append(sb_scope, pci0_scope); 1522 1523 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1524 aml_append(field, aml_named_field("PRQ0", 8)); 1525 aml_append(field, aml_named_field("PRQ1", 8)); 1526 aml_append(field, aml_named_field("PRQ2", 8)); 1527 aml_append(field, aml_named_field("PRQ3", 8)); 1528 aml_append(sb_scope, field); 1529 1530 aml_append(sb_scope, build_irq_status_method()); 1531 aml_append(sb_scope, build_iqcr_method(true)); 1532 1533 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1534 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1535 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1536 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1537 1538 dev = aml_device("LNKS"); 1539 { 1540 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1541 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1542 1543 crs = aml_resource_template(); 1544 irqs = 9; 1545 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1546 AML_ACTIVE_HIGH, AML_SHARED, 1547 &irqs, 1)); 1548 aml_append(dev, aml_name_decl("_PRS", crs)); 1549 1550 /* The SCI cannot be disabled and is always attached to GSI 9, 1551 * so these are no-ops. We only need this link to override the 1552 * polarity to active high and match the content of the MADT. 1553 */ 1554 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1555 aml_append(method, aml_return(aml_int(0x0b))); 1556 aml_append(dev, method); 1557 1558 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1559 aml_append(dev, method); 1560 1561 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1562 aml_append(method, aml_return(aml_name("_PRS"))); 1563 aml_append(dev, method); 1564 1565 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1566 aml_append(dev, method); 1567 } 1568 aml_append(sb_scope, dev); 1569 1570 aml_append(table, sb_scope); 1571 } 1572 1573 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1574 { 1575 int i; 1576 int head; 1577 Aml *pkg; 1578 char base = name[3] < 'E' ? 'A' : 'E'; 1579 char *s = g_strdup(name); 1580 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1581 1582 assert(strlen(s) == 4); 1583 1584 head = name[3] - base; 1585 for (i = 0; i < 4; i++) { 1586 if (head + i > 3) { 1587 head = i * -1; 1588 } 1589 s[3] = base + head + i; 1590 pkg = aml_package(4); 1591 aml_append(pkg, a_nr); 1592 aml_append(pkg, aml_int(i)); 1593 aml_append(pkg, aml_name("%s", s)); 1594 aml_append(pkg, aml_int(0)); 1595 aml_append(ctx, pkg); 1596 } 1597 g_free(s); 1598 } 1599 1600 static Aml *build_q35_routing_table(const char *str) 1601 { 1602 int i; 1603 Aml *pkg; 1604 char *name = g_strdup_printf("%s ", str); 1605 1606 pkg = aml_package(128); 1607 for (i = 0; i < 0x18; i++) { 1608 name[3] = 'E' + (i & 0x3); 1609 append_q35_prt_entry(pkg, i, name); 1610 } 1611 1612 name[3] = 'E'; 1613 append_q35_prt_entry(pkg, 0x18, name); 1614 1615 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1616 for (i = 0x0019; i < 0x1e; i++) { 1617 name[3] = 'A'; 1618 append_q35_prt_entry(pkg, i, name); 1619 } 1620 1621 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1622 name[3] = 'E'; 1623 append_q35_prt_entry(pkg, 0x1e, name); 1624 name[3] = 'A'; 1625 append_q35_prt_entry(pkg, 0x1f, name); 1626 1627 g_free(name); 1628 return pkg; 1629 } 1630 1631 static void build_q35_pci0_int(Aml *table) 1632 { 1633 Aml *field; 1634 Aml *method; 1635 Aml *sb_scope = aml_scope("_SB"); 1636 Aml *pci0_scope = aml_scope("PCI0"); 1637 1638 /* Zero => PIC mode, One => APIC Mode */ 1639 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1640 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1641 { 1642 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1643 } 1644 aml_append(table, method); 1645 1646 aml_append(pci0_scope, 1647 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1648 aml_append(pci0_scope, 1649 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1650 1651 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1652 { 1653 Aml *if_ctx; 1654 Aml *else_ctx; 1655 1656 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1657 section 6.2.8.1 */ 1658 /* Note: we provide the same info as the PCI routing 1659 table of the Bochs BIOS */ 1660 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1661 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1662 aml_append(method, if_ctx); 1663 else_ctx = aml_else(); 1664 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1665 aml_append(method, else_ctx); 1666 } 1667 aml_append(pci0_scope, method); 1668 aml_append(sb_scope, pci0_scope); 1669 1670 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1671 aml_append(field, aml_named_field("PRQA", 8)); 1672 aml_append(field, aml_named_field("PRQB", 8)); 1673 aml_append(field, aml_named_field("PRQC", 8)); 1674 aml_append(field, aml_named_field("PRQD", 8)); 1675 aml_append(field, aml_reserved_field(0x20)); 1676 aml_append(field, aml_named_field("PRQE", 8)); 1677 aml_append(field, aml_named_field("PRQF", 8)); 1678 aml_append(field, aml_named_field("PRQG", 8)); 1679 aml_append(field, aml_named_field("PRQH", 8)); 1680 aml_append(sb_scope, field); 1681 1682 aml_append(sb_scope, build_irq_status_method()); 1683 aml_append(sb_scope, build_iqcr_method(false)); 1684 1685 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1686 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1687 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1688 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1689 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1690 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1691 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1692 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1693 1694 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1695 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1696 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1697 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1698 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1699 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1700 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1701 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1702 1703 aml_append(table, sb_scope); 1704 } 1705 1706 static void build_q35_isa_bridge(Aml *table) 1707 { 1708 Aml *dev; 1709 Aml *scope; 1710 Aml *field; 1711 1712 scope = aml_scope("_SB.PCI0"); 1713 dev = aml_device("ISA"); 1714 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1715 1716 /* ICH9 PCI to ISA irq remapping */ 1717 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1718 aml_int(0x60), 0x0C)); 1719 1720 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1721 aml_int(0x80), 0x02)); 1722 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1723 aml_append(field, aml_named_field("COMA", 3)); 1724 aml_append(field, aml_reserved_field(1)); 1725 aml_append(field, aml_named_field("COMB", 3)); 1726 aml_append(field, aml_reserved_field(1)); 1727 aml_append(field, aml_named_field("LPTD", 2)); 1728 aml_append(dev, field); 1729 1730 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1731 aml_int(0x82), 0x02)); 1732 /* enable bits */ 1733 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1734 aml_append(field, aml_named_field("CAEN", 1)); 1735 aml_append(field, aml_named_field("CBEN", 1)); 1736 aml_append(field, aml_named_field("LPEN", 1)); 1737 aml_append(dev, field); 1738 1739 aml_append(scope, dev); 1740 aml_append(table, scope); 1741 } 1742 1743 static void build_piix4_pm(Aml *table) 1744 { 1745 Aml *dev; 1746 Aml *scope; 1747 1748 scope = aml_scope("_SB.PCI0"); 1749 dev = aml_device("PX13"); 1750 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1751 1752 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1753 aml_int(0x00), 0xff)); 1754 aml_append(scope, dev); 1755 aml_append(table, scope); 1756 } 1757 1758 static void build_piix4_isa_bridge(Aml *table) 1759 { 1760 Aml *dev; 1761 Aml *scope; 1762 Aml *field; 1763 1764 scope = aml_scope("_SB.PCI0"); 1765 dev = aml_device("ISA"); 1766 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1767 1768 /* PIIX PCI to ISA irq remapping */ 1769 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1770 aml_int(0x60), 0x04)); 1771 /* enable bits */ 1772 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1773 /* Offset(0x5f),, 7, */ 1774 aml_append(field, aml_reserved_field(0x2f8)); 1775 aml_append(field, aml_reserved_field(7)); 1776 aml_append(field, aml_named_field("LPEN", 1)); 1777 /* Offset(0x67),, 3, */ 1778 aml_append(field, aml_reserved_field(0x38)); 1779 aml_append(field, aml_reserved_field(3)); 1780 aml_append(field, aml_named_field("CAEN", 1)); 1781 aml_append(field, aml_reserved_field(3)); 1782 aml_append(field, aml_named_field("CBEN", 1)); 1783 aml_append(dev, field); 1784 1785 aml_append(scope, dev); 1786 aml_append(table, scope); 1787 } 1788 1789 static void build_piix4_pci_hotplug(Aml *table) 1790 { 1791 Aml *scope; 1792 Aml *field; 1793 Aml *method; 1794 1795 scope = aml_scope("_SB.PCI0"); 1796 1797 aml_append(scope, 1798 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1799 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1800 aml_append(field, aml_named_field("PCIU", 32)); 1801 aml_append(field, aml_named_field("PCID", 32)); 1802 aml_append(scope, field); 1803 1804 aml_append(scope, 1805 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1806 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1807 aml_append(field, aml_named_field("B0EJ", 32)); 1808 aml_append(scope, field); 1809 1810 aml_append(scope, 1811 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1812 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1813 aml_append(field, aml_named_field("BNUM", 32)); 1814 aml_append(scope, field); 1815 1816 aml_append(scope, aml_mutex("BLCK", 0)); 1817 1818 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1819 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1820 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1821 aml_append(method, 1822 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1823 aml_append(method, aml_release(aml_name("BLCK"))); 1824 aml_append(method, aml_return(aml_int(0))); 1825 aml_append(scope, method); 1826 1827 aml_append(table, scope); 1828 } 1829 1830 static Aml *build_q35_osc_method(void) 1831 { 1832 Aml *if_ctx; 1833 Aml *if_ctx2; 1834 Aml *else_ctx; 1835 Aml *method; 1836 Aml *a_cwd1 = aml_name("CDW1"); 1837 Aml *a_ctrl = aml_local(0); 1838 1839 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1840 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1841 1842 if_ctx = aml_if(aml_equal( 1843 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1844 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1845 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1846 1847 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1848 1849 /* 1850 * Always allow native PME, AER (no dependencies) 1851 * Never allow SHPC (no SHPC controller in this system) 1852 */ 1853 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1854 1855 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1856 /* Unknown revision */ 1857 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1858 aml_append(if_ctx, if_ctx2); 1859 1860 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1861 /* Capabilities bits were masked */ 1862 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1863 aml_append(if_ctx, if_ctx2); 1864 1865 /* Update DWORD3 in the buffer */ 1866 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1867 aml_append(method, if_ctx); 1868 1869 else_ctx = aml_else(); 1870 /* Unrecognized UUID */ 1871 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1872 aml_append(method, else_ctx); 1873 1874 aml_append(method, aml_return(aml_arg(3))); 1875 return method; 1876 } 1877 1878 static void 1879 build_dsdt(GArray *table_data, BIOSLinker *linker, 1880 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1881 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1882 { 1883 CrsRangeEntry *entry; 1884 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1885 CrsRangeSet crs_range_set; 1886 PCMachineState *pcms = PC_MACHINE(machine); 1887 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1888 uint32_t nr_mem = machine->ram_slots; 1889 int root_bus_limit = 0xFF; 1890 PCIBus *bus = NULL; 1891 int i; 1892 1893 dsdt = init_aml_allocator(); 1894 1895 /* Reserve space for header */ 1896 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1897 1898 build_dbg_aml(dsdt); 1899 if (misc->is_piix4) { 1900 sb_scope = aml_scope("_SB"); 1901 dev = aml_device("PCI0"); 1902 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1903 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1904 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1905 aml_append(sb_scope, dev); 1906 aml_append(dsdt, sb_scope); 1907 1908 build_hpet_aml(dsdt); 1909 build_piix4_pm(dsdt); 1910 build_piix4_isa_bridge(dsdt); 1911 build_isa_devices_aml(dsdt); 1912 build_piix4_pci_hotplug(dsdt); 1913 build_piix4_pci0_int(dsdt); 1914 } else { 1915 sb_scope = aml_scope("_SB"); 1916 dev = aml_device("PCI0"); 1917 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1918 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1919 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1920 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1921 aml_append(dev, build_q35_osc_method()); 1922 aml_append(sb_scope, dev); 1923 aml_append(dsdt, sb_scope); 1924 1925 build_hpet_aml(dsdt); 1926 build_q35_isa_bridge(dsdt); 1927 build_isa_devices_aml(dsdt); 1928 build_q35_pci0_int(dsdt); 1929 } 1930 1931 if (pcmc->legacy_cpu_hotplug) { 1932 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1933 } else { 1934 CPUHotplugFeatures opts = { 1935 .apci_1_compatible = true, .has_legacy_cphp = true 1936 }; 1937 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1938 "\\_SB.PCI0", "\\_GPE._E02"); 1939 } 1940 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1941 1942 scope = aml_scope("_GPE"); 1943 { 1944 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1945 1946 if (misc->is_piix4) { 1947 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1948 aml_append(method, 1949 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1950 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1951 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1952 aml_append(scope, method); 1953 } 1954 1955 if (pcms->acpi_nvdimm_state.is_enabled) { 1956 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1957 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1958 aml_int(0x80))); 1959 aml_append(scope, method); 1960 } 1961 } 1962 aml_append(dsdt, scope); 1963 1964 crs_range_set_init(&crs_range_set); 1965 bus = PC_MACHINE(machine)->bus; 1966 if (bus) { 1967 QLIST_FOREACH(bus, &bus->child, sibling) { 1968 uint8_t bus_num = pci_bus_num(bus); 1969 uint8_t numa_node = pci_bus_numa_node(bus); 1970 1971 /* look only for expander root buses */ 1972 if (!pci_bus_is_root(bus)) { 1973 continue; 1974 } 1975 1976 if (bus_num < root_bus_limit) { 1977 root_bus_limit = bus_num - 1; 1978 } 1979 1980 scope = aml_scope("\\_SB"); 1981 dev = aml_device("PC%.02X", bus_num); 1982 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1983 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1984 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1985 if (pci_bus_is_express(bus)) { 1986 aml_append(dev, build_q35_osc_method()); 1987 } 1988 1989 if (numa_node != NUMA_NODE_UNASSIGNED) { 1990 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1991 } 1992 1993 aml_append(dev, build_prt(false)); 1994 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1995 aml_append(dev, aml_name_decl("_CRS", crs)); 1996 aml_append(scope, dev); 1997 aml_append(dsdt, scope); 1998 } 1999 } 2000 2001 scope = aml_scope("\\_SB.PCI0"); 2002 /* build PCI0._CRS */ 2003 crs = aml_resource_template(); 2004 aml_append(crs, 2005 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 2006 0x0000, 0x0, root_bus_limit, 2007 0x0000, root_bus_limit + 1)); 2008 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2009 2010 aml_append(crs, 2011 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2012 AML_POS_DECODE, AML_ENTIRE_RANGE, 2013 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2014 2015 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 2016 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 2017 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 2018 aml_append(crs, 2019 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2020 AML_POS_DECODE, AML_ENTIRE_RANGE, 2021 0x0000, entry->base, entry->limit, 2022 0x0000, entry->limit - entry->base + 1)); 2023 } 2024 2025 aml_append(crs, 2026 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2027 AML_CACHEABLE, AML_READ_WRITE, 2028 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2029 2030 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 2031 range_lob(pci_hole), 2032 range_upb(pci_hole)); 2033 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 2034 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 2035 aml_append(crs, 2036 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2037 AML_NON_CACHEABLE, AML_READ_WRITE, 2038 0, entry->base, entry->limit, 2039 0, entry->limit - entry->base + 1)); 2040 } 2041 2042 if (!range_is_empty(pci_hole64)) { 2043 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 2044 range_lob(pci_hole64), 2045 range_upb(pci_hole64)); 2046 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 2047 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 2048 aml_append(crs, 2049 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 2050 AML_MAX_FIXED, 2051 AML_CACHEABLE, AML_READ_WRITE, 2052 0, entry->base, entry->limit, 2053 0, entry->limit - entry->base + 1)); 2054 } 2055 } 2056 2057 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2058 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2059 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2060 } 2061 aml_append(scope, aml_name_decl("_CRS", crs)); 2062 2063 /* reserve GPE0 block resources */ 2064 dev = aml_device("GPE0"); 2065 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2066 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2067 /* device present, functioning, decoding, not shown in UI */ 2068 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2069 crs = aml_resource_template(); 2070 aml_append(crs, 2071 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2072 ); 2073 aml_append(dev, aml_name_decl("_CRS", crs)); 2074 aml_append(scope, dev); 2075 2076 crs_range_set_free(&crs_range_set); 2077 2078 /* reserve PCIHP resources */ 2079 if (pm->pcihp_io_len) { 2080 dev = aml_device("PHPR"); 2081 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2082 aml_append(dev, 2083 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2084 /* device present, functioning, decoding, not shown in UI */ 2085 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2086 crs = aml_resource_template(); 2087 aml_append(crs, 2088 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2089 pm->pcihp_io_len) 2090 ); 2091 aml_append(dev, aml_name_decl("_CRS", crs)); 2092 aml_append(scope, dev); 2093 } 2094 aml_append(dsdt, scope); 2095 2096 /* create S3_ / S4_ / S5_ packages if necessary */ 2097 scope = aml_scope("\\"); 2098 if (!pm->s3_disabled) { 2099 pkg = aml_package(4); 2100 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2101 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2102 aml_append(pkg, aml_int(0)); /* reserved */ 2103 aml_append(pkg, aml_int(0)); /* reserved */ 2104 aml_append(scope, aml_name_decl("_S3", pkg)); 2105 } 2106 2107 if (!pm->s4_disabled) { 2108 pkg = aml_package(4); 2109 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2110 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2111 aml_append(pkg, aml_int(pm->s4_val)); 2112 aml_append(pkg, aml_int(0)); /* reserved */ 2113 aml_append(pkg, aml_int(0)); /* reserved */ 2114 aml_append(scope, aml_name_decl("_S4", pkg)); 2115 } 2116 2117 pkg = aml_package(4); 2118 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2119 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2120 aml_append(pkg, aml_int(0)); /* reserved */ 2121 aml_append(pkg, aml_int(0)); /* reserved */ 2122 aml_append(scope, aml_name_decl("_S5", pkg)); 2123 aml_append(dsdt, scope); 2124 2125 /* create fw_cfg node, unconditionally */ 2126 { 2127 /* when using port i/o, the 8-bit data register *always* overlaps 2128 * with half of the 16-bit control register. Hence, the total size 2129 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2130 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2131 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2132 "dma_enabled", NULL) ? 2133 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2134 FW_CFG_CTL_SIZE; 2135 2136 scope = aml_scope("\\_SB.PCI0"); 2137 dev = aml_device("FWCF"); 2138 2139 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2140 2141 /* device present, functioning, decoding, not shown in UI */ 2142 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2143 2144 crs = aml_resource_template(); 2145 aml_append(crs, 2146 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2147 ); 2148 aml_append(dev, aml_name_decl("_CRS", crs)); 2149 2150 aml_append(scope, dev); 2151 aml_append(dsdt, scope); 2152 } 2153 2154 if (misc->applesmc_io_base) { 2155 scope = aml_scope("\\_SB.PCI0.ISA"); 2156 dev = aml_device("SMC"); 2157 2158 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2159 /* device present, functioning, decoding, not shown in UI */ 2160 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2161 2162 crs = aml_resource_template(); 2163 aml_append(crs, 2164 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2165 0x01, APPLESMC_MAX_DATA_LENGTH) 2166 ); 2167 aml_append(crs, aml_irq_no_flags(6)); 2168 aml_append(dev, aml_name_decl("_CRS", crs)); 2169 2170 aml_append(scope, dev); 2171 aml_append(dsdt, scope); 2172 } 2173 2174 if (misc->pvpanic_port) { 2175 scope = aml_scope("\\_SB.PCI0.ISA"); 2176 2177 dev = aml_device("PEVT"); 2178 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2179 2180 crs = aml_resource_template(); 2181 aml_append(crs, 2182 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2183 ); 2184 aml_append(dev, aml_name_decl("_CRS", crs)); 2185 2186 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2187 aml_int(misc->pvpanic_port), 1)); 2188 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2189 aml_append(field, aml_named_field("PEPT", 8)); 2190 aml_append(dev, field); 2191 2192 /* device present, functioning, decoding, shown in UI */ 2193 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2194 2195 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2196 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2197 aml_append(method, aml_return(aml_local(0))); 2198 aml_append(dev, method); 2199 2200 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2201 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2202 aml_append(dev, method); 2203 2204 aml_append(scope, dev); 2205 aml_append(dsdt, scope); 2206 } 2207 2208 sb_scope = aml_scope("\\_SB"); 2209 { 2210 Object *pci_host; 2211 PCIBus *bus = NULL; 2212 2213 pci_host = acpi_get_i386_pci_host(); 2214 if (pci_host) { 2215 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2216 } 2217 2218 if (bus) { 2219 Aml *scope = aml_scope("PCI0"); 2220 /* Scan all PCI buses. Generate tables to support hotplug. */ 2221 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2222 2223 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2224 dev = aml_device("ISA.TPM"); 2225 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2226 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2227 crs = aml_resource_template(); 2228 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2229 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2230 /* 2231 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2232 Rewrite to take IRQ from TPM device model and 2233 fix default IRQ value there to use some unused IRQ 2234 */ 2235 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2236 aml_append(dev, aml_name_decl("_CRS", crs)); 2237 aml_append(scope, dev); 2238 } 2239 2240 aml_append(sb_scope, scope); 2241 } 2242 } 2243 aml_append(dsdt, sb_scope); 2244 2245 /* copy AML table into ACPI tables blob and patch header there */ 2246 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2247 build_header(linker, table_data, 2248 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2249 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2250 free_aml_allocator(); 2251 } 2252 2253 static void 2254 build_hpet(GArray *table_data, BIOSLinker *linker) 2255 { 2256 Acpi20Hpet *hpet; 2257 2258 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2259 /* Note timer_block_id value must be kept in sync with value advertised by 2260 * emulated hpet 2261 */ 2262 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2263 hpet->addr.address = cpu_to_le64(HPET_BASE); 2264 build_header(linker, table_data, 2265 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2266 } 2267 2268 static void 2269 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2270 { 2271 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2272 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2273 unsigned log_addr_offset = 2274 (char *)&tcpa->log_area_start_address - table_data->data; 2275 2276 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2277 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2278 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2279 2280 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2281 false /* high memory */); 2282 2283 /* log area start address to be filled by Guest linker */ 2284 bios_linker_loader_add_pointer(linker, 2285 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2286 ACPI_BUILD_TPMLOG_FILE, 0); 2287 2288 build_header(linker, table_data, 2289 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2290 } 2291 2292 static void 2293 build_tpm2(GArray *table_data, BIOSLinker *linker) 2294 { 2295 Acpi20TPM2 *tpm2_ptr; 2296 2297 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2298 2299 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2300 tpm2_ptr->control_area_address = cpu_to_le64(0); 2301 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2302 2303 build_header(linker, table_data, 2304 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2305 } 2306 2307 static void 2308 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2309 { 2310 AcpiSystemResourceAffinityTable *srat; 2311 AcpiSratMemoryAffinity *numamem; 2312 2313 int i; 2314 int srat_start, numa_start, slots; 2315 uint64_t mem_len, mem_base, next_base; 2316 MachineClass *mc = MACHINE_GET_CLASS(machine); 2317 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2318 PCMachineState *pcms = PC_MACHINE(machine); 2319 ram_addr_t hotplugabble_address_space_size = 2320 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2321 NULL); 2322 2323 srat_start = table_data->len; 2324 2325 srat = acpi_data_push(table_data, sizeof *srat); 2326 srat->reserved1 = cpu_to_le32(1); 2327 2328 for (i = 0; i < apic_ids->len; i++) { 2329 int node_id = apic_ids->cpus[i].props.node_id; 2330 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2331 2332 if (apic_id < 255) { 2333 AcpiSratProcessorAffinity *core; 2334 2335 core = acpi_data_push(table_data, sizeof *core); 2336 core->type = ACPI_SRAT_PROCESSOR_APIC; 2337 core->length = sizeof(*core); 2338 core->local_apic_id = apic_id; 2339 core->proximity_lo = node_id; 2340 memset(core->proximity_hi, 0, 3); 2341 core->local_sapic_eid = 0; 2342 core->flags = cpu_to_le32(1); 2343 } else { 2344 AcpiSratProcessorX2ApicAffinity *core; 2345 2346 core = acpi_data_push(table_data, sizeof *core); 2347 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2348 core->length = sizeof(*core); 2349 core->x2apic_id = cpu_to_le32(apic_id); 2350 core->proximity_domain = cpu_to_le32(node_id); 2351 core->flags = cpu_to_le32(1); 2352 } 2353 } 2354 2355 2356 /* the memory map is a bit tricky, it contains at least one hole 2357 * from 640k-1M and possibly another one from 3.5G-4G. 2358 */ 2359 next_base = 0; 2360 numa_start = table_data->len; 2361 2362 numamem = acpi_data_push(table_data, sizeof *numamem); 2363 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED); 2364 next_base = 1024 * 1024; 2365 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2366 mem_base = next_base; 2367 mem_len = pcms->node_mem[i - 1]; 2368 if (i == 1) { 2369 mem_len -= 1024 * 1024; 2370 } 2371 next_base = mem_base + mem_len; 2372 2373 /* Cut out the ACPI_PCI hole */ 2374 if (mem_base <= pcms->below_4g_mem_size && 2375 next_base > pcms->below_4g_mem_size) { 2376 mem_len -= next_base - pcms->below_4g_mem_size; 2377 if (mem_len > 0) { 2378 numamem = acpi_data_push(table_data, sizeof *numamem); 2379 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2380 MEM_AFFINITY_ENABLED); 2381 } 2382 mem_base = 1ULL << 32; 2383 mem_len = next_base - pcms->below_4g_mem_size; 2384 next_base += (1ULL << 32) - pcms->below_4g_mem_size; 2385 } 2386 numamem = acpi_data_push(table_data, sizeof *numamem); 2387 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2388 MEM_AFFINITY_ENABLED); 2389 } 2390 slots = (table_data->len - numa_start) / sizeof *numamem; 2391 for (; slots < pcms->numa_nodes + 2; slots++) { 2392 numamem = acpi_data_push(table_data, sizeof *numamem); 2393 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2394 } 2395 2396 /* 2397 * Entry is required for Windows to enable memory hotplug in OS 2398 * and for Linux to enable SWIOTLB when booted with less than 2399 * 4G of RAM. Windows works better if the entry sets proximity 2400 * to the highest NUMA node in the machine. 2401 * Memory devices may override proximity set by this entry, 2402 * providing _PXM method if necessary. 2403 */ 2404 if (hotplugabble_address_space_size) { 2405 numamem = acpi_data_push(table_data, sizeof *numamem); 2406 build_srat_memory(numamem, pcms->hotplug_memory.base, 2407 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2408 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2409 } 2410 2411 build_header(linker, table_data, 2412 (void *)(table_data->data + srat_start), 2413 "SRAT", 2414 table_data->len - srat_start, 1, NULL, NULL); 2415 } 2416 2417 static void 2418 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) 2419 { 2420 AcpiTableMcfg *mcfg; 2421 const char *sig; 2422 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2423 2424 mcfg = acpi_data_push(table_data, len); 2425 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2426 /* Only a single allocation so no need to play with segments */ 2427 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2428 mcfg->allocation[0].start_bus_number = 0; 2429 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2430 2431 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2432 * To avoid table size changes (which create migration issues), 2433 * always create the table even if there are no allocations, 2434 * but set the signature to a reserved value in this case. 2435 * ACPI spec requires OSPMs to ignore such tables. 2436 */ 2437 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2438 /* Reserved signature: ignored by OSPM */ 2439 sig = "QEMU"; 2440 } else { 2441 sig = "MCFG"; 2442 } 2443 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2444 } 2445 2446 /* 2447 * VT-d spec 8.1 DMA Remapping Reporting Structure 2448 * (version Oct. 2014 or later) 2449 */ 2450 static void 2451 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2452 { 2453 int dmar_start = table_data->len; 2454 2455 AcpiTableDmar *dmar; 2456 AcpiDmarHardwareUnit *drhd; 2457 AcpiDmarRootPortATS *atsr; 2458 uint8_t dmar_flags = 0; 2459 X86IOMMUState *iommu = x86_iommu_get_default(); 2460 AcpiDmarDeviceScope *scope = NULL; 2461 /* Root complex IOAPIC use one path[0] only */ 2462 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2463 2464 assert(iommu); 2465 if (iommu->intr_supported) { 2466 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2467 } 2468 2469 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2470 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2471 dmar->flags = dmar_flags; 2472 2473 /* DMAR Remapping Hardware Unit Definition structure */ 2474 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2475 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2476 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2477 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2478 drhd->pci_segment = cpu_to_le16(0); 2479 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2480 2481 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2482 * 8.3.1 (version Oct. 2014 or later). */ 2483 scope = &drhd->scope[0]; 2484 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2485 scope->length = ioapic_scope_size; 2486 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2487 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2488 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2489 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2490 2491 if (iommu->dt_supported) { 2492 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2493 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2494 atsr->length = cpu_to_le16(sizeof(*atsr)); 2495 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2496 atsr->pci_segment = cpu_to_le16(0); 2497 } 2498 2499 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2500 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2501 } 2502 /* 2503 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2504 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2505 */ 2506 static void 2507 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2508 { 2509 int iommu_start = table_data->len; 2510 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2511 2512 /* IVRS header */ 2513 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2514 /* IVinfo - IO virtualization information common to all 2515 * IOMMU units in a system 2516 */ 2517 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2518 /* reserved */ 2519 build_append_int_noprefix(table_data, 0, 8); 2520 2521 /* IVHD definition - type 10h */ 2522 build_append_int_noprefix(table_data, 0x10, 1); 2523 /* virtualization flags */ 2524 build_append_int_noprefix(table_data, 2525 (1UL << 0) | /* HtTunEn */ 2526 (1UL << 4) | /* iotblSup */ 2527 (1UL << 6) | /* PrefSup */ 2528 (1UL << 7), /* PPRSup */ 2529 1); 2530 /* IVHD length */ 2531 build_append_int_noprefix(table_data, 0x24, 2); 2532 /* DeviceID */ 2533 build_append_int_noprefix(table_data, s->devid, 2); 2534 /* Capability offset */ 2535 build_append_int_noprefix(table_data, s->capab_offset, 2); 2536 /* IOMMU base address */ 2537 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2538 /* PCI Segment Group */ 2539 build_append_int_noprefix(table_data, 0, 2); 2540 /* IOMMU info */ 2541 build_append_int_noprefix(table_data, 0, 2); 2542 /* IOMMU Feature Reporting */ 2543 build_append_int_noprefix(table_data, 2544 (48UL << 30) | /* HATS */ 2545 (48UL << 28) | /* GATS */ 2546 (1UL << 2), /* GTSup */ 2547 4); 2548 /* 2549 * Type 1 device entry reporting all devices 2550 * These are 4-byte device entries currently reporting the range of 2551 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2552 */ 2553 build_append_int_noprefix(table_data, 0x0000001, 4); 2554 2555 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2556 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2557 } 2558 2559 static GArray * 2560 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset) 2561 { 2562 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2563 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address); 2564 unsigned rsdt_pa_offset = 2565 (char *)&rsdp->rsdt_physical_address - rsdp_table->data; 2566 2567 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16, 2568 true /* fseg memory */); 2569 2570 memcpy(&rsdp->signature, "RSD PTR ", 8); 2571 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2572 /* Address to be filled by Guest linker */ 2573 bios_linker_loader_add_pointer(linker, 2574 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size, 2575 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset); 2576 2577 /* Checksum to be filled by Guest linker */ 2578 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2579 (char *)rsdp - rsdp_table->data, sizeof *rsdp, 2580 (char *)&rsdp->checksum - rsdp_table->data); 2581 2582 return rsdp_table; 2583 } 2584 2585 typedef 2586 struct AcpiBuildState { 2587 /* Copy of table in RAM (for patching). */ 2588 MemoryRegion *table_mr; 2589 /* Is table patched? */ 2590 uint8_t patched; 2591 void *rsdp; 2592 MemoryRegion *rsdp_mr; 2593 MemoryRegion *linker_mr; 2594 } AcpiBuildState; 2595 2596 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2597 { 2598 Object *pci_host; 2599 QObject *o; 2600 2601 pci_host = acpi_get_i386_pci_host(); 2602 g_assert(pci_host); 2603 2604 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2605 if (!o) { 2606 return false; 2607 } 2608 mcfg->mcfg_base = qnum_get_uint(qobject_to_qnum(o)); 2609 qobject_decref(o); 2610 2611 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2612 assert(o); 2613 mcfg->mcfg_size = qnum_get_uint(qobject_to_qnum(o)); 2614 qobject_decref(o); 2615 return true; 2616 } 2617 2618 static 2619 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2620 { 2621 PCMachineState *pcms = PC_MACHINE(machine); 2622 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2623 GArray *table_offsets; 2624 unsigned facs, dsdt, rsdt, fadt; 2625 AcpiPmInfo pm; 2626 AcpiMiscInfo misc; 2627 AcpiMcfgInfo mcfg; 2628 Range pci_hole, pci_hole64; 2629 uint8_t *u; 2630 size_t aml_len = 0; 2631 GArray *tables_blob = tables->table_data; 2632 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2633 Object *vmgenid_dev; 2634 2635 acpi_get_pm_info(&pm); 2636 acpi_get_misc_info(&misc); 2637 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2638 acpi_get_slic_oem(&slic_oem); 2639 2640 table_offsets = g_array_new(false, true /* clear */, 2641 sizeof(uint32_t)); 2642 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2643 2644 bios_linker_loader_alloc(tables->linker, 2645 ACPI_BUILD_TABLE_FILE, tables_blob, 2646 64 /* Ensure FACS is aligned */, 2647 false /* high memory */); 2648 2649 /* 2650 * FACS is pointed to by FADT. 2651 * We place it first since it's the only table that has alignment 2652 * requirements. 2653 */ 2654 facs = tables_blob->len; 2655 build_facs(tables_blob, tables->linker); 2656 2657 /* DSDT is pointed to by FADT */ 2658 dsdt = tables_blob->len; 2659 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2660 &pci_hole, &pci_hole64, machine); 2661 2662 /* Count the size of the DSDT and SSDT, we will need it for legacy 2663 * sizing of ACPI tables. 2664 */ 2665 aml_len += tables_blob->len - dsdt; 2666 2667 /* ACPI tables pointed to by RSDT */ 2668 fadt = tables_blob->len; 2669 acpi_add_table(table_offsets, tables_blob); 2670 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt, 2671 slic_oem.id, slic_oem.table_id); 2672 aml_len += tables_blob->len - fadt; 2673 2674 acpi_add_table(table_offsets, tables_blob); 2675 build_madt(tables_blob, tables->linker, pcms); 2676 2677 vmgenid_dev = find_vmgenid_dev(); 2678 if (vmgenid_dev) { 2679 acpi_add_table(table_offsets, tables_blob); 2680 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2681 tables->vmgenid, tables->linker); 2682 } 2683 2684 if (misc.has_hpet) { 2685 acpi_add_table(table_offsets, tables_blob); 2686 build_hpet(tables_blob, tables->linker); 2687 } 2688 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2689 acpi_add_table(table_offsets, tables_blob); 2690 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2691 2692 if (misc.tpm_version == TPM_VERSION_2_0) { 2693 acpi_add_table(table_offsets, tables_blob); 2694 build_tpm2(tables_blob, tables->linker); 2695 } 2696 } 2697 if (pcms->numa_nodes) { 2698 acpi_add_table(table_offsets, tables_blob); 2699 build_srat(tables_blob, tables->linker, machine); 2700 if (have_numa_distance) { 2701 acpi_add_table(table_offsets, tables_blob); 2702 build_slit(tables_blob, tables->linker); 2703 } 2704 } 2705 if (acpi_get_mcfg(&mcfg)) { 2706 acpi_add_table(table_offsets, tables_blob); 2707 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2708 } 2709 if (x86_iommu_get_default()) { 2710 IommuType IOMMUType = x86_iommu_get_type(); 2711 if (IOMMUType == TYPE_AMD) { 2712 acpi_add_table(table_offsets, tables_blob); 2713 build_amd_iommu(tables_blob, tables->linker); 2714 } else if (IOMMUType == TYPE_INTEL) { 2715 acpi_add_table(table_offsets, tables_blob); 2716 build_dmar_q35(tables_blob, tables->linker); 2717 } 2718 } 2719 if (pcms->acpi_nvdimm_state.is_enabled) { 2720 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2721 &pcms->acpi_nvdimm_state, machine->ram_slots); 2722 } 2723 2724 /* Add tables supplied by user (if any) */ 2725 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2726 unsigned len = acpi_table_len(u); 2727 2728 acpi_add_table(table_offsets, tables_blob); 2729 g_array_append_vals(tables_blob, u, len); 2730 } 2731 2732 /* RSDT is pointed to by RSDP */ 2733 rsdt = tables_blob->len; 2734 build_rsdt(tables_blob, tables->linker, table_offsets, 2735 slic_oem.id, slic_oem.table_id); 2736 2737 /* RSDP is in FSEG memory, so allocate it separately */ 2738 build_rsdp(tables->rsdp, tables->linker, rsdt); 2739 2740 /* We'll expose it all to Guest so we want to reduce 2741 * chance of size changes. 2742 * 2743 * We used to align the tables to 4k, but of course this would 2744 * too simple to be enough. 4k turned out to be too small an 2745 * alignment very soon, and in fact it is almost impossible to 2746 * keep the table size stable for all (max_cpus, max_memory_slots) 2747 * combinations. So the table size is always 64k for pc-i440fx-2.1 2748 * and we give an error if the table grows beyond that limit. 2749 * 2750 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2751 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2752 * than 2.0 and we can always pad the smaller tables with zeros. We can 2753 * then use the exact size of the 2.0 tables. 2754 * 2755 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2756 */ 2757 if (pcmc->legacy_acpi_table_size) { 2758 /* Subtracting aml_len gives the size of fixed tables. Then add the 2759 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2760 */ 2761 int legacy_aml_len = 2762 pcmc->legacy_acpi_table_size + 2763 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2764 int legacy_table_size = 2765 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2766 ACPI_BUILD_ALIGN_SIZE); 2767 if (tables_blob->len > legacy_table_size) { 2768 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2769 warn_report("migration may not work."); 2770 } 2771 g_array_set_size(tables_blob, legacy_table_size); 2772 } else { 2773 /* Make sure we have a buffer in case we need to resize the tables. */ 2774 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2775 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2776 warn_report("ACPI tables are larger than 64k."); 2777 warn_report("migration may not work."); 2778 warn_report("please remove CPUs, NUMA nodes, " 2779 "memory slots or PCI bridges."); 2780 } 2781 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2782 } 2783 2784 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2785 2786 /* Cleanup memory that's no longer used. */ 2787 g_array_free(table_offsets, true); 2788 } 2789 2790 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2791 { 2792 uint32_t size = acpi_data_len(data); 2793 2794 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2795 memory_region_ram_resize(mr, size, &error_abort); 2796 2797 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2798 memory_region_set_dirty(mr, 0, size); 2799 } 2800 2801 static void acpi_build_update(void *build_opaque) 2802 { 2803 AcpiBuildState *build_state = build_opaque; 2804 AcpiBuildTables tables; 2805 2806 /* No state to update or already patched? Nothing to do. */ 2807 if (!build_state || build_state->patched) { 2808 return; 2809 } 2810 build_state->patched = 1; 2811 2812 acpi_build_tables_init(&tables); 2813 2814 acpi_build(&tables, MACHINE(qdev_get_machine())); 2815 2816 acpi_ram_update(build_state->table_mr, tables.table_data); 2817 2818 if (build_state->rsdp) { 2819 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2820 } else { 2821 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2822 } 2823 2824 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2825 acpi_build_tables_cleanup(&tables, true); 2826 } 2827 2828 static void acpi_build_reset(void *build_opaque) 2829 { 2830 AcpiBuildState *build_state = build_opaque; 2831 build_state->patched = 0; 2832 } 2833 2834 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2835 GArray *blob, const char *name, 2836 uint64_t max_size) 2837 { 2838 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2839 name, acpi_build_update, build_state, NULL, true); 2840 } 2841 2842 static const VMStateDescription vmstate_acpi_build = { 2843 .name = "acpi_build", 2844 .version_id = 1, 2845 .minimum_version_id = 1, 2846 .fields = (VMStateField[]) { 2847 VMSTATE_UINT8(patched, AcpiBuildState), 2848 VMSTATE_END_OF_LIST() 2849 }, 2850 }; 2851 2852 void acpi_setup(void) 2853 { 2854 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2855 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2856 AcpiBuildTables tables; 2857 AcpiBuildState *build_state; 2858 Object *vmgenid_dev; 2859 2860 if (!pcms->fw_cfg) { 2861 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2862 return; 2863 } 2864 2865 if (!pcms->acpi_build_enabled) { 2866 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2867 return; 2868 } 2869 2870 if (!acpi_enabled) { 2871 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2872 return; 2873 } 2874 2875 build_state = g_malloc0(sizeof *build_state); 2876 2877 acpi_set_pci_info(); 2878 2879 acpi_build_tables_init(&tables); 2880 acpi_build(&tables, MACHINE(pcms)); 2881 2882 /* Now expose it all to Guest */ 2883 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2884 ACPI_BUILD_TABLE_FILE, 2885 ACPI_BUILD_TABLE_MAX_SIZE); 2886 assert(build_state->table_mr != NULL); 2887 2888 build_state->linker_mr = 2889 acpi_add_rom_blob(build_state, tables.linker->cmd_blob, 2890 "etc/table-loader", 0); 2891 2892 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2893 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2894 2895 vmgenid_dev = find_vmgenid_dev(); 2896 if (vmgenid_dev) { 2897 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2898 tables.vmgenid); 2899 } 2900 2901 if (!pcmc->rsdp_in_ram) { 2902 /* 2903 * Keep for compatibility with old machine types. 2904 * Though RSDP is small, its contents isn't immutable, so 2905 * we'll update it along with the rest of tables on guest access. 2906 */ 2907 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2908 2909 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2910 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2911 acpi_build_update, build_state, 2912 build_state->rsdp, rsdp_size, true); 2913 build_state->rsdp_mr = NULL; 2914 } else { 2915 build_state->rsdp = NULL; 2916 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2917 ACPI_BUILD_RSDP_FILE, 0); 2918 } 2919 2920 qemu_register_reset(acpi_build_reset, build_state); 2921 acpi_build_reset(build_state); 2922 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2923 2924 /* Cleanup tables but don't free the memory: we track it 2925 * in build_state. 2926 */ 2927 acpi_build_tables_cleanup(&tables, false); 2928 } 2929