1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "acpi-build.h" 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "hw/i386/pc.h" 32 #include "target-i386/cpu.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/acpi/bios-linker-loader.h" 38 #include "hw/loader.h" 39 #include "hw/isa/isa.h" 40 #include "hw/block/fdc.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "hw/mem/nvdimm.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "sysemu/tpm_backend.h" 46 #include "hw/timer/mc146818rtc_regs.h" 47 48 /* Supported chipsets: */ 49 #include "hw/acpi/piix4.h" 50 #include "hw/acpi/pcihp.h" 51 #include "hw/i386/ich9.h" 52 #include "hw/pci/pci_bus.h" 53 #include "hw/pci-host/q35.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/timer/hpet.h" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 64 * a little bit, there should be plenty of free space since the DSDT 65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 66 */ 67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 68 #define ACPI_BUILD_ALIGN_SIZE 0x1000 69 70 #define ACPI_BUILD_TABLE_SIZE 0x20000 71 72 /* #define DEBUG_ACPI_BUILD */ 73 #ifdef DEBUG_ACPI_BUILD 74 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 76 #else 77 #define ACPI_BUILD_DPRINTF(fmt, ...) 78 #endif 79 80 typedef struct AcpiCpuInfo { 81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 82 } AcpiCpuInfo; 83 84 typedef struct AcpiMcfgInfo { 85 uint64_t mcfg_base; 86 uint32_t mcfg_size; 87 } AcpiMcfgInfo; 88 89 typedef struct AcpiPmInfo { 90 bool s3_disabled; 91 bool s4_disabled; 92 bool pcihp_bridge_en; 93 uint8_t s4_val; 94 uint16_t sci_int; 95 uint8_t acpi_enable_cmd; 96 uint8_t acpi_disable_cmd; 97 uint32_t gpe0_blk; 98 uint32_t gpe0_blk_len; 99 uint32_t io_base; 100 uint16_t cpu_hp_io_base; 101 uint16_t cpu_hp_io_len; 102 uint16_t mem_hp_io_base; 103 uint16_t mem_hp_io_len; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool is_piix4; 110 bool has_hpet; 111 TPMVersion tpm_version; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 static 126 int acpi_add_cpu_info(Object *o, void *opaque) 127 { 128 AcpiCpuInfo *cpu = opaque; 129 uint64_t apic_id; 130 131 if (object_dynamic_cast(o, TYPE_CPU)) { 132 apic_id = object_property_get_int(o, "apic-id", NULL); 133 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 134 135 set_bit(apic_id, cpu->found_cpus); 136 } 137 138 object_child_foreach(o, acpi_add_cpu_info, opaque); 139 return 0; 140 } 141 142 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 143 { 144 Object *root = object_get_root(); 145 146 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 147 object_child_foreach(root, acpi_add_cpu_info, cpu); 148 } 149 150 static void acpi_get_pm_info(AcpiPmInfo *pm) 151 { 152 Object *piix = piix4_pm_find(); 153 Object *lpc = ich9_lpc_find(); 154 Object *obj = NULL; 155 QObject *o; 156 157 pm->cpu_hp_io_base = 0; 158 pm->pcihp_io_base = 0; 159 pm->pcihp_io_len = 0; 160 if (piix) { 161 obj = piix; 162 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 163 pm->pcihp_io_base = 164 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 165 pm->pcihp_io_len = 166 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 167 } 168 if (lpc) { 169 obj = lpc; 170 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 171 } 172 assert(obj); 173 174 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 175 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 176 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 177 178 /* Fill in optional s3/s4 related properties */ 179 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 180 if (o) { 181 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 182 } else { 183 pm->s3_disabled = false; 184 } 185 qobject_decref(o); 186 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 187 if (o) { 188 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 189 } else { 190 pm->s4_disabled = false; 191 } 192 qobject_decref(o); 193 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 194 if (o) { 195 pm->s4_val = qint_get_int(qobject_to_qint(o)); 196 } else { 197 pm->s4_val = false; 198 } 199 qobject_decref(o); 200 201 /* Fill in mandatory properties */ 202 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 203 204 pm->acpi_enable_cmd = object_property_get_int(obj, 205 ACPI_PM_PROP_ACPI_ENABLE_CMD, 206 NULL); 207 pm->acpi_disable_cmd = object_property_get_int(obj, 208 ACPI_PM_PROP_ACPI_DISABLE_CMD, 209 NULL); 210 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 211 NULL); 212 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 213 NULL); 214 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 215 NULL); 216 pm->pcihp_bridge_en = 217 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 218 NULL); 219 } 220 221 static void acpi_get_misc_info(AcpiMiscInfo *info) 222 { 223 Object *piix = piix4_pm_find(); 224 Object *lpc = ich9_lpc_find(); 225 assert(!!piix != !!lpc); 226 227 if (piix) { 228 info->is_piix4 = true; 229 } 230 if (lpc) { 231 info->is_piix4 = false; 232 } 233 234 info->has_hpet = hpet_find(); 235 info->tpm_version = tpm_get_version(); 236 info->pvpanic_port = pvpanic_port(); 237 info->applesmc_io_base = applesmc_port(); 238 } 239 240 /* 241 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 242 * On i386 arch we only have two pci hosts, so we can look only for them. 243 */ 244 static Object *acpi_get_i386_pci_host(void) 245 { 246 PCIHostState *host; 247 248 host = OBJECT_CHECK(PCIHostState, 249 object_resolve_path("/machine/i440fx", NULL), 250 TYPE_PCI_HOST_BRIDGE); 251 if (!host) { 252 host = OBJECT_CHECK(PCIHostState, 253 object_resolve_path("/machine/q35", NULL), 254 TYPE_PCI_HOST_BRIDGE); 255 } 256 257 return OBJECT(host); 258 } 259 260 static void acpi_get_pci_info(PcPciInfo *info) 261 { 262 Object *pci_host; 263 264 265 pci_host = acpi_get_i386_pci_host(); 266 g_assert(pci_host); 267 268 info->w32.begin = object_property_get_int(pci_host, 269 PCI_HOST_PROP_PCI_HOLE_START, 270 NULL); 271 info->w32.end = object_property_get_int(pci_host, 272 PCI_HOST_PROP_PCI_HOLE_END, 273 NULL); 274 info->w64.begin = object_property_get_int(pci_host, 275 PCI_HOST_PROP_PCI_HOLE64_START, 276 NULL); 277 info->w64.end = object_property_get_int(pci_host, 278 PCI_HOST_PROP_PCI_HOLE64_END, 279 NULL); 280 } 281 282 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 283 284 static void acpi_align_size(GArray *blob, unsigned align) 285 { 286 /* Align size to multiple of given size. This reduces the chance 287 * we need to change size in the future (breaking cross version migration). 288 */ 289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 290 } 291 292 /* FACS */ 293 static void 294 build_facs(GArray *table_data, GArray *linker) 295 { 296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 297 memcpy(&facs->signature, "FACS", 4); 298 facs->length = cpu_to_le32(sizeof(*facs)); 299 } 300 301 /* Load chipset information in FADT */ 302 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 303 { 304 fadt->model = 1; 305 fadt->reserved1 = 0; 306 fadt->sci_int = cpu_to_le16(pm->sci_int); 307 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 308 fadt->acpi_enable = pm->acpi_enable_cmd; 309 fadt->acpi_disable = pm->acpi_disable_cmd; 310 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 311 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 312 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 313 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 314 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 315 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 316 fadt->pm1_evt_len = 4; 317 fadt->pm1_cnt_len = 2; 318 fadt->pm_tmr_len = 4; 319 fadt->gpe0_blk_len = pm->gpe0_blk_len; 320 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 321 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 322 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 323 (1 << ACPI_FADT_F_PROC_C1) | 324 (1 << ACPI_FADT_F_SLP_BUTTON) | 325 (1 << ACPI_FADT_F_RTC_S4)); 326 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 327 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 328 * For more than 8 CPUs, "Clustered Logical" mode has to be used 329 */ 330 if (max_cpus > 8) { 331 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 332 } 333 fadt->century = RTC_CENTURY; 334 } 335 336 337 /* FADT */ 338 static void 339 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 340 unsigned facs, unsigned dsdt, 341 const char *oem_id, const char *oem_table_id) 342 { 343 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 344 345 fadt->firmware_ctrl = cpu_to_le32(facs); 346 /* FACS address to be filled by Guest linker */ 347 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 348 ACPI_BUILD_TABLE_FILE, 349 table_data, &fadt->firmware_ctrl, 350 sizeof fadt->firmware_ctrl); 351 352 fadt->dsdt = cpu_to_le32(dsdt); 353 /* DSDT address to be filled by Guest linker */ 354 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 355 ACPI_BUILD_TABLE_FILE, 356 table_data, &fadt->dsdt, 357 sizeof fadt->dsdt); 358 359 fadt_setup(fadt, pm); 360 361 build_header(linker, table_data, 362 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id); 363 } 364 365 static void 366 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu) 367 { 368 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 369 int madt_start = table_data->len; 370 371 AcpiMultipleApicTable *madt; 372 AcpiMadtIoApic *io_apic; 373 AcpiMadtIntsrcovr *intsrcovr; 374 AcpiMadtLocalNmi *local_nmi; 375 int i; 376 377 madt = acpi_data_push(table_data, sizeof *madt); 378 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 379 madt->flags = cpu_to_le32(1); 380 381 for (i = 0; i < pcms->apic_id_limit; i++) { 382 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 383 apic->type = ACPI_APIC_PROCESSOR; 384 apic->length = sizeof(*apic); 385 apic->processor_id = i; 386 apic->local_apic_id = i; 387 if (test_bit(i, cpu->found_cpus)) { 388 apic->flags = cpu_to_le32(1); 389 } else { 390 apic->flags = cpu_to_le32(0); 391 } 392 } 393 io_apic = acpi_data_push(table_data, sizeof *io_apic); 394 io_apic->type = ACPI_APIC_IO; 395 io_apic->length = sizeof(*io_apic); 396 #define ACPI_BUILD_IOAPIC_ID 0x0 397 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 398 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 399 io_apic->interrupt = cpu_to_le32(0); 400 401 if (pcms->apic_xrupt_override) { 402 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 403 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 404 intsrcovr->length = sizeof(*intsrcovr); 405 intsrcovr->source = 0; 406 intsrcovr->gsi = cpu_to_le32(2); 407 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 408 } 409 for (i = 1; i < 16; i++) { 410 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 411 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 412 /* No need for a INT source override structure. */ 413 continue; 414 } 415 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 416 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 417 intsrcovr->length = sizeof(*intsrcovr); 418 intsrcovr->source = i; 419 intsrcovr->gsi = cpu_to_le32(i); 420 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 421 } 422 423 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 424 local_nmi->type = ACPI_APIC_LOCAL_NMI; 425 local_nmi->length = sizeof(*local_nmi); 426 local_nmi->processor_id = 0xff; /* all processors */ 427 local_nmi->flags = cpu_to_le16(0); 428 local_nmi->lint = 1; /* ACPI_LINT1 */ 429 430 build_header(linker, table_data, 431 (void *)(table_data->data + madt_start), "APIC", 432 table_data->len - madt_start, 1, NULL, NULL); 433 } 434 435 /* Assign BSEL property to all buses. In the future, this can be changed 436 * to only assign to buses that support hotplug. 437 */ 438 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 439 { 440 unsigned *bsel_alloc = opaque; 441 unsigned *bus_bsel; 442 443 if (qbus_is_hotpluggable(BUS(bus))) { 444 bus_bsel = g_malloc(sizeof *bus_bsel); 445 446 *bus_bsel = (*bsel_alloc)++; 447 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 448 bus_bsel, NULL); 449 } 450 451 return bsel_alloc; 452 } 453 454 static void acpi_set_pci_info(void) 455 { 456 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 457 unsigned bsel_alloc = 0; 458 459 if (bus) { 460 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 461 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 462 } 463 } 464 465 static void build_append_pcihp_notify_entry(Aml *method, int slot) 466 { 467 Aml *if_ctx; 468 int32_t devfn = PCI_DEVFN(slot, 0); 469 470 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 471 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 472 aml_append(method, if_ctx); 473 } 474 475 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 476 bool pcihp_bridge_en) 477 { 478 Aml *dev, *notify_method, *method; 479 QObject *bsel; 480 PCIBus *sec; 481 int i; 482 483 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 484 if (bsel) { 485 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 486 487 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 488 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 489 } 490 491 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 492 DeviceClass *dc; 493 PCIDeviceClass *pc; 494 PCIDevice *pdev = bus->devices[i]; 495 int slot = PCI_SLOT(i); 496 bool hotplug_enabled_dev; 497 bool bridge_in_acpi; 498 499 if (!pdev) { 500 if (bsel) { /* add hotplug slots for non present devices */ 501 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 502 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 503 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 504 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 505 aml_append(method, 506 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 507 ); 508 aml_append(dev, method); 509 aml_append(parent_scope, dev); 510 511 build_append_pcihp_notify_entry(notify_method, slot); 512 } 513 continue; 514 } 515 516 pc = PCI_DEVICE_GET_CLASS(pdev); 517 dc = DEVICE_GET_CLASS(pdev); 518 519 /* When hotplug for bridges is enabled, bridges are 520 * described in ACPI separately (see build_pci_bus_end). 521 * In this case they aren't themselves hot-pluggable. 522 * Hotplugged bridges *are* hot-pluggable. 523 */ 524 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 525 !DEVICE(pdev)->hotplugged; 526 527 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 528 529 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 530 continue; 531 } 532 533 /* start to compose PCI slot descriptor */ 534 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 535 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 536 537 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 538 /* add VGA specific AML methods */ 539 int s3d; 540 541 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 542 s3d = 3; 543 } else { 544 s3d = 0; 545 } 546 547 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 548 aml_append(method, aml_return(aml_int(0))); 549 aml_append(dev, method); 550 551 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 552 aml_append(method, aml_return(aml_int(0))); 553 aml_append(dev, method); 554 555 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 556 aml_append(method, aml_return(aml_int(s3d))); 557 aml_append(dev, method); 558 } else if (hotplug_enabled_dev) { 559 /* add _SUN/_EJ0 to make slot hotpluggable */ 560 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 561 562 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 563 aml_append(method, 564 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 565 ); 566 aml_append(dev, method); 567 568 if (bsel) { 569 build_append_pcihp_notify_entry(notify_method, slot); 570 } 571 } else if (bridge_in_acpi) { 572 /* 573 * device is coldplugged bridge, 574 * add child device descriptions into its scope 575 */ 576 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 577 578 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 579 } 580 /* slot descriptor has been composed, add it into parent context */ 581 aml_append(parent_scope, dev); 582 } 583 584 if (bsel) { 585 aml_append(parent_scope, notify_method); 586 } 587 588 /* Append PCNT method to notify about events on local and child buses. 589 * Add unconditionally for root since DSDT expects it. 590 */ 591 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 592 593 /* If bus supports hotplug select it and notify about local events */ 594 if (bsel) { 595 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 596 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 597 aml_append(method, 598 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 599 ); 600 aml_append(method, 601 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 602 ); 603 } 604 605 /* Notify about child bus events in any case */ 606 if (pcihp_bridge_en) { 607 QLIST_FOREACH(sec, &bus->child, sibling) { 608 int32_t devfn = sec->parent_dev->devfn; 609 610 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 611 } 612 } 613 aml_append(parent_scope, method); 614 qobject_decref(bsel); 615 } 616 617 /** 618 * build_prt_entry: 619 * @link_name: link name for PCI route entry 620 * 621 * build AML package containing a PCI route entry for @link_name 622 */ 623 static Aml *build_prt_entry(const char *link_name) 624 { 625 Aml *a_zero = aml_int(0); 626 Aml *pkg = aml_package(4); 627 aml_append(pkg, a_zero); 628 aml_append(pkg, a_zero); 629 aml_append(pkg, aml_name("%s", link_name)); 630 aml_append(pkg, a_zero); 631 return pkg; 632 } 633 634 /* 635 * initialize_route - Initialize the interrupt routing rule 636 * through a specific LINK: 637 * if (lnk_idx == idx) 638 * route using link 'link_name' 639 */ 640 static Aml *initialize_route(Aml *route, const char *link_name, 641 Aml *lnk_idx, int idx) 642 { 643 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 644 Aml *pkg = build_prt_entry(link_name); 645 646 aml_append(if_ctx, aml_store(pkg, route)); 647 648 return if_ctx; 649 } 650 651 /* 652 * build_prt - Define interrupt rounting rules 653 * 654 * Returns an array of 128 routes, one for each device, 655 * based on device location. 656 * The main goal is to equaly distribute the interrupts 657 * over the 4 existing ACPI links (works only for i440fx). 658 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 659 * 660 */ 661 static Aml *build_prt(bool is_pci0_prt) 662 { 663 Aml *method, *while_ctx, *pin, *res; 664 665 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 666 res = aml_local(0); 667 pin = aml_local(1); 668 aml_append(method, aml_store(aml_package(128), res)); 669 aml_append(method, aml_store(aml_int(0), pin)); 670 671 /* while (pin < 128) */ 672 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 673 { 674 Aml *slot = aml_local(2); 675 Aml *lnk_idx = aml_local(3); 676 Aml *route = aml_local(4); 677 678 /* slot = pin >> 2 */ 679 aml_append(while_ctx, 680 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 681 /* lnk_idx = (slot + pin) & 3 */ 682 aml_append(while_ctx, 683 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 684 lnk_idx)); 685 686 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 687 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 688 if (is_pci0_prt) { 689 Aml *if_device_1, *if_pin_4, *else_pin_4; 690 691 /* device 1 is the power-management device, needs SCI */ 692 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 693 { 694 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 695 { 696 aml_append(if_pin_4, 697 aml_store(build_prt_entry("LNKS"), route)); 698 } 699 aml_append(if_device_1, if_pin_4); 700 else_pin_4 = aml_else(); 701 { 702 aml_append(else_pin_4, 703 aml_store(build_prt_entry("LNKA"), route)); 704 } 705 aml_append(if_device_1, else_pin_4); 706 } 707 aml_append(while_ctx, if_device_1); 708 } else { 709 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 710 } 711 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 712 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 713 714 /* route[0] = 0x[slot]FFFF */ 715 aml_append(while_ctx, 716 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 717 NULL), 718 aml_index(route, aml_int(0)))); 719 /* route[1] = pin & 3 */ 720 aml_append(while_ctx, 721 aml_store(aml_and(pin, aml_int(3), NULL), 722 aml_index(route, aml_int(1)))); 723 /* res[pin] = route */ 724 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 725 /* pin++ */ 726 aml_append(while_ctx, aml_increment(pin)); 727 } 728 aml_append(method, while_ctx); 729 /* return res*/ 730 aml_append(method, aml_return(res)); 731 732 return method; 733 } 734 735 typedef struct CrsRangeEntry { 736 uint64_t base; 737 uint64_t limit; 738 } CrsRangeEntry; 739 740 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 741 { 742 CrsRangeEntry *entry; 743 744 entry = g_malloc(sizeof(*entry)); 745 entry->base = base; 746 entry->limit = limit; 747 748 g_ptr_array_add(ranges, entry); 749 } 750 751 static void crs_range_free(gpointer data) 752 { 753 CrsRangeEntry *entry = (CrsRangeEntry *)data; 754 g_free(entry); 755 } 756 757 static gint crs_range_compare(gconstpointer a, gconstpointer b) 758 { 759 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 760 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 761 762 return (int64_t)entry_a->base - (int64_t)entry_b->base; 763 } 764 765 /* 766 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 767 * interval, computes the 'free' ranges from the same interval. 768 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 769 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 770 */ 771 static void crs_replace_with_free_ranges(GPtrArray *ranges, 772 uint64_t start, uint64_t end) 773 { 774 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free); 775 uint64_t free_base = start; 776 int i; 777 778 g_ptr_array_sort(ranges, crs_range_compare); 779 for (i = 0; i < ranges->len; i++) { 780 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 781 782 if (free_base < used->base) { 783 crs_range_insert(free_ranges, free_base, used->base - 1); 784 } 785 786 free_base = used->limit + 1; 787 } 788 789 if (free_base < end) { 790 crs_range_insert(free_ranges, free_base, end); 791 } 792 793 g_ptr_array_set_size(ranges, 0); 794 for (i = 0; i < free_ranges->len; i++) { 795 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 796 } 797 798 g_ptr_array_free(free_ranges, false); 799 } 800 801 /* 802 * crs_range_merge - merges adjacent ranges in the given array. 803 * Array elements are deleted and replaced with the merged ranges. 804 */ 805 static void crs_range_merge(GPtrArray *range) 806 { 807 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 808 CrsRangeEntry *entry; 809 uint64_t range_base, range_limit; 810 int i; 811 812 if (!range->len) { 813 return; 814 } 815 816 g_ptr_array_sort(range, crs_range_compare); 817 818 entry = g_ptr_array_index(range, 0); 819 range_base = entry->base; 820 range_limit = entry->limit; 821 for (i = 1; i < range->len; i++) { 822 entry = g_ptr_array_index(range, i); 823 if (entry->base - 1 == range_limit) { 824 range_limit = entry->limit; 825 } else { 826 crs_range_insert(tmp, range_base, range_limit); 827 range_base = entry->base; 828 range_limit = entry->limit; 829 } 830 } 831 crs_range_insert(tmp, range_base, range_limit); 832 833 g_ptr_array_set_size(range, 0); 834 for (i = 0; i < tmp->len; i++) { 835 entry = g_ptr_array_index(tmp, i); 836 crs_range_insert(range, entry->base, entry->limit); 837 } 838 g_ptr_array_free(tmp, true); 839 } 840 841 static Aml *build_crs(PCIHostState *host, 842 GPtrArray *io_ranges, GPtrArray *mem_ranges) 843 { 844 Aml *crs = aml_resource_template(); 845 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 846 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 847 CrsRangeEntry *entry; 848 uint8_t max_bus = pci_bus_num(host->bus); 849 uint8_t type; 850 int devfn; 851 int i; 852 853 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 854 uint64_t range_base, range_limit; 855 PCIDevice *dev = host->bus->devices[devfn]; 856 857 if (!dev) { 858 continue; 859 } 860 861 for (i = 0; i < PCI_NUM_REGIONS; i++) { 862 PCIIORegion *r = &dev->io_regions[i]; 863 864 range_base = r->addr; 865 range_limit = r->addr + r->size - 1; 866 867 /* 868 * Work-around for old bioses 869 * that do not support multiple root buses 870 */ 871 if (!range_base || range_base > range_limit) { 872 continue; 873 } 874 875 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 876 crs_range_insert(host_io_ranges, range_base, range_limit); 877 } else { /* "memory" */ 878 crs_range_insert(host_mem_ranges, range_base, range_limit); 879 } 880 } 881 882 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 883 if (type == PCI_HEADER_TYPE_BRIDGE) { 884 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 885 if (subordinate > max_bus) { 886 max_bus = subordinate; 887 } 888 889 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 890 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 891 892 /* 893 * Work-around for old bioses 894 * that do not support multiple root buses 895 */ 896 if (range_base && range_base <= range_limit) { 897 crs_range_insert(host_io_ranges, range_base, range_limit); 898 } 899 900 range_base = 901 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 902 range_limit = 903 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 904 905 /* 906 * Work-around for old bioses 907 * that do not support multiple root buses 908 */ 909 if (range_base && range_base <= range_limit) { 910 crs_range_insert(host_mem_ranges, range_base, range_limit); 911 } 912 913 range_base = 914 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 915 range_limit = 916 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 917 918 /* 919 * Work-around for old bioses 920 * that do not support multiple root buses 921 */ 922 if (range_base && range_base <= range_limit) { 923 crs_range_insert(host_mem_ranges, range_base, range_limit); 924 } 925 } 926 } 927 928 crs_range_merge(host_io_ranges); 929 for (i = 0; i < host_io_ranges->len; i++) { 930 entry = g_ptr_array_index(host_io_ranges, i); 931 aml_append(crs, 932 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 933 AML_POS_DECODE, AML_ENTIRE_RANGE, 934 0, entry->base, entry->limit, 0, 935 entry->limit - entry->base + 1)); 936 crs_range_insert(io_ranges, entry->base, entry->limit); 937 } 938 g_ptr_array_free(host_io_ranges, true); 939 940 crs_range_merge(host_mem_ranges); 941 for (i = 0; i < host_mem_ranges->len; i++) { 942 entry = g_ptr_array_index(host_mem_ranges, i); 943 aml_append(crs, 944 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 945 AML_MAX_FIXED, AML_NON_CACHEABLE, 946 AML_READ_WRITE, 947 0, entry->base, entry->limit, 0, 948 entry->limit - entry->base + 1)); 949 crs_range_insert(mem_ranges, entry->base, entry->limit); 950 } 951 g_ptr_array_free(host_mem_ranges, true); 952 953 aml_append(crs, 954 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 955 0, 956 pci_bus_num(host->bus), 957 max_bus, 958 0, 959 max_bus - pci_bus_num(host->bus) + 1)); 960 961 return crs; 962 } 963 964 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus, 965 AcpiCpuInfo *cpu, AcpiPmInfo *pm) 966 { 967 int i; 968 Aml *dev; 969 Aml *crs; 970 Aml *pkg; 971 Aml *field; 972 Aml *ifctx; 973 Aml *method; 974 975 /* The current AML generator can cover the APIC ID range [0..255], 976 * inclusive, for VCPU hotplug. */ 977 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 978 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 979 980 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 981 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 982 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 983 aml_append(dev, 984 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 985 ); 986 /* device present, functioning, decoding, not shown in UI */ 987 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 988 crs = aml_resource_template(); 989 aml_append(crs, 990 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 991 pm->cpu_hp_io_len) 992 ); 993 aml_append(dev, aml_name_decl("_CRS", crs)); 994 aml_append(sb_scope, dev); 995 /* declare CPU hotplug MMIO region and PRS field to access it */ 996 aml_append(sb_scope, aml_operation_region( 997 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len)); 998 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 999 aml_append(field, aml_named_field("PRS", 256)); 1000 aml_append(sb_scope, field); 1001 1002 /* build Processor object for each processor */ 1003 for (i = 0; i < acpi_cpus; i++) { 1004 dev = aml_processor(i, 0, 0, "CP%.02X", i); 1005 1006 method = aml_method("_MAT", 0, AML_NOTSERIALIZED); 1007 aml_append(method, 1008 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i)))); 1009 aml_append(dev, method); 1010 1011 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1012 aml_append(method, 1013 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i)))); 1014 aml_append(dev, method); 1015 1016 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1017 aml_append(method, 1018 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0))) 1019 ); 1020 aml_append(dev, method); 1021 1022 aml_append(sb_scope, dev); 1023 } 1024 1025 /* build this code: 1026 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 1027 */ 1028 /* Arg0 = Processor ID = APIC ID */ 1029 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1030 for (i = 0; i < acpi_cpus; i++) { 1031 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1032 aml_append(ifctx, 1033 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 1034 ); 1035 aml_append(method, ifctx); 1036 } 1037 aml_append(sb_scope, method); 1038 1039 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 1040 * 1041 * Note: The ability to create variable-sized packages was first 1042 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 1043 * ith up to 255 elements. Windows guests up to win2k8 fail when 1044 * VarPackageOp is used. 1045 */ 1046 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 1047 aml_varpackage(acpi_cpus); 1048 1049 for (i = 0; i < acpi_cpus; i++) { 1050 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 1051 aml_append(pkg, aml_int(b)); 1052 } 1053 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); 1054 } 1055 1056 static void build_memory_devices(Aml *sb_scope, int nr_mem, 1057 uint16_t io_base, uint16_t io_len) 1058 { 1059 int i; 1060 Aml *scope; 1061 Aml *crs; 1062 Aml *field; 1063 Aml *dev; 1064 Aml *method; 1065 Aml *ifctx; 1066 1067 /* build memory devices */ 1068 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 1069 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE); 1070 aml_append(scope, 1071 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem)) 1072 ); 1073 1074 crs = aml_resource_template(); 1075 aml_append(crs, 1076 aml_io(AML_DECODE16, io_base, io_base, 0, io_len) 1077 ); 1078 aml_append(scope, aml_name_decl("_CRS", crs)); 1079 1080 aml_append(scope, aml_operation_region( 1081 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO, 1082 aml_int(io_base), io_len) 1083 ); 1084 1085 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1086 AML_NOLOCK, AML_PRESERVE); 1087 aml_append(field, /* read only */ 1088 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32)); 1089 aml_append(field, /* read only */ 1090 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32)); 1091 aml_append(field, /* read only */ 1092 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32)); 1093 aml_append(field, /* read only */ 1094 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32)); 1095 aml_append(field, /* read only */ 1096 aml_named_field(MEMORY_SLOT_PROXIMITY, 32)); 1097 aml_append(scope, field); 1098 1099 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC, 1100 AML_NOLOCK, AML_WRITE_AS_ZEROS); 1101 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 1102 aml_append(field, /* 1 if enabled, read only */ 1103 aml_named_field(MEMORY_SLOT_ENABLED, 1)); 1104 aml_append(field, 1105 /*(read) 1 if has a insert event. (write) 1 to clear event */ 1106 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1)); 1107 aml_append(field, 1108 /* (read) 1 if has a remove event. (write) 1 to clear event */ 1109 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1)); 1110 aml_append(field, 1111 /* initiates device eject, write only */ 1112 aml_named_field(MEMORY_SLOT_EJECT, 1)); 1113 aml_append(scope, field); 1114 1115 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1116 AML_NOLOCK, AML_PRESERVE); 1117 aml_append(field, /* DIMM selector, write only */ 1118 aml_named_field(MEMORY_SLOT_SLECTOR, 32)); 1119 aml_append(field, /* _OST event code, write only */ 1120 aml_named_field(MEMORY_SLOT_OST_EVENT, 32)); 1121 aml_append(field, /* _OST status code, write only */ 1122 aml_named_field(MEMORY_SLOT_OST_STATUS, 32)); 1123 aml_append(scope, field); 1124 aml_append(sb_scope, scope); 1125 1126 for (i = 0; i < nr_mem; i++) { 1127 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "." 1128 const char *s; 1129 1130 dev = aml_device("MP%02X", i); 1131 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 1132 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 1133 1134 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1135 s = BASEPATH MEMORY_SLOT_CRS_METHOD; 1136 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1137 aml_append(dev, method); 1138 1139 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1140 s = BASEPATH MEMORY_SLOT_STATUS_METHOD; 1141 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1142 aml_append(dev, method); 1143 1144 method = aml_method("_PXM", 0, AML_NOTSERIALIZED); 1145 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD; 1146 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1147 aml_append(dev, method); 1148 1149 method = aml_method("_OST", 3, AML_NOTSERIALIZED); 1150 s = BASEPATH MEMORY_SLOT_OST_METHOD; 1151 1152 aml_append(method, aml_return(aml_call4( 1153 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 1154 ))); 1155 aml_append(dev, method); 1156 1157 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1158 s = BASEPATH MEMORY_SLOT_EJECT_METHOD; 1159 aml_append(method, aml_return(aml_call2( 1160 s, aml_name("_UID"), aml_arg(0)))); 1161 aml_append(dev, method); 1162 1163 aml_append(sb_scope, dev); 1164 } 1165 1166 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 1167 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 1168 */ 1169 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1170 for (i = 0; i < nr_mem; i++) { 1171 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1172 aml_append(ifctx, 1173 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 1174 ); 1175 aml_append(method, ifctx); 1176 } 1177 aml_append(sb_scope, method); 1178 } 1179 1180 static void build_hpet_aml(Aml *table) 1181 { 1182 Aml *crs; 1183 Aml *field; 1184 Aml *method; 1185 Aml *if_ctx; 1186 Aml *scope = aml_scope("_SB"); 1187 Aml *dev = aml_device("HPET"); 1188 Aml *zero = aml_int(0); 1189 Aml *id = aml_local(0); 1190 Aml *period = aml_local(1); 1191 1192 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1193 aml_append(dev, aml_name_decl("_UID", zero)); 1194 1195 aml_append(dev, 1196 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1197 HPET_LEN)); 1198 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1199 aml_append(field, aml_named_field("VEND", 32)); 1200 aml_append(field, aml_named_field("PRD", 32)); 1201 aml_append(dev, field); 1202 1203 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1204 aml_append(method, aml_store(aml_name("VEND"), id)); 1205 aml_append(method, aml_store(aml_name("PRD"), period)); 1206 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1207 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1208 aml_equal(id, aml_int(0xffff)))); 1209 { 1210 aml_append(if_ctx, aml_return(zero)); 1211 } 1212 aml_append(method, if_ctx); 1213 1214 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1215 aml_lgreater(period, aml_int(100000000)))); 1216 { 1217 aml_append(if_ctx, aml_return(zero)); 1218 } 1219 aml_append(method, if_ctx); 1220 1221 aml_append(method, aml_return(aml_int(0x0F))); 1222 aml_append(dev, method); 1223 1224 crs = aml_resource_template(); 1225 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1226 aml_append(dev, aml_name_decl("_CRS", crs)); 1227 1228 aml_append(scope, dev); 1229 aml_append(table, scope); 1230 } 1231 1232 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1233 { 1234 Aml *dev, *fdi; 1235 uint8_t maxc, maxh, maxs; 1236 1237 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1238 1239 dev = aml_device("FLP%c", 'A' + idx); 1240 1241 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1242 1243 fdi = aml_package(16); 1244 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1245 aml_append(fdi, 1246 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1247 /* 1248 * the values below are the limits of the drive, and are thus independent 1249 * of the inserted media 1250 */ 1251 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1252 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1253 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1254 /* 1255 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1256 * the drive type, so shall we 1257 */ 1258 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1259 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1260 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1261 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1262 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1263 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1264 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1265 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1266 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1267 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1268 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1269 1270 aml_append(dev, aml_name_decl("_FDI", fdi)); 1271 return dev; 1272 } 1273 1274 static Aml *build_fdc_device_aml(ISADevice *fdc) 1275 { 1276 int i; 1277 Aml *dev; 1278 Aml *crs; 1279 1280 #define ACPI_FDE_MAX_FD 4 1281 uint32_t fde_buf[5] = { 1282 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1283 cpu_to_le32(2) /* tape presence (2 == never present) */ 1284 }; 1285 1286 dev = aml_device("FDC0"); 1287 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1288 1289 crs = aml_resource_template(); 1290 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1291 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1292 aml_append(crs, aml_irq_no_flags(6)); 1293 aml_append(crs, 1294 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1295 aml_append(dev, aml_name_decl("_CRS", crs)); 1296 1297 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1298 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1299 1300 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1301 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1302 aml_append(dev, build_fdinfo_aml(i, type)); 1303 } 1304 } 1305 aml_append(dev, aml_name_decl("_FDE", 1306 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1307 1308 return dev; 1309 } 1310 1311 static Aml *build_rtc_device_aml(void) 1312 { 1313 Aml *dev; 1314 Aml *crs; 1315 1316 dev = aml_device("RTC"); 1317 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1318 crs = aml_resource_template(); 1319 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1320 aml_append(crs, aml_irq_no_flags(8)); 1321 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1322 aml_append(dev, aml_name_decl("_CRS", crs)); 1323 1324 return dev; 1325 } 1326 1327 static Aml *build_kbd_device_aml(void) 1328 { 1329 Aml *dev; 1330 Aml *crs; 1331 Aml *method; 1332 1333 dev = aml_device("KBD"); 1334 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1335 1336 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1337 aml_append(method, aml_return(aml_int(0x0f))); 1338 aml_append(dev, method); 1339 1340 crs = aml_resource_template(); 1341 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1342 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1343 aml_append(crs, aml_irq_no_flags(1)); 1344 aml_append(dev, aml_name_decl("_CRS", crs)); 1345 1346 return dev; 1347 } 1348 1349 static Aml *build_mouse_device_aml(void) 1350 { 1351 Aml *dev; 1352 Aml *crs; 1353 Aml *method; 1354 1355 dev = aml_device("MOU"); 1356 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1357 1358 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1359 aml_append(method, aml_return(aml_int(0x0f))); 1360 aml_append(dev, method); 1361 1362 crs = aml_resource_template(); 1363 aml_append(crs, aml_irq_no_flags(12)); 1364 aml_append(dev, aml_name_decl("_CRS", crs)); 1365 1366 return dev; 1367 } 1368 1369 static Aml *build_lpt_device_aml(void) 1370 { 1371 Aml *dev; 1372 Aml *crs; 1373 Aml *method; 1374 Aml *if_ctx; 1375 Aml *else_ctx; 1376 Aml *zero = aml_int(0); 1377 Aml *is_present = aml_local(0); 1378 1379 dev = aml_device("LPT"); 1380 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1381 1382 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1383 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1384 if_ctx = aml_if(aml_equal(is_present, zero)); 1385 { 1386 aml_append(if_ctx, aml_return(aml_int(0x00))); 1387 } 1388 aml_append(method, if_ctx); 1389 else_ctx = aml_else(); 1390 { 1391 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1392 } 1393 aml_append(method, else_ctx); 1394 aml_append(dev, method); 1395 1396 crs = aml_resource_template(); 1397 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1398 aml_append(crs, aml_irq_no_flags(7)); 1399 aml_append(dev, aml_name_decl("_CRS", crs)); 1400 1401 return dev; 1402 } 1403 1404 static Aml *build_com_device_aml(uint8_t uid) 1405 { 1406 Aml *dev; 1407 Aml *crs; 1408 Aml *method; 1409 Aml *if_ctx; 1410 Aml *else_ctx; 1411 Aml *zero = aml_int(0); 1412 Aml *is_present = aml_local(0); 1413 const char *enabled_field = "CAEN"; 1414 uint8_t irq = 4; 1415 uint16_t io_port = 0x03F8; 1416 1417 assert(uid == 1 || uid == 2); 1418 if (uid == 2) { 1419 enabled_field = "CBEN"; 1420 irq = 3; 1421 io_port = 0x02F8; 1422 } 1423 1424 dev = aml_device("COM%d", uid); 1425 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1426 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1427 1428 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1429 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1430 if_ctx = aml_if(aml_equal(is_present, zero)); 1431 { 1432 aml_append(if_ctx, aml_return(aml_int(0x00))); 1433 } 1434 aml_append(method, if_ctx); 1435 else_ctx = aml_else(); 1436 { 1437 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1438 } 1439 aml_append(method, else_ctx); 1440 aml_append(dev, method); 1441 1442 crs = aml_resource_template(); 1443 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1444 aml_append(crs, aml_irq_no_flags(irq)); 1445 aml_append(dev, aml_name_decl("_CRS", crs)); 1446 1447 return dev; 1448 } 1449 1450 static void build_isa_devices_aml(Aml *table) 1451 { 1452 ISADevice *fdc = pc_find_fdc0(); 1453 1454 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1455 1456 aml_append(scope, build_rtc_device_aml()); 1457 aml_append(scope, build_kbd_device_aml()); 1458 aml_append(scope, build_mouse_device_aml()); 1459 if (fdc) { 1460 aml_append(scope, build_fdc_device_aml(fdc)); 1461 } 1462 aml_append(scope, build_lpt_device_aml()); 1463 aml_append(scope, build_com_device_aml(1)); 1464 aml_append(scope, build_com_device_aml(2)); 1465 1466 aml_append(table, scope); 1467 } 1468 1469 static void build_dbg_aml(Aml *table) 1470 { 1471 Aml *field; 1472 Aml *method; 1473 Aml *while_ctx; 1474 Aml *scope = aml_scope("\\"); 1475 Aml *buf = aml_local(0); 1476 Aml *len = aml_local(1); 1477 Aml *idx = aml_local(2); 1478 1479 aml_append(scope, 1480 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1481 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1482 aml_append(field, aml_named_field("DBGB", 8)); 1483 aml_append(scope, field); 1484 1485 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1486 1487 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1488 aml_append(method, aml_to_buffer(buf, buf)); 1489 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1490 aml_append(method, aml_store(aml_int(0), idx)); 1491 1492 while_ctx = aml_while(aml_lless(idx, len)); 1493 aml_append(while_ctx, 1494 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1495 aml_append(while_ctx, aml_increment(idx)); 1496 aml_append(method, while_ctx); 1497 1498 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1499 aml_append(scope, method); 1500 1501 aml_append(table, scope); 1502 } 1503 1504 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1505 { 1506 Aml *dev; 1507 Aml *crs; 1508 Aml *method; 1509 uint32_t irqs[] = {5, 10, 11}; 1510 1511 dev = aml_device("%s", name); 1512 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1513 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1514 1515 crs = aml_resource_template(); 1516 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1517 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1518 aml_append(dev, aml_name_decl("_PRS", crs)); 1519 1520 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1521 aml_append(method, aml_return(aml_call1("IQST", reg))); 1522 aml_append(dev, method); 1523 1524 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1525 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1526 aml_append(dev, method); 1527 1528 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1529 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1530 aml_append(dev, method); 1531 1532 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1533 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1534 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1535 aml_append(dev, method); 1536 1537 return dev; 1538 } 1539 1540 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1541 { 1542 Aml *dev; 1543 Aml *crs; 1544 Aml *method; 1545 uint32_t irqs; 1546 1547 dev = aml_device("%s", name); 1548 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1549 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1550 1551 crs = aml_resource_template(); 1552 irqs = gsi; 1553 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1554 AML_SHARED, &irqs, 1)); 1555 aml_append(dev, aml_name_decl("_PRS", crs)); 1556 1557 aml_append(dev, aml_name_decl("_CRS", crs)); 1558 1559 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1560 aml_append(dev, method); 1561 1562 return dev; 1563 } 1564 1565 /* _CRS method - get current settings */ 1566 static Aml *build_iqcr_method(bool is_piix4) 1567 { 1568 Aml *if_ctx; 1569 uint32_t irqs; 1570 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1571 Aml *crs = aml_resource_template(); 1572 1573 irqs = 0; 1574 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1575 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1576 aml_append(method, aml_name_decl("PRR0", crs)); 1577 1578 aml_append(method, 1579 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1580 1581 if (is_piix4) { 1582 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1583 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1584 aml_append(method, if_ctx); 1585 } else { 1586 aml_append(method, 1587 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1588 aml_name("PRRI"))); 1589 } 1590 1591 aml_append(method, aml_return(aml_name("PRR0"))); 1592 return method; 1593 } 1594 1595 /* _STA method - get status */ 1596 static Aml *build_irq_status_method(void) 1597 { 1598 Aml *if_ctx; 1599 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1600 1601 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1602 aml_append(if_ctx, aml_return(aml_int(0x09))); 1603 aml_append(method, if_ctx); 1604 aml_append(method, aml_return(aml_int(0x0B))); 1605 return method; 1606 } 1607 1608 static void build_piix4_pci0_int(Aml *table) 1609 { 1610 Aml *dev; 1611 Aml *crs; 1612 Aml *field; 1613 Aml *method; 1614 uint32_t irqs; 1615 Aml *sb_scope = aml_scope("_SB"); 1616 Aml *pci0_scope = aml_scope("PCI0"); 1617 1618 aml_append(pci0_scope, build_prt(true)); 1619 aml_append(sb_scope, pci0_scope); 1620 1621 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1622 aml_append(field, aml_named_field("PRQ0", 8)); 1623 aml_append(field, aml_named_field("PRQ1", 8)); 1624 aml_append(field, aml_named_field("PRQ2", 8)); 1625 aml_append(field, aml_named_field("PRQ3", 8)); 1626 aml_append(sb_scope, field); 1627 1628 aml_append(sb_scope, build_irq_status_method()); 1629 aml_append(sb_scope, build_iqcr_method(true)); 1630 1631 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1632 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1633 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1634 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1635 1636 dev = aml_device("LNKS"); 1637 { 1638 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1639 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1640 1641 crs = aml_resource_template(); 1642 irqs = 9; 1643 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1644 AML_ACTIVE_HIGH, AML_SHARED, 1645 &irqs, 1)); 1646 aml_append(dev, aml_name_decl("_PRS", crs)); 1647 1648 /* The SCI cannot be disabled and is always attached to GSI 9, 1649 * so these are no-ops. We only need this link to override the 1650 * polarity to active high and match the content of the MADT. 1651 */ 1652 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1653 aml_append(method, aml_return(aml_int(0x0b))); 1654 aml_append(dev, method); 1655 1656 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1657 aml_append(dev, method); 1658 1659 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1660 aml_append(method, aml_return(aml_name("_PRS"))); 1661 aml_append(dev, method); 1662 1663 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1664 aml_append(dev, method); 1665 } 1666 aml_append(sb_scope, dev); 1667 1668 aml_append(table, sb_scope); 1669 } 1670 1671 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1672 { 1673 int i; 1674 int head; 1675 Aml *pkg; 1676 char base = name[3] < 'E' ? 'A' : 'E'; 1677 char *s = g_strdup(name); 1678 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1679 1680 assert(strlen(s) == 4); 1681 1682 head = name[3] - base; 1683 for (i = 0; i < 4; i++) { 1684 if (head + i > 3) { 1685 head = i * -1; 1686 } 1687 s[3] = base + head + i; 1688 pkg = aml_package(4); 1689 aml_append(pkg, a_nr); 1690 aml_append(pkg, aml_int(i)); 1691 aml_append(pkg, aml_name("%s", s)); 1692 aml_append(pkg, aml_int(0)); 1693 aml_append(ctx, pkg); 1694 } 1695 g_free(s); 1696 } 1697 1698 static Aml *build_q35_routing_table(const char *str) 1699 { 1700 int i; 1701 Aml *pkg; 1702 char *name = g_strdup_printf("%s ", str); 1703 1704 pkg = aml_package(128); 1705 for (i = 0; i < 0x18; i++) { 1706 name[3] = 'E' + (i & 0x3); 1707 append_q35_prt_entry(pkg, i, name); 1708 } 1709 1710 name[3] = 'E'; 1711 append_q35_prt_entry(pkg, 0x18, name); 1712 1713 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1714 for (i = 0x0019; i < 0x1e; i++) { 1715 name[3] = 'A'; 1716 append_q35_prt_entry(pkg, i, name); 1717 } 1718 1719 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1720 name[3] = 'E'; 1721 append_q35_prt_entry(pkg, 0x1e, name); 1722 name[3] = 'A'; 1723 append_q35_prt_entry(pkg, 0x1f, name); 1724 1725 g_free(name); 1726 return pkg; 1727 } 1728 1729 static void build_q35_pci0_int(Aml *table) 1730 { 1731 Aml *field; 1732 Aml *method; 1733 Aml *sb_scope = aml_scope("_SB"); 1734 Aml *pci0_scope = aml_scope("PCI0"); 1735 1736 /* Zero => PIC mode, One => APIC Mode */ 1737 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1738 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1739 { 1740 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1741 } 1742 aml_append(table, method); 1743 1744 aml_append(pci0_scope, 1745 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1746 aml_append(pci0_scope, 1747 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1748 1749 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1750 { 1751 Aml *if_ctx; 1752 Aml *else_ctx; 1753 1754 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1755 section 6.2.8.1 */ 1756 /* Note: we provide the same info as the PCI routing 1757 table of the Bochs BIOS */ 1758 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1759 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1760 aml_append(method, if_ctx); 1761 else_ctx = aml_else(); 1762 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1763 aml_append(method, else_ctx); 1764 } 1765 aml_append(pci0_scope, method); 1766 aml_append(sb_scope, pci0_scope); 1767 1768 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1769 aml_append(field, aml_named_field("PRQA", 8)); 1770 aml_append(field, aml_named_field("PRQB", 8)); 1771 aml_append(field, aml_named_field("PRQC", 8)); 1772 aml_append(field, aml_named_field("PRQD", 8)); 1773 aml_append(field, aml_reserved_field(0x20)); 1774 aml_append(field, aml_named_field("PRQE", 8)); 1775 aml_append(field, aml_named_field("PRQF", 8)); 1776 aml_append(field, aml_named_field("PRQG", 8)); 1777 aml_append(field, aml_named_field("PRQH", 8)); 1778 aml_append(sb_scope, field); 1779 1780 aml_append(sb_scope, build_irq_status_method()); 1781 aml_append(sb_scope, build_iqcr_method(false)); 1782 1783 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1784 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1785 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1786 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1787 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1788 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1789 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1790 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1791 1792 /* 1793 * TODO: UID probably shouldn't be the same for GSIx devices 1794 * but that's how it was in original ASL so keep it for now 1795 */ 1796 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10)); 1797 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11)); 1798 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12)); 1799 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13)); 1800 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14)); 1801 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15)); 1802 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16)); 1803 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17)); 1804 1805 aml_append(table, sb_scope); 1806 } 1807 1808 static void build_q35_isa_bridge(Aml *table) 1809 { 1810 Aml *dev; 1811 Aml *scope; 1812 Aml *field; 1813 1814 scope = aml_scope("_SB.PCI0"); 1815 dev = aml_device("ISA"); 1816 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1817 1818 /* ICH9 PCI to ISA irq remapping */ 1819 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1820 aml_int(0x60), 0x0C)); 1821 1822 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1823 aml_int(0x80), 0x02)); 1824 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1825 aml_append(field, aml_named_field("COMA", 3)); 1826 aml_append(field, aml_reserved_field(1)); 1827 aml_append(field, aml_named_field("COMB", 3)); 1828 aml_append(field, aml_reserved_field(1)); 1829 aml_append(field, aml_named_field("LPTD", 2)); 1830 aml_append(dev, field); 1831 1832 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1833 aml_int(0x82), 0x02)); 1834 /* enable bits */ 1835 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1836 aml_append(field, aml_named_field("CAEN", 1)); 1837 aml_append(field, aml_named_field("CBEN", 1)); 1838 aml_append(field, aml_named_field("LPEN", 1)); 1839 aml_append(dev, field); 1840 1841 aml_append(scope, dev); 1842 aml_append(table, scope); 1843 } 1844 1845 static void build_piix4_pm(Aml *table) 1846 { 1847 Aml *dev; 1848 Aml *scope; 1849 1850 scope = aml_scope("_SB.PCI0"); 1851 dev = aml_device("PX13"); 1852 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1853 1854 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1855 aml_int(0x00), 0xff)); 1856 aml_append(scope, dev); 1857 aml_append(table, scope); 1858 } 1859 1860 static void build_piix4_isa_bridge(Aml *table) 1861 { 1862 Aml *dev; 1863 Aml *scope; 1864 Aml *field; 1865 1866 scope = aml_scope("_SB.PCI0"); 1867 dev = aml_device("ISA"); 1868 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1869 1870 /* PIIX PCI to ISA irq remapping */ 1871 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1872 aml_int(0x60), 0x04)); 1873 /* enable bits */ 1874 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1875 /* Offset(0x5f),, 7, */ 1876 aml_append(field, aml_reserved_field(0x2f8)); 1877 aml_append(field, aml_reserved_field(7)); 1878 aml_append(field, aml_named_field("LPEN", 1)); 1879 /* Offset(0x67),, 3, */ 1880 aml_append(field, aml_reserved_field(0x38)); 1881 aml_append(field, aml_reserved_field(3)); 1882 aml_append(field, aml_named_field("CAEN", 1)); 1883 aml_append(field, aml_reserved_field(3)); 1884 aml_append(field, aml_named_field("CBEN", 1)); 1885 aml_append(dev, field); 1886 1887 aml_append(scope, dev); 1888 aml_append(table, scope); 1889 } 1890 1891 static void build_piix4_pci_hotplug(Aml *table) 1892 { 1893 Aml *scope; 1894 Aml *field; 1895 Aml *method; 1896 1897 scope = aml_scope("_SB.PCI0"); 1898 1899 aml_append(scope, 1900 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1901 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1902 aml_append(field, aml_named_field("PCIU", 32)); 1903 aml_append(field, aml_named_field("PCID", 32)); 1904 aml_append(scope, field); 1905 1906 aml_append(scope, 1907 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1908 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1909 aml_append(field, aml_named_field("B0EJ", 32)); 1910 aml_append(scope, field); 1911 1912 aml_append(scope, 1913 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1914 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1915 aml_append(field, aml_named_field("BNUM", 32)); 1916 aml_append(scope, field); 1917 1918 aml_append(scope, aml_mutex("BLCK", 0)); 1919 1920 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1921 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1922 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1923 aml_append(method, 1924 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1925 aml_append(method, aml_release(aml_name("BLCK"))); 1926 aml_append(method, aml_return(aml_int(0))); 1927 aml_append(scope, method); 1928 1929 aml_append(table, scope); 1930 } 1931 1932 static Aml *build_q35_osc_method(void) 1933 { 1934 Aml *if_ctx; 1935 Aml *if_ctx2; 1936 Aml *else_ctx; 1937 Aml *method; 1938 Aml *a_cwd1 = aml_name("CDW1"); 1939 Aml *a_ctrl = aml_name("CTRL"); 1940 1941 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1942 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1943 1944 if_ctx = aml_if(aml_equal( 1945 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1946 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1947 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1948 1949 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 1950 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1951 1952 /* 1953 * Always allow native PME, AER (no dependencies) 1954 * Never allow SHPC (no SHPC controller in this system) 1955 */ 1956 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1957 1958 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1959 /* Unknown revision */ 1960 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1961 aml_append(if_ctx, if_ctx2); 1962 1963 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1964 /* Capabilities bits were masked */ 1965 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1966 aml_append(if_ctx, if_ctx2); 1967 1968 /* Update DWORD3 in the buffer */ 1969 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1970 aml_append(method, if_ctx); 1971 1972 else_ctx = aml_else(); 1973 /* Unrecognized UUID */ 1974 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1975 aml_append(method, else_ctx); 1976 1977 aml_append(method, aml_return(aml_arg(3))); 1978 return method; 1979 } 1980 1981 static void 1982 build_dsdt(GArray *table_data, GArray *linker, 1983 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 1984 PcPciInfo *pci) 1985 { 1986 CrsRangeEntry *entry; 1987 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1988 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1989 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1990 MachineState *machine = MACHINE(qdev_get_machine()); 1991 PCMachineState *pcms = PC_MACHINE(machine); 1992 uint32_t nr_mem = machine->ram_slots; 1993 int root_bus_limit = 0xFF; 1994 PCIBus *bus = NULL; 1995 int i; 1996 1997 dsdt = init_aml_allocator(); 1998 1999 /* Reserve space for header */ 2000 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 2001 2002 build_dbg_aml(dsdt); 2003 if (misc->is_piix4) { 2004 sb_scope = aml_scope("_SB"); 2005 dev = aml_device("PCI0"); 2006 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2007 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2008 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2009 aml_append(sb_scope, dev); 2010 aml_append(dsdt, sb_scope); 2011 2012 build_hpet_aml(dsdt); 2013 build_piix4_pm(dsdt); 2014 build_piix4_isa_bridge(dsdt); 2015 build_isa_devices_aml(dsdt); 2016 build_piix4_pci_hotplug(dsdt); 2017 build_piix4_pci0_int(dsdt); 2018 } else { 2019 sb_scope = aml_scope("_SB"); 2020 aml_append(sb_scope, 2021 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c)); 2022 aml_append(sb_scope, 2023 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01)); 2024 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 2025 aml_append(field, aml_named_field("PCIB", 8)); 2026 aml_append(sb_scope, field); 2027 aml_append(dsdt, sb_scope); 2028 2029 sb_scope = aml_scope("_SB"); 2030 dev = aml_device("PCI0"); 2031 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 2032 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 2033 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2034 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2035 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 2036 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 2037 aml_append(dev, build_q35_osc_method()); 2038 aml_append(sb_scope, dev); 2039 aml_append(dsdt, sb_scope); 2040 2041 build_hpet_aml(dsdt); 2042 build_q35_isa_bridge(dsdt); 2043 build_isa_devices_aml(dsdt); 2044 build_q35_pci0_int(dsdt); 2045 } 2046 2047 build_cpu_hotplug_aml(dsdt); 2048 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, 2049 pm->mem_hp_io_len); 2050 2051 scope = aml_scope("_GPE"); 2052 { 2053 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 2054 2055 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); 2056 2057 if (misc->is_piix4) { 2058 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 2059 aml_append(method, 2060 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 2061 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 2062 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 2063 aml_append(scope, method); 2064 } else { 2065 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); 2066 } 2067 2068 method = aml_method("_E02", 0, AML_NOTSERIALIZED); 2069 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); 2070 aml_append(scope, method); 2071 2072 method = aml_method("_E03", 0, AML_NOTSERIALIZED); 2073 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); 2074 aml_append(scope, method); 2075 2076 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); 2077 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); 2078 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); 2079 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); 2080 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); 2081 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); 2082 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); 2083 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); 2084 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); 2085 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); 2086 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); 2087 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); 2088 } 2089 aml_append(dsdt, scope); 2090 2091 bus = PC_MACHINE(machine)->bus; 2092 if (bus) { 2093 QLIST_FOREACH(bus, &bus->child, sibling) { 2094 uint8_t bus_num = pci_bus_num(bus); 2095 uint8_t numa_node = pci_bus_numa_node(bus); 2096 2097 /* look only for expander root buses */ 2098 if (!pci_bus_is_root(bus)) { 2099 continue; 2100 } 2101 2102 if (bus_num < root_bus_limit) { 2103 root_bus_limit = bus_num - 1; 2104 } 2105 2106 scope = aml_scope("\\_SB"); 2107 dev = aml_device("PC%.02X", bus_num); 2108 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 2109 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2110 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 2111 2112 if (numa_node != NUMA_NODE_UNASSIGNED) { 2113 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 2114 } 2115 2116 aml_append(dev, build_prt(false)); 2117 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), 2118 io_ranges, mem_ranges); 2119 aml_append(dev, aml_name_decl("_CRS", crs)); 2120 aml_append(scope, dev); 2121 aml_append(dsdt, scope); 2122 } 2123 } 2124 2125 scope = aml_scope("\\_SB.PCI0"); 2126 /* build PCI0._CRS */ 2127 crs = aml_resource_template(); 2128 aml_append(crs, 2129 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 2130 0x0000, 0x0, root_bus_limit, 2131 0x0000, root_bus_limit + 1)); 2132 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2133 2134 aml_append(crs, 2135 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2136 AML_POS_DECODE, AML_ENTIRE_RANGE, 2137 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2138 2139 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); 2140 for (i = 0; i < io_ranges->len; i++) { 2141 entry = g_ptr_array_index(io_ranges, i); 2142 aml_append(crs, 2143 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2144 AML_POS_DECODE, AML_ENTIRE_RANGE, 2145 0x0000, entry->base, entry->limit, 2146 0x0000, entry->limit - entry->base + 1)); 2147 } 2148 2149 aml_append(crs, 2150 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2151 AML_CACHEABLE, AML_READ_WRITE, 2152 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2153 2154 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); 2155 for (i = 0; i < mem_ranges->len; i++) { 2156 entry = g_ptr_array_index(mem_ranges, i); 2157 aml_append(crs, 2158 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2159 AML_NON_CACHEABLE, AML_READ_WRITE, 2160 0, entry->base, entry->limit, 2161 0, entry->limit - entry->base + 1)); 2162 } 2163 2164 if (pci->w64.begin) { 2165 aml_append(crs, 2166 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2167 AML_CACHEABLE, AML_READ_WRITE, 2168 0, pci->w64.begin, pci->w64.end - 1, 0, 2169 pci->w64.end - pci->w64.begin)); 2170 } 2171 aml_append(scope, aml_name_decl("_CRS", crs)); 2172 2173 /* reserve GPE0 block resources */ 2174 dev = aml_device("GPE0"); 2175 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2176 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2177 /* device present, functioning, decoding, not shown in UI */ 2178 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2179 crs = aml_resource_template(); 2180 aml_append(crs, 2181 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2182 ); 2183 aml_append(dev, aml_name_decl("_CRS", crs)); 2184 aml_append(scope, dev); 2185 2186 g_ptr_array_free(io_ranges, true); 2187 g_ptr_array_free(mem_ranges, true); 2188 2189 /* reserve PCIHP resources */ 2190 if (pm->pcihp_io_len) { 2191 dev = aml_device("PHPR"); 2192 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2193 aml_append(dev, 2194 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2195 /* device present, functioning, decoding, not shown in UI */ 2196 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2197 crs = aml_resource_template(); 2198 aml_append(crs, 2199 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2200 pm->pcihp_io_len) 2201 ); 2202 aml_append(dev, aml_name_decl("_CRS", crs)); 2203 aml_append(scope, dev); 2204 } 2205 aml_append(dsdt, scope); 2206 2207 /* create S3_ / S4_ / S5_ packages if necessary */ 2208 scope = aml_scope("\\"); 2209 if (!pm->s3_disabled) { 2210 pkg = aml_package(4); 2211 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2212 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2213 aml_append(pkg, aml_int(0)); /* reserved */ 2214 aml_append(pkg, aml_int(0)); /* reserved */ 2215 aml_append(scope, aml_name_decl("_S3", pkg)); 2216 } 2217 2218 if (!pm->s4_disabled) { 2219 pkg = aml_package(4); 2220 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2221 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2222 aml_append(pkg, aml_int(pm->s4_val)); 2223 aml_append(pkg, aml_int(0)); /* reserved */ 2224 aml_append(pkg, aml_int(0)); /* reserved */ 2225 aml_append(scope, aml_name_decl("_S4", pkg)); 2226 } 2227 2228 pkg = aml_package(4); 2229 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2230 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2231 aml_append(pkg, aml_int(0)); /* reserved */ 2232 aml_append(pkg, aml_int(0)); /* reserved */ 2233 aml_append(scope, aml_name_decl("_S5", pkg)); 2234 aml_append(dsdt, scope); 2235 2236 /* create fw_cfg node, unconditionally */ 2237 { 2238 /* when using port i/o, the 8-bit data register *always* overlaps 2239 * with half of the 16-bit control register. Hence, the total size 2240 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2241 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2242 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2243 "dma_enabled", NULL) ? 2244 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2245 FW_CFG_CTL_SIZE; 2246 2247 scope = aml_scope("\\_SB.PCI0"); 2248 dev = aml_device("FWCF"); 2249 2250 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2251 2252 /* device present, functioning, decoding, not shown in UI */ 2253 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2254 2255 crs = aml_resource_template(); 2256 aml_append(crs, 2257 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2258 ); 2259 aml_append(dev, aml_name_decl("_CRS", crs)); 2260 2261 aml_append(scope, dev); 2262 aml_append(dsdt, scope); 2263 } 2264 2265 if (misc->applesmc_io_base) { 2266 scope = aml_scope("\\_SB.PCI0.ISA"); 2267 dev = aml_device("SMC"); 2268 2269 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2270 /* device present, functioning, decoding, not shown in UI */ 2271 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2272 2273 crs = aml_resource_template(); 2274 aml_append(crs, 2275 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2276 0x01, APPLESMC_MAX_DATA_LENGTH) 2277 ); 2278 aml_append(crs, aml_irq_no_flags(6)); 2279 aml_append(dev, aml_name_decl("_CRS", crs)); 2280 2281 aml_append(scope, dev); 2282 aml_append(dsdt, scope); 2283 } 2284 2285 if (misc->pvpanic_port) { 2286 scope = aml_scope("\\_SB.PCI0.ISA"); 2287 2288 dev = aml_device("PEVT"); 2289 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2290 2291 crs = aml_resource_template(); 2292 aml_append(crs, 2293 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2294 ); 2295 aml_append(dev, aml_name_decl("_CRS", crs)); 2296 2297 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2298 aml_int(misc->pvpanic_port), 1)); 2299 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2300 aml_append(field, aml_named_field("PEPT", 8)); 2301 aml_append(dev, field); 2302 2303 /* device present, functioning, decoding, shown in UI */ 2304 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2305 2306 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2307 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2308 aml_append(method, aml_return(aml_local(0))); 2309 aml_append(dev, method); 2310 2311 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2312 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2313 aml_append(dev, method); 2314 2315 aml_append(scope, dev); 2316 aml_append(dsdt, scope); 2317 } 2318 2319 sb_scope = aml_scope("\\_SB"); 2320 { 2321 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm); 2322 2323 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, 2324 pm->mem_hp_io_len); 2325 2326 { 2327 Object *pci_host; 2328 PCIBus *bus = NULL; 2329 2330 pci_host = acpi_get_i386_pci_host(); 2331 if (pci_host) { 2332 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2333 } 2334 2335 if (bus) { 2336 Aml *scope = aml_scope("PCI0"); 2337 /* Scan all PCI buses. Generate tables to support hotplug. */ 2338 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2339 2340 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2341 dev = aml_device("ISA.TPM"); 2342 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2343 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2344 crs = aml_resource_template(); 2345 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2346 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2347 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); 2348 aml_append(dev, aml_name_decl("_CRS", crs)); 2349 aml_append(scope, dev); 2350 } 2351 2352 aml_append(sb_scope, scope); 2353 } 2354 } 2355 aml_append(dsdt, sb_scope); 2356 } 2357 2358 /* copy AML table into ACPI tables blob and patch header there */ 2359 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2360 build_header(linker, table_data, 2361 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2362 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2363 free_aml_allocator(); 2364 } 2365 2366 static void 2367 build_hpet(GArray *table_data, GArray *linker) 2368 { 2369 Acpi20Hpet *hpet; 2370 2371 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2372 /* Note timer_block_id value must be kept in sync with value advertised by 2373 * emulated hpet 2374 */ 2375 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2376 hpet->addr.address = cpu_to_le64(HPET_BASE); 2377 build_header(linker, table_data, 2378 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2379 } 2380 2381 static void 2382 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 2383 { 2384 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2385 uint64_t log_area_start_address = acpi_data_len(tcpalog); 2386 2387 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2388 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2389 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 2390 2391 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 2392 false /* high memory */); 2393 2394 /* log area start address to be filled by Guest linker */ 2395 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2396 ACPI_BUILD_TPMLOG_FILE, 2397 table_data, &tcpa->log_area_start_address, 2398 sizeof(tcpa->log_area_start_address)); 2399 2400 build_header(linker, table_data, 2401 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2402 2403 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2404 } 2405 2406 static void 2407 build_tpm2(GArray *table_data, GArray *linker) 2408 { 2409 Acpi20TPM2 *tpm2_ptr; 2410 2411 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2412 2413 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2414 tpm2_ptr->control_area_address = cpu_to_le64(0); 2415 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2416 2417 build_header(linker, table_data, 2418 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2419 } 2420 2421 typedef enum { 2422 MEM_AFFINITY_NOFLAGS = 0, 2423 MEM_AFFINITY_ENABLED = (1 << 0), 2424 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 2425 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 2426 } MemoryAffinityFlags; 2427 2428 static void 2429 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 2430 uint64_t len, int node, MemoryAffinityFlags flags) 2431 { 2432 numamem->type = ACPI_SRAT_MEMORY; 2433 numamem->length = sizeof(*numamem); 2434 memset(numamem->proximity, 0, 4); 2435 numamem->proximity[0] = node; 2436 numamem->flags = cpu_to_le32(flags); 2437 numamem->base_addr = cpu_to_le64(base); 2438 numamem->range_length = cpu_to_le64(len); 2439 } 2440 2441 static void 2442 build_srat(GArray *table_data, GArray *linker) 2443 { 2444 AcpiSystemResourceAffinityTable *srat; 2445 AcpiSratProcessorAffinity *core; 2446 AcpiSratMemoryAffinity *numamem; 2447 2448 int i; 2449 uint64_t curnode; 2450 int srat_start, numa_start, slots; 2451 uint64_t mem_len, mem_base, next_base; 2452 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2453 ram_addr_t hotplugabble_address_space_size = 2454 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2455 NULL); 2456 2457 srat_start = table_data->len; 2458 2459 srat = acpi_data_push(table_data, sizeof *srat); 2460 srat->reserved1 = cpu_to_le32(1); 2461 core = (void *)(srat + 1); 2462 2463 for (i = 0; i < pcms->apic_id_limit; ++i) { 2464 core = acpi_data_push(table_data, sizeof *core); 2465 core->type = ACPI_SRAT_PROCESSOR; 2466 core->length = sizeof(*core); 2467 core->local_apic_id = i; 2468 curnode = pcms->node_cpu[i]; 2469 core->proximity_lo = curnode; 2470 memset(core->proximity_hi, 0, 3); 2471 core->local_sapic_eid = 0; 2472 core->flags = cpu_to_le32(1); 2473 } 2474 2475 2476 /* the memory map is a bit tricky, it contains at least one hole 2477 * from 640k-1M and possibly another one from 3.5G-4G. 2478 */ 2479 next_base = 0; 2480 numa_start = table_data->len; 2481 2482 numamem = acpi_data_push(table_data, sizeof *numamem); 2483 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 2484 next_base = 1024 * 1024; 2485 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2486 mem_base = next_base; 2487 mem_len = pcms->node_mem[i - 1]; 2488 if (i == 1) { 2489 mem_len -= 1024 * 1024; 2490 } 2491 next_base = mem_base + mem_len; 2492 2493 /* Cut out the ACPI_PCI hole */ 2494 if (mem_base <= pcms->below_4g_mem_size && 2495 next_base > pcms->below_4g_mem_size) { 2496 mem_len -= next_base - pcms->below_4g_mem_size; 2497 if (mem_len > 0) { 2498 numamem = acpi_data_push(table_data, sizeof *numamem); 2499 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2500 MEM_AFFINITY_ENABLED); 2501 } 2502 mem_base = 1ULL << 32; 2503 mem_len = next_base - pcms->below_4g_mem_size; 2504 next_base += (1ULL << 32) - pcms->below_4g_mem_size; 2505 } 2506 numamem = acpi_data_push(table_data, sizeof *numamem); 2507 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2508 MEM_AFFINITY_ENABLED); 2509 } 2510 slots = (table_data->len - numa_start) / sizeof *numamem; 2511 for (; slots < pcms->numa_nodes + 2; slots++) { 2512 numamem = acpi_data_push(table_data, sizeof *numamem); 2513 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2514 } 2515 2516 /* 2517 * Entry is required for Windows to enable memory hotplug in OS. 2518 * Memory devices may override proximity set by this entry, 2519 * providing _PXM method if necessary. 2520 */ 2521 if (hotplugabble_address_space_size) { 2522 numamem = acpi_data_push(table_data, sizeof *numamem); 2523 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, 2524 hotplugabble_address_space_size, 0, 2525 MEM_AFFINITY_HOTPLUGGABLE | 2526 MEM_AFFINITY_ENABLED); 2527 } 2528 2529 build_header(linker, table_data, 2530 (void *)(table_data->data + srat_start), 2531 "SRAT", 2532 table_data->len - srat_start, 1, NULL, NULL); 2533 } 2534 2535 static void 2536 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 2537 { 2538 AcpiTableMcfg *mcfg; 2539 const char *sig; 2540 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2541 2542 mcfg = acpi_data_push(table_data, len); 2543 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2544 /* Only a single allocation so no need to play with segments */ 2545 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2546 mcfg->allocation[0].start_bus_number = 0; 2547 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2548 2549 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2550 * To avoid table size changes (which create migration issues), 2551 * always create the table even if there are no allocations, 2552 * but set the signature to a reserved value in this case. 2553 * ACPI spec requires OSPMs to ignore such tables. 2554 */ 2555 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2556 /* Reserved signature: ignored by OSPM */ 2557 sig = "QEMU"; 2558 } else { 2559 sig = "MCFG"; 2560 } 2561 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2562 } 2563 2564 static void 2565 build_dmar_q35(GArray *table_data, GArray *linker) 2566 { 2567 int dmar_start = table_data->len; 2568 2569 AcpiTableDmar *dmar; 2570 AcpiDmarHardwareUnit *drhd; 2571 2572 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2573 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2574 dmar->flags = 0; /* No intr_remap for now */ 2575 2576 /* DMAR Remapping Hardware Unit Definition structure */ 2577 drhd = acpi_data_push(table_data, sizeof(*drhd)); 2578 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2579 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 2580 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2581 drhd->pci_segment = cpu_to_le16(0); 2582 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2583 2584 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2585 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2586 } 2587 2588 static GArray * 2589 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 2590 { 2591 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2592 2593 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 2594 true /* fseg memory */); 2595 2596 memcpy(&rsdp->signature, "RSD PTR ", 8); 2597 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2598 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 2599 /* Address to be filled by Guest linker */ 2600 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 2601 ACPI_BUILD_TABLE_FILE, 2602 rsdp_table, &rsdp->rsdt_physical_address, 2603 sizeof rsdp->rsdt_physical_address); 2604 rsdp->checksum = 0; 2605 /* Checksum to be filled by Guest linker */ 2606 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2607 rsdp_table, rsdp, sizeof *rsdp, 2608 &rsdp->checksum); 2609 2610 return rsdp_table; 2611 } 2612 2613 typedef 2614 struct AcpiBuildState { 2615 /* Copy of table in RAM (for patching). */ 2616 MemoryRegion *table_mr; 2617 /* Is table patched? */ 2618 uint8_t patched; 2619 void *rsdp; 2620 MemoryRegion *rsdp_mr; 2621 MemoryRegion *linker_mr; 2622 } AcpiBuildState; 2623 2624 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2625 { 2626 Object *pci_host; 2627 QObject *o; 2628 2629 pci_host = acpi_get_i386_pci_host(); 2630 g_assert(pci_host); 2631 2632 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2633 if (!o) { 2634 return false; 2635 } 2636 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 2637 qobject_decref(o); 2638 2639 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2640 assert(o); 2641 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 2642 qobject_decref(o); 2643 return true; 2644 } 2645 2646 static bool acpi_has_iommu(void) 2647 { 2648 bool ambiguous; 2649 Object *intel_iommu; 2650 2651 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 2652 &ambiguous); 2653 return intel_iommu && !ambiguous; 2654 } 2655 2656 static bool acpi_has_nvdimm(void) 2657 { 2658 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2659 2660 return pcms->nvdimm; 2661 } 2662 2663 static 2664 void acpi_build(AcpiBuildTables *tables) 2665 { 2666 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2667 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2668 GArray *table_offsets; 2669 unsigned facs, dsdt, rsdt, fadt; 2670 AcpiCpuInfo cpu; 2671 AcpiPmInfo pm; 2672 AcpiMiscInfo misc; 2673 AcpiMcfgInfo mcfg; 2674 PcPciInfo pci; 2675 uint8_t *u; 2676 size_t aml_len = 0; 2677 GArray *tables_blob = tables->table_data; 2678 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2679 2680 acpi_get_cpu_info(&cpu); 2681 acpi_get_pm_info(&pm); 2682 acpi_get_misc_info(&misc); 2683 acpi_get_pci_info(&pci); 2684 acpi_get_slic_oem(&slic_oem); 2685 2686 table_offsets = g_array_new(false, true /* clear */, 2687 sizeof(uint32_t)); 2688 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2689 2690 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 2691 64 /* Ensure FACS is aligned */, 2692 false /* high memory */); 2693 2694 /* 2695 * FACS is pointed to by FADT. 2696 * We place it first since it's the only table that has alignment 2697 * requirements. 2698 */ 2699 facs = tables_blob->len; 2700 build_facs(tables_blob, tables->linker); 2701 2702 /* DSDT is pointed to by FADT */ 2703 dsdt = tables_blob->len; 2704 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci); 2705 2706 /* Count the size of the DSDT and SSDT, we will need it for legacy 2707 * sizing of ACPI tables. 2708 */ 2709 aml_len += tables_blob->len - dsdt; 2710 2711 /* ACPI tables pointed to by RSDT */ 2712 fadt = tables_blob->len; 2713 acpi_add_table(table_offsets, tables_blob); 2714 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt, 2715 slic_oem.id, slic_oem.table_id); 2716 aml_len += tables_blob->len - fadt; 2717 2718 acpi_add_table(table_offsets, tables_blob); 2719 build_madt(tables_blob, tables->linker, &cpu); 2720 2721 if (misc.has_hpet) { 2722 acpi_add_table(table_offsets, tables_blob); 2723 build_hpet(tables_blob, tables->linker); 2724 } 2725 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2726 acpi_add_table(table_offsets, tables_blob); 2727 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2728 2729 if (misc.tpm_version == TPM_VERSION_2_0) { 2730 acpi_add_table(table_offsets, tables_blob); 2731 build_tpm2(tables_blob, tables->linker); 2732 } 2733 } 2734 if (pcms->numa_nodes) { 2735 acpi_add_table(table_offsets, tables_blob); 2736 build_srat(tables_blob, tables->linker); 2737 } 2738 if (acpi_get_mcfg(&mcfg)) { 2739 acpi_add_table(table_offsets, tables_blob); 2740 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2741 } 2742 if (acpi_has_iommu()) { 2743 acpi_add_table(table_offsets, tables_blob); 2744 build_dmar_q35(tables_blob, tables->linker); 2745 } 2746 2747 if (acpi_has_nvdimm()) { 2748 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); 2749 } 2750 2751 /* Add tables supplied by user (if any) */ 2752 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2753 unsigned len = acpi_table_len(u); 2754 2755 acpi_add_table(table_offsets, tables_blob); 2756 g_array_append_vals(tables_blob, u, len); 2757 } 2758 2759 /* RSDT is pointed to by RSDP */ 2760 rsdt = tables_blob->len; 2761 build_rsdt(tables_blob, tables->linker, table_offsets, 2762 slic_oem.id, slic_oem.table_id); 2763 2764 /* RSDP is in FSEG memory, so allocate it separately */ 2765 build_rsdp(tables->rsdp, tables->linker, rsdt); 2766 2767 /* We'll expose it all to Guest so we want to reduce 2768 * chance of size changes. 2769 * 2770 * We used to align the tables to 4k, but of course this would 2771 * too simple to be enough. 4k turned out to be too small an 2772 * alignment very soon, and in fact it is almost impossible to 2773 * keep the table size stable for all (max_cpus, max_memory_slots) 2774 * combinations. So the table size is always 64k for pc-i440fx-2.1 2775 * and we give an error if the table grows beyond that limit. 2776 * 2777 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2778 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2779 * than 2.0 and we can always pad the smaller tables with zeros. We can 2780 * then use the exact size of the 2.0 tables. 2781 * 2782 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2783 */ 2784 if (pcmc->legacy_acpi_table_size) { 2785 /* Subtracting aml_len gives the size of fixed tables. Then add the 2786 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2787 */ 2788 int legacy_aml_len = 2789 pcmc->legacy_acpi_table_size + 2790 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 2791 int legacy_table_size = 2792 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2793 ACPI_BUILD_ALIGN_SIZE); 2794 if (tables_blob->len > legacy_table_size) { 2795 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2796 error_report("Warning: migration may not work."); 2797 } 2798 g_array_set_size(tables_blob, legacy_table_size); 2799 } else { 2800 /* Make sure we have a buffer in case we need to resize the tables. */ 2801 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2802 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2803 error_report("Warning: ACPI tables are larger than 64k."); 2804 error_report("Warning: migration may not work."); 2805 error_report("Warning: please remove CPUs, NUMA nodes, " 2806 "memory slots or PCI bridges."); 2807 } 2808 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2809 } 2810 2811 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 2812 2813 /* Cleanup memory that's no longer used. */ 2814 g_array_free(table_offsets, true); 2815 } 2816 2817 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2818 { 2819 uint32_t size = acpi_data_len(data); 2820 2821 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2822 memory_region_ram_resize(mr, size, &error_abort); 2823 2824 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2825 memory_region_set_dirty(mr, 0, size); 2826 } 2827 2828 static void acpi_build_update(void *build_opaque) 2829 { 2830 AcpiBuildState *build_state = build_opaque; 2831 AcpiBuildTables tables; 2832 2833 /* No state to update or already patched? Nothing to do. */ 2834 if (!build_state || build_state->patched) { 2835 return; 2836 } 2837 build_state->patched = 1; 2838 2839 acpi_build_tables_init(&tables); 2840 2841 acpi_build(&tables); 2842 2843 acpi_ram_update(build_state->table_mr, tables.table_data); 2844 2845 if (build_state->rsdp) { 2846 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2847 } else { 2848 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2849 } 2850 2851 acpi_ram_update(build_state->linker_mr, tables.linker); 2852 acpi_build_tables_cleanup(&tables, true); 2853 } 2854 2855 static void acpi_build_reset(void *build_opaque) 2856 { 2857 AcpiBuildState *build_state = build_opaque; 2858 build_state->patched = 0; 2859 } 2860 2861 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2862 GArray *blob, const char *name, 2863 uint64_t max_size) 2864 { 2865 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2866 name, acpi_build_update, build_state); 2867 } 2868 2869 static const VMStateDescription vmstate_acpi_build = { 2870 .name = "acpi_build", 2871 .version_id = 1, 2872 .minimum_version_id = 1, 2873 .fields = (VMStateField[]) { 2874 VMSTATE_UINT8(patched, AcpiBuildState), 2875 VMSTATE_END_OF_LIST() 2876 }, 2877 }; 2878 2879 void acpi_setup(void) 2880 { 2881 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2882 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2883 AcpiBuildTables tables; 2884 AcpiBuildState *build_state; 2885 2886 if (!pcms->fw_cfg) { 2887 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2888 return; 2889 } 2890 2891 if (!pcmc->has_acpi_build) { 2892 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2893 return; 2894 } 2895 2896 if (!acpi_enabled) { 2897 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2898 return; 2899 } 2900 2901 build_state = g_malloc0(sizeof *build_state); 2902 2903 acpi_set_pci_info(); 2904 2905 acpi_build_tables_init(&tables); 2906 acpi_build(&tables); 2907 2908 /* Now expose it all to Guest */ 2909 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2910 ACPI_BUILD_TABLE_FILE, 2911 ACPI_BUILD_TABLE_MAX_SIZE); 2912 assert(build_state->table_mr != NULL); 2913 2914 build_state->linker_mr = 2915 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 2916 2917 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2918 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2919 2920 if (!pcmc->rsdp_in_ram) { 2921 /* 2922 * Keep for compatibility with old machine types. 2923 * Though RSDP is small, its contents isn't immutable, so 2924 * we'll update it along with the rest of tables on guest access. 2925 */ 2926 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2927 2928 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2929 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2930 acpi_build_update, build_state, 2931 build_state->rsdp, rsdp_size); 2932 build_state->rsdp_mr = NULL; 2933 } else { 2934 build_state->rsdp = NULL; 2935 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2936 ACPI_BUILD_RSDP_FILE, 0); 2937 } 2938 2939 qemu_register_reset(acpi_build_reset, build_state); 2940 acpi_build_reset(build_state); 2941 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2942 2943 /* Cleanup tables but don't free the memory: we track it 2944 * in build_state. 2945 */ 2946 acpi_build_tables_cleanup(&tables, false); 2947 } 2948