1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 80 #include CONFIG_DEVICES 81 82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 84 * a little bit, there should be plenty of free space since the DSDT 85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 86 */ 87 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * comforms to ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static Object *object_resolve_type_unambiguous(const char *typename) 196 { 197 bool ambig; 198 Object *o = object_resolve_path_type("", typename, &ambig); 199 200 if (ambig || !o) { 201 return NULL; 202 } 203 return o; 204 } 205 206 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 207 { 208 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 209 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 210 Object *obj = piix ? piix : lpc; 211 QObject *o; 212 pm->cpu_hp_io_base = 0; 213 pm->pcihp_io_base = 0; 214 pm->pcihp_io_len = 0; 215 pm->smi_on_cpuhp = false; 216 pm->smi_on_cpu_unplug = false; 217 218 assert(obj); 219 init_common_fadt_data(machine, obj, &pm->fadt); 220 if (piix) { 221 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 222 pm->fadt.rev = 1; 223 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 224 } 225 if (lpc) { 226 uint64_t smi_features = object_property_get_uint(lpc, 227 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 228 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 229 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 230 pm->fadt.reset_reg = r; 231 pm->fadt.reset_val = 0xf; 232 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 233 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 234 pm->smi_on_cpuhp = 235 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 236 pm->smi_on_cpu_unplug = 237 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 238 } 239 pm->pcihp_io_base = 240 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 241 pm->pcihp_io_len = 242 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 243 244 /* The above need not be conditional on machine type because the reset port 245 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 246 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 247 248 /* Fill in optional s3/s4 related properties */ 249 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 250 if (o) { 251 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 252 } else { 253 pm->s3_disabled = false; 254 } 255 qobject_unref(o); 256 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 257 if (o) { 258 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 259 } else { 260 pm->s4_disabled = false; 261 } 262 qobject_unref(o); 263 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 264 if (o) { 265 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 266 } else { 267 pm->s4_val = false; 268 } 269 qobject_unref(o); 270 271 pm->pcihp_bridge_en = 272 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 273 NULL); 274 pm->pcihp_root_en = 275 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 276 NULL); 277 } 278 279 static void acpi_get_misc_info(AcpiMiscInfo *info) 280 { 281 info->has_hpet = hpet_find(); 282 #ifdef CONFIG_TPM 283 info->tpm_version = tpm_get_version(tpm_find()); 284 #endif 285 } 286 287 /* 288 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 289 * On i386 arch we only have two pci hosts, so we can look only for them. 290 */ 291 Object *acpi_get_i386_pci_host(void) 292 { 293 PCIHostState *host; 294 295 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 296 if (!host) { 297 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 298 } 299 300 return OBJECT(host); 301 } 302 303 static void acpi_get_pci_holes(Range *hole, Range *hole64) 304 { 305 Object *pci_host; 306 307 pci_host = acpi_get_i386_pci_host(); 308 309 if (!pci_host) { 310 return; 311 } 312 313 range_set_bounds1(hole, 314 object_property_get_uint(pci_host, 315 PCI_HOST_PROP_PCI_HOLE_START, 316 NULL), 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE_END, 319 NULL)); 320 range_set_bounds1(hole64, 321 object_property_get_uint(pci_host, 322 PCI_HOST_PROP_PCI_HOLE64_START, 323 NULL), 324 object_property_get_uint(pci_host, 325 PCI_HOST_PROP_PCI_HOLE64_END, 326 NULL)); 327 } 328 329 static void acpi_align_size(GArray *blob, unsigned align) 330 { 331 /* Align size to multiple of given size. This reduces the chance 332 * we need to change size in the future (breaking cross version migration). 333 */ 334 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 335 } 336 337 /* 338 * ACPI spec 1.0b, 339 * 5.2.6 Firmware ACPI Control Structure 340 */ 341 static void 342 build_facs(GArray *table_data) 343 { 344 const char *sig = "FACS"; 345 const uint8_t reserved[40] = {}; 346 347 g_array_append_vals(table_data, sig, 4); /* Signature */ 348 build_append_int_noprefix(table_data, 64, 4); /* Length */ 349 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 350 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 351 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 352 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 353 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 354 } 355 356 Aml *aml_pci_device_dsm(void) 357 { 358 Aml *method; 359 360 method = aml_method("_DSM", 4, AML_SERIALIZED); 361 { 362 Aml *params = aml_local(0); 363 Aml *pkg = aml_package(2); 364 aml_append(pkg, aml_name("BSEL")); 365 aml_append(pkg, aml_name("ASUN")); 366 aml_append(method, aml_store(pkg, params)); 367 aml_append(method, 368 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 369 aml_arg(2), aml_arg(3), params)) 370 ); 371 } 372 return method; 373 } 374 375 static void build_append_pcihp_notify_entry(Aml *method, int slot) 376 { 377 Aml *if_ctx; 378 int32_t devfn = PCI_DEVFN(slot, 0); 379 380 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 381 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 382 aml_append(method, if_ctx); 383 } 384 385 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 386 { 387 const PCIDevice *pdev = bus->devices[devfn]; 388 389 if (PCI_FUNC(devfn)) { 390 if (IS_PCI_BRIDGE(pdev)) { 391 /* 392 * Ignore only hotplugged PCI bridges on !0 functions, but 393 * allow describing cold plugged bridges on all functions 394 */ 395 if (DEVICE(pdev)->hotplugged) { 396 return true; 397 } 398 } else if (!get_dev_aml_func(DEVICE(pdev))) { 399 /* 400 * Ignore all other devices on !0 functions unless they 401 * have AML description (i.e have get_dev_aml_func() != 0) 402 */ 403 return true; 404 } 405 } 406 return false; 407 } 408 409 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 410 { 411 PCIDevice *pdev = bus->devices[devfn]; 412 if (pdev) { 413 return is_devfn_ignored_generic(devfn, bus) || 414 !DEVICE_GET_CLASS(pdev)->hotpluggable || 415 /* Cold plugged bridges aren't themselves hot-pluggable */ 416 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 417 } else { /* non populated slots */ 418 /* 419 * hotplug is supported only for non-multifunction device 420 * so generate device description only for function 0 421 */ 422 if (PCI_FUNC(devfn) || 423 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 424 return true; 425 } 426 } 427 return false; 428 } 429 430 static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus, 431 QObject *bsel) 432 { 433 int devfn; 434 Aml *dev, *notify_method = NULL, *method; 435 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 436 437 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 438 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 439 440 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 441 int slot = PCI_SLOT(devfn); 442 int adr = slot << 16 | PCI_FUNC(devfn); 443 444 if (is_devfn_ignored_hotplug(devfn, bus)) { 445 continue; 446 } 447 448 if (bus->devices[devfn]) { 449 dev = aml_scope("S%.02X", devfn); 450 } else { 451 dev = aml_device("S%.02X", devfn); 452 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 453 } 454 455 /* 456 * Can't declare _SUN here for every device as it changes 'slot' 457 * enumeration order in linux kernel, so use another variable for it 458 */ 459 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 460 aml_append(dev, aml_pci_device_dsm()); 461 462 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 463 /* add _EJ0 to make slot hotpluggable */ 464 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 465 aml_append(method, 466 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 467 ); 468 aml_append(dev, method); 469 470 build_append_pcihp_notify_entry(notify_method, slot); 471 472 /* device descriptor has been composed, add it into parent context */ 473 aml_append(parent_scope, dev); 474 } 475 aml_append(parent_scope, notify_method); 476 } 477 478 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 479 { 480 QObject *bsel; 481 int devfn; 482 Aml *dev; 483 484 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 485 486 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 487 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 488 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 489 PCIDevice *pdev = bus->devices[devfn]; 490 491 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 492 continue; 493 } 494 495 /* start to compose PCI device descriptor */ 496 dev = aml_device("S%.02X", devfn); 497 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 498 499 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 500 501 /* device descriptor has been composed, add it into parent context */ 502 aml_append(parent_scope, dev); 503 } 504 505 if (bsel) { 506 build_append_pcihp_slots(parent_scope, bus, bsel); 507 } 508 509 qobject_unref(bsel); 510 } 511 512 static bool build_append_notfication_callback(Aml *parent_scope, 513 const PCIBus *bus) 514 { 515 Aml *method; 516 PCIBus *sec; 517 QObject *bsel; 518 int nr_notifiers = 0; 519 520 QLIST_FOREACH(sec, &bus->child, sibling) { 521 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 522 if (pci_bus_is_root(sec) || 523 !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) { 524 continue; 525 } 526 nr_notifiers = nr_notifiers + 527 build_append_notfication_callback(br_scope, sec); 528 aml_append(parent_scope, br_scope); 529 } 530 531 /* 532 * Append PCNT method to notify about events on local and child buses. 533 * ps: hostbridge might not have hotplug (bsel) enabled but might have 534 * child bridges that do have bsel. 535 */ 536 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 537 538 /* If bus supports hotplug select it and notify about local events */ 539 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 540 if (bsel) { 541 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 542 543 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 544 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 545 aml_int(1))); /* Device Check */ 546 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 547 aml_int(3))); /* Eject Request */ 548 nr_notifiers++; 549 } 550 551 /* Notify about child bus events in any case */ 552 QLIST_FOREACH(sec, &bus->child, sibling) { 553 if (pci_bus_is_root(sec) || 554 !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) { 555 continue; 556 } 557 558 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 559 } 560 561 aml_append(parent_scope, method); 562 qobject_unref(bsel); 563 return !!nr_notifiers; 564 } 565 566 static Aml *aml_pci_pdsm(void) 567 { 568 Aml *method, *UUID, *ifctx, *ifctx1; 569 Aml *ret = aml_local(0); 570 Aml *caps = aml_local(1); 571 Aml *acpi_index = aml_local(2); 572 Aml *zero = aml_int(0); 573 Aml *one = aml_int(1); 574 Aml *func = aml_arg(2); 575 Aml *rev = aml_arg(1); 576 Aml *params = aml_arg(4); 577 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 578 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 579 580 method = aml_method("PDSM", 5, AML_SERIALIZED); 581 582 /* get supported functions */ 583 ifctx = aml_if(aml_equal(func, zero)); 584 { 585 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 586 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); 587 aml_append(ifctx, aml_store(zero, caps)); 588 589 /* 590 * PCI Firmware Specification 3.1 591 * 4.6. _DSM Definitions for PCI 592 */ 593 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 594 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 595 { 596 /* call is for unsupported UUID, bail out */ 597 aml_append(ifctx1, aml_return(ret)); 598 } 599 aml_append(ifctx, ifctx1); 600 601 ifctx1 = aml_if(aml_lless(rev, aml_int(2))); 602 { 603 /* call is for unsupported REV, bail out */ 604 aml_append(ifctx1, aml_return(ret)); 605 } 606 aml_append(ifctx, ifctx1); 607 608 aml_append(ifctx, 609 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 610 /* 611 * advertise function 7 if device has acpi-index 612 * acpi_index values: 613 * 0: not present (default value) 614 * FFFFFFFF: not supported (old QEMU without PIDX reg) 615 * other: device's acpi-index 616 */ 617 ifctx1 = aml_if(aml_lnot( 618 aml_or(aml_equal(acpi_index, zero), 619 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 620 )); 621 { 622 /* have supported functions */ 623 aml_append(ifctx1, aml_or(caps, one, caps)); 624 /* support for function 7 */ 625 aml_append(ifctx1, 626 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 627 } 628 aml_append(ifctx, ifctx1); 629 630 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 631 aml_append(ifctx, aml_return(ret)); 632 } 633 aml_append(method, ifctx); 634 635 /* handle specific functions requests */ 636 /* 637 * PCI Firmware Specification 3.1 638 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 639 * Operating Systems 640 */ 641 ifctx = aml_if(aml_equal(func, aml_int(7))); 642 { 643 Aml *pkg = aml_package(2); 644 645 aml_append(pkg, zero); 646 /* 647 * optional, if not impl. should return null string 648 */ 649 aml_append(pkg, aml_string("%s", "")); 650 aml_append(ifctx, aml_store(pkg, ret)); 651 652 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 653 /* 654 * update acpi-index to actual value 655 */ 656 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 657 aml_append(ifctx, aml_return(ret)); 658 } 659 660 aml_append(method, ifctx); 661 return method; 662 } 663 664 /** 665 * build_prt_entry: 666 * @link_name: link name for PCI route entry 667 * 668 * build AML package containing a PCI route entry for @link_name 669 */ 670 static Aml *build_prt_entry(const char *link_name) 671 { 672 Aml *a_zero = aml_int(0); 673 Aml *pkg = aml_package(4); 674 aml_append(pkg, a_zero); 675 aml_append(pkg, a_zero); 676 aml_append(pkg, aml_name("%s", link_name)); 677 aml_append(pkg, a_zero); 678 return pkg; 679 } 680 681 /* 682 * initialize_route - Initialize the interrupt routing rule 683 * through a specific LINK: 684 * if (lnk_idx == idx) 685 * route using link 'link_name' 686 */ 687 static Aml *initialize_route(Aml *route, const char *link_name, 688 Aml *lnk_idx, int idx) 689 { 690 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 691 Aml *pkg = build_prt_entry(link_name); 692 693 aml_append(if_ctx, aml_store(pkg, route)); 694 695 return if_ctx; 696 } 697 698 /* 699 * build_prt - Define interrupt rounting rules 700 * 701 * Returns an array of 128 routes, one for each device, 702 * based on device location. 703 * The main goal is to equaly distribute the interrupts 704 * over the 4 existing ACPI links (works only for i440fx). 705 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 706 * 707 */ 708 static Aml *build_prt(bool is_pci0_prt) 709 { 710 Aml *method, *while_ctx, *pin, *res; 711 712 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 713 res = aml_local(0); 714 pin = aml_local(1); 715 aml_append(method, aml_store(aml_package(128), res)); 716 aml_append(method, aml_store(aml_int(0), pin)); 717 718 /* while (pin < 128) */ 719 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 720 { 721 Aml *slot = aml_local(2); 722 Aml *lnk_idx = aml_local(3); 723 Aml *route = aml_local(4); 724 725 /* slot = pin >> 2 */ 726 aml_append(while_ctx, 727 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 728 /* lnk_idx = (slot + pin) & 3 */ 729 aml_append(while_ctx, 730 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 731 lnk_idx)); 732 733 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 734 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 735 if (is_pci0_prt) { 736 Aml *if_device_1, *if_pin_4, *else_pin_4; 737 738 /* device 1 is the power-management device, needs SCI */ 739 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 740 { 741 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 742 { 743 aml_append(if_pin_4, 744 aml_store(build_prt_entry("LNKS"), route)); 745 } 746 aml_append(if_device_1, if_pin_4); 747 else_pin_4 = aml_else(); 748 { 749 aml_append(else_pin_4, 750 aml_store(build_prt_entry("LNKA"), route)); 751 } 752 aml_append(if_device_1, else_pin_4); 753 } 754 aml_append(while_ctx, if_device_1); 755 } else { 756 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 757 } 758 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 759 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 760 761 /* route[0] = 0x[slot]FFFF */ 762 aml_append(while_ctx, 763 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 764 NULL), 765 aml_index(route, aml_int(0)))); 766 /* route[1] = pin & 3 */ 767 aml_append(while_ctx, 768 aml_store(aml_and(pin, aml_int(3), NULL), 769 aml_index(route, aml_int(1)))); 770 /* res[pin] = route */ 771 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 772 /* pin++ */ 773 aml_append(while_ctx, aml_increment(pin)); 774 } 775 aml_append(method, while_ctx); 776 /* return res*/ 777 aml_append(method, aml_return(res)); 778 779 return method; 780 } 781 782 static void build_hpet_aml(Aml *table) 783 { 784 Aml *crs; 785 Aml *field; 786 Aml *method; 787 Aml *if_ctx; 788 Aml *scope = aml_scope("_SB"); 789 Aml *dev = aml_device("HPET"); 790 Aml *zero = aml_int(0); 791 Aml *id = aml_local(0); 792 Aml *period = aml_local(1); 793 794 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 795 aml_append(dev, aml_name_decl("_UID", zero)); 796 797 aml_append(dev, 798 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 799 HPET_LEN)); 800 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 801 aml_append(field, aml_named_field("VEND", 32)); 802 aml_append(field, aml_named_field("PRD", 32)); 803 aml_append(dev, field); 804 805 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 806 aml_append(method, aml_store(aml_name("VEND"), id)); 807 aml_append(method, aml_store(aml_name("PRD"), period)); 808 aml_append(method, aml_shiftright(id, aml_int(16), id)); 809 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 810 aml_equal(id, aml_int(0xffff)))); 811 { 812 aml_append(if_ctx, aml_return(zero)); 813 } 814 aml_append(method, if_ctx); 815 816 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 817 aml_lgreater(period, aml_int(100000000)))); 818 { 819 aml_append(if_ctx, aml_return(zero)); 820 } 821 aml_append(method, if_ctx); 822 823 aml_append(method, aml_return(aml_int(0x0F))); 824 aml_append(dev, method); 825 826 crs = aml_resource_template(); 827 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 828 aml_append(dev, aml_name_decl("_CRS", crs)); 829 830 aml_append(scope, dev); 831 aml_append(table, scope); 832 } 833 834 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 835 { 836 Aml *dev; 837 Aml *method; 838 Aml *crs; 839 840 dev = aml_device("VMBS"); 841 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 842 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 843 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 844 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 845 846 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 847 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 848 aml_name("STA"))); 849 aml_append(dev, method); 850 851 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 852 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 853 aml_name("STA"))); 854 aml_append(dev, method); 855 856 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 857 aml_append(method, aml_return(aml_name("STA"))); 858 aml_append(dev, method); 859 860 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 861 862 crs = aml_resource_template(); 863 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 864 aml_append(dev, aml_name_decl("_CRS", crs)); 865 866 return dev; 867 } 868 869 static void build_dbg_aml(Aml *table) 870 { 871 Aml *field; 872 Aml *method; 873 Aml *while_ctx; 874 Aml *scope = aml_scope("\\"); 875 Aml *buf = aml_local(0); 876 Aml *len = aml_local(1); 877 Aml *idx = aml_local(2); 878 879 aml_append(scope, 880 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 881 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 882 aml_append(field, aml_named_field("DBGB", 8)); 883 aml_append(scope, field); 884 885 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 886 887 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 888 aml_append(method, aml_to_buffer(buf, buf)); 889 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 890 aml_append(method, aml_store(aml_int(0), idx)); 891 892 while_ctx = aml_while(aml_lless(idx, len)); 893 aml_append(while_ctx, 894 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 895 aml_append(while_ctx, aml_increment(idx)); 896 aml_append(method, while_ctx); 897 898 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 899 aml_append(scope, method); 900 901 aml_append(table, scope); 902 } 903 904 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 905 { 906 Aml *dev; 907 Aml *crs; 908 Aml *method; 909 uint32_t irqs[] = {5, 10, 11}; 910 911 dev = aml_device("%s", name); 912 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 913 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 914 915 crs = aml_resource_template(); 916 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 917 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 918 aml_append(dev, aml_name_decl("_PRS", crs)); 919 920 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 921 aml_append(method, aml_return(aml_call1("IQST", reg))); 922 aml_append(dev, method); 923 924 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 925 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 926 aml_append(dev, method); 927 928 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 929 aml_append(method, aml_return(aml_call1("IQCR", reg))); 930 aml_append(dev, method); 931 932 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 933 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 934 aml_append(method, aml_store(aml_name("PRRI"), reg)); 935 aml_append(dev, method); 936 937 return dev; 938 } 939 940 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 941 { 942 Aml *dev; 943 Aml *crs; 944 Aml *method; 945 uint32_t irqs; 946 947 dev = aml_device("%s", name); 948 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 949 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 950 951 crs = aml_resource_template(); 952 irqs = gsi; 953 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 954 AML_SHARED, &irqs, 1)); 955 aml_append(dev, aml_name_decl("_PRS", crs)); 956 957 aml_append(dev, aml_name_decl("_CRS", crs)); 958 959 /* 960 * _DIS can be no-op because the interrupt cannot be disabled. 961 */ 962 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 963 aml_append(dev, method); 964 965 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 966 aml_append(dev, method); 967 968 return dev; 969 } 970 971 /* _CRS method - get current settings */ 972 static Aml *build_iqcr_method(bool is_piix4) 973 { 974 Aml *if_ctx; 975 uint32_t irqs; 976 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 977 Aml *crs = aml_resource_template(); 978 979 irqs = 0; 980 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 981 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 982 aml_append(method, aml_name_decl("PRR0", crs)); 983 984 aml_append(method, 985 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 986 987 if (is_piix4) { 988 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 989 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 990 aml_append(method, if_ctx); 991 } else { 992 aml_append(method, 993 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 994 aml_name("PRRI"))); 995 } 996 997 aml_append(method, aml_return(aml_name("PRR0"))); 998 return method; 999 } 1000 1001 /* _STA method - get status */ 1002 static Aml *build_irq_status_method(void) 1003 { 1004 Aml *if_ctx; 1005 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1006 1007 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1008 aml_append(if_ctx, aml_return(aml_int(0x09))); 1009 aml_append(method, if_ctx); 1010 aml_append(method, aml_return(aml_int(0x0B))); 1011 return method; 1012 } 1013 1014 static void build_piix4_pci0_int(Aml *table) 1015 { 1016 Aml *dev; 1017 Aml *crs; 1018 Aml *method; 1019 uint32_t irqs; 1020 Aml *sb_scope = aml_scope("_SB"); 1021 Aml *pci0_scope = aml_scope("PCI0"); 1022 1023 aml_append(pci0_scope, build_prt(true)); 1024 aml_append(sb_scope, pci0_scope); 1025 1026 aml_append(sb_scope, build_irq_status_method()); 1027 aml_append(sb_scope, build_iqcr_method(true)); 1028 1029 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1030 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1031 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1032 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1033 1034 dev = aml_device("LNKS"); 1035 { 1036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1037 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1038 1039 crs = aml_resource_template(); 1040 irqs = 9; 1041 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1042 AML_ACTIVE_HIGH, AML_SHARED, 1043 &irqs, 1)); 1044 aml_append(dev, aml_name_decl("_PRS", crs)); 1045 1046 /* The SCI cannot be disabled and is always attached to GSI 9, 1047 * so these are no-ops. We only need this link to override the 1048 * polarity to active high and match the content of the MADT. 1049 */ 1050 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1051 aml_append(method, aml_return(aml_int(0x0b))); 1052 aml_append(dev, method); 1053 1054 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_name("_PRS"))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1062 aml_append(dev, method); 1063 } 1064 aml_append(sb_scope, dev); 1065 1066 aml_append(table, sb_scope); 1067 } 1068 1069 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1070 { 1071 int i; 1072 int head; 1073 Aml *pkg; 1074 char base = name[3] < 'E' ? 'A' : 'E'; 1075 char *s = g_strdup(name); 1076 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1077 1078 assert(strlen(s) == 4); 1079 1080 head = name[3] - base; 1081 for (i = 0; i < 4; i++) { 1082 if (head + i > 3) { 1083 head = i * -1; 1084 } 1085 s[3] = base + head + i; 1086 pkg = aml_package(4); 1087 aml_append(pkg, a_nr); 1088 aml_append(pkg, aml_int(i)); 1089 aml_append(pkg, aml_name("%s", s)); 1090 aml_append(pkg, aml_int(0)); 1091 aml_append(ctx, pkg); 1092 } 1093 g_free(s); 1094 } 1095 1096 static Aml *build_q35_routing_table(const char *str) 1097 { 1098 int i; 1099 Aml *pkg; 1100 char *name = g_strdup_printf("%s ", str); 1101 1102 pkg = aml_package(128); 1103 for (i = 0; i < 0x18; i++) { 1104 name[3] = 'E' + (i & 0x3); 1105 append_q35_prt_entry(pkg, i, name); 1106 } 1107 1108 name[3] = 'E'; 1109 append_q35_prt_entry(pkg, 0x18, name); 1110 1111 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1112 for (i = 0x0019; i < 0x1e; i++) { 1113 name[3] = 'A'; 1114 append_q35_prt_entry(pkg, i, name); 1115 } 1116 1117 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1118 name[3] = 'E'; 1119 append_q35_prt_entry(pkg, 0x1e, name); 1120 name[3] = 'A'; 1121 append_q35_prt_entry(pkg, 0x1f, name); 1122 1123 g_free(name); 1124 return pkg; 1125 } 1126 1127 static void build_q35_pci0_int(Aml *table) 1128 { 1129 Aml *method; 1130 Aml *sb_scope = aml_scope("_SB"); 1131 Aml *pci0_scope = aml_scope("PCI0"); 1132 1133 /* Zero => PIC mode, One => APIC Mode */ 1134 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1135 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1136 { 1137 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1138 } 1139 aml_append(table, method); 1140 1141 aml_append(pci0_scope, 1142 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1143 aml_append(pci0_scope, 1144 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1145 1146 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1147 { 1148 Aml *if_ctx; 1149 Aml *else_ctx; 1150 1151 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1152 section 6.2.8.1 */ 1153 /* Note: we provide the same info as the PCI routing 1154 table of the Bochs BIOS */ 1155 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1156 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1157 aml_append(method, if_ctx); 1158 else_ctx = aml_else(); 1159 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1160 aml_append(method, else_ctx); 1161 } 1162 aml_append(pci0_scope, method); 1163 aml_append(sb_scope, pci0_scope); 1164 1165 aml_append(sb_scope, build_irq_status_method()); 1166 aml_append(sb_scope, build_iqcr_method(false)); 1167 1168 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1169 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1170 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1171 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1172 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1173 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1174 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1175 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1176 1177 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1178 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1179 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1180 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1181 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1182 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1183 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1184 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1185 1186 aml_append(table, sb_scope); 1187 } 1188 1189 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1190 { 1191 Aml *dev; 1192 Aml *resource_template; 1193 1194 /* DRAM controller */ 1195 dev = aml_device("DRAC"); 1196 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1197 1198 resource_template = aml_resource_template(); 1199 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1200 aml_append(resource_template, 1201 aml_qword_memory(AML_POS_DECODE, 1202 AML_MIN_FIXED, 1203 AML_MAX_FIXED, 1204 AML_NON_CACHEABLE, 1205 AML_READ_WRITE, 1206 0x0000000000000000, 1207 mcfg->base, 1208 mcfg->base + mcfg->size - 1, 1209 0x0000000000000000, 1210 mcfg->size)); 1211 } else { 1212 aml_append(resource_template, 1213 aml_dword_memory(AML_POS_DECODE, 1214 AML_MIN_FIXED, 1215 AML_MAX_FIXED, 1216 AML_NON_CACHEABLE, 1217 AML_READ_WRITE, 1218 0x0000000000000000, 1219 mcfg->base, 1220 mcfg->base + mcfg->size - 1, 1221 0x0000000000000000, 1222 mcfg->size)); 1223 } 1224 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1225 1226 return dev; 1227 } 1228 1229 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1230 { 1231 Aml *scope; 1232 Aml *field; 1233 Aml *method; 1234 1235 scope = aml_scope("_SB.PCI0"); 1236 1237 aml_append(scope, 1238 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1239 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1240 aml_append(field, aml_named_field("PCIU", 32)); 1241 aml_append(field, aml_named_field("PCID", 32)); 1242 aml_append(scope, field); 1243 1244 aml_append(scope, 1245 aml_operation_region("SEJ", AML_SYSTEM_IO, 1246 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1247 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1248 aml_append(field, aml_named_field("B0EJ", 32)); 1249 aml_append(scope, field); 1250 1251 aml_append(scope, 1252 aml_operation_region("BNMR", AML_SYSTEM_IO, 1253 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1254 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1255 aml_append(field, aml_named_field("BNUM", 32)); 1256 aml_append(field, aml_named_field("PIDX", 32)); 1257 aml_append(scope, field); 1258 1259 aml_append(scope, aml_mutex("BLCK", 0)); 1260 1261 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1262 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1263 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1264 aml_append(method, 1265 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1266 aml_append(method, aml_release(aml_name("BLCK"))); 1267 aml_append(method, aml_return(aml_int(0))); 1268 aml_append(scope, method); 1269 1270 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1271 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1272 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1273 aml_append(method, 1274 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1275 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1276 aml_append(method, aml_release(aml_name("BLCK"))); 1277 aml_append(method, aml_return(aml_local(0))); 1278 aml_append(scope, method); 1279 1280 aml_append(scope, aml_pci_pdsm()); 1281 1282 aml_append(table, scope); 1283 } 1284 1285 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1286 { 1287 Aml *if_ctx; 1288 Aml *if_ctx2; 1289 Aml *else_ctx; 1290 Aml *method; 1291 Aml *a_cwd1 = aml_name("CDW1"); 1292 Aml *a_ctrl = aml_local(0); 1293 1294 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1295 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1296 1297 if_ctx = aml_if(aml_equal( 1298 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1299 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1300 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1301 1302 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1303 1304 /* 1305 * Always allow native PME, AER (no dependencies) 1306 * Allow SHPC (PCI bridges can have SHPC controller) 1307 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1308 */ 1309 aml_append(if_ctx, aml_and(a_ctrl, 1310 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1311 1312 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1313 /* Unknown revision */ 1314 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1315 aml_append(if_ctx, if_ctx2); 1316 1317 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1318 /* Capabilities bits were masked */ 1319 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1320 aml_append(if_ctx, if_ctx2); 1321 1322 /* Update DWORD3 in the buffer */ 1323 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1324 aml_append(method, if_ctx); 1325 1326 else_ctx = aml_else(); 1327 /* Unrecognized UUID */ 1328 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1329 aml_append(method, else_ctx); 1330 1331 aml_append(method, aml_return(aml_arg(3))); 1332 return method; 1333 } 1334 1335 static void build_acpi0017(Aml *table) 1336 { 1337 Aml *dev, *scope, *method; 1338 1339 scope = aml_scope("_SB"); 1340 dev = aml_device("CXLM"); 1341 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1342 1343 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1344 aml_append(method, aml_return(aml_int(0x01))); 1345 aml_append(dev, method); 1346 1347 aml_append(scope, dev); 1348 aml_append(table, scope); 1349 } 1350 1351 static void 1352 build_dsdt(GArray *table_data, BIOSLinker *linker, 1353 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1354 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1355 { 1356 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1357 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1358 CrsRangeEntry *entry; 1359 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1360 CrsRangeSet crs_range_set; 1361 PCMachineState *pcms = PC_MACHINE(machine); 1362 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1363 X86MachineState *x86ms = X86_MACHINE(machine); 1364 AcpiMcfgInfo mcfg; 1365 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1366 uint32_t nr_mem = machine->ram_slots; 1367 int root_bus_limit = 0xFF; 1368 PCIBus *bus = NULL; 1369 #ifdef CONFIG_TPM 1370 TPMIf *tpm = tpm_find(); 1371 #endif 1372 bool cxl_present = false; 1373 int i; 1374 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1375 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1376 .oem_table_id = x86ms->oem_table_id }; 1377 1378 assert(!!i440fx != !!q35); 1379 1380 acpi_table_begin(&table, table_data); 1381 dsdt = init_aml_allocator(); 1382 1383 build_dbg_aml(dsdt); 1384 if (i440fx) { 1385 sb_scope = aml_scope("_SB"); 1386 dev = aml_device("PCI0"); 1387 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1388 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1389 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1390 aml_append(sb_scope, dev); 1391 aml_append(dsdt, sb_scope); 1392 1393 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1394 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1395 } 1396 build_piix4_pci0_int(dsdt); 1397 } else if (q35) { 1398 sb_scope = aml_scope("_SB"); 1399 dev = aml_device("PCI0"); 1400 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1401 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1402 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1403 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1404 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1405 aml_append(sb_scope, dev); 1406 if (mcfg_valid) { 1407 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1408 } 1409 1410 if (pm->smi_on_cpuhp) { 1411 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1412 dev = aml_device("PCI0.SMI0"); 1413 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1414 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1415 crs = aml_resource_template(); 1416 aml_append(crs, 1417 aml_io( 1418 AML_DECODE16, 1419 ACPI_PORT_SMI_CMD, 1420 ACPI_PORT_SMI_CMD, 1421 1, 1422 2) 1423 ); 1424 aml_append(dev, aml_name_decl("_CRS", crs)); 1425 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1426 aml_int(ACPI_PORT_SMI_CMD), 2)); 1427 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1428 AML_WRITE_AS_ZEROS); 1429 aml_append(field, aml_named_field("SMIC", 8)); 1430 aml_append(field, aml_reserved_field(8)); 1431 aml_append(dev, field); 1432 aml_append(sb_scope, dev); 1433 } 1434 1435 aml_append(dsdt, sb_scope); 1436 1437 if (pm->pcihp_bridge_en) { 1438 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1439 } 1440 build_q35_pci0_int(dsdt); 1441 } 1442 1443 if (misc->has_hpet) { 1444 build_hpet_aml(dsdt); 1445 } 1446 1447 if (vmbus_bridge) { 1448 sb_scope = aml_scope("_SB"); 1449 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1450 aml_append(dsdt, sb_scope); 1451 } 1452 1453 scope = aml_scope("_GPE"); 1454 { 1455 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1456 if (machine->nvdimms_state->is_enabled) { 1457 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1458 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1459 aml_int(0x80))); 1460 aml_append(scope, method); 1461 } 1462 } 1463 aml_append(dsdt, scope); 1464 1465 if (pcmc->legacy_cpu_hotplug) { 1466 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1467 } else { 1468 CPUHotplugFeatures opts = { 1469 .acpi_1_compatible = true, .has_legacy_cphp = true, 1470 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1471 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1472 }; 1473 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1474 "\\_SB.PCI0", "\\_GPE._E02"); 1475 } 1476 1477 if (pcms->memhp_io_base && nr_mem) { 1478 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1479 "\\_GPE._E03", AML_SYSTEM_IO, 1480 pcms->memhp_io_base); 1481 } 1482 1483 crs_range_set_init(&crs_range_set); 1484 bus = PC_MACHINE(machine)->bus; 1485 if (bus) { 1486 QLIST_FOREACH(bus, &bus->child, sibling) { 1487 uint8_t bus_num = pci_bus_num(bus); 1488 uint8_t numa_node = pci_bus_numa_node(bus); 1489 1490 /* look only for expander root buses */ 1491 if (!pci_bus_is_root(bus)) { 1492 continue; 1493 } 1494 1495 if (bus_num < root_bus_limit) { 1496 root_bus_limit = bus_num - 1; 1497 } 1498 1499 scope = aml_scope("\\_SB"); 1500 1501 if (pci_bus_is_cxl(bus)) { 1502 dev = aml_device("CL%.02X", bus_num); 1503 } else { 1504 dev = aml_device("PC%.02X", bus_num); 1505 } 1506 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1507 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1508 if (pci_bus_is_cxl(bus)) { 1509 struct Aml *pkg = aml_package(2); 1510 1511 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1512 aml_append(pkg, aml_eisaid("PNP0A08")); 1513 aml_append(pkg, aml_eisaid("PNP0A03")); 1514 aml_append(dev, aml_name_decl("_CID", pkg)); 1515 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1516 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1517 build_cxl_osc_method(dev); 1518 } else if (pci_bus_is_express(bus)) { 1519 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1520 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1521 1522 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1523 aml_append(dev, build_q35_osc_method(true)); 1524 } else { 1525 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1526 } 1527 1528 if (numa_node != NUMA_NODE_UNASSIGNED) { 1529 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1530 } 1531 1532 aml_append(dev, build_prt(false)); 1533 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1534 0, 0, 0, 0); 1535 aml_append(dev, aml_name_decl("_CRS", crs)); 1536 aml_append(scope, dev); 1537 aml_append(dsdt, scope); 1538 1539 /* Handle the ranges for the PXB expanders */ 1540 if (pci_bus_is_cxl(bus)) { 1541 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1542 uint64_t base = mr->addr; 1543 1544 cxl_present = true; 1545 crs_range_insert(crs_range_set.mem_ranges, base, 1546 base + memory_region_size(mr) - 1); 1547 } 1548 } 1549 } 1550 1551 if (cxl_present) { 1552 build_acpi0017(dsdt); 1553 } 1554 1555 /* 1556 * At this point crs_range_set has all the ranges used by pci 1557 * busses *other* than PCI0. These ranges will be excluded from 1558 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1559 * too. 1560 */ 1561 if (mcfg_valid) { 1562 crs_range_insert(crs_range_set.mem_ranges, 1563 mcfg.base, mcfg.base + mcfg.size - 1); 1564 } 1565 1566 scope = aml_scope("\\_SB.PCI0"); 1567 /* build PCI0._CRS */ 1568 crs = aml_resource_template(); 1569 aml_append(crs, 1570 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1571 0x0000, 0x0, root_bus_limit, 1572 0x0000, root_bus_limit + 1)); 1573 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1574 1575 aml_append(crs, 1576 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1577 AML_POS_DECODE, AML_ENTIRE_RANGE, 1578 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1579 1580 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1581 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1582 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1583 aml_append(crs, 1584 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1585 AML_POS_DECODE, AML_ENTIRE_RANGE, 1586 0x0000, entry->base, entry->limit, 1587 0x0000, entry->limit - entry->base + 1)); 1588 } 1589 1590 aml_append(crs, 1591 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1592 AML_CACHEABLE, AML_READ_WRITE, 1593 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1594 1595 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1596 range_lob(pci_hole), 1597 range_upb(pci_hole)); 1598 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1599 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1600 aml_append(crs, 1601 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1602 AML_NON_CACHEABLE, AML_READ_WRITE, 1603 0, entry->base, entry->limit, 1604 0, entry->limit - entry->base + 1)); 1605 } 1606 1607 if (!range_is_empty(pci_hole64)) { 1608 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1609 range_lob(pci_hole64), 1610 range_upb(pci_hole64)); 1611 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1612 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1613 aml_append(crs, 1614 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1615 AML_MAX_FIXED, 1616 AML_CACHEABLE, AML_READ_WRITE, 1617 0, entry->base, entry->limit, 1618 0, entry->limit - entry->base + 1)); 1619 } 1620 } 1621 1622 #ifdef CONFIG_TPM 1623 if (TPM_IS_TIS_ISA(tpm_find())) { 1624 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1625 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1626 } 1627 #endif 1628 aml_append(scope, aml_name_decl("_CRS", crs)); 1629 1630 /* reserve GPE0 block resources */ 1631 dev = aml_device("GPE0"); 1632 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1633 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1634 /* device present, functioning, decoding, not shown in UI */ 1635 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1636 crs = aml_resource_template(); 1637 aml_append(crs, 1638 aml_io( 1639 AML_DECODE16, 1640 pm->fadt.gpe0_blk.address, 1641 pm->fadt.gpe0_blk.address, 1642 1, 1643 pm->fadt.gpe0_blk.bit_width / 8) 1644 ); 1645 aml_append(dev, aml_name_decl("_CRS", crs)); 1646 aml_append(scope, dev); 1647 1648 crs_range_set_free(&crs_range_set); 1649 1650 /* reserve PCIHP resources */ 1651 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1652 dev = aml_device("PHPR"); 1653 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1654 aml_append(dev, 1655 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1656 /* device present, functioning, decoding, not shown in UI */ 1657 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1658 crs = aml_resource_template(); 1659 aml_append(crs, 1660 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1661 pm->pcihp_io_len) 1662 ); 1663 aml_append(dev, aml_name_decl("_CRS", crs)); 1664 aml_append(scope, dev); 1665 } 1666 aml_append(dsdt, scope); 1667 1668 /* create S3_ / S4_ / S5_ packages if necessary */ 1669 scope = aml_scope("\\"); 1670 if (!pm->s3_disabled) { 1671 pkg = aml_package(4); 1672 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1673 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1674 aml_append(pkg, aml_int(0)); /* reserved */ 1675 aml_append(pkg, aml_int(0)); /* reserved */ 1676 aml_append(scope, aml_name_decl("_S3", pkg)); 1677 } 1678 1679 if (!pm->s4_disabled) { 1680 pkg = aml_package(4); 1681 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1682 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1683 aml_append(pkg, aml_int(pm->s4_val)); 1684 aml_append(pkg, aml_int(0)); /* reserved */ 1685 aml_append(pkg, aml_int(0)); /* reserved */ 1686 aml_append(scope, aml_name_decl("_S4", pkg)); 1687 } 1688 1689 pkg = aml_package(4); 1690 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1691 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1692 aml_append(pkg, aml_int(0)); /* reserved */ 1693 aml_append(pkg, aml_int(0)); /* reserved */ 1694 aml_append(scope, aml_name_decl("_S5", pkg)); 1695 aml_append(dsdt, scope); 1696 1697 /* create fw_cfg node, unconditionally */ 1698 { 1699 scope = aml_scope("\\_SB.PCI0"); 1700 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1701 aml_append(dsdt, scope); 1702 } 1703 1704 sb_scope = aml_scope("\\_SB"); 1705 { 1706 Object *pci_host = acpi_get_i386_pci_host(); 1707 1708 if (pci_host) { 1709 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1710 Aml *scope = aml_scope("PCI0"); 1711 /* Scan all PCI buses. Generate tables to support hotplug. */ 1712 build_append_pci_bus_devices(scope, bus); 1713 aml_append(sb_scope, scope); 1714 } 1715 } 1716 1717 #ifdef CONFIG_TPM 1718 if (TPM_IS_CRB(tpm)) { 1719 dev = aml_device("TPM"); 1720 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1721 aml_append(dev, aml_name_decl("_STR", 1722 aml_string("TPM 2.0 Device"))); 1723 crs = aml_resource_template(); 1724 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1725 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1726 aml_append(dev, aml_name_decl("_CRS", crs)); 1727 1728 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1729 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1730 1731 tpm_build_ppi_acpi(tpm, dev); 1732 1733 aml_append(sb_scope, dev); 1734 } 1735 #endif 1736 1737 if (pcms->sgx_epc.size != 0) { 1738 uint64_t epc_base = pcms->sgx_epc.base; 1739 uint64_t epc_size = pcms->sgx_epc.size; 1740 1741 dev = aml_device("EPC"); 1742 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1743 aml_append(dev, aml_name_decl("_STR", 1744 aml_unicode("Enclave Page Cache 1.0"))); 1745 crs = aml_resource_template(); 1746 aml_append(crs, 1747 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1748 AML_MAX_FIXED, AML_NON_CACHEABLE, 1749 AML_READ_WRITE, 0, epc_base, 1750 epc_base + epc_size - 1, 0, epc_size)); 1751 aml_append(dev, aml_name_decl("_CRS", crs)); 1752 1753 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1754 aml_append(method, aml_return(aml_int(0x0f))); 1755 aml_append(dev, method); 1756 1757 aml_append(sb_scope, dev); 1758 } 1759 aml_append(dsdt, sb_scope); 1760 1761 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1762 bool has_pcnt; 1763 1764 Object *pci_host = acpi_get_i386_pci_host(); 1765 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1766 1767 scope = aml_scope("\\_SB.PCI0"); 1768 has_pcnt = build_append_notfication_callback(scope, bus); 1769 if (has_pcnt) { 1770 aml_append(dsdt, scope); 1771 } 1772 1773 scope = aml_scope("_GPE"); 1774 { 1775 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1776 if (has_pcnt) { 1777 aml_append(method, 1778 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1779 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1780 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1781 } 1782 aml_append(scope, method); 1783 } 1784 aml_append(dsdt, scope); 1785 } 1786 1787 /* copy AML table into ACPI tables blob and patch header there */ 1788 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1789 acpi_table_end(linker, &table); 1790 free_aml_allocator(); 1791 } 1792 1793 /* 1794 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1795 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1796 */ 1797 static void 1798 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1799 const char *oem_table_id) 1800 { 1801 AcpiTable table = { .sig = "HPET", .rev = 1, 1802 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1803 1804 acpi_table_begin(&table, table_data); 1805 /* Note timer_block_id value must be kept in sync with value advertised by 1806 * emulated hpet 1807 */ 1808 /* Event Timer Block ID */ 1809 build_append_int_noprefix(table_data, 0x8086a201, 4); 1810 /* BASE_ADDRESS */ 1811 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1812 /* HPET Number */ 1813 build_append_int_noprefix(table_data, 0, 1); 1814 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1815 build_append_int_noprefix(table_data, 0, 2); 1816 /* Page Protection And OEM Attribute */ 1817 build_append_int_noprefix(table_data, 0, 1); 1818 acpi_table_end(linker, &table); 1819 } 1820 1821 #ifdef CONFIG_TPM 1822 /* 1823 * TCPA Description Table 1824 * 1825 * Following Level 00, Rev 00.37 of specs: 1826 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1827 * 7.1.2 ACPI Table Layout 1828 */ 1829 static void 1830 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1831 const char *oem_id, const char *oem_table_id) 1832 { 1833 unsigned log_addr_offset; 1834 AcpiTable table = { .sig = "TCPA", .rev = 2, 1835 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1836 1837 acpi_table_begin(&table, table_data); 1838 /* Platform Class */ 1839 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1840 /* Log Area Minimum Length (LAML) */ 1841 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1842 /* Log Area Start Address (LASA) */ 1843 log_addr_offset = table_data->len; 1844 build_append_int_noprefix(table_data, 0, 8); 1845 1846 /* allocate/reserve space for TPM log area */ 1847 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1848 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1849 false /* high memory */); 1850 /* log area start address to be filled by Guest linker */ 1851 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1852 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1853 1854 acpi_table_end(linker, &table); 1855 } 1856 #endif 1857 1858 #define HOLE_640K_START (640 * KiB) 1859 #define HOLE_640K_END (1 * MiB) 1860 1861 /* 1862 * ACPI spec, Revision 3.0 1863 * 5.2.15 System Resource Affinity Table (SRAT) 1864 */ 1865 static void 1866 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1867 { 1868 int i; 1869 int numa_mem_start, slots; 1870 uint64_t mem_len, mem_base, next_base; 1871 MachineClass *mc = MACHINE_GET_CLASS(machine); 1872 X86MachineState *x86ms = X86_MACHINE(machine); 1873 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1874 PCMachineState *pcms = PC_MACHINE(machine); 1875 int nb_numa_nodes = machine->numa_state->num_nodes; 1876 NodeInfo *numa_info = machine->numa_state->nodes; 1877 ram_addr_t hotpluggable_address_space_size = 1878 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1879 NULL); 1880 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1881 .oem_table_id = x86ms->oem_table_id }; 1882 1883 acpi_table_begin(&table, table_data); 1884 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1885 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1886 1887 for (i = 0; i < apic_ids->len; i++) { 1888 int node_id = apic_ids->cpus[i].props.node_id; 1889 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1890 1891 if (apic_id < 255) { 1892 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1893 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1894 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1895 /* Proximity Domain [7:0] */ 1896 build_append_int_noprefix(table_data, node_id, 1); 1897 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1898 /* Flags, Table 5-36 */ 1899 build_append_int_noprefix(table_data, 1, 4); 1900 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1901 /* Proximity Domain [31:8] */ 1902 build_append_int_noprefix(table_data, 0, 3); 1903 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1904 } else { 1905 /* 1906 * ACPI spec, Revision 4.0 1907 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1908 */ 1909 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1910 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1911 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1912 /* Proximity Domain */ 1913 build_append_int_noprefix(table_data, node_id, 4); 1914 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1915 /* Flags, Table 5-39 */ 1916 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1917 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1918 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1919 } 1920 } 1921 1922 /* the memory map is a bit tricky, it contains at least one hole 1923 * from 640k-1M and possibly another one from 3.5G-4G. 1924 */ 1925 next_base = 0; 1926 numa_mem_start = table_data->len; 1927 1928 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1929 mem_base = next_base; 1930 mem_len = numa_info[i - 1].node_mem; 1931 next_base = mem_base + mem_len; 1932 1933 /* Cut out the 640K hole */ 1934 if (mem_base <= HOLE_640K_START && 1935 next_base > HOLE_640K_START) { 1936 mem_len -= next_base - HOLE_640K_START; 1937 if (mem_len > 0) { 1938 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1939 MEM_AFFINITY_ENABLED); 1940 } 1941 1942 /* Check for the rare case: 640K < RAM < 1M */ 1943 if (next_base <= HOLE_640K_END) { 1944 next_base = HOLE_640K_END; 1945 continue; 1946 } 1947 mem_base = HOLE_640K_END; 1948 mem_len = next_base - HOLE_640K_END; 1949 } 1950 1951 /* Cut out the ACPI_PCI hole */ 1952 if (mem_base <= x86ms->below_4g_mem_size && 1953 next_base > x86ms->below_4g_mem_size) { 1954 mem_len -= next_base - x86ms->below_4g_mem_size; 1955 if (mem_len > 0) { 1956 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1957 MEM_AFFINITY_ENABLED); 1958 } 1959 mem_base = x86ms->above_4g_mem_start; 1960 mem_len = next_base - x86ms->below_4g_mem_size; 1961 next_base = mem_base + mem_len; 1962 } 1963 1964 if (mem_len > 0) { 1965 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1966 MEM_AFFINITY_ENABLED); 1967 } 1968 } 1969 1970 if (machine->nvdimms_state->is_enabled) { 1971 nvdimm_build_srat(table_data); 1972 } 1973 1974 sgx_epc_build_srat(table_data); 1975 1976 /* 1977 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1978 * without these entries. But I recall there were issues the last time I 1979 * tried to remove it with some ancient guest OS, however I can't remember 1980 * what that was so keep this around for now 1981 */ 1982 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1983 for (; slots < nb_numa_nodes + 2; slots++) { 1984 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1985 } 1986 1987 /* 1988 * Entry is required for Windows to enable memory hotplug in OS 1989 * and for Linux to enable SWIOTLB when booted with less than 1990 * 4G of RAM. Windows works better if the entry sets proximity 1991 * to the highest NUMA node in the machine. 1992 * Memory devices may override proximity set by this entry, 1993 * providing _PXM method if necessary. 1994 */ 1995 if (hotpluggable_address_space_size) { 1996 build_srat_memory(table_data, machine->device_memory->base, 1997 hotpluggable_address_space_size, nb_numa_nodes - 1, 1998 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1999 } 2000 2001 acpi_table_end(linker, &table); 2002 } 2003 2004 /* 2005 * Insert DMAR scope for PCI bridges and endpoint devcie 2006 */ 2007 static void 2008 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2009 { 2010 const size_t device_scope_size = 6 /* device scope structure */ + 2011 2 /* 1 path entry */; 2012 GArray *scope_blob = opaque; 2013 2014 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2015 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2016 build_append_int_noprefix(scope_blob, 0x02, 1); 2017 } else { 2018 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2019 build_append_int_noprefix(scope_blob, 0x01, 1); 2020 } 2021 2022 /* length */ 2023 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2024 /* reserved */ 2025 build_append_int_noprefix(scope_blob, 0, 2); 2026 /* enumeration_id */ 2027 build_append_int_noprefix(scope_blob, 0, 1); 2028 /* bus */ 2029 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2030 /* device */ 2031 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2032 /* function */ 2033 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2034 } 2035 2036 /* For a given PCI host bridge, walk and insert DMAR scope */ 2037 static int 2038 dmar_host_bridges(Object *obj, void *opaque) 2039 { 2040 GArray *scope_blob = opaque; 2041 2042 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2043 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2044 2045 if (bus && !pci_bus_bypass_iommu(bus)) { 2046 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2047 } 2048 } 2049 2050 return 0; 2051 } 2052 2053 /* 2054 * Intel ® Virtualization Technology for Directed I/O 2055 * Architecture Specification. Revision 3.3 2056 * 8.1 DMA Remapping Reporting Structure 2057 */ 2058 static void 2059 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2060 const char *oem_table_id) 2061 { 2062 uint8_t dmar_flags = 0; 2063 uint8_t rsvd10[10] = {}; 2064 /* Root complex IOAPIC uses one path only */ 2065 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2066 2 /* 1 path entry */; 2067 X86IOMMUState *iommu = x86_iommu_get_default(); 2068 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2069 GArray *scope_blob = g_array_new(false, true, 1); 2070 2071 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2072 .oem_table_id = oem_table_id }; 2073 2074 /* 2075 * A PCI bus walk, for each PCI host bridge. 2076 * Insert scope for each PCI bridge and endpoint device which 2077 * is attached to a bus with iommu enabled. 2078 */ 2079 object_child_foreach_recursive(object_get_root(), 2080 dmar_host_bridges, scope_blob); 2081 2082 assert(iommu); 2083 if (x86_iommu_ir_supported(iommu)) { 2084 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2085 } 2086 2087 acpi_table_begin(&table, table_data); 2088 /* Host Address Width */ 2089 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2090 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2091 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2092 2093 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2094 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2095 /* Length */ 2096 build_append_int_noprefix(table_data, 2097 16 + ioapic_scope_size + scope_blob->len, 2); 2098 /* Flags */ 2099 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2100 1); 2101 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2102 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2103 /* Register Base Address */ 2104 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2105 2106 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2107 * 8.3.1 (version Oct. 2014 or later). */ 2108 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2109 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2110 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2111 /* Enumeration ID */ 2112 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2113 /* Start Bus Number */ 2114 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2115 /* Path, {Device, Function} pair */ 2116 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2117 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2118 2119 /* Add scope found above */ 2120 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2121 g_array_free(scope_blob, true); 2122 2123 if (iommu->dt_supported) { 2124 /* 8.5 Root Port ATS Capability Reporting Structure */ 2125 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2126 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2127 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2128 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2129 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2130 } 2131 2132 acpi_table_end(linker, &table); 2133 } 2134 2135 /* 2136 * Windows ACPI Emulated Devices Table 2137 * (Version 1.0 - April 6, 2009) 2138 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2139 * 2140 * Helpful to speedup Windows guests and ignored by others. 2141 */ 2142 static void 2143 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2144 const char *oem_table_id) 2145 { 2146 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2147 .oem_table_id = oem_table_id }; 2148 2149 acpi_table_begin(&table, table_data); 2150 /* 2151 * Set "ACPI PM timer good" flag. 2152 * 2153 * Tells Windows guests that our ACPI PM timer is reliable in the 2154 * sense that guest can read it only once to obtain a reliable value. 2155 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2156 */ 2157 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2158 acpi_table_end(linker, &table); 2159 } 2160 2161 /* 2162 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2163 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2164 */ 2165 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2166 2167 /* 2168 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2169 * necessary for the PCI topology. 2170 */ 2171 static void 2172 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2173 { 2174 GArray *table_data = opaque; 2175 uint32_t entry; 2176 2177 /* "Select" IVHD entry, type 0x2 */ 2178 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2179 build_append_int_noprefix(table_data, entry, 4); 2180 2181 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2182 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2183 uint8_t sec = pci_bus_num(sec_bus); 2184 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2185 2186 if (pci_bus_is_express(sec_bus)) { 2187 /* 2188 * Walk the bus if there are subordinates, otherwise use a range 2189 * to cover an entire leaf bus. We could potentially also use a 2190 * range for traversed buses, but we'd need to take care not to 2191 * create both Select and Range entries covering the same device. 2192 * This is easier and potentially more compact. 2193 * 2194 * An example bare metal system seems to use Select entries for 2195 * root ports without a slot (ie. built-ins) and Range entries 2196 * when there is a slot. The same system also only hard-codes 2197 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2198 * making no effort to support nested bridges. We attempt to 2199 * be more thorough here. 2200 */ 2201 if (sec == sub) { /* leaf bus */ 2202 /* "Start of Range" IVHD entry, type 0x3 */ 2203 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2204 build_append_int_noprefix(table_data, entry, 4); 2205 /* "End of Range" IVHD entry, type 0x4 */ 2206 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2207 build_append_int_noprefix(table_data, entry, 4); 2208 } else { 2209 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2210 } 2211 } else { 2212 /* 2213 * If the secondary bus is conventional, then we need to create an 2214 * Alias range for everything downstream. The range covers the 2215 * first devfn on the secondary bus to the last devfn on the 2216 * subordinate bus. The alias target depends on legacy versus 2217 * express bridges, just as in pci_device_iommu_address_space(). 2218 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2219 */ 2220 uint16_t dev_id_a, dev_id_b; 2221 2222 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2223 2224 if (pci_is_express(dev) && 2225 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2226 dev_id_b = dev_id_a; 2227 } else { 2228 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2229 } 2230 2231 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2232 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2233 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2234 2235 /* "End of Range" IVHD entry, type 0x4 */ 2236 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2237 build_append_int_noprefix(table_data, entry, 4); 2238 } 2239 } 2240 } 2241 2242 /* For all PCI host bridges, walk and insert IVHD entries */ 2243 static int 2244 ivrs_host_bridges(Object *obj, void *opaque) 2245 { 2246 GArray *ivhd_blob = opaque; 2247 2248 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2249 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2250 2251 if (bus && !pci_bus_bypass_iommu(bus)) { 2252 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2253 } 2254 } 2255 2256 return 0; 2257 } 2258 2259 static void 2260 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2261 const char *oem_table_id) 2262 { 2263 int ivhd_table_len = 24; 2264 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2265 GArray *ivhd_blob = g_array_new(false, true, 1); 2266 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2267 .oem_table_id = oem_table_id }; 2268 2269 acpi_table_begin(&table, table_data); 2270 /* IVinfo - IO virtualization information common to all 2271 * IOMMU units in a system 2272 */ 2273 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2274 /* reserved */ 2275 build_append_int_noprefix(table_data, 0, 8); 2276 2277 /* IVHD definition - type 10h */ 2278 build_append_int_noprefix(table_data, 0x10, 1); 2279 /* virtualization flags */ 2280 build_append_int_noprefix(table_data, 2281 (1UL << 0) | /* HtTunEn */ 2282 (1UL << 4) | /* iotblSup */ 2283 (1UL << 6) | /* PrefSup */ 2284 (1UL << 7), /* PPRSup */ 2285 1); 2286 2287 /* 2288 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2289 * complete set of IVHD entries. Do this into a separate blob so that we 2290 * can calculate the total IVRS table length here and then append the new 2291 * blob further below. Fall back to an entry covering all devices, which 2292 * is sufficient when no aliases are present. 2293 */ 2294 object_child_foreach_recursive(object_get_root(), 2295 ivrs_host_bridges, ivhd_blob); 2296 2297 if (!ivhd_blob->len) { 2298 /* 2299 * Type 1 device entry reporting all devices 2300 * These are 4-byte device entries currently reporting the range of 2301 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2302 */ 2303 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2304 } 2305 2306 ivhd_table_len += ivhd_blob->len; 2307 2308 /* 2309 * When interrupt remapping is supported, we add a special IVHD device 2310 * for type IO-APIC. 2311 */ 2312 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2313 ivhd_table_len += 8; 2314 } 2315 2316 /* IVHD length */ 2317 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2318 /* DeviceID */ 2319 build_append_int_noprefix(table_data, s->devid, 2); 2320 /* Capability offset */ 2321 build_append_int_noprefix(table_data, s->capab_offset, 2); 2322 /* IOMMU base address */ 2323 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2324 /* PCI Segment Group */ 2325 build_append_int_noprefix(table_data, 0, 2); 2326 /* IOMMU info */ 2327 build_append_int_noprefix(table_data, 0, 2); 2328 /* IOMMU Feature Reporting */ 2329 build_append_int_noprefix(table_data, 2330 (48UL << 30) | /* HATS */ 2331 (48UL << 28) | /* GATS */ 2332 (1UL << 2) | /* GTSup */ 2333 (1UL << 6), /* GASup */ 2334 4); 2335 2336 /* IVHD entries as found above */ 2337 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2338 g_array_free(ivhd_blob, TRUE); 2339 2340 /* 2341 * Add a special IVHD device type. 2342 * Refer to spec - Table 95: IVHD device entry type codes 2343 * 2344 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2345 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2346 */ 2347 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2348 build_append_int_noprefix(table_data, 2349 (0x1ull << 56) | /* type IOAPIC */ 2350 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2351 0x48, /* special device */ 2352 8); 2353 } 2354 acpi_table_end(linker, &table); 2355 } 2356 2357 typedef 2358 struct AcpiBuildState { 2359 /* Copy of table in RAM (for patching). */ 2360 MemoryRegion *table_mr; 2361 /* Is table patched? */ 2362 uint8_t patched; 2363 void *rsdp; 2364 MemoryRegion *rsdp_mr; 2365 MemoryRegion *linker_mr; 2366 } AcpiBuildState; 2367 2368 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2369 { 2370 Object *pci_host; 2371 QObject *o; 2372 2373 pci_host = acpi_get_i386_pci_host(); 2374 if (!pci_host) { 2375 return false; 2376 } 2377 2378 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2379 if (!o) { 2380 return false; 2381 } 2382 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2383 qobject_unref(o); 2384 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2385 return false; 2386 } 2387 2388 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2389 assert(o); 2390 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2391 qobject_unref(o); 2392 return true; 2393 } 2394 2395 static 2396 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2397 { 2398 PCMachineState *pcms = PC_MACHINE(machine); 2399 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2400 X86MachineState *x86ms = X86_MACHINE(machine); 2401 DeviceState *iommu = pcms->iommu; 2402 GArray *table_offsets; 2403 unsigned facs, dsdt, rsdt, fadt; 2404 AcpiPmInfo pm; 2405 AcpiMiscInfo misc; 2406 AcpiMcfgInfo mcfg; 2407 Range pci_hole = {}, pci_hole64 = {}; 2408 uint8_t *u; 2409 size_t aml_len = 0; 2410 GArray *tables_blob = tables->table_data; 2411 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2412 Object *vmgenid_dev; 2413 char *oem_id; 2414 char *oem_table_id; 2415 2416 acpi_get_pm_info(machine, &pm); 2417 acpi_get_misc_info(&misc); 2418 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2419 acpi_get_slic_oem(&slic_oem); 2420 2421 if (slic_oem.id) { 2422 oem_id = slic_oem.id; 2423 } else { 2424 oem_id = x86ms->oem_id; 2425 } 2426 2427 if (slic_oem.table_id) { 2428 oem_table_id = slic_oem.table_id; 2429 } else { 2430 oem_table_id = x86ms->oem_table_id; 2431 } 2432 2433 table_offsets = g_array_new(false, true /* clear */, 2434 sizeof(uint32_t)); 2435 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2436 2437 bios_linker_loader_alloc(tables->linker, 2438 ACPI_BUILD_TABLE_FILE, tables_blob, 2439 64 /* Ensure FACS is aligned */, 2440 false /* high memory */); 2441 2442 /* 2443 * FACS is pointed to by FADT. 2444 * We place it first since it's the only table that has alignment 2445 * requirements. 2446 */ 2447 facs = tables_blob->len; 2448 build_facs(tables_blob); 2449 2450 /* DSDT is pointed to by FADT */ 2451 dsdt = tables_blob->len; 2452 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2453 &pci_hole, &pci_hole64, machine); 2454 2455 /* Count the size of the DSDT and SSDT, we will need it for legacy 2456 * sizing of ACPI tables. 2457 */ 2458 aml_len += tables_blob->len - dsdt; 2459 2460 /* ACPI tables pointed to by RSDT */ 2461 fadt = tables_blob->len; 2462 acpi_add_table(table_offsets, tables_blob); 2463 pm.fadt.facs_tbl_offset = &facs; 2464 pm.fadt.dsdt_tbl_offset = &dsdt; 2465 pm.fadt.xdsdt_tbl_offset = &dsdt; 2466 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2467 aml_len += tables_blob->len - fadt; 2468 2469 acpi_add_table(table_offsets, tables_blob); 2470 acpi_build_madt(tables_blob, tables->linker, x86ms, 2471 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2472 x86ms->oem_table_id); 2473 2474 #ifdef CONFIG_ACPI_ERST 2475 { 2476 Object *erst_dev; 2477 erst_dev = find_erst_dev(); 2478 if (erst_dev) { 2479 acpi_add_table(table_offsets, tables_blob); 2480 build_erst(tables_blob, tables->linker, erst_dev, 2481 x86ms->oem_id, x86ms->oem_table_id); 2482 } 2483 } 2484 #endif 2485 2486 vmgenid_dev = find_vmgenid_dev(); 2487 if (vmgenid_dev) { 2488 acpi_add_table(table_offsets, tables_blob); 2489 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2490 tables->vmgenid, tables->linker, x86ms->oem_id); 2491 } 2492 2493 if (misc.has_hpet) { 2494 acpi_add_table(table_offsets, tables_blob); 2495 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2496 x86ms->oem_table_id); 2497 } 2498 #ifdef CONFIG_TPM 2499 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2500 if (misc.tpm_version == TPM_VERSION_1_2) { 2501 acpi_add_table(table_offsets, tables_blob); 2502 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2503 x86ms->oem_id, x86ms->oem_table_id); 2504 } else { /* TPM_VERSION_2_0 */ 2505 acpi_add_table(table_offsets, tables_blob); 2506 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2507 x86ms->oem_id, x86ms->oem_table_id); 2508 } 2509 } 2510 #endif 2511 if (machine->numa_state->num_nodes) { 2512 acpi_add_table(table_offsets, tables_blob); 2513 build_srat(tables_blob, tables->linker, machine); 2514 if (machine->numa_state->have_numa_distance) { 2515 acpi_add_table(table_offsets, tables_blob); 2516 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2517 x86ms->oem_table_id); 2518 } 2519 if (machine->numa_state->hmat_enabled) { 2520 acpi_add_table(table_offsets, tables_blob); 2521 build_hmat(tables_blob, tables->linker, machine->numa_state, 2522 x86ms->oem_id, x86ms->oem_table_id); 2523 } 2524 } 2525 if (acpi_get_mcfg(&mcfg)) { 2526 acpi_add_table(table_offsets, tables_blob); 2527 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2528 x86ms->oem_table_id); 2529 } 2530 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2531 acpi_add_table(table_offsets, tables_blob); 2532 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2533 x86ms->oem_table_id); 2534 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2535 acpi_add_table(table_offsets, tables_blob); 2536 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2537 x86ms->oem_table_id); 2538 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2539 PCIDevice *pdev = PCI_DEVICE(iommu); 2540 2541 acpi_add_table(table_offsets, tables_blob); 2542 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2543 x86ms->oem_id, x86ms->oem_table_id); 2544 } 2545 if (machine->nvdimms_state->is_enabled) { 2546 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2547 machine->nvdimms_state, machine->ram_slots, 2548 x86ms->oem_id, x86ms->oem_table_id); 2549 } 2550 if (pcms->cxl_devices_state.is_enabled) { 2551 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2552 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2553 } 2554 2555 acpi_add_table(table_offsets, tables_blob); 2556 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2557 2558 /* Add tables supplied by user (if any) */ 2559 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2560 unsigned len = acpi_table_len(u); 2561 2562 acpi_add_table(table_offsets, tables_blob); 2563 g_array_append_vals(tables_blob, u, len); 2564 } 2565 2566 /* RSDT is pointed to by RSDP */ 2567 rsdt = tables_blob->len; 2568 build_rsdt(tables_blob, tables->linker, table_offsets, 2569 oem_id, oem_table_id); 2570 2571 /* RSDP is in FSEG memory, so allocate it separately */ 2572 { 2573 AcpiRsdpData rsdp_data = { 2574 .revision = 0, 2575 .oem_id = x86ms->oem_id, 2576 .xsdt_tbl_offset = NULL, 2577 .rsdt_tbl_offset = &rsdt, 2578 }; 2579 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2580 if (!pcmc->rsdp_in_ram) { 2581 /* We used to allocate some extra space for RSDP revision 2 but 2582 * only used the RSDP revision 0 space. The extra bytes were 2583 * zeroed out and not used. 2584 * Here we continue wasting those extra 16 bytes to make sure we 2585 * don't break migration for machine types 2.2 and older due to 2586 * RSDP blob size mismatch. 2587 */ 2588 build_append_int_noprefix(tables->rsdp, 0, 16); 2589 } 2590 } 2591 2592 /* We'll expose it all to Guest so we want to reduce 2593 * chance of size changes. 2594 * 2595 * We used to align the tables to 4k, but of course this would 2596 * too simple to be enough. 4k turned out to be too small an 2597 * alignment very soon, and in fact it is almost impossible to 2598 * keep the table size stable for all (max_cpus, max_memory_slots) 2599 * combinations. So the table size is always 64k for pc-i440fx-2.1 2600 * and we give an error if the table grows beyond that limit. 2601 * 2602 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2603 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2604 * than 2.0 and we can always pad the smaller tables with zeros. We can 2605 * then use the exact size of the 2.0 tables. 2606 * 2607 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2608 */ 2609 if (pcmc->legacy_acpi_table_size) { 2610 /* Subtracting aml_len gives the size of fixed tables. Then add the 2611 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2612 */ 2613 int legacy_aml_len = 2614 pcmc->legacy_acpi_table_size + 2615 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2616 int legacy_table_size = 2617 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2618 ACPI_BUILD_ALIGN_SIZE); 2619 if (tables_blob->len > legacy_table_size) { 2620 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2621 warn_report("ACPI table size %u exceeds %d bytes," 2622 " migration may not work", 2623 tables_blob->len, legacy_table_size); 2624 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2625 " or PCI bridges."); 2626 } 2627 g_array_set_size(tables_blob, legacy_table_size); 2628 } else { 2629 /* Make sure we have a buffer in case we need to resize the tables. */ 2630 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2631 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2632 warn_report("ACPI table size %u exceeds %d bytes," 2633 " migration may not work", 2634 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2635 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2636 " or PCI bridges."); 2637 } 2638 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2639 } 2640 2641 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2642 2643 /* Cleanup memory that's no longer used. */ 2644 g_array_free(table_offsets, true); 2645 g_free(slic_oem.id); 2646 g_free(slic_oem.table_id); 2647 } 2648 2649 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2650 { 2651 uint32_t size = acpi_data_len(data); 2652 2653 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2654 memory_region_ram_resize(mr, size, &error_abort); 2655 2656 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2657 memory_region_set_dirty(mr, 0, size); 2658 } 2659 2660 static void acpi_build_update(void *build_opaque) 2661 { 2662 AcpiBuildState *build_state = build_opaque; 2663 AcpiBuildTables tables; 2664 2665 /* No state to update or already patched? Nothing to do. */ 2666 if (!build_state || build_state->patched) { 2667 return; 2668 } 2669 build_state->patched = 1; 2670 2671 acpi_build_tables_init(&tables); 2672 2673 acpi_build(&tables, MACHINE(qdev_get_machine())); 2674 2675 acpi_ram_update(build_state->table_mr, tables.table_data); 2676 2677 if (build_state->rsdp) { 2678 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2679 } else { 2680 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2681 } 2682 2683 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2684 acpi_build_tables_cleanup(&tables, true); 2685 } 2686 2687 static void acpi_build_reset(void *build_opaque) 2688 { 2689 AcpiBuildState *build_state = build_opaque; 2690 build_state->patched = 0; 2691 } 2692 2693 static const VMStateDescription vmstate_acpi_build = { 2694 .name = "acpi_build", 2695 .version_id = 1, 2696 .minimum_version_id = 1, 2697 .fields = (VMStateField[]) { 2698 VMSTATE_UINT8(patched, AcpiBuildState), 2699 VMSTATE_END_OF_LIST() 2700 }, 2701 }; 2702 2703 void acpi_setup(void) 2704 { 2705 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2706 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2707 X86MachineState *x86ms = X86_MACHINE(pcms); 2708 AcpiBuildTables tables; 2709 AcpiBuildState *build_state; 2710 Object *vmgenid_dev; 2711 #ifdef CONFIG_TPM 2712 TPMIf *tpm; 2713 static FwCfgTPMConfig tpm_config; 2714 #endif 2715 2716 if (!x86ms->fw_cfg) { 2717 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2718 return; 2719 } 2720 2721 if (!pcms->acpi_build_enabled) { 2722 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2723 return; 2724 } 2725 2726 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2727 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2728 return; 2729 } 2730 2731 build_state = g_malloc0(sizeof *build_state); 2732 2733 acpi_build_tables_init(&tables); 2734 acpi_build(&tables, MACHINE(pcms)); 2735 2736 /* Now expose it all to Guest */ 2737 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2738 build_state, tables.table_data, 2739 ACPI_BUILD_TABLE_FILE); 2740 assert(build_state->table_mr != NULL); 2741 2742 build_state->linker_mr = 2743 acpi_add_rom_blob(acpi_build_update, build_state, 2744 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2745 2746 #ifdef CONFIG_TPM 2747 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2748 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2749 2750 tpm = tpm_find(); 2751 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2752 tpm_config = (FwCfgTPMConfig) { 2753 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2754 .tpm_version = tpm_get_version(tpm), 2755 .tpmppi_version = TPM_PPI_VERSION_1_30 2756 }; 2757 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2758 &tpm_config, sizeof tpm_config); 2759 } 2760 #endif 2761 2762 vmgenid_dev = find_vmgenid_dev(); 2763 if (vmgenid_dev) { 2764 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2765 tables.vmgenid); 2766 } 2767 2768 if (!pcmc->rsdp_in_ram) { 2769 /* 2770 * Keep for compatibility with old machine types. 2771 * Though RSDP is small, its contents isn't immutable, so 2772 * we'll update it along with the rest of tables on guest access. 2773 */ 2774 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2775 2776 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2777 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2778 acpi_build_update, NULL, build_state, 2779 build_state->rsdp, rsdp_size, true); 2780 build_state->rsdp_mr = NULL; 2781 } else { 2782 build_state->rsdp = NULL; 2783 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2784 build_state, tables.rsdp, 2785 ACPI_BUILD_RSDP_FILE); 2786 } 2787 2788 qemu_register_reset(acpi_build_reset, build_state); 2789 acpi_build_reset(build_state); 2790 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2791 2792 /* Cleanup tables but don't free the memory: we track it 2793 * in build_state. 2794 */ 2795 acpi_build_tables_cleanup(&tables, false); 2796 } 2797