1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/rtc/mc146818rtc_regs.h" 48 #include "migration/vmstate.h" 49 #include "hw/mem/memory-device.h" 50 #include "hw/mem/nvdimm.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "hw/hyperv/vmbus-bridge.h" 54 55 /* Supported chipsets: */ 56 #include "hw/southbridge/piix.h" 57 #include "hw/acpi/pcihp.h" 58 #include "hw/i386/fw_cfg.h" 59 #include "hw/i386/ich9.h" 60 #include "hw/pci/pci_bus.h" 61 #include "hw/pci-host/q35.h" 62 #include "hw/i386/x86-iommu.h" 63 64 #include "hw/acpi/aml-build.h" 65 #include "hw/acpi/utils.h" 66 #include "hw/acpi/pci.h" 67 68 #include "qom/qom-qobject.h" 69 #include "hw/i386/amd_iommu.h" 70 #include "hw/i386/intel_iommu.h" 71 72 #include "hw/acpi/ipmi.h" 73 #include "hw/acpi/hmat.h" 74 75 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 76 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 77 * a little bit, there should be plenty of free space since the DSDT 78 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 79 */ 80 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 81 #define ACPI_BUILD_ALIGN_SIZE 0x1000 82 83 #define ACPI_BUILD_TABLE_SIZE 0x20000 84 85 /* #define DEBUG_ACPI_BUILD */ 86 #ifdef DEBUG_ACPI_BUILD 87 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 88 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 89 #else 90 #define ACPI_BUILD_DPRINTF(fmt, ...) 91 #endif 92 93 typedef struct AcpiPmInfo { 94 bool s3_disabled; 95 bool s4_disabled; 96 bool pcihp_bridge_en; 97 bool smi_on_cpuhp; 98 bool smi_on_cpu_unplug; 99 bool pcihp_root_en; 100 uint8_t s4_val; 101 AcpiFadtData fadt; 102 uint16_t cpu_hp_io_base; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 #ifdef CONFIG_TPM 111 TPMVersion tpm_version; 112 #endif 113 const unsigned char *dsdt_code; 114 unsigned dsdt_size; 115 uint16_t pvpanic_port; 116 uint16_t applesmc_io_base; 117 } AcpiMiscInfo; 118 119 typedef struct AcpiBuildPciBusHotplugState { 120 GArray *device_table; 121 GArray *notify_table; 122 struct AcpiBuildPciBusHotplugState *parent; 123 bool pcihp_bridge_en; 124 } AcpiBuildPciBusHotplugState; 125 126 typedef struct FwCfgTPMConfig { 127 uint32_t tpmppi_address; 128 uint8_t tpm_version; 129 uint8_t tpmppi_version; 130 } QEMU_PACKED FwCfgTPMConfig; 131 132 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 133 134 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 135 .space_id = AML_AS_SYSTEM_IO, 136 .address = NVDIMM_ACPI_IO_BASE, 137 .bit_width = NVDIMM_ACPI_IO_LEN << 3 138 }; 139 140 static void init_common_fadt_data(MachineState *ms, Object *o, 141 AcpiFadtData *data) 142 { 143 X86MachineState *x86ms = X86_MACHINE(ms); 144 /* 145 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 146 * behavior for compatibility irrelevant to smm_enabled, which doesn't 147 * comforms to ACPI spec. 148 */ 149 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 150 true : x86_machine_is_smm_enabled(x86ms); 151 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 152 AmlAddressSpace as = AML_AS_SYSTEM_IO; 153 AcpiFadtData fadt = { 154 .rev = 3, 155 .flags = 156 (1 << ACPI_FADT_F_WBINVD) | 157 (1 << ACPI_FADT_F_PROC_C1) | 158 (1 << ACPI_FADT_F_SLP_BUTTON) | 159 (1 << ACPI_FADT_F_RTC_S4) | 160 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 161 /* APIC destination mode ("Flat Logical") has an upper limit of 8 162 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 163 * used 164 */ 165 ((ms->smp.max_cpus > 8) ? 166 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 167 .int_model = 1 /* Multiple APIC */, 168 .rtc_century = RTC_CENTURY, 169 .plvl2_lat = 0xfff /* C2 state not supported */, 170 .plvl3_lat = 0xfff /* C3 state not supported */, 171 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 172 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 173 .acpi_enable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 176 0, 177 .acpi_disable_cmd = 178 smm_enabled ? 179 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 180 0, 181 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 182 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 183 .address = io + 0x04 }, 184 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 185 .gpe0_blk = { .space_id = as, .bit_width = 186 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 187 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 188 }, 189 }; 190 *data = fadt; 191 } 192 193 static Object *object_resolve_type_unambiguous(const char *typename) 194 { 195 bool ambig; 196 Object *o = object_resolve_path_type("", typename, &ambig); 197 198 if (ambig || !o) { 199 return NULL; 200 } 201 return o; 202 } 203 204 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 205 { 206 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 207 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 208 Object *obj = piix ? piix : lpc; 209 QObject *o; 210 pm->cpu_hp_io_base = 0; 211 pm->pcihp_io_base = 0; 212 pm->pcihp_io_len = 0; 213 pm->smi_on_cpuhp = false; 214 pm->smi_on_cpu_unplug = false; 215 216 assert(obj); 217 init_common_fadt_data(machine, obj, &pm->fadt); 218 if (piix) { 219 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 220 pm->fadt.rev = 1; 221 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 222 } 223 if (lpc) { 224 uint64_t smi_features = object_property_get_uint(lpc, 225 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 226 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 227 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 228 pm->fadt.reset_reg = r; 229 pm->fadt.reset_val = 0xf; 230 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 231 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 232 pm->smi_on_cpuhp = 233 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 234 pm->smi_on_cpu_unplug = 235 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 236 } 237 pm->pcihp_io_base = 238 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 239 pm->pcihp_io_len = 240 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 241 242 /* The above need not be conditional on machine type because the reset port 243 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 244 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 245 246 /* Fill in optional s3/s4 related properties */ 247 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 248 if (o) { 249 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 250 } else { 251 pm->s3_disabled = false; 252 } 253 qobject_unref(o); 254 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 255 if (o) { 256 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 257 } else { 258 pm->s4_disabled = false; 259 } 260 qobject_unref(o); 261 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 262 if (o) { 263 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 264 } else { 265 pm->s4_val = false; 266 } 267 qobject_unref(o); 268 269 pm->pcihp_bridge_en = 270 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 271 NULL); 272 pm->pcihp_root_en = 273 object_property_get_bool(obj, "acpi-root-pci-hotplug", 274 NULL); 275 } 276 277 static void acpi_get_misc_info(AcpiMiscInfo *info) 278 { 279 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 280 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 281 assert(!!piix != !!lpc); 282 283 if (piix) { 284 info->is_piix4 = true; 285 } 286 if (lpc) { 287 info->is_piix4 = false; 288 } 289 290 info->has_hpet = hpet_find(); 291 #ifdef CONFIG_TPM 292 info->tpm_version = tpm_get_version(tpm_find()); 293 #endif 294 info->pvpanic_port = pvpanic_port(); 295 info->applesmc_io_base = applesmc_port(); 296 } 297 298 /* 299 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 300 * On i386 arch we only have two pci hosts, so we can look only for them. 301 */ 302 Object *acpi_get_i386_pci_host(void) 303 { 304 PCIHostState *host; 305 306 host = OBJECT_CHECK(PCIHostState, 307 object_resolve_path("/machine/i440fx", NULL), 308 TYPE_PCI_HOST_BRIDGE); 309 if (!host) { 310 host = OBJECT_CHECK(PCIHostState, 311 object_resolve_path("/machine/q35", NULL), 312 TYPE_PCI_HOST_BRIDGE); 313 } 314 315 return OBJECT(host); 316 } 317 318 static void acpi_get_pci_holes(Range *hole, Range *hole64) 319 { 320 Object *pci_host; 321 322 pci_host = acpi_get_i386_pci_host(); 323 324 if (!pci_host) { 325 return; 326 } 327 328 range_set_bounds1(hole, 329 object_property_get_uint(pci_host, 330 PCI_HOST_PROP_PCI_HOLE_START, 331 NULL), 332 object_property_get_uint(pci_host, 333 PCI_HOST_PROP_PCI_HOLE_END, 334 NULL)); 335 range_set_bounds1(hole64, 336 object_property_get_uint(pci_host, 337 PCI_HOST_PROP_PCI_HOLE64_START, 338 NULL), 339 object_property_get_uint(pci_host, 340 PCI_HOST_PROP_PCI_HOLE64_END, 341 NULL)); 342 } 343 344 static void acpi_align_size(GArray *blob, unsigned align) 345 { 346 /* Align size to multiple of given size. This reduces the chance 347 * we need to change size in the future (breaking cross version migration). 348 */ 349 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 350 } 351 352 /* FACS */ 353 static void 354 build_facs(GArray *table_data) 355 { 356 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 357 memcpy(&facs->signature, "FACS", 4); 358 facs->length = cpu_to_le32(sizeof(*facs)); 359 } 360 361 static void build_append_pcihp_notify_entry(Aml *method, int slot) 362 { 363 Aml *if_ctx; 364 int32_t devfn = PCI_DEVFN(slot, 0); 365 366 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 367 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 368 aml_append(method, if_ctx); 369 } 370 371 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 372 bool pcihp_bridge_en) 373 { 374 Aml *dev, *notify_method = NULL, *method; 375 QObject *bsel; 376 PCIBus *sec; 377 int devfn; 378 379 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 380 if (bsel) { 381 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 382 383 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 384 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 385 } 386 387 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 388 DeviceClass *dc; 389 PCIDeviceClass *pc; 390 PCIDevice *pdev = bus->devices[devfn]; 391 int slot = PCI_SLOT(devfn); 392 int func = PCI_FUNC(devfn); 393 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 394 int adr = slot << 16 | func; 395 bool hotplug_enabled_dev; 396 bool bridge_in_acpi; 397 bool cold_plugged_bridge; 398 399 if (!pdev) { 400 /* 401 * add hotplug slots for non present devices. 402 * hotplug is supported only for non-multifunction device 403 * so generate device description only for function 0 404 */ 405 if (bsel && !func) { 406 if (pci_bus_is_express(bus) && slot > 0) { 407 break; 408 } 409 dev = aml_device("S%.02X", devfn); 410 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 411 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 412 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 413 aml_append(method, 414 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 415 ); 416 aml_append(dev, method); 417 method = aml_method("_DSM", 4, AML_SERIALIZED); 418 aml_append(method, 419 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 420 aml_arg(2), aml_arg(3), 421 aml_name("BSEL"), aml_name("_SUN"))) 422 ); 423 aml_append(dev, method); 424 aml_append(parent_scope, dev); 425 426 build_append_pcihp_notify_entry(notify_method, slot); 427 } 428 continue; 429 } 430 431 pc = PCI_DEVICE_GET_CLASS(pdev); 432 dc = DEVICE_GET_CLASS(pdev); 433 434 /* 435 * Cold plugged bridges aren't themselves hot-pluggable. 436 * Hotplugged bridges *are* hot-pluggable. 437 */ 438 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 439 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 440 441 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 442 443 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 444 continue; 445 } 446 447 /* 448 * allow describing coldplugged bridges in ACPI even if they are not 449 * on function 0, as they are not unpluggable, for all other devices 450 * generate description only for function 0 per slot 451 */ 452 if (func && !bridge_in_acpi) { 453 continue; 454 } 455 456 /* start to compose PCI device descriptor */ 457 dev = aml_device("S%.02X", devfn); 458 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 459 460 if (bsel) { 461 /* 462 * Can't declare _SUN here for every device as it changes 'slot' 463 * enumeration order in linux kernel, so use another variable for it 464 */ 465 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 466 method = aml_method("_DSM", 4, AML_SERIALIZED); 467 aml_append(method, aml_return( 468 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 469 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 470 )); 471 aml_append(dev, method); 472 } 473 474 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 475 /* add VGA specific AML methods */ 476 int s3d; 477 478 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 479 s3d = 3; 480 } else { 481 s3d = 0; 482 } 483 484 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 485 aml_append(method, aml_return(aml_int(0))); 486 aml_append(dev, method); 487 488 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 489 aml_append(method, aml_return(aml_int(0))); 490 aml_append(dev, method); 491 492 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 493 aml_append(method, aml_return(aml_int(s3d))); 494 aml_append(dev, method); 495 } else if (hotplug_enabled_dev) { 496 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 497 /* add _EJ0 to make slot hotpluggable */ 498 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 499 aml_append(method, 500 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 501 ); 502 aml_append(dev, method); 503 504 if (bsel) { 505 build_append_pcihp_notify_entry(notify_method, slot); 506 } 507 } else if (bridge_in_acpi) { 508 /* 509 * device is coldplugged bridge, 510 * add child device descriptions into its scope 511 */ 512 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 513 514 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 515 } 516 /* device descriptor has been composed, add it into parent context */ 517 aml_append(parent_scope, dev); 518 } 519 520 if (bsel) { 521 aml_append(parent_scope, notify_method); 522 } 523 524 /* Append PCNT method to notify about events on local and child buses. 525 * Add this method for root bus only when hotplug is enabled since DSDT 526 * expects it. 527 */ 528 if (bsel || pcihp_bridge_en) { 529 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 530 531 /* If bus supports hotplug select it and notify about local events */ 532 if (bsel) { 533 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 534 535 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 536 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 537 aml_int(1))); /* Device Check */ 538 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 539 aml_int(3))); /* Eject Request */ 540 } 541 542 /* Notify about child bus events in any case */ 543 if (pcihp_bridge_en) { 544 QLIST_FOREACH(sec, &bus->child, sibling) { 545 if (pci_bus_is_root(sec)) { 546 continue; 547 } 548 549 aml_append(method, aml_name("^S%.02X.PCNT", 550 sec->parent_dev->devfn)); 551 } 552 } 553 554 aml_append(parent_scope, method); 555 } 556 qobject_unref(bsel); 557 } 558 559 Aml *aml_pci_device_dsm(void) 560 { 561 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 562 Aml *acpi_index = aml_local(0); 563 Aml *zero = aml_int(0); 564 Aml *bnum = aml_arg(4); 565 Aml *func = aml_arg(2); 566 Aml *rev = aml_arg(1); 567 Aml *sun = aml_arg(5); 568 569 method = aml_method("PDSM", 6, AML_SERIALIZED); 570 571 /* 572 * PCI Firmware Specification 3.1 573 * 4.6. _DSM Definitions for PCI 574 */ 575 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 576 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 577 { 578 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index)); 579 ifctx1 = aml_if(aml_equal(func, zero)); 580 { 581 uint8_t byte_list[1]; 582 583 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 584 { 585 /* 586 * advertise function 7 if device has acpi-index 587 * acpi_index values: 588 * 0: not present (default value) 589 * FFFFFFFF: not supported (old QEMU without PIDX reg) 590 * other: device's acpi-index 591 */ 592 ifctx3 = aml_if(aml_lnot( 593 aml_or(aml_equal(acpi_index, zero), 594 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 595 )); 596 { 597 byte_list[0] = 598 1 /* have supported functions */ | 599 1 << 7 /* support for function 7 */ 600 ; 601 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 602 } 603 aml_append(ifctx2, ifctx3); 604 } 605 aml_append(ifctx1, ifctx2); 606 607 byte_list[0] = 0; /* nothing supported */ 608 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 609 } 610 aml_append(ifctx, ifctx1); 611 elsectx = aml_else(); 612 /* 613 * PCI Firmware Specification 3.1 614 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 615 * Operating Systems 616 */ 617 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 618 { 619 Aml *pkg = aml_package(2); 620 Aml *ret = aml_local(1); 621 622 aml_append(pkg, zero); 623 /* 624 * optional, if not impl. should return null string 625 */ 626 aml_append(pkg, aml_string("%s", "")); 627 aml_append(ifctx1, aml_store(pkg, ret)); 628 /* 629 * update acpi-index to actual value 630 */ 631 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 632 aml_append(ifctx1, aml_return(ret)); 633 } 634 aml_append(elsectx, ifctx1); 635 aml_append(ifctx, elsectx); 636 } 637 aml_append(method, ifctx); 638 return method; 639 } 640 641 /** 642 * build_prt_entry: 643 * @link_name: link name for PCI route entry 644 * 645 * build AML package containing a PCI route entry for @link_name 646 */ 647 static Aml *build_prt_entry(const char *link_name) 648 { 649 Aml *a_zero = aml_int(0); 650 Aml *pkg = aml_package(4); 651 aml_append(pkg, a_zero); 652 aml_append(pkg, a_zero); 653 aml_append(pkg, aml_name("%s", link_name)); 654 aml_append(pkg, a_zero); 655 return pkg; 656 } 657 658 /* 659 * initialize_route - Initialize the interrupt routing rule 660 * through a specific LINK: 661 * if (lnk_idx == idx) 662 * route using link 'link_name' 663 */ 664 static Aml *initialize_route(Aml *route, const char *link_name, 665 Aml *lnk_idx, int idx) 666 { 667 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 668 Aml *pkg = build_prt_entry(link_name); 669 670 aml_append(if_ctx, aml_store(pkg, route)); 671 672 return if_ctx; 673 } 674 675 /* 676 * build_prt - Define interrupt rounting rules 677 * 678 * Returns an array of 128 routes, one for each device, 679 * based on device location. 680 * The main goal is to equaly distribute the interrupts 681 * over the 4 existing ACPI links (works only for i440fx). 682 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 683 * 684 */ 685 static Aml *build_prt(bool is_pci0_prt) 686 { 687 Aml *method, *while_ctx, *pin, *res; 688 689 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 690 res = aml_local(0); 691 pin = aml_local(1); 692 aml_append(method, aml_store(aml_package(128), res)); 693 aml_append(method, aml_store(aml_int(0), pin)); 694 695 /* while (pin < 128) */ 696 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 697 { 698 Aml *slot = aml_local(2); 699 Aml *lnk_idx = aml_local(3); 700 Aml *route = aml_local(4); 701 702 /* slot = pin >> 2 */ 703 aml_append(while_ctx, 704 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 705 /* lnk_idx = (slot + pin) & 3 */ 706 aml_append(while_ctx, 707 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 708 lnk_idx)); 709 710 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 711 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 712 if (is_pci0_prt) { 713 Aml *if_device_1, *if_pin_4, *else_pin_4; 714 715 /* device 1 is the power-management device, needs SCI */ 716 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 717 { 718 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 719 { 720 aml_append(if_pin_4, 721 aml_store(build_prt_entry("LNKS"), route)); 722 } 723 aml_append(if_device_1, if_pin_4); 724 else_pin_4 = aml_else(); 725 { 726 aml_append(else_pin_4, 727 aml_store(build_prt_entry("LNKA"), route)); 728 } 729 aml_append(if_device_1, else_pin_4); 730 } 731 aml_append(while_ctx, if_device_1); 732 } else { 733 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 734 } 735 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 736 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 737 738 /* route[0] = 0x[slot]FFFF */ 739 aml_append(while_ctx, 740 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 741 NULL), 742 aml_index(route, aml_int(0)))); 743 /* route[1] = pin & 3 */ 744 aml_append(while_ctx, 745 aml_store(aml_and(pin, aml_int(3), NULL), 746 aml_index(route, aml_int(1)))); 747 /* res[pin] = route */ 748 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 749 /* pin++ */ 750 aml_append(while_ctx, aml_increment(pin)); 751 } 752 aml_append(method, while_ctx); 753 /* return res*/ 754 aml_append(method, aml_return(res)); 755 756 return method; 757 } 758 759 static void build_hpet_aml(Aml *table) 760 { 761 Aml *crs; 762 Aml *field; 763 Aml *method; 764 Aml *if_ctx; 765 Aml *scope = aml_scope("_SB"); 766 Aml *dev = aml_device("HPET"); 767 Aml *zero = aml_int(0); 768 Aml *id = aml_local(0); 769 Aml *period = aml_local(1); 770 771 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 772 aml_append(dev, aml_name_decl("_UID", zero)); 773 774 aml_append(dev, 775 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 776 HPET_LEN)); 777 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 778 aml_append(field, aml_named_field("VEND", 32)); 779 aml_append(field, aml_named_field("PRD", 32)); 780 aml_append(dev, field); 781 782 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 783 aml_append(method, aml_store(aml_name("VEND"), id)); 784 aml_append(method, aml_store(aml_name("PRD"), period)); 785 aml_append(method, aml_shiftright(id, aml_int(16), id)); 786 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 787 aml_equal(id, aml_int(0xffff)))); 788 { 789 aml_append(if_ctx, aml_return(zero)); 790 } 791 aml_append(method, if_ctx); 792 793 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 794 aml_lgreater(period, aml_int(100000000)))); 795 { 796 aml_append(if_ctx, aml_return(zero)); 797 } 798 aml_append(method, if_ctx); 799 800 aml_append(method, aml_return(aml_int(0x0F))); 801 aml_append(dev, method); 802 803 crs = aml_resource_template(); 804 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 805 aml_append(dev, aml_name_decl("_CRS", crs)); 806 807 aml_append(scope, dev); 808 aml_append(table, scope); 809 } 810 811 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 812 { 813 Aml *dev; 814 Aml *method; 815 Aml *crs; 816 817 dev = aml_device("VMBS"); 818 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 819 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 820 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 821 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 822 823 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 824 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 825 aml_name("STA"))); 826 aml_append(dev, method); 827 828 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 829 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 830 aml_name("STA"))); 831 aml_append(dev, method); 832 833 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 834 aml_append(method, aml_return(aml_name("STA"))); 835 aml_append(dev, method); 836 837 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 838 839 crs = aml_resource_template(); 840 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 841 aml_append(dev, aml_name_decl("_CRS", crs)); 842 843 return dev; 844 } 845 846 static void build_isa_devices_aml(Aml *table) 847 { 848 bool ambiguous; 849 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 850 Aml *scope; 851 852 assert(obj && !ambiguous); 853 854 scope = aml_scope("_SB.PCI0.ISA"); 855 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 856 isa_build_aml(ISA_BUS(obj), scope); 857 858 aml_append(table, scope); 859 } 860 861 static void build_dbg_aml(Aml *table) 862 { 863 Aml *field; 864 Aml *method; 865 Aml *while_ctx; 866 Aml *scope = aml_scope("\\"); 867 Aml *buf = aml_local(0); 868 Aml *len = aml_local(1); 869 Aml *idx = aml_local(2); 870 871 aml_append(scope, 872 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 873 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 874 aml_append(field, aml_named_field("DBGB", 8)); 875 aml_append(scope, field); 876 877 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 878 879 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 880 aml_append(method, aml_to_buffer(buf, buf)); 881 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 882 aml_append(method, aml_store(aml_int(0), idx)); 883 884 while_ctx = aml_while(aml_lless(idx, len)); 885 aml_append(while_ctx, 886 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 887 aml_append(while_ctx, aml_increment(idx)); 888 aml_append(method, while_ctx); 889 890 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 891 aml_append(scope, method); 892 893 aml_append(table, scope); 894 } 895 896 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 897 { 898 Aml *dev; 899 Aml *crs; 900 Aml *method; 901 uint32_t irqs[] = {5, 10, 11}; 902 903 dev = aml_device("%s", name); 904 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 905 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 906 907 crs = aml_resource_template(); 908 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 909 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 910 aml_append(dev, aml_name_decl("_PRS", crs)); 911 912 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 913 aml_append(method, aml_return(aml_call1("IQST", reg))); 914 aml_append(dev, method); 915 916 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 917 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 918 aml_append(dev, method); 919 920 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 921 aml_append(method, aml_return(aml_call1("IQCR", reg))); 922 aml_append(dev, method); 923 924 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 925 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 926 aml_append(method, aml_store(aml_name("PRRI"), reg)); 927 aml_append(dev, method); 928 929 return dev; 930 } 931 932 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 933 { 934 Aml *dev; 935 Aml *crs; 936 Aml *method; 937 uint32_t irqs; 938 939 dev = aml_device("%s", name); 940 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 941 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 942 943 crs = aml_resource_template(); 944 irqs = gsi; 945 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 946 AML_SHARED, &irqs, 1)); 947 aml_append(dev, aml_name_decl("_PRS", crs)); 948 949 aml_append(dev, aml_name_decl("_CRS", crs)); 950 951 /* 952 * _DIS can be no-op because the interrupt cannot be disabled. 953 */ 954 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 955 aml_append(dev, method); 956 957 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 958 aml_append(dev, method); 959 960 return dev; 961 } 962 963 /* _CRS method - get current settings */ 964 static Aml *build_iqcr_method(bool is_piix4) 965 { 966 Aml *if_ctx; 967 uint32_t irqs; 968 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 969 Aml *crs = aml_resource_template(); 970 971 irqs = 0; 972 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 973 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 974 aml_append(method, aml_name_decl("PRR0", crs)); 975 976 aml_append(method, 977 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 978 979 if (is_piix4) { 980 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 981 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 982 aml_append(method, if_ctx); 983 } else { 984 aml_append(method, 985 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 986 aml_name("PRRI"))); 987 } 988 989 aml_append(method, aml_return(aml_name("PRR0"))); 990 return method; 991 } 992 993 /* _STA method - get status */ 994 static Aml *build_irq_status_method(void) 995 { 996 Aml *if_ctx; 997 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 998 999 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1000 aml_append(if_ctx, aml_return(aml_int(0x09))); 1001 aml_append(method, if_ctx); 1002 aml_append(method, aml_return(aml_int(0x0B))); 1003 return method; 1004 } 1005 1006 static void build_piix4_pci0_int(Aml *table) 1007 { 1008 Aml *dev; 1009 Aml *crs; 1010 Aml *field; 1011 Aml *method; 1012 uint32_t irqs; 1013 Aml *sb_scope = aml_scope("_SB"); 1014 Aml *pci0_scope = aml_scope("PCI0"); 1015 1016 aml_append(pci0_scope, build_prt(true)); 1017 aml_append(sb_scope, pci0_scope); 1018 1019 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1020 aml_append(field, aml_named_field("PRQ0", 8)); 1021 aml_append(field, aml_named_field("PRQ1", 8)); 1022 aml_append(field, aml_named_field("PRQ2", 8)); 1023 aml_append(field, aml_named_field("PRQ3", 8)); 1024 aml_append(sb_scope, field); 1025 1026 aml_append(sb_scope, build_irq_status_method()); 1027 aml_append(sb_scope, build_iqcr_method(true)); 1028 1029 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1030 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1031 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1032 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1033 1034 dev = aml_device("LNKS"); 1035 { 1036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1037 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1038 1039 crs = aml_resource_template(); 1040 irqs = 9; 1041 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1042 AML_ACTIVE_HIGH, AML_SHARED, 1043 &irqs, 1)); 1044 aml_append(dev, aml_name_decl("_PRS", crs)); 1045 1046 /* The SCI cannot be disabled and is always attached to GSI 9, 1047 * so these are no-ops. We only need this link to override the 1048 * polarity to active high and match the content of the MADT. 1049 */ 1050 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1051 aml_append(method, aml_return(aml_int(0x0b))); 1052 aml_append(dev, method); 1053 1054 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_name("_PRS"))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1062 aml_append(dev, method); 1063 } 1064 aml_append(sb_scope, dev); 1065 1066 aml_append(table, sb_scope); 1067 } 1068 1069 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1070 { 1071 int i; 1072 int head; 1073 Aml *pkg; 1074 char base = name[3] < 'E' ? 'A' : 'E'; 1075 char *s = g_strdup(name); 1076 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1077 1078 assert(strlen(s) == 4); 1079 1080 head = name[3] - base; 1081 for (i = 0; i < 4; i++) { 1082 if (head + i > 3) { 1083 head = i * -1; 1084 } 1085 s[3] = base + head + i; 1086 pkg = aml_package(4); 1087 aml_append(pkg, a_nr); 1088 aml_append(pkg, aml_int(i)); 1089 aml_append(pkg, aml_name("%s", s)); 1090 aml_append(pkg, aml_int(0)); 1091 aml_append(ctx, pkg); 1092 } 1093 g_free(s); 1094 } 1095 1096 static Aml *build_q35_routing_table(const char *str) 1097 { 1098 int i; 1099 Aml *pkg; 1100 char *name = g_strdup_printf("%s ", str); 1101 1102 pkg = aml_package(128); 1103 for (i = 0; i < 0x18; i++) { 1104 name[3] = 'E' + (i & 0x3); 1105 append_q35_prt_entry(pkg, i, name); 1106 } 1107 1108 name[3] = 'E'; 1109 append_q35_prt_entry(pkg, 0x18, name); 1110 1111 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1112 for (i = 0x0019; i < 0x1e; i++) { 1113 name[3] = 'A'; 1114 append_q35_prt_entry(pkg, i, name); 1115 } 1116 1117 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1118 name[3] = 'E'; 1119 append_q35_prt_entry(pkg, 0x1e, name); 1120 name[3] = 'A'; 1121 append_q35_prt_entry(pkg, 0x1f, name); 1122 1123 g_free(name); 1124 return pkg; 1125 } 1126 1127 static void build_q35_pci0_int(Aml *table) 1128 { 1129 Aml *field; 1130 Aml *method; 1131 Aml *sb_scope = aml_scope("_SB"); 1132 Aml *pci0_scope = aml_scope("PCI0"); 1133 1134 /* Zero => PIC mode, One => APIC Mode */ 1135 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1136 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1137 { 1138 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1139 } 1140 aml_append(table, method); 1141 1142 aml_append(pci0_scope, 1143 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1144 aml_append(pci0_scope, 1145 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1146 1147 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1148 { 1149 Aml *if_ctx; 1150 Aml *else_ctx; 1151 1152 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1153 section 6.2.8.1 */ 1154 /* Note: we provide the same info as the PCI routing 1155 table of the Bochs BIOS */ 1156 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1157 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1158 aml_append(method, if_ctx); 1159 else_ctx = aml_else(); 1160 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1161 aml_append(method, else_ctx); 1162 } 1163 aml_append(pci0_scope, method); 1164 aml_append(sb_scope, pci0_scope); 1165 1166 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1167 aml_append(field, aml_named_field("PRQA", 8)); 1168 aml_append(field, aml_named_field("PRQB", 8)); 1169 aml_append(field, aml_named_field("PRQC", 8)); 1170 aml_append(field, aml_named_field("PRQD", 8)); 1171 aml_append(field, aml_reserved_field(0x20)); 1172 aml_append(field, aml_named_field("PRQE", 8)); 1173 aml_append(field, aml_named_field("PRQF", 8)); 1174 aml_append(field, aml_named_field("PRQG", 8)); 1175 aml_append(field, aml_named_field("PRQH", 8)); 1176 aml_append(sb_scope, field); 1177 1178 aml_append(sb_scope, build_irq_status_method()); 1179 aml_append(sb_scope, build_iqcr_method(false)); 1180 1181 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1182 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1183 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1184 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1185 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1186 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1187 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1188 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1189 1190 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1191 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1192 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1193 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1194 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1195 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1196 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1197 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1198 1199 aml_append(table, sb_scope); 1200 } 1201 1202 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1203 { 1204 Aml *dev; 1205 Aml *resource_template; 1206 1207 /* DRAM controller */ 1208 dev = aml_device("DRAC"); 1209 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1210 1211 resource_template = aml_resource_template(); 1212 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1213 aml_append(resource_template, 1214 aml_qword_memory(AML_POS_DECODE, 1215 AML_MIN_FIXED, 1216 AML_MAX_FIXED, 1217 AML_NON_CACHEABLE, 1218 AML_READ_WRITE, 1219 0x0000000000000000, 1220 mcfg->base, 1221 mcfg->base + mcfg->size - 1, 1222 0x0000000000000000, 1223 mcfg->size)); 1224 } else { 1225 aml_append(resource_template, 1226 aml_dword_memory(AML_POS_DECODE, 1227 AML_MIN_FIXED, 1228 AML_MAX_FIXED, 1229 AML_NON_CACHEABLE, 1230 AML_READ_WRITE, 1231 0x0000000000000000, 1232 mcfg->base, 1233 mcfg->base + mcfg->size - 1, 1234 0x0000000000000000, 1235 mcfg->size)); 1236 } 1237 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1238 1239 return dev; 1240 } 1241 1242 static void build_q35_isa_bridge(Aml *table) 1243 { 1244 Aml *dev; 1245 Aml *scope; 1246 1247 scope = aml_scope("_SB.PCI0"); 1248 dev = aml_device("ISA"); 1249 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1250 1251 /* ICH9 PCI to ISA irq remapping */ 1252 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1253 aml_int(0x60), 0x0C)); 1254 1255 aml_append(scope, dev); 1256 aml_append(table, scope); 1257 } 1258 1259 static void build_piix4_isa_bridge(Aml *table) 1260 { 1261 Aml *dev; 1262 Aml *scope; 1263 1264 scope = aml_scope("_SB.PCI0"); 1265 dev = aml_device("ISA"); 1266 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1267 1268 /* PIIX PCI to ISA irq remapping */ 1269 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1270 aml_int(0x60), 0x04)); 1271 1272 aml_append(scope, dev); 1273 aml_append(table, scope); 1274 } 1275 1276 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1277 { 1278 Aml *scope; 1279 Aml *field; 1280 Aml *method; 1281 1282 scope = aml_scope("_SB.PCI0"); 1283 1284 aml_append(scope, 1285 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1286 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1287 aml_append(field, aml_named_field("PCIU", 32)); 1288 aml_append(field, aml_named_field("PCID", 32)); 1289 aml_append(scope, field); 1290 1291 aml_append(scope, 1292 aml_operation_region("SEJ", AML_SYSTEM_IO, 1293 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1294 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1295 aml_append(field, aml_named_field("B0EJ", 32)); 1296 aml_append(scope, field); 1297 1298 aml_append(scope, 1299 aml_operation_region("BNMR", AML_SYSTEM_IO, 1300 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1301 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1302 aml_append(field, aml_named_field("BNUM", 32)); 1303 aml_append(field, aml_named_field("PIDX", 32)); 1304 aml_append(scope, field); 1305 1306 aml_append(scope, aml_mutex("BLCK", 0)); 1307 1308 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1309 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1310 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1311 aml_append(method, 1312 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1313 aml_append(method, aml_release(aml_name("BLCK"))); 1314 aml_append(method, aml_return(aml_int(0))); 1315 aml_append(scope, method); 1316 1317 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1318 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1319 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1320 aml_append(method, 1321 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1322 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1323 aml_append(method, aml_release(aml_name("BLCK"))); 1324 aml_append(method, aml_return(aml_local(0))); 1325 aml_append(scope, method); 1326 1327 aml_append(scope, aml_pci_device_dsm()); 1328 1329 aml_append(table, scope); 1330 } 1331 1332 static Aml *build_q35_osc_method(void) 1333 { 1334 Aml *if_ctx; 1335 Aml *if_ctx2; 1336 Aml *else_ctx; 1337 Aml *method; 1338 Aml *a_cwd1 = aml_name("CDW1"); 1339 Aml *a_ctrl = aml_local(0); 1340 1341 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1342 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1343 1344 if_ctx = aml_if(aml_equal( 1345 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1346 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1347 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1348 1349 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1350 1351 /* 1352 * Always allow native PME, AER (no dependencies) 1353 * Allow SHPC (PCI bridges can have SHPC controller) 1354 */ 1355 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1356 1357 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1358 /* Unknown revision */ 1359 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1360 aml_append(if_ctx, if_ctx2); 1361 1362 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1363 /* Capabilities bits were masked */ 1364 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1365 aml_append(if_ctx, if_ctx2); 1366 1367 /* Update DWORD3 in the buffer */ 1368 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1369 aml_append(method, if_ctx); 1370 1371 else_ctx = aml_else(); 1372 /* Unrecognized UUID */ 1373 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1374 aml_append(method, else_ctx); 1375 1376 aml_append(method, aml_return(aml_arg(3))); 1377 return method; 1378 } 1379 1380 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1381 { 1382 Aml *scope = aml_scope("_SB.PCI0"); 1383 Aml *dev = aml_device("SMB0"); 1384 1385 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1386 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1387 aml_append(scope, dev); 1388 aml_append(table, scope); 1389 } 1390 1391 static void 1392 build_dsdt(GArray *table_data, BIOSLinker *linker, 1393 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1394 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1395 { 1396 CrsRangeEntry *entry; 1397 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1398 CrsRangeSet crs_range_set; 1399 PCMachineState *pcms = PC_MACHINE(machine); 1400 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1401 X86MachineState *x86ms = X86_MACHINE(machine); 1402 AcpiMcfgInfo mcfg; 1403 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1404 uint32_t nr_mem = machine->ram_slots; 1405 int root_bus_limit = 0xFF; 1406 PCIBus *bus = NULL; 1407 #ifdef CONFIG_TPM 1408 TPMIf *tpm = tpm_find(); 1409 #endif 1410 int i; 1411 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1412 1413 dsdt = init_aml_allocator(); 1414 1415 /* Reserve space for header */ 1416 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1417 1418 build_dbg_aml(dsdt); 1419 if (misc->is_piix4) { 1420 sb_scope = aml_scope("_SB"); 1421 dev = aml_device("PCI0"); 1422 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1423 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1424 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1425 aml_append(sb_scope, dev); 1426 aml_append(dsdt, sb_scope); 1427 1428 if (misc->has_hpet) { 1429 build_hpet_aml(dsdt); 1430 } 1431 build_piix4_isa_bridge(dsdt); 1432 build_isa_devices_aml(dsdt); 1433 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1434 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1435 } 1436 build_piix4_pci0_int(dsdt); 1437 } else { 1438 sb_scope = aml_scope("_SB"); 1439 dev = aml_device("PCI0"); 1440 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1441 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1442 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1443 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1444 aml_append(dev, build_q35_osc_method()); 1445 aml_append(sb_scope, dev); 1446 if (mcfg_valid) { 1447 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1448 } 1449 1450 if (pm->smi_on_cpuhp) { 1451 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1452 dev = aml_device("PCI0.SMI0"); 1453 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1454 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1455 crs = aml_resource_template(); 1456 aml_append(crs, 1457 aml_io( 1458 AML_DECODE16, 1459 ACPI_PORT_SMI_CMD, 1460 ACPI_PORT_SMI_CMD, 1461 1, 1462 2) 1463 ); 1464 aml_append(dev, aml_name_decl("_CRS", crs)); 1465 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1466 aml_int(ACPI_PORT_SMI_CMD), 2)); 1467 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1468 AML_WRITE_AS_ZEROS); 1469 aml_append(field, aml_named_field("SMIC", 8)); 1470 aml_append(field, aml_reserved_field(8)); 1471 aml_append(dev, field); 1472 aml_append(sb_scope, dev); 1473 } 1474 1475 aml_append(dsdt, sb_scope); 1476 1477 if (misc->has_hpet) { 1478 build_hpet_aml(dsdt); 1479 } 1480 build_q35_isa_bridge(dsdt); 1481 build_isa_devices_aml(dsdt); 1482 if (pm->pcihp_bridge_en) { 1483 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1484 } 1485 build_q35_pci0_int(dsdt); 1486 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1487 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1488 } 1489 } 1490 1491 if (vmbus_bridge) { 1492 sb_scope = aml_scope("_SB"); 1493 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1494 aml_append(dsdt, sb_scope); 1495 } 1496 1497 if (pcmc->legacy_cpu_hotplug) { 1498 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1499 } else { 1500 CPUHotplugFeatures opts = { 1501 .acpi_1_compatible = true, .has_legacy_cphp = true, 1502 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1503 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1504 }; 1505 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1506 "\\_SB.PCI0", "\\_GPE._E02"); 1507 } 1508 1509 if (pcms->memhp_io_base && nr_mem) { 1510 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1511 "\\_GPE._E03", AML_SYSTEM_IO, 1512 pcms->memhp_io_base); 1513 } 1514 1515 scope = aml_scope("_GPE"); 1516 { 1517 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1518 1519 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1520 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1521 aml_append(method, 1522 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1523 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1524 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1525 aml_append(scope, method); 1526 } 1527 1528 if (machine->nvdimms_state->is_enabled) { 1529 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1530 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1531 aml_int(0x80))); 1532 aml_append(scope, method); 1533 } 1534 } 1535 aml_append(dsdt, scope); 1536 1537 crs_range_set_init(&crs_range_set); 1538 bus = PC_MACHINE(machine)->bus; 1539 if (bus) { 1540 QLIST_FOREACH(bus, &bus->child, sibling) { 1541 uint8_t bus_num = pci_bus_num(bus); 1542 uint8_t numa_node = pci_bus_numa_node(bus); 1543 1544 /* look only for expander root buses */ 1545 if (!pci_bus_is_root(bus)) { 1546 continue; 1547 } 1548 1549 if (bus_num < root_bus_limit) { 1550 root_bus_limit = bus_num - 1; 1551 } 1552 1553 scope = aml_scope("\\_SB"); 1554 dev = aml_device("PC%.02X", bus_num); 1555 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1556 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1557 if (pci_bus_is_express(bus)) { 1558 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1559 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1560 aml_append(dev, build_q35_osc_method()); 1561 } else { 1562 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1563 } 1564 1565 if (numa_node != NUMA_NODE_UNASSIGNED) { 1566 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1567 } 1568 1569 aml_append(dev, build_prt(false)); 1570 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1571 0, 0, 0, 0); 1572 aml_append(dev, aml_name_decl("_CRS", crs)); 1573 aml_append(scope, dev); 1574 aml_append(dsdt, scope); 1575 } 1576 } 1577 1578 /* 1579 * At this point crs_range_set has all the ranges used by pci 1580 * busses *other* than PCI0. These ranges will be excluded from 1581 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1582 * too. 1583 */ 1584 if (mcfg_valid) { 1585 crs_range_insert(crs_range_set.mem_ranges, 1586 mcfg.base, mcfg.base + mcfg.size - 1); 1587 } 1588 1589 scope = aml_scope("\\_SB.PCI0"); 1590 /* build PCI0._CRS */ 1591 crs = aml_resource_template(); 1592 aml_append(crs, 1593 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1594 0x0000, 0x0, root_bus_limit, 1595 0x0000, root_bus_limit + 1)); 1596 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1597 1598 aml_append(crs, 1599 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1600 AML_POS_DECODE, AML_ENTIRE_RANGE, 1601 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1602 1603 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1604 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1605 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1606 aml_append(crs, 1607 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1608 AML_POS_DECODE, AML_ENTIRE_RANGE, 1609 0x0000, entry->base, entry->limit, 1610 0x0000, entry->limit - entry->base + 1)); 1611 } 1612 1613 aml_append(crs, 1614 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1615 AML_CACHEABLE, AML_READ_WRITE, 1616 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1617 1618 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1619 range_lob(pci_hole), 1620 range_upb(pci_hole)); 1621 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1622 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1623 aml_append(crs, 1624 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1625 AML_NON_CACHEABLE, AML_READ_WRITE, 1626 0, entry->base, entry->limit, 1627 0, entry->limit - entry->base + 1)); 1628 } 1629 1630 if (!range_is_empty(pci_hole64)) { 1631 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1632 range_lob(pci_hole64), 1633 range_upb(pci_hole64)); 1634 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1635 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1636 aml_append(crs, 1637 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1638 AML_MAX_FIXED, 1639 AML_CACHEABLE, AML_READ_WRITE, 1640 0, entry->base, entry->limit, 1641 0, entry->limit - entry->base + 1)); 1642 } 1643 } 1644 1645 #ifdef CONFIG_TPM 1646 if (TPM_IS_TIS_ISA(tpm_find())) { 1647 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1648 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1649 } 1650 #endif 1651 aml_append(scope, aml_name_decl("_CRS", crs)); 1652 1653 /* reserve GPE0 block resources */ 1654 dev = aml_device("GPE0"); 1655 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1656 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1657 /* device present, functioning, decoding, not shown in UI */ 1658 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1659 crs = aml_resource_template(); 1660 aml_append(crs, 1661 aml_io( 1662 AML_DECODE16, 1663 pm->fadt.gpe0_blk.address, 1664 pm->fadt.gpe0_blk.address, 1665 1, 1666 pm->fadt.gpe0_blk.bit_width / 8) 1667 ); 1668 aml_append(dev, aml_name_decl("_CRS", crs)); 1669 aml_append(scope, dev); 1670 1671 crs_range_set_free(&crs_range_set); 1672 1673 /* reserve PCIHP resources */ 1674 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1675 dev = aml_device("PHPR"); 1676 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1677 aml_append(dev, 1678 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1679 /* device present, functioning, decoding, not shown in UI */ 1680 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1681 crs = aml_resource_template(); 1682 aml_append(crs, 1683 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1684 pm->pcihp_io_len) 1685 ); 1686 aml_append(dev, aml_name_decl("_CRS", crs)); 1687 aml_append(scope, dev); 1688 } 1689 aml_append(dsdt, scope); 1690 1691 /* create S3_ / S4_ / S5_ packages if necessary */ 1692 scope = aml_scope("\\"); 1693 if (!pm->s3_disabled) { 1694 pkg = aml_package(4); 1695 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1696 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1697 aml_append(pkg, aml_int(0)); /* reserved */ 1698 aml_append(pkg, aml_int(0)); /* reserved */ 1699 aml_append(scope, aml_name_decl("_S3", pkg)); 1700 } 1701 1702 if (!pm->s4_disabled) { 1703 pkg = aml_package(4); 1704 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1705 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1706 aml_append(pkg, aml_int(pm->s4_val)); 1707 aml_append(pkg, aml_int(0)); /* reserved */ 1708 aml_append(pkg, aml_int(0)); /* reserved */ 1709 aml_append(scope, aml_name_decl("_S4", pkg)); 1710 } 1711 1712 pkg = aml_package(4); 1713 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1714 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1715 aml_append(pkg, aml_int(0)); /* reserved */ 1716 aml_append(pkg, aml_int(0)); /* reserved */ 1717 aml_append(scope, aml_name_decl("_S5", pkg)); 1718 aml_append(dsdt, scope); 1719 1720 /* create fw_cfg node, unconditionally */ 1721 { 1722 scope = aml_scope("\\_SB.PCI0"); 1723 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1724 aml_append(dsdt, scope); 1725 } 1726 1727 if (misc->applesmc_io_base) { 1728 scope = aml_scope("\\_SB.PCI0.ISA"); 1729 dev = aml_device("SMC"); 1730 1731 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1732 /* device present, functioning, decoding, not shown in UI */ 1733 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1734 1735 crs = aml_resource_template(); 1736 aml_append(crs, 1737 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1738 0x01, APPLESMC_MAX_DATA_LENGTH) 1739 ); 1740 aml_append(crs, aml_irq_no_flags(6)); 1741 aml_append(dev, aml_name_decl("_CRS", crs)); 1742 1743 aml_append(scope, dev); 1744 aml_append(dsdt, scope); 1745 } 1746 1747 if (misc->pvpanic_port) { 1748 scope = aml_scope("\\_SB.PCI0.ISA"); 1749 1750 dev = aml_device("PEVT"); 1751 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1752 1753 crs = aml_resource_template(); 1754 aml_append(crs, 1755 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1756 ); 1757 aml_append(dev, aml_name_decl("_CRS", crs)); 1758 1759 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1760 aml_int(misc->pvpanic_port), 1)); 1761 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1762 aml_append(field, aml_named_field("PEPT", 8)); 1763 aml_append(dev, field); 1764 1765 /* device present, functioning, decoding, shown in UI */ 1766 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1767 1768 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1769 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1770 aml_append(method, aml_return(aml_local(0))); 1771 aml_append(dev, method); 1772 1773 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1774 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1775 aml_append(dev, method); 1776 1777 aml_append(scope, dev); 1778 aml_append(dsdt, scope); 1779 } 1780 1781 sb_scope = aml_scope("\\_SB"); 1782 { 1783 Object *pci_host; 1784 PCIBus *bus = NULL; 1785 1786 pci_host = acpi_get_i386_pci_host(); 1787 1788 if (pci_host) { 1789 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1790 } 1791 1792 if (bus) { 1793 Aml *scope = aml_scope("PCI0"); 1794 /* Scan all PCI buses. Generate tables to support hotplug. */ 1795 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1796 1797 #ifdef CONFIG_TPM 1798 if (TPM_IS_TIS_ISA(tpm)) { 1799 if (misc->tpm_version == TPM_VERSION_2_0) { 1800 dev = aml_device("TPM"); 1801 aml_append(dev, aml_name_decl("_HID", 1802 aml_string("MSFT0101"))); 1803 } else { 1804 dev = aml_device("ISA.TPM"); 1805 aml_append(dev, aml_name_decl("_HID", 1806 aml_eisaid("PNP0C31"))); 1807 } 1808 1809 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1810 crs = aml_resource_template(); 1811 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1812 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1813 /* 1814 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1815 Rewrite to take IRQ from TPM device model and 1816 fix default IRQ value there to use some unused IRQ 1817 */ 1818 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1819 aml_append(dev, aml_name_decl("_CRS", crs)); 1820 1821 tpm_build_ppi_acpi(tpm, dev); 1822 1823 aml_append(scope, dev); 1824 } 1825 #endif 1826 1827 aml_append(sb_scope, scope); 1828 } 1829 } 1830 1831 #ifdef CONFIG_TPM 1832 if (TPM_IS_CRB(tpm)) { 1833 dev = aml_device("TPM"); 1834 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1835 crs = aml_resource_template(); 1836 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1837 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1838 aml_append(dev, aml_name_decl("_CRS", crs)); 1839 1840 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1841 1842 tpm_build_ppi_acpi(tpm, dev); 1843 1844 aml_append(sb_scope, dev); 1845 } 1846 #endif 1847 1848 aml_append(dsdt, sb_scope); 1849 1850 /* copy AML table into ACPI tables blob and patch header there */ 1851 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1852 build_header(linker, table_data, 1853 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1854 "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id); 1855 free_aml_allocator(); 1856 } 1857 1858 static void 1859 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1860 const char *oem_table_id) 1861 { 1862 Acpi20Hpet *hpet; 1863 int hpet_start = table_data->len; 1864 1865 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1866 /* Note timer_block_id value must be kept in sync with value advertised by 1867 * emulated hpet 1868 */ 1869 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1870 hpet->addr.address = cpu_to_le64(HPET_BASE); 1871 build_header(linker, table_data, 1872 (void *)(table_data->data + hpet_start), 1873 "HPET", sizeof(*hpet), 1, oem_id, oem_table_id); 1874 } 1875 1876 #ifdef CONFIG_TPM 1877 static void 1878 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1879 const char *oem_id, const char *oem_table_id) 1880 { 1881 int tcpa_start = table_data->len; 1882 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1883 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1884 unsigned log_addr_offset = 1885 (char *)&tcpa->log_area_start_address - table_data->data; 1886 1887 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1888 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1889 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1890 1891 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1892 false /* high memory */); 1893 1894 /* log area start address to be filled by Guest linker */ 1895 bios_linker_loader_add_pointer(linker, 1896 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1897 ACPI_BUILD_TPMLOG_FILE, 0); 1898 1899 build_header(linker, table_data, 1900 (void *)(table_data->data + tcpa_start), 1901 "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id); 1902 } 1903 #endif 1904 1905 #define HOLE_640K_START (640 * KiB) 1906 #define HOLE_640K_END (1 * MiB) 1907 1908 static void 1909 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1910 { 1911 AcpiSystemResourceAffinityTable *srat; 1912 AcpiSratMemoryAffinity *numamem; 1913 1914 int i; 1915 int srat_start, numa_start, slots; 1916 uint64_t mem_len, mem_base, next_base; 1917 MachineClass *mc = MACHINE_GET_CLASS(machine); 1918 X86MachineState *x86ms = X86_MACHINE(machine); 1919 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1920 PCMachineState *pcms = PC_MACHINE(machine); 1921 ram_addr_t hotplugabble_address_space_size = 1922 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1923 NULL); 1924 1925 srat_start = table_data->len; 1926 1927 srat = acpi_data_push(table_data, sizeof *srat); 1928 srat->reserved1 = cpu_to_le32(1); 1929 1930 for (i = 0; i < apic_ids->len; i++) { 1931 int node_id = apic_ids->cpus[i].props.node_id; 1932 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1933 1934 if (apic_id < 255) { 1935 AcpiSratProcessorAffinity *core; 1936 1937 core = acpi_data_push(table_data, sizeof *core); 1938 core->type = ACPI_SRAT_PROCESSOR_APIC; 1939 core->length = sizeof(*core); 1940 core->local_apic_id = apic_id; 1941 core->proximity_lo = node_id; 1942 memset(core->proximity_hi, 0, 3); 1943 core->local_sapic_eid = 0; 1944 core->flags = cpu_to_le32(1); 1945 } else { 1946 AcpiSratProcessorX2ApicAffinity *core; 1947 1948 core = acpi_data_push(table_data, sizeof *core); 1949 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 1950 core->length = sizeof(*core); 1951 core->x2apic_id = cpu_to_le32(apic_id); 1952 core->proximity_domain = cpu_to_le32(node_id); 1953 core->flags = cpu_to_le32(1); 1954 } 1955 } 1956 1957 1958 /* the memory map is a bit tricky, it contains at least one hole 1959 * from 640k-1M and possibly another one from 3.5G-4G. 1960 */ 1961 next_base = 0; 1962 numa_start = table_data->len; 1963 1964 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 1965 mem_base = next_base; 1966 mem_len = pcms->node_mem[i - 1]; 1967 next_base = mem_base + mem_len; 1968 1969 /* Cut out the 640K hole */ 1970 if (mem_base <= HOLE_640K_START && 1971 next_base > HOLE_640K_START) { 1972 mem_len -= next_base - HOLE_640K_START; 1973 if (mem_len > 0) { 1974 numamem = acpi_data_push(table_data, sizeof *numamem); 1975 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1976 MEM_AFFINITY_ENABLED); 1977 } 1978 1979 /* Check for the rare case: 640K < RAM < 1M */ 1980 if (next_base <= HOLE_640K_END) { 1981 next_base = HOLE_640K_END; 1982 continue; 1983 } 1984 mem_base = HOLE_640K_END; 1985 mem_len = next_base - HOLE_640K_END; 1986 } 1987 1988 /* Cut out the ACPI_PCI hole */ 1989 if (mem_base <= x86ms->below_4g_mem_size && 1990 next_base > x86ms->below_4g_mem_size) { 1991 mem_len -= next_base - x86ms->below_4g_mem_size; 1992 if (mem_len > 0) { 1993 numamem = acpi_data_push(table_data, sizeof *numamem); 1994 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1995 MEM_AFFINITY_ENABLED); 1996 } 1997 mem_base = 1ULL << 32; 1998 mem_len = next_base - x86ms->below_4g_mem_size; 1999 next_base = mem_base + mem_len; 2000 } 2001 2002 if (mem_len > 0) { 2003 numamem = acpi_data_push(table_data, sizeof *numamem); 2004 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2005 MEM_AFFINITY_ENABLED); 2006 } 2007 } 2008 2009 if (machine->nvdimms_state->is_enabled) { 2010 nvdimm_build_srat(table_data); 2011 } 2012 2013 slots = (table_data->len - numa_start) / sizeof *numamem; 2014 for (; slots < pcms->numa_nodes + 2; slots++) { 2015 numamem = acpi_data_push(table_data, sizeof *numamem); 2016 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2017 } 2018 2019 /* 2020 * Entry is required for Windows to enable memory hotplug in OS 2021 * and for Linux to enable SWIOTLB when booted with less than 2022 * 4G of RAM. Windows works better if the entry sets proximity 2023 * to the highest NUMA node in the machine. 2024 * Memory devices may override proximity set by this entry, 2025 * providing _PXM method if necessary. 2026 */ 2027 if (hotplugabble_address_space_size) { 2028 numamem = acpi_data_push(table_data, sizeof *numamem); 2029 build_srat_memory(numamem, machine->device_memory->base, 2030 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2031 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2032 } 2033 2034 build_header(linker, table_data, 2035 (void *)(table_data->data + srat_start), 2036 "SRAT", 2037 table_data->len - srat_start, 1, x86ms->oem_id, 2038 x86ms->oem_table_id); 2039 } 2040 2041 /* 2042 * Insert DMAR scope for PCI bridges and endpoint devcie 2043 */ 2044 static void 2045 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2046 { 2047 GArray *scope_blob = opaque; 2048 AcpiDmarDeviceScope *scope = NULL; 2049 2050 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2051 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2052 build_append_int_noprefix(scope_blob, 0x02, 1); 2053 } else { 2054 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2055 build_append_int_noprefix(scope_blob, 0x01, 1); 2056 } 2057 2058 /* length */ 2059 build_append_int_noprefix(scope_blob, 2060 sizeof(*scope) + sizeof(scope->path[0]), 1); 2061 /* reserved */ 2062 build_append_int_noprefix(scope_blob, 0, 2); 2063 /* enumeration_id */ 2064 build_append_int_noprefix(scope_blob, 0, 1); 2065 /* bus */ 2066 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2067 /* device */ 2068 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2069 /* function */ 2070 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2071 } 2072 2073 /* For a given PCI host bridge, walk and insert DMAR scope */ 2074 static int 2075 dmar_host_bridges(Object *obj, void *opaque) 2076 { 2077 GArray *scope_blob = opaque; 2078 2079 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2080 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2081 2082 if (bus && !pci_bus_bypass_iommu(bus)) { 2083 pci_for_each_device(bus, pci_bus_num(bus), insert_scope, 2084 scope_blob); 2085 } 2086 } 2087 2088 return 0; 2089 } 2090 2091 /* 2092 * VT-d spec 8.1 DMA Remapping Reporting Structure 2093 * (version Oct. 2014 or later) 2094 */ 2095 static void 2096 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2097 const char *oem_table_id) 2098 { 2099 int dmar_start = table_data->len; 2100 2101 AcpiTableDmar *dmar; 2102 AcpiDmarHardwareUnit *drhd; 2103 AcpiDmarRootPortATS *atsr; 2104 uint8_t dmar_flags = 0; 2105 X86IOMMUState *iommu = x86_iommu_get_default(); 2106 AcpiDmarDeviceScope *scope = NULL; 2107 /* Root complex IOAPIC use one path[0] only */ 2108 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2109 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2110 GArray *scope_blob = g_array_new(false, true, 1); 2111 2112 /* 2113 * A PCI bus walk, for each PCI host bridge. 2114 * Insert scope for each PCI bridge and endpoint device which 2115 * is attached to a bus with iommu enabled. 2116 */ 2117 object_child_foreach_recursive(object_get_root(), 2118 dmar_host_bridges, scope_blob); 2119 2120 assert(iommu); 2121 if (x86_iommu_ir_supported(iommu)) { 2122 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2123 } 2124 2125 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2126 dmar->host_address_width = intel_iommu->aw_bits - 1; 2127 dmar->flags = dmar_flags; 2128 2129 /* DMAR Remapping Hardware Unit Definition structure */ 2130 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2131 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2132 drhd->length = 2133 cpu_to_le16(sizeof(*drhd) + ioapic_scope_size + scope_blob->len); 2134 drhd->flags = 0; /* Don't include all pci device */ 2135 drhd->pci_segment = cpu_to_le16(0); 2136 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2137 2138 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2139 * 8.3.1 (version Oct. 2014 or later). */ 2140 scope = &drhd->scope[0]; 2141 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2142 scope->length = ioapic_scope_size; 2143 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2144 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2145 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2146 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2147 2148 /* Add scope found above */ 2149 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2150 g_array_free(scope_blob, true); 2151 2152 if (iommu->dt_supported) { 2153 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2154 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2155 atsr->length = cpu_to_le16(sizeof(*atsr)); 2156 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2157 atsr->pci_segment = cpu_to_le16(0); 2158 } 2159 2160 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2161 "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id); 2162 } 2163 2164 /* 2165 * Windows ACPI Emulated Devices Table 2166 * (Version 1.0 - April 6, 2009) 2167 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2168 * 2169 * Helpful to speedup Windows guests and ignored by others. 2170 */ 2171 static void 2172 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2173 const char *oem_table_id) 2174 { 2175 int waet_start = table_data->len; 2176 2177 /* WAET header */ 2178 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2179 /* 2180 * Set "ACPI PM timer good" flag. 2181 * 2182 * Tells Windows guests that our ACPI PM timer is reliable in the 2183 * sense that guest can read it only once to obtain a reliable value. 2184 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2185 */ 2186 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2187 2188 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2189 "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id); 2190 } 2191 2192 /* 2193 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2194 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2195 */ 2196 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2197 2198 /* 2199 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2200 * necessary for the PCI topology. 2201 */ 2202 static void 2203 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2204 { 2205 GArray *table_data = opaque; 2206 uint32_t entry; 2207 2208 /* "Select" IVHD entry, type 0x2 */ 2209 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2210 build_append_int_noprefix(table_data, entry, 4); 2211 2212 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2213 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2214 uint8_t sec = pci_bus_num(sec_bus); 2215 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2216 2217 if (pci_bus_is_express(sec_bus)) { 2218 /* 2219 * Walk the bus if there are subordinates, otherwise use a range 2220 * to cover an entire leaf bus. We could potentially also use a 2221 * range for traversed buses, but we'd need to take care not to 2222 * create both Select and Range entries covering the same device. 2223 * This is easier and potentially more compact. 2224 * 2225 * An example bare metal system seems to use Select entries for 2226 * root ports without a slot (ie. built-ins) and Range entries 2227 * when there is a slot. The same system also only hard-codes 2228 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2229 * making no effort to support nested bridges. We attempt to 2230 * be more thorough here. 2231 */ 2232 if (sec == sub) { /* leaf bus */ 2233 /* "Start of Range" IVHD entry, type 0x3 */ 2234 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2235 build_append_int_noprefix(table_data, entry, 4); 2236 /* "End of Range" IVHD entry, type 0x4 */ 2237 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2238 build_append_int_noprefix(table_data, entry, 4); 2239 } else { 2240 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2241 } 2242 } else { 2243 /* 2244 * If the secondary bus is conventional, then we need to create an 2245 * Alias range for everything downstream. The range covers the 2246 * first devfn on the secondary bus to the last devfn on the 2247 * subordinate bus. The alias target depends on legacy versus 2248 * express bridges, just as in pci_device_iommu_address_space(). 2249 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2250 */ 2251 uint16_t dev_id_a, dev_id_b; 2252 2253 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2254 2255 if (pci_is_express(dev) && 2256 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2257 dev_id_b = dev_id_a; 2258 } else { 2259 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2260 } 2261 2262 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2263 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2264 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2265 2266 /* "End of Range" IVHD entry, type 0x4 */ 2267 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2268 build_append_int_noprefix(table_data, entry, 4); 2269 } 2270 } 2271 } 2272 2273 /* For all PCI host bridges, walk and insert IVHD entries */ 2274 static int 2275 ivrs_host_bridges(Object *obj, void *opaque) 2276 { 2277 GArray *ivhd_blob = opaque; 2278 2279 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2280 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2281 2282 if (bus && !pci_bus_bypass_iommu(bus)) { 2283 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2284 } 2285 } 2286 2287 return 0; 2288 } 2289 2290 static void 2291 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2292 const char *oem_table_id) 2293 { 2294 int ivhd_table_len = 24; 2295 int iommu_start = table_data->len; 2296 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2297 GArray *ivhd_blob = g_array_new(false, true, 1); 2298 2299 /* IVRS header */ 2300 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2301 /* IVinfo - IO virtualization information common to all 2302 * IOMMU units in a system 2303 */ 2304 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2305 /* reserved */ 2306 build_append_int_noprefix(table_data, 0, 8); 2307 2308 /* IVHD definition - type 10h */ 2309 build_append_int_noprefix(table_data, 0x10, 1); 2310 /* virtualization flags */ 2311 build_append_int_noprefix(table_data, 2312 (1UL << 0) | /* HtTunEn */ 2313 (1UL << 4) | /* iotblSup */ 2314 (1UL << 6) | /* PrefSup */ 2315 (1UL << 7), /* PPRSup */ 2316 1); 2317 2318 /* 2319 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2320 * complete set of IVHD entries. Do this into a separate blob so that we 2321 * can calculate the total IVRS table length here and then append the new 2322 * blob further below. Fall back to an entry covering all devices, which 2323 * is sufficient when no aliases are present. 2324 */ 2325 object_child_foreach_recursive(object_get_root(), 2326 ivrs_host_bridges, ivhd_blob); 2327 2328 if (!ivhd_blob->len) { 2329 /* 2330 * Type 1 device entry reporting all devices 2331 * These are 4-byte device entries currently reporting the range of 2332 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2333 */ 2334 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2335 } 2336 2337 ivhd_table_len += ivhd_blob->len; 2338 2339 /* 2340 * When interrupt remapping is supported, we add a special IVHD device 2341 * for type IO-APIC. 2342 */ 2343 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2344 ivhd_table_len += 8; 2345 } 2346 2347 /* IVHD length */ 2348 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2349 /* DeviceID */ 2350 build_append_int_noprefix(table_data, s->devid, 2); 2351 /* Capability offset */ 2352 build_append_int_noprefix(table_data, s->capab_offset, 2); 2353 /* IOMMU base address */ 2354 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2355 /* PCI Segment Group */ 2356 build_append_int_noprefix(table_data, 0, 2); 2357 /* IOMMU info */ 2358 build_append_int_noprefix(table_data, 0, 2); 2359 /* IOMMU Feature Reporting */ 2360 build_append_int_noprefix(table_data, 2361 (48UL << 30) | /* HATS */ 2362 (48UL << 28) | /* GATS */ 2363 (1UL << 2) | /* GTSup */ 2364 (1UL << 6), /* GASup */ 2365 4); 2366 2367 /* IVHD entries as found above */ 2368 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2369 g_array_free(ivhd_blob, TRUE); 2370 2371 /* 2372 * Add a special IVHD device type. 2373 * Refer to spec - Table 95: IVHD device entry type codes 2374 * 2375 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2376 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2377 */ 2378 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2379 build_append_int_noprefix(table_data, 2380 (0x1ull << 56) | /* type IOAPIC */ 2381 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2382 0x48, /* special device */ 2383 8); 2384 } 2385 2386 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2387 "IVRS", table_data->len - iommu_start, 1, oem_id, 2388 oem_table_id); 2389 } 2390 2391 typedef 2392 struct AcpiBuildState { 2393 /* Copy of table in RAM (for patching). */ 2394 MemoryRegion *table_mr; 2395 /* Is table patched? */ 2396 uint8_t patched; 2397 void *rsdp; 2398 MemoryRegion *rsdp_mr; 2399 MemoryRegion *linker_mr; 2400 } AcpiBuildState; 2401 2402 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2403 { 2404 Object *pci_host; 2405 QObject *o; 2406 2407 pci_host = acpi_get_i386_pci_host(); 2408 if (!pci_host) { 2409 return false; 2410 } 2411 2412 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2413 if (!o) { 2414 return false; 2415 } 2416 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2417 qobject_unref(o); 2418 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2419 return false; 2420 } 2421 2422 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2423 assert(o); 2424 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2425 qobject_unref(o); 2426 return true; 2427 } 2428 2429 static 2430 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2431 { 2432 PCMachineState *pcms = PC_MACHINE(machine); 2433 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2434 X86MachineState *x86ms = X86_MACHINE(machine); 2435 GArray *table_offsets; 2436 unsigned facs, dsdt, rsdt, fadt; 2437 AcpiPmInfo pm; 2438 AcpiMiscInfo misc; 2439 AcpiMcfgInfo mcfg; 2440 Range pci_hole = {}, pci_hole64 = {}; 2441 uint8_t *u; 2442 size_t aml_len = 0; 2443 GArray *tables_blob = tables->table_data; 2444 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2445 Object *vmgenid_dev; 2446 char *oem_id; 2447 char *oem_table_id; 2448 2449 acpi_get_pm_info(machine, &pm); 2450 acpi_get_misc_info(&misc); 2451 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2452 acpi_get_slic_oem(&slic_oem); 2453 2454 if (slic_oem.id) { 2455 oem_id = slic_oem.id; 2456 } else { 2457 oem_id = x86ms->oem_id; 2458 } 2459 2460 if (slic_oem.table_id) { 2461 oem_table_id = slic_oem.table_id; 2462 } else { 2463 oem_table_id = x86ms->oem_table_id; 2464 } 2465 2466 table_offsets = g_array_new(false, true /* clear */, 2467 sizeof(uint32_t)); 2468 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2469 2470 bios_linker_loader_alloc(tables->linker, 2471 ACPI_BUILD_TABLE_FILE, tables_blob, 2472 64 /* Ensure FACS is aligned */, 2473 false /* high memory */); 2474 2475 /* 2476 * FACS is pointed to by FADT. 2477 * We place it first since it's the only table that has alignment 2478 * requirements. 2479 */ 2480 facs = tables_blob->len; 2481 build_facs(tables_blob); 2482 2483 /* DSDT is pointed to by FADT */ 2484 dsdt = tables_blob->len; 2485 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2486 &pci_hole, &pci_hole64, machine); 2487 2488 /* Count the size of the DSDT and SSDT, we will need it for legacy 2489 * sizing of ACPI tables. 2490 */ 2491 aml_len += tables_blob->len - dsdt; 2492 2493 /* ACPI tables pointed to by RSDT */ 2494 fadt = tables_blob->len; 2495 acpi_add_table(table_offsets, tables_blob); 2496 pm.fadt.facs_tbl_offset = &facs; 2497 pm.fadt.dsdt_tbl_offset = &dsdt; 2498 pm.fadt.xdsdt_tbl_offset = &dsdt; 2499 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2500 aml_len += tables_blob->len - fadt; 2501 2502 acpi_add_table(table_offsets, tables_blob); 2503 acpi_build_madt(tables_blob, tables->linker, x86ms, 2504 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2505 x86ms->oem_table_id); 2506 2507 vmgenid_dev = find_vmgenid_dev(); 2508 if (vmgenid_dev) { 2509 acpi_add_table(table_offsets, tables_blob); 2510 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2511 tables->vmgenid, tables->linker, x86ms->oem_id); 2512 } 2513 2514 if (misc.has_hpet) { 2515 acpi_add_table(table_offsets, tables_blob); 2516 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2517 x86ms->oem_table_id); 2518 } 2519 #ifdef CONFIG_TPM 2520 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2521 if (misc.tpm_version == TPM_VERSION_1_2) { 2522 acpi_add_table(table_offsets, tables_blob); 2523 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2524 x86ms->oem_id, x86ms->oem_table_id); 2525 } else { /* TPM_VERSION_2_0 */ 2526 acpi_add_table(table_offsets, tables_blob); 2527 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2528 x86ms->oem_id, x86ms->oem_table_id); 2529 } 2530 } 2531 #endif 2532 if (pcms->numa_nodes) { 2533 acpi_add_table(table_offsets, tables_blob); 2534 build_srat(tables_blob, tables->linker, machine); 2535 if (machine->numa_state->have_numa_distance) { 2536 acpi_add_table(table_offsets, tables_blob); 2537 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2538 x86ms->oem_table_id); 2539 } 2540 if (machine->numa_state->hmat_enabled) { 2541 acpi_add_table(table_offsets, tables_blob); 2542 build_hmat(tables_blob, tables->linker, machine->numa_state, 2543 x86ms->oem_id, x86ms->oem_table_id); 2544 } 2545 } 2546 if (acpi_get_mcfg(&mcfg)) { 2547 acpi_add_table(table_offsets, tables_blob); 2548 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2549 x86ms->oem_table_id); 2550 } 2551 if (x86_iommu_get_default()) { 2552 IommuType IOMMUType = x86_iommu_get_type(); 2553 if (IOMMUType == TYPE_AMD) { 2554 acpi_add_table(table_offsets, tables_blob); 2555 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2556 x86ms->oem_table_id); 2557 } else if (IOMMUType == TYPE_INTEL) { 2558 acpi_add_table(table_offsets, tables_blob); 2559 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2560 x86ms->oem_table_id); 2561 } 2562 } 2563 if (machine->nvdimms_state->is_enabled) { 2564 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2565 machine->nvdimms_state, machine->ram_slots, 2566 x86ms->oem_id, x86ms->oem_table_id); 2567 } 2568 2569 acpi_add_table(table_offsets, tables_blob); 2570 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2571 2572 /* Add tables supplied by user (if any) */ 2573 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2574 unsigned len = acpi_table_len(u); 2575 2576 acpi_add_table(table_offsets, tables_blob); 2577 g_array_append_vals(tables_blob, u, len); 2578 } 2579 2580 /* RSDT is pointed to by RSDP */ 2581 rsdt = tables_blob->len; 2582 build_rsdt(tables_blob, tables->linker, table_offsets, 2583 oem_id, oem_table_id); 2584 2585 /* RSDP is in FSEG memory, so allocate it separately */ 2586 { 2587 AcpiRsdpData rsdp_data = { 2588 .revision = 0, 2589 .oem_id = x86ms->oem_id, 2590 .xsdt_tbl_offset = NULL, 2591 .rsdt_tbl_offset = &rsdt, 2592 }; 2593 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2594 if (!pcmc->rsdp_in_ram) { 2595 /* We used to allocate some extra space for RSDP revision 2 but 2596 * only used the RSDP revision 0 space. The extra bytes were 2597 * zeroed out and not used. 2598 * Here we continue wasting those extra 16 bytes to make sure we 2599 * don't break migration for machine types 2.2 and older due to 2600 * RSDP blob size mismatch. 2601 */ 2602 build_append_int_noprefix(tables->rsdp, 0, 16); 2603 } 2604 } 2605 2606 /* We'll expose it all to Guest so we want to reduce 2607 * chance of size changes. 2608 * 2609 * We used to align the tables to 4k, but of course this would 2610 * too simple to be enough. 4k turned out to be too small an 2611 * alignment very soon, and in fact it is almost impossible to 2612 * keep the table size stable for all (max_cpus, max_memory_slots) 2613 * combinations. So the table size is always 64k for pc-i440fx-2.1 2614 * and we give an error if the table grows beyond that limit. 2615 * 2616 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2617 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2618 * than 2.0 and we can always pad the smaller tables with zeros. We can 2619 * then use the exact size of the 2.0 tables. 2620 * 2621 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2622 */ 2623 if (pcmc->legacy_acpi_table_size) { 2624 /* Subtracting aml_len gives the size of fixed tables. Then add the 2625 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2626 */ 2627 int legacy_aml_len = 2628 pcmc->legacy_acpi_table_size + 2629 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2630 int legacy_table_size = 2631 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2632 ACPI_BUILD_ALIGN_SIZE); 2633 if (tables_blob->len > legacy_table_size) { 2634 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2635 warn_report("ACPI table size %u exceeds %d bytes," 2636 " migration may not work", 2637 tables_blob->len, legacy_table_size); 2638 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2639 " or PCI bridges."); 2640 } 2641 g_array_set_size(tables_blob, legacy_table_size); 2642 } else { 2643 /* Make sure we have a buffer in case we need to resize the tables. */ 2644 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2645 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2646 warn_report("ACPI table size %u exceeds %d bytes," 2647 " migration may not work", 2648 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2649 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2650 " or PCI bridges."); 2651 } 2652 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2653 } 2654 2655 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2656 2657 /* Cleanup memory that's no longer used. */ 2658 g_array_free(table_offsets, true); 2659 } 2660 2661 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2662 { 2663 uint32_t size = acpi_data_len(data); 2664 2665 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2666 memory_region_ram_resize(mr, size, &error_abort); 2667 2668 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2669 memory_region_set_dirty(mr, 0, size); 2670 } 2671 2672 static void acpi_build_update(void *build_opaque) 2673 { 2674 AcpiBuildState *build_state = build_opaque; 2675 AcpiBuildTables tables; 2676 2677 /* No state to update or already patched? Nothing to do. */ 2678 if (!build_state || build_state->patched) { 2679 return; 2680 } 2681 build_state->patched = 1; 2682 2683 acpi_build_tables_init(&tables); 2684 2685 acpi_build(&tables, MACHINE(qdev_get_machine())); 2686 2687 acpi_ram_update(build_state->table_mr, tables.table_data); 2688 2689 if (build_state->rsdp) { 2690 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2691 } else { 2692 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2693 } 2694 2695 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2696 acpi_build_tables_cleanup(&tables, true); 2697 } 2698 2699 static void acpi_build_reset(void *build_opaque) 2700 { 2701 AcpiBuildState *build_state = build_opaque; 2702 build_state->patched = 0; 2703 } 2704 2705 static const VMStateDescription vmstate_acpi_build = { 2706 .name = "acpi_build", 2707 .version_id = 1, 2708 .minimum_version_id = 1, 2709 .fields = (VMStateField[]) { 2710 VMSTATE_UINT8(patched, AcpiBuildState), 2711 VMSTATE_END_OF_LIST() 2712 }, 2713 }; 2714 2715 void acpi_setup(void) 2716 { 2717 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2718 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2719 X86MachineState *x86ms = X86_MACHINE(pcms); 2720 AcpiBuildTables tables; 2721 AcpiBuildState *build_state; 2722 Object *vmgenid_dev; 2723 #ifdef CONFIG_TPM 2724 TPMIf *tpm; 2725 static FwCfgTPMConfig tpm_config; 2726 #endif 2727 2728 if (!x86ms->fw_cfg) { 2729 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2730 return; 2731 } 2732 2733 if (!pcms->acpi_build_enabled) { 2734 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2735 return; 2736 } 2737 2738 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2739 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2740 return; 2741 } 2742 2743 build_state = g_malloc0(sizeof *build_state); 2744 2745 acpi_build_tables_init(&tables); 2746 acpi_build(&tables, MACHINE(pcms)); 2747 2748 /* Now expose it all to Guest */ 2749 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2750 build_state, tables.table_data, 2751 ACPI_BUILD_TABLE_FILE); 2752 assert(build_state->table_mr != NULL); 2753 2754 build_state->linker_mr = 2755 acpi_add_rom_blob(acpi_build_update, build_state, 2756 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2757 2758 #ifdef CONFIG_TPM 2759 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2760 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2761 2762 tpm = tpm_find(); 2763 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2764 tpm_config = (FwCfgTPMConfig) { 2765 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2766 .tpm_version = tpm_get_version(tpm), 2767 .tpmppi_version = TPM_PPI_VERSION_1_30 2768 }; 2769 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2770 &tpm_config, sizeof tpm_config); 2771 } 2772 #endif 2773 2774 vmgenid_dev = find_vmgenid_dev(); 2775 if (vmgenid_dev) { 2776 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2777 tables.vmgenid); 2778 } 2779 2780 if (!pcmc->rsdp_in_ram) { 2781 /* 2782 * Keep for compatibility with old machine types. 2783 * Though RSDP is small, its contents isn't immutable, so 2784 * we'll update it along with the rest of tables on guest access. 2785 */ 2786 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2787 2788 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2789 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2790 acpi_build_update, NULL, build_state, 2791 build_state->rsdp, rsdp_size, true); 2792 build_state->rsdp_mr = NULL; 2793 } else { 2794 build_state->rsdp = NULL; 2795 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2796 build_state, tables.rsdp, 2797 ACPI_BUILD_RSDP_FILE); 2798 } 2799 2800 qemu_register_reset(acpi_build_reset, build_state); 2801 acpi_build_reset(build_state); 2802 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2803 2804 /* Cleanup tables but don't free the memory: we track it 2805 * in build_state. 2806 */ 2807 acpi_build_tables_cleanup(&tables, false); 2808 } 2809