1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "acpi-build.h" 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "hw/i386/pc.h" 32 #include "target-i386/cpu.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/acpi/bios-linker-loader.h" 38 #include "hw/loader.h" 39 #include "hw/isa/isa.h" 40 #include "hw/block/fdc.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 #include "sysemu/tpm_backend.h" 45 #include "hw/timer/mc146818rtc_regs.h" 46 47 /* Supported chipsets: */ 48 #include "hw/acpi/piix4.h" 49 #include "hw/acpi/pcihp.h" 50 #include "hw/i386/ich9.h" 51 #include "hw/pci/pci_bus.h" 52 #include "hw/pci-host/q35.h" 53 #include "hw/i386/intel_iommu.h" 54 #include "hw/timer/hpet.h" 55 56 #include "hw/acpi/aml-build.h" 57 58 #include "qapi/qmp/qint.h" 59 #include "qom/qom-qobject.h" 60 61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 63 * a little bit, there should be plenty of free space since the DSDT 64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 65 */ 66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 67 #define ACPI_BUILD_ALIGN_SIZE 0x1000 68 69 #define ACPI_BUILD_TABLE_SIZE 0x20000 70 71 /* #define DEBUG_ACPI_BUILD */ 72 #ifdef DEBUG_ACPI_BUILD 73 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 75 #else 76 #define ACPI_BUILD_DPRINTF(fmt, ...) 77 #endif 78 79 typedef struct AcpiCpuInfo { 80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 81 } AcpiCpuInfo; 82 83 typedef struct AcpiMcfgInfo { 84 uint64_t mcfg_base; 85 uint32_t mcfg_size; 86 } AcpiMcfgInfo; 87 88 typedef struct AcpiPmInfo { 89 bool s3_disabled; 90 bool s4_disabled; 91 bool pcihp_bridge_en; 92 uint8_t s4_val; 93 uint16_t sci_int; 94 uint8_t acpi_enable_cmd; 95 uint8_t acpi_disable_cmd; 96 uint32_t gpe0_blk; 97 uint32_t gpe0_blk_len; 98 uint32_t io_base; 99 uint16_t cpu_hp_io_base; 100 uint16_t cpu_hp_io_len; 101 uint16_t mem_hp_io_base; 102 uint16_t mem_hp_io_len; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 static 125 int acpi_add_cpu_info(Object *o, void *opaque) 126 { 127 AcpiCpuInfo *cpu = opaque; 128 uint64_t apic_id; 129 130 if (object_dynamic_cast(o, TYPE_CPU)) { 131 apic_id = object_property_get_int(o, "apic-id", NULL); 132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 133 134 set_bit(apic_id, cpu->found_cpus); 135 } 136 137 object_child_foreach(o, acpi_add_cpu_info, opaque); 138 return 0; 139 } 140 141 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 142 { 143 Object *root = object_get_root(); 144 145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 146 object_child_foreach(root, acpi_add_cpu_info, cpu); 147 } 148 149 static void acpi_get_pm_info(AcpiPmInfo *pm) 150 { 151 Object *piix = piix4_pm_find(); 152 Object *lpc = ich9_lpc_find(); 153 Object *obj = NULL; 154 QObject *o; 155 156 pm->cpu_hp_io_base = 0; 157 pm->pcihp_io_base = 0; 158 pm->pcihp_io_len = 0; 159 if (piix) { 160 obj = piix; 161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 162 pm->pcihp_io_base = 163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 164 pm->pcihp_io_len = 165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 166 } 167 if (lpc) { 168 obj = lpc; 169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 170 } 171 assert(obj); 172 173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 176 177 /* Fill in optional s3/s4 related properties */ 178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 179 if (o) { 180 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 181 } else { 182 pm->s3_disabled = false; 183 } 184 qobject_decref(o); 185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 186 if (o) { 187 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 188 } else { 189 pm->s4_disabled = false; 190 } 191 qobject_decref(o); 192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 193 if (o) { 194 pm->s4_val = qint_get_int(qobject_to_qint(o)); 195 } else { 196 pm->s4_val = false; 197 } 198 qobject_decref(o); 199 200 /* Fill in mandatory properties */ 201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 202 203 pm->acpi_enable_cmd = object_property_get_int(obj, 204 ACPI_PM_PROP_ACPI_ENABLE_CMD, 205 NULL); 206 pm->acpi_disable_cmd = object_property_get_int(obj, 207 ACPI_PM_PROP_ACPI_DISABLE_CMD, 208 NULL); 209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 210 NULL); 211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 212 NULL); 213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 214 NULL); 215 pm->pcihp_bridge_en = 216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 217 NULL); 218 } 219 220 static void acpi_get_misc_info(AcpiMiscInfo *info) 221 { 222 Object *piix = piix4_pm_find(); 223 Object *lpc = ich9_lpc_find(); 224 assert(!!piix != !!lpc); 225 226 if (piix) { 227 info->is_piix4 = true; 228 } 229 if (lpc) { 230 info->is_piix4 = false; 231 } 232 233 info->has_hpet = hpet_find(); 234 info->tpm_version = tpm_get_version(); 235 info->pvpanic_port = pvpanic_port(); 236 info->applesmc_io_base = applesmc_port(); 237 } 238 239 /* 240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 241 * On i386 arch we only have two pci hosts, so we can look only for them. 242 */ 243 static Object *acpi_get_i386_pci_host(void) 244 { 245 PCIHostState *host; 246 247 host = OBJECT_CHECK(PCIHostState, 248 object_resolve_path("/machine/i440fx", NULL), 249 TYPE_PCI_HOST_BRIDGE); 250 if (!host) { 251 host = OBJECT_CHECK(PCIHostState, 252 object_resolve_path("/machine/q35", NULL), 253 TYPE_PCI_HOST_BRIDGE); 254 } 255 256 return OBJECT(host); 257 } 258 259 static void acpi_get_pci_info(PcPciInfo *info) 260 { 261 Object *pci_host; 262 263 264 pci_host = acpi_get_i386_pci_host(); 265 g_assert(pci_host); 266 267 info->w32.begin = object_property_get_int(pci_host, 268 PCI_HOST_PROP_PCI_HOLE_START, 269 NULL); 270 info->w32.end = object_property_get_int(pci_host, 271 PCI_HOST_PROP_PCI_HOLE_END, 272 NULL); 273 info->w64.begin = object_property_get_int(pci_host, 274 PCI_HOST_PROP_PCI_HOLE64_START, 275 NULL); 276 info->w64.end = object_property_get_int(pci_host, 277 PCI_HOST_PROP_PCI_HOLE64_END, 278 NULL); 279 } 280 281 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 282 283 static void acpi_align_size(GArray *blob, unsigned align) 284 { 285 /* Align size to multiple of given size. This reduces the chance 286 * we need to change size in the future (breaking cross version migration). 287 */ 288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 289 } 290 291 /* FACS */ 292 static void 293 build_facs(GArray *table_data, GArray *linker) 294 { 295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 296 memcpy(&facs->signature, "FACS", 4); 297 facs->length = cpu_to_le32(sizeof(*facs)); 298 } 299 300 /* Load chipset information in FADT */ 301 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 302 { 303 fadt->model = 1; 304 fadt->reserved1 = 0; 305 fadt->sci_int = cpu_to_le16(pm->sci_int); 306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 307 fadt->acpi_enable = pm->acpi_enable_cmd; 308 fadt->acpi_disable = pm->acpi_disable_cmd; 309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 314 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 315 fadt->pm1_evt_len = 4; 316 fadt->pm1_cnt_len = 2; 317 fadt->pm_tmr_len = 4; 318 fadt->gpe0_blk_len = pm->gpe0_blk_len; 319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 322 (1 << ACPI_FADT_F_PROC_C1) | 323 (1 << ACPI_FADT_F_SLP_BUTTON) | 324 (1 << ACPI_FADT_F_RTC_S4)); 325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 327 * For more than 8 CPUs, "Clustered Logical" mode has to be used 328 */ 329 if (max_cpus > 8) { 330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 331 } 332 fadt->century = RTC_CENTURY; 333 } 334 335 336 /* FADT */ 337 static void 338 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 339 unsigned facs, unsigned dsdt, 340 const char *oem_id, const char *oem_table_id) 341 { 342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 343 344 fadt->firmware_ctrl = cpu_to_le32(facs); 345 /* FACS address to be filled by Guest linker */ 346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 347 ACPI_BUILD_TABLE_FILE, 348 table_data, &fadt->firmware_ctrl, 349 sizeof fadt->firmware_ctrl); 350 351 fadt->dsdt = cpu_to_le32(dsdt); 352 /* DSDT address to be filled by Guest linker */ 353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 354 ACPI_BUILD_TABLE_FILE, 355 table_data, &fadt->dsdt, 356 sizeof fadt->dsdt); 357 358 fadt_setup(fadt, pm); 359 360 build_header(linker, table_data, 361 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id); 362 } 363 364 static void 365 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu) 366 { 367 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 368 int madt_start = table_data->len; 369 370 AcpiMultipleApicTable *madt; 371 AcpiMadtIoApic *io_apic; 372 AcpiMadtIntsrcovr *intsrcovr; 373 AcpiMadtLocalNmi *local_nmi; 374 int i; 375 376 madt = acpi_data_push(table_data, sizeof *madt); 377 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 378 madt->flags = cpu_to_le32(1); 379 380 for (i = 0; i < pcms->apic_id_limit; i++) { 381 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 382 apic->type = ACPI_APIC_PROCESSOR; 383 apic->length = sizeof(*apic); 384 apic->processor_id = i; 385 apic->local_apic_id = i; 386 if (test_bit(i, cpu->found_cpus)) { 387 apic->flags = cpu_to_le32(1); 388 } else { 389 apic->flags = cpu_to_le32(0); 390 } 391 } 392 io_apic = acpi_data_push(table_data, sizeof *io_apic); 393 io_apic->type = ACPI_APIC_IO; 394 io_apic->length = sizeof(*io_apic); 395 #define ACPI_BUILD_IOAPIC_ID 0x0 396 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 397 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 398 io_apic->interrupt = cpu_to_le32(0); 399 400 if (pcms->apic_xrupt_override) { 401 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 402 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 403 intsrcovr->length = sizeof(*intsrcovr); 404 intsrcovr->source = 0; 405 intsrcovr->gsi = cpu_to_le32(2); 406 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 407 } 408 for (i = 1; i < 16; i++) { 409 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 410 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 411 /* No need for a INT source override structure. */ 412 continue; 413 } 414 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 415 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 416 intsrcovr->length = sizeof(*intsrcovr); 417 intsrcovr->source = i; 418 intsrcovr->gsi = cpu_to_le32(i); 419 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 420 } 421 422 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 423 local_nmi->type = ACPI_APIC_LOCAL_NMI; 424 local_nmi->length = sizeof(*local_nmi); 425 local_nmi->processor_id = 0xff; /* all processors */ 426 local_nmi->flags = cpu_to_le16(0); 427 local_nmi->lint = 1; /* ACPI_LINT1 */ 428 429 build_header(linker, table_data, 430 (void *)(table_data->data + madt_start), "APIC", 431 table_data->len - madt_start, 1, NULL, NULL); 432 } 433 434 /* Assign BSEL property to all buses. In the future, this can be changed 435 * to only assign to buses that support hotplug. 436 */ 437 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 438 { 439 unsigned *bsel_alloc = opaque; 440 unsigned *bus_bsel; 441 442 if (qbus_is_hotpluggable(BUS(bus))) { 443 bus_bsel = g_malloc(sizeof *bus_bsel); 444 445 *bus_bsel = (*bsel_alloc)++; 446 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 447 bus_bsel, NULL); 448 } 449 450 return bsel_alloc; 451 } 452 453 static void acpi_set_pci_info(void) 454 { 455 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 456 unsigned bsel_alloc = 0; 457 458 if (bus) { 459 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 460 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 461 } 462 } 463 464 static void build_append_pcihp_notify_entry(Aml *method, int slot) 465 { 466 Aml *if_ctx; 467 int32_t devfn = PCI_DEVFN(slot, 0); 468 469 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 470 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 471 aml_append(method, if_ctx); 472 } 473 474 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 475 bool pcihp_bridge_en) 476 { 477 Aml *dev, *notify_method, *method; 478 QObject *bsel; 479 PCIBus *sec; 480 int i; 481 482 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 483 if (bsel) { 484 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 485 486 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 487 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 488 } 489 490 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 491 DeviceClass *dc; 492 PCIDeviceClass *pc; 493 PCIDevice *pdev = bus->devices[i]; 494 int slot = PCI_SLOT(i); 495 bool hotplug_enabled_dev; 496 bool bridge_in_acpi; 497 498 if (!pdev) { 499 if (bsel) { /* add hotplug slots for non present devices */ 500 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 501 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 502 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 503 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 504 aml_append(method, 505 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 506 ); 507 aml_append(dev, method); 508 aml_append(parent_scope, dev); 509 510 build_append_pcihp_notify_entry(notify_method, slot); 511 } 512 continue; 513 } 514 515 pc = PCI_DEVICE_GET_CLASS(pdev); 516 dc = DEVICE_GET_CLASS(pdev); 517 518 /* When hotplug for bridges is enabled, bridges are 519 * described in ACPI separately (see build_pci_bus_end). 520 * In this case they aren't themselves hot-pluggable. 521 * Hotplugged bridges *are* hot-pluggable. 522 */ 523 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 524 !DEVICE(pdev)->hotplugged; 525 526 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 527 528 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 529 continue; 530 } 531 532 /* start to compose PCI slot descriptor */ 533 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 534 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 535 536 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 537 /* add VGA specific AML methods */ 538 int s3d; 539 540 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 541 s3d = 3; 542 } else { 543 s3d = 0; 544 } 545 546 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 547 aml_append(method, aml_return(aml_int(0))); 548 aml_append(dev, method); 549 550 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 551 aml_append(method, aml_return(aml_int(0))); 552 aml_append(dev, method); 553 554 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 555 aml_append(method, aml_return(aml_int(s3d))); 556 aml_append(dev, method); 557 } else if (hotplug_enabled_dev) { 558 /* add _SUN/_EJ0 to make slot hotpluggable */ 559 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 560 561 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 562 aml_append(method, 563 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 564 ); 565 aml_append(dev, method); 566 567 if (bsel) { 568 build_append_pcihp_notify_entry(notify_method, slot); 569 } 570 } else if (bridge_in_acpi) { 571 /* 572 * device is coldplugged bridge, 573 * add child device descriptions into its scope 574 */ 575 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 576 577 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 578 } 579 /* slot descriptor has been composed, add it into parent context */ 580 aml_append(parent_scope, dev); 581 } 582 583 if (bsel) { 584 aml_append(parent_scope, notify_method); 585 } 586 587 /* Append PCNT method to notify about events on local and child buses. 588 * Add unconditionally for root since DSDT expects it. 589 */ 590 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 591 592 /* If bus supports hotplug select it and notify about local events */ 593 if (bsel) { 594 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 595 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 596 aml_append(method, 597 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 598 ); 599 aml_append(method, 600 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 601 ); 602 } 603 604 /* Notify about child bus events in any case */ 605 if (pcihp_bridge_en) { 606 QLIST_FOREACH(sec, &bus->child, sibling) { 607 int32_t devfn = sec->parent_dev->devfn; 608 609 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 610 } 611 } 612 aml_append(parent_scope, method); 613 qobject_decref(bsel); 614 } 615 616 /** 617 * build_prt_entry: 618 * @link_name: link name for PCI route entry 619 * 620 * build AML package containing a PCI route entry for @link_name 621 */ 622 static Aml *build_prt_entry(const char *link_name) 623 { 624 Aml *a_zero = aml_int(0); 625 Aml *pkg = aml_package(4); 626 aml_append(pkg, a_zero); 627 aml_append(pkg, a_zero); 628 aml_append(pkg, aml_name("%s", link_name)); 629 aml_append(pkg, a_zero); 630 return pkg; 631 } 632 633 /* 634 * initialize_route - Initialize the interrupt routing rule 635 * through a specific LINK: 636 * if (lnk_idx == idx) 637 * route using link 'link_name' 638 */ 639 static Aml *initialize_route(Aml *route, const char *link_name, 640 Aml *lnk_idx, int idx) 641 { 642 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 643 Aml *pkg = build_prt_entry(link_name); 644 645 aml_append(if_ctx, aml_store(pkg, route)); 646 647 return if_ctx; 648 } 649 650 /* 651 * build_prt - Define interrupt rounting rules 652 * 653 * Returns an array of 128 routes, one for each device, 654 * based on device location. 655 * The main goal is to equaly distribute the interrupts 656 * over the 4 existing ACPI links (works only for i440fx). 657 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 658 * 659 */ 660 static Aml *build_prt(bool is_pci0_prt) 661 { 662 Aml *method, *while_ctx, *pin, *res; 663 664 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 665 res = aml_local(0); 666 pin = aml_local(1); 667 aml_append(method, aml_store(aml_package(128), res)); 668 aml_append(method, aml_store(aml_int(0), pin)); 669 670 /* while (pin < 128) */ 671 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 672 { 673 Aml *slot = aml_local(2); 674 Aml *lnk_idx = aml_local(3); 675 Aml *route = aml_local(4); 676 677 /* slot = pin >> 2 */ 678 aml_append(while_ctx, 679 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 680 /* lnk_idx = (slot + pin) & 3 */ 681 aml_append(while_ctx, 682 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 683 lnk_idx)); 684 685 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 686 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 687 if (is_pci0_prt) { 688 Aml *if_device_1, *if_pin_4, *else_pin_4; 689 690 /* device 1 is the power-management device, needs SCI */ 691 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 692 { 693 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 694 { 695 aml_append(if_pin_4, 696 aml_store(build_prt_entry("LNKS"), route)); 697 } 698 aml_append(if_device_1, if_pin_4); 699 else_pin_4 = aml_else(); 700 { 701 aml_append(else_pin_4, 702 aml_store(build_prt_entry("LNKA"), route)); 703 } 704 aml_append(if_device_1, else_pin_4); 705 } 706 aml_append(while_ctx, if_device_1); 707 } else { 708 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 709 } 710 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 711 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 712 713 /* route[0] = 0x[slot]FFFF */ 714 aml_append(while_ctx, 715 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 716 NULL), 717 aml_index(route, aml_int(0)))); 718 /* route[1] = pin & 3 */ 719 aml_append(while_ctx, 720 aml_store(aml_and(pin, aml_int(3), NULL), 721 aml_index(route, aml_int(1)))); 722 /* res[pin] = route */ 723 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 724 /* pin++ */ 725 aml_append(while_ctx, aml_increment(pin)); 726 } 727 aml_append(method, while_ctx); 728 /* return res*/ 729 aml_append(method, aml_return(res)); 730 731 return method; 732 } 733 734 typedef struct CrsRangeEntry { 735 uint64_t base; 736 uint64_t limit; 737 } CrsRangeEntry; 738 739 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 740 { 741 CrsRangeEntry *entry; 742 743 entry = g_malloc(sizeof(*entry)); 744 entry->base = base; 745 entry->limit = limit; 746 747 g_ptr_array_add(ranges, entry); 748 } 749 750 static void crs_range_free(gpointer data) 751 { 752 CrsRangeEntry *entry = (CrsRangeEntry *)data; 753 g_free(entry); 754 } 755 756 static gint crs_range_compare(gconstpointer a, gconstpointer b) 757 { 758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 760 761 return (int64_t)entry_a->base - (int64_t)entry_b->base; 762 } 763 764 /* 765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 766 * interval, computes the 'free' ranges from the same interval. 767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 768 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 769 */ 770 static void crs_replace_with_free_ranges(GPtrArray *ranges, 771 uint64_t start, uint64_t end) 772 { 773 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free); 774 uint64_t free_base = start; 775 int i; 776 777 g_ptr_array_sort(ranges, crs_range_compare); 778 for (i = 0; i < ranges->len; i++) { 779 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 780 781 if (free_base < used->base) { 782 crs_range_insert(free_ranges, free_base, used->base - 1); 783 } 784 785 free_base = used->limit + 1; 786 } 787 788 if (free_base < end) { 789 crs_range_insert(free_ranges, free_base, end); 790 } 791 792 g_ptr_array_set_size(ranges, 0); 793 for (i = 0; i < free_ranges->len; i++) { 794 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 795 } 796 797 g_ptr_array_free(free_ranges, false); 798 } 799 800 /* 801 * crs_range_merge - merges adjacent ranges in the given array. 802 * Array elements are deleted and replaced with the merged ranges. 803 */ 804 static void crs_range_merge(GPtrArray *range) 805 { 806 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 807 CrsRangeEntry *entry; 808 uint64_t range_base, range_limit; 809 int i; 810 811 if (!range->len) { 812 return; 813 } 814 815 g_ptr_array_sort(range, crs_range_compare); 816 817 entry = g_ptr_array_index(range, 0); 818 range_base = entry->base; 819 range_limit = entry->limit; 820 for (i = 1; i < range->len; i++) { 821 entry = g_ptr_array_index(range, i); 822 if (entry->base - 1 == range_limit) { 823 range_limit = entry->limit; 824 } else { 825 crs_range_insert(tmp, range_base, range_limit); 826 range_base = entry->base; 827 range_limit = entry->limit; 828 } 829 } 830 crs_range_insert(tmp, range_base, range_limit); 831 832 g_ptr_array_set_size(range, 0); 833 for (i = 0; i < tmp->len; i++) { 834 entry = g_ptr_array_index(tmp, i); 835 crs_range_insert(range, entry->base, entry->limit); 836 } 837 g_ptr_array_free(tmp, true); 838 } 839 840 static Aml *build_crs(PCIHostState *host, 841 GPtrArray *io_ranges, GPtrArray *mem_ranges) 842 { 843 Aml *crs = aml_resource_template(); 844 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 845 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 846 CrsRangeEntry *entry; 847 uint8_t max_bus = pci_bus_num(host->bus); 848 uint8_t type; 849 int devfn; 850 int i; 851 852 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 853 uint64_t range_base, range_limit; 854 PCIDevice *dev = host->bus->devices[devfn]; 855 856 if (!dev) { 857 continue; 858 } 859 860 for (i = 0; i < PCI_NUM_REGIONS; i++) { 861 PCIIORegion *r = &dev->io_regions[i]; 862 863 range_base = r->addr; 864 range_limit = r->addr + r->size - 1; 865 866 /* 867 * Work-around for old bioses 868 * that do not support multiple root buses 869 */ 870 if (!range_base || range_base > range_limit) { 871 continue; 872 } 873 874 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 875 crs_range_insert(host_io_ranges, range_base, range_limit); 876 } else { /* "memory" */ 877 crs_range_insert(host_mem_ranges, range_base, range_limit); 878 } 879 } 880 881 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 882 if (type == PCI_HEADER_TYPE_BRIDGE) { 883 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 884 if (subordinate > max_bus) { 885 max_bus = subordinate; 886 } 887 888 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 889 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 890 891 /* 892 * Work-around for old bioses 893 * that do not support multiple root buses 894 */ 895 if (range_base && range_base <= range_limit) { 896 crs_range_insert(host_io_ranges, range_base, range_limit); 897 } 898 899 range_base = 900 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 901 range_limit = 902 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 903 904 /* 905 * Work-around for old bioses 906 * that do not support multiple root buses 907 */ 908 if (range_base && range_base <= range_limit) { 909 crs_range_insert(host_mem_ranges, range_base, range_limit); 910 } 911 912 range_base = 913 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 914 range_limit = 915 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 916 917 /* 918 * Work-around for old bioses 919 * that do not support multiple root buses 920 */ 921 if (range_base && range_base <= range_limit) { 922 crs_range_insert(host_mem_ranges, range_base, range_limit); 923 } 924 } 925 } 926 927 crs_range_merge(host_io_ranges); 928 for (i = 0; i < host_io_ranges->len; i++) { 929 entry = g_ptr_array_index(host_io_ranges, i); 930 aml_append(crs, 931 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 932 AML_POS_DECODE, AML_ENTIRE_RANGE, 933 0, entry->base, entry->limit, 0, 934 entry->limit - entry->base + 1)); 935 crs_range_insert(io_ranges, entry->base, entry->limit); 936 } 937 g_ptr_array_free(host_io_ranges, true); 938 939 crs_range_merge(host_mem_ranges); 940 for (i = 0; i < host_mem_ranges->len; i++) { 941 entry = g_ptr_array_index(host_mem_ranges, i); 942 aml_append(crs, 943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 944 AML_MAX_FIXED, AML_NON_CACHEABLE, 945 AML_READ_WRITE, 946 0, entry->base, entry->limit, 0, 947 entry->limit - entry->base + 1)); 948 crs_range_insert(mem_ranges, entry->base, entry->limit); 949 } 950 g_ptr_array_free(host_mem_ranges, true); 951 952 aml_append(crs, 953 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 954 0, 955 pci_bus_num(host->bus), 956 max_bus, 957 0, 958 max_bus - pci_bus_num(host->bus) + 1)); 959 960 return crs; 961 } 962 963 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus, 964 AcpiCpuInfo *cpu, AcpiPmInfo *pm) 965 { 966 int i; 967 Aml *dev; 968 Aml *crs; 969 Aml *pkg; 970 Aml *field; 971 Aml *ifctx; 972 Aml *method; 973 974 /* The current AML generator can cover the APIC ID range [0..255], 975 * inclusive, for VCPU hotplug. */ 976 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 977 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 978 979 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 980 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 981 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 982 aml_append(dev, 983 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 984 ); 985 /* device present, functioning, decoding, not shown in UI */ 986 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 987 crs = aml_resource_template(); 988 aml_append(crs, 989 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 990 pm->cpu_hp_io_len) 991 ); 992 aml_append(dev, aml_name_decl("_CRS", crs)); 993 aml_append(sb_scope, dev); 994 /* declare CPU hotplug MMIO region and PRS field to access it */ 995 aml_append(sb_scope, aml_operation_region( 996 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len)); 997 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 998 aml_append(field, aml_named_field("PRS", 256)); 999 aml_append(sb_scope, field); 1000 1001 /* build Processor object for each processor */ 1002 for (i = 0; i < acpi_cpus; i++) { 1003 dev = aml_processor(i, 0, 0, "CP%.02X", i); 1004 1005 method = aml_method("_MAT", 0, AML_NOTSERIALIZED); 1006 aml_append(method, 1007 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i)))); 1008 aml_append(dev, method); 1009 1010 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1011 aml_append(method, 1012 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i)))); 1013 aml_append(dev, method); 1014 1015 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1016 aml_append(method, 1017 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0))) 1018 ); 1019 aml_append(dev, method); 1020 1021 aml_append(sb_scope, dev); 1022 } 1023 1024 /* build this code: 1025 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 1026 */ 1027 /* Arg0 = Processor ID = APIC ID */ 1028 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1029 for (i = 0; i < acpi_cpus; i++) { 1030 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1031 aml_append(ifctx, 1032 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 1033 ); 1034 aml_append(method, ifctx); 1035 } 1036 aml_append(sb_scope, method); 1037 1038 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 1039 * 1040 * Note: The ability to create variable-sized packages was first 1041 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 1042 * ith up to 255 elements. Windows guests up to win2k8 fail when 1043 * VarPackageOp is used. 1044 */ 1045 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 1046 aml_varpackage(acpi_cpus); 1047 1048 for (i = 0; i < acpi_cpus; i++) { 1049 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 1050 aml_append(pkg, aml_int(b)); 1051 } 1052 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); 1053 } 1054 1055 static void build_memory_devices(Aml *sb_scope, int nr_mem, 1056 uint16_t io_base, uint16_t io_len) 1057 { 1058 int i; 1059 Aml *scope; 1060 Aml *crs; 1061 Aml *field; 1062 Aml *dev; 1063 Aml *method; 1064 Aml *ifctx; 1065 1066 /* build memory devices */ 1067 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 1068 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE); 1069 aml_append(scope, 1070 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem)) 1071 ); 1072 1073 crs = aml_resource_template(); 1074 aml_append(crs, 1075 aml_io(AML_DECODE16, io_base, io_base, 0, io_len) 1076 ); 1077 aml_append(scope, aml_name_decl("_CRS", crs)); 1078 1079 aml_append(scope, aml_operation_region( 1080 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO, 1081 aml_int(io_base), io_len) 1082 ); 1083 1084 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1085 AML_NOLOCK, AML_PRESERVE); 1086 aml_append(field, /* read only */ 1087 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32)); 1088 aml_append(field, /* read only */ 1089 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32)); 1090 aml_append(field, /* read only */ 1091 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32)); 1092 aml_append(field, /* read only */ 1093 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32)); 1094 aml_append(field, /* read only */ 1095 aml_named_field(MEMORY_SLOT_PROXIMITY, 32)); 1096 aml_append(scope, field); 1097 1098 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC, 1099 AML_NOLOCK, AML_WRITE_AS_ZEROS); 1100 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 1101 aml_append(field, /* 1 if enabled, read only */ 1102 aml_named_field(MEMORY_SLOT_ENABLED, 1)); 1103 aml_append(field, 1104 /*(read) 1 if has a insert event. (write) 1 to clear event */ 1105 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1)); 1106 aml_append(field, 1107 /* (read) 1 if has a remove event. (write) 1 to clear event */ 1108 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1)); 1109 aml_append(field, 1110 /* initiates device eject, write only */ 1111 aml_named_field(MEMORY_SLOT_EJECT, 1)); 1112 aml_append(scope, field); 1113 1114 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1115 AML_NOLOCK, AML_PRESERVE); 1116 aml_append(field, /* DIMM selector, write only */ 1117 aml_named_field(MEMORY_SLOT_SLECTOR, 32)); 1118 aml_append(field, /* _OST event code, write only */ 1119 aml_named_field(MEMORY_SLOT_OST_EVENT, 32)); 1120 aml_append(field, /* _OST status code, write only */ 1121 aml_named_field(MEMORY_SLOT_OST_STATUS, 32)); 1122 aml_append(scope, field); 1123 aml_append(sb_scope, scope); 1124 1125 for (i = 0; i < nr_mem; i++) { 1126 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "." 1127 const char *s; 1128 1129 dev = aml_device("MP%02X", i); 1130 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 1131 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 1132 1133 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1134 s = BASEPATH MEMORY_SLOT_CRS_METHOD; 1135 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1136 aml_append(dev, method); 1137 1138 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1139 s = BASEPATH MEMORY_SLOT_STATUS_METHOD; 1140 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1141 aml_append(dev, method); 1142 1143 method = aml_method("_PXM", 0, AML_NOTSERIALIZED); 1144 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD; 1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1146 aml_append(dev, method); 1147 1148 method = aml_method("_OST", 3, AML_NOTSERIALIZED); 1149 s = BASEPATH MEMORY_SLOT_OST_METHOD; 1150 1151 aml_append(method, aml_return(aml_call4( 1152 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 1153 ))); 1154 aml_append(dev, method); 1155 1156 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1157 s = BASEPATH MEMORY_SLOT_EJECT_METHOD; 1158 aml_append(method, aml_return(aml_call2( 1159 s, aml_name("_UID"), aml_arg(0)))); 1160 aml_append(dev, method); 1161 1162 aml_append(sb_scope, dev); 1163 } 1164 1165 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 1166 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 1167 */ 1168 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1169 for (i = 0; i < nr_mem; i++) { 1170 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1171 aml_append(ifctx, 1172 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 1173 ); 1174 aml_append(method, ifctx); 1175 } 1176 aml_append(sb_scope, method); 1177 } 1178 1179 static void build_hpet_aml(Aml *table) 1180 { 1181 Aml *crs; 1182 Aml *field; 1183 Aml *method; 1184 Aml *if_ctx; 1185 Aml *scope = aml_scope("_SB"); 1186 Aml *dev = aml_device("HPET"); 1187 Aml *zero = aml_int(0); 1188 Aml *id = aml_local(0); 1189 Aml *period = aml_local(1); 1190 1191 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1192 aml_append(dev, aml_name_decl("_UID", zero)); 1193 1194 aml_append(dev, 1195 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1196 HPET_LEN)); 1197 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1198 aml_append(field, aml_named_field("VEND", 32)); 1199 aml_append(field, aml_named_field("PRD", 32)); 1200 aml_append(dev, field); 1201 1202 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1203 aml_append(method, aml_store(aml_name("VEND"), id)); 1204 aml_append(method, aml_store(aml_name("PRD"), period)); 1205 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1206 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1207 aml_equal(id, aml_int(0xffff)))); 1208 { 1209 aml_append(if_ctx, aml_return(zero)); 1210 } 1211 aml_append(method, if_ctx); 1212 1213 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1214 aml_lgreater(period, aml_int(100000000)))); 1215 { 1216 aml_append(if_ctx, aml_return(zero)); 1217 } 1218 aml_append(method, if_ctx); 1219 1220 aml_append(method, aml_return(aml_int(0x0F))); 1221 aml_append(dev, method); 1222 1223 crs = aml_resource_template(); 1224 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1225 aml_append(dev, aml_name_decl("_CRS", crs)); 1226 1227 aml_append(scope, dev); 1228 aml_append(table, scope); 1229 } 1230 1231 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1232 { 1233 Aml *dev, *fdi; 1234 uint8_t maxc, maxh, maxs; 1235 1236 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1237 1238 dev = aml_device("FLP%c", 'A' + idx); 1239 1240 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1241 1242 fdi = aml_package(16); 1243 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1244 aml_append(fdi, 1245 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1246 /* 1247 * the values below are the limits of the drive, and are thus independent 1248 * of the inserted media 1249 */ 1250 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1251 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1252 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1253 /* 1254 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1255 * the drive type, so shall we 1256 */ 1257 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1258 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1259 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1260 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1261 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1262 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1263 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1264 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1265 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1266 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1267 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1268 1269 aml_append(dev, aml_name_decl("_FDI", fdi)); 1270 return dev; 1271 } 1272 1273 static Aml *build_fdc_device_aml(ISADevice *fdc) 1274 { 1275 int i; 1276 Aml *dev; 1277 Aml *crs; 1278 1279 #define ACPI_FDE_MAX_FD 4 1280 uint32_t fde_buf[5] = { 1281 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1282 cpu_to_le32(2) /* tape presence (2 == never present) */ 1283 }; 1284 1285 dev = aml_device("FDC0"); 1286 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1287 1288 crs = aml_resource_template(); 1289 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1290 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1291 aml_append(crs, aml_irq_no_flags(6)); 1292 aml_append(crs, 1293 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1294 aml_append(dev, aml_name_decl("_CRS", crs)); 1295 1296 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1297 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1298 1299 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1300 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1301 aml_append(dev, build_fdinfo_aml(i, type)); 1302 } 1303 } 1304 aml_append(dev, aml_name_decl("_FDE", 1305 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1306 1307 return dev; 1308 } 1309 1310 static Aml *build_rtc_device_aml(void) 1311 { 1312 Aml *dev; 1313 Aml *crs; 1314 1315 dev = aml_device("RTC"); 1316 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1317 crs = aml_resource_template(); 1318 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1319 aml_append(crs, aml_irq_no_flags(8)); 1320 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1321 aml_append(dev, aml_name_decl("_CRS", crs)); 1322 1323 return dev; 1324 } 1325 1326 static Aml *build_kbd_device_aml(void) 1327 { 1328 Aml *dev; 1329 Aml *crs; 1330 Aml *method; 1331 1332 dev = aml_device("KBD"); 1333 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1334 1335 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1336 aml_append(method, aml_return(aml_int(0x0f))); 1337 aml_append(dev, method); 1338 1339 crs = aml_resource_template(); 1340 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1341 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1342 aml_append(crs, aml_irq_no_flags(1)); 1343 aml_append(dev, aml_name_decl("_CRS", crs)); 1344 1345 return dev; 1346 } 1347 1348 static Aml *build_mouse_device_aml(void) 1349 { 1350 Aml *dev; 1351 Aml *crs; 1352 Aml *method; 1353 1354 dev = aml_device("MOU"); 1355 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1356 1357 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1358 aml_append(method, aml_return(aml_int(0x0f))); 1359 aml_append(dev, method); 1360 1361 crs = aml_resource_template(); 1362 aml_append(crs, aml_irq_no_flags(12)); 1363 aml_append(dev, aml_name_decl("_CRS", crs)); 1364 1365 return dev; 1366 } 1367 1368 static Aml *build_lpt_device_aml(void) 1369 { 1370 Aml *dev; 1371 Aml *crs; 1372 Aml *method; 1373 Aml *if_ctx; 1374 Aml *else_ctx; 1375 Aml *zero = aml_int(0); 1376 Aml *is_present = aml_local(0); 1377 1378 dev = aml_device("LPT"); 1379 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1380 1381 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1382 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1383 if_ctx = aml_if(aml_equal(is_present, zero)); 1384 { 1385 aml_append(if_ctx, aml_return(aml_int(0x00))); 1386 } 1387 aml_append(method, if_ctx); 1388 else_ctx = aml_else(); 1389 { 1390 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1391 } 1392 aml_append(method, else_ctx); 1393 aml_append(dev, method); 1394 1395 crs = aml_resource_template(); 1396 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1397 aml_append(crs, aml_irq_no_flags(7)); 1398 aml_append(dev, aml_name_decl("_CRS", crs)); 1399 1400 return dev; 1401 } 1402 1403 static Aml *build_com_device_aml(uint8_t uid) 1404 { 1405 Aml *dev; 1406 Aml *crs; 1407 Aml *method; 1408 Aml *if_ctx; 1409 Aml *else_ctx; 1410 Aml *zero = aml_int(0); 1411 Aml *is_present = aml_local(0); 1412 const char *enabled_field = "CAEN"; 1413 uint8_t irq = 4; 1414 uint16_t io_port = 0x03F8; 1415 1416 assert(uid == 1 || uid == 2); 1417 if (uid == 2) { 1418 enabled_field = "CBEN"; 1419 irq = 3; 1420 io_port = 0x02F8; 1421 } 1422 1423 dev = aml_device("COM%d", uid); 1424 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1425 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1426 1427 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1428 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1429 if_ctx = aml_if(aml_equal(is_present, zero)); 1430 { 1431 aml_append(if_ctx, aml_return(aml_int(0x00))); 1432 } 1433 aml_append(method, if_ctx); 1434 else_ctx = aml_else(); 1435 { 1436 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1437 } 1438 aml_append(method, else_ctx); 1439 aml_append(dev, method); 1440 1441 crs = aml_resource_template(); 1442 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1443 aml_append(crs, aml_irq_no_flags(irq)); 1444 aml_append(dev, aml_name_decl("_CRS", crs)); 1445 1446 return dev; 1447 } 1448 1449 static void build_isa_devices_aml(Aml *table) 1450 { 1451 ISADevice *fdc = pc_find_fdc0(); 1452 1453 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1454 1455 aml_append(scope, build_rtc_device_aml()); 1456 aml_append(scope, build_kbd_device_aml()); 1457 aml_append(scope, build_mouse_device_aml()); 1458 if (fdc) { 1459 aml_append(scope, build_fdc_device_aml(fdc)); 1460 } 1461 aml_append(scope, build_lpt_device_aml()); 1462 aml_append(scope, build_com_device_aml(1)); 1463 aml_append(scope, build_com_device_aml(2)); 1464 1465 aml_append(table, scope); 1466 } 1467 1468 static void build_dbg_aml(Aml *table) 1469 { 1470 Aml *field; 1471 Aml *method; 1472 Aml *while_ctx; 1473 Aml *scope = aml_scope("\\"); 1474 Aml *buf = aml_local(0); 1475 Aml *len = aml_local(1); 1476 Aml *idx = aml_local(2); 1477 1478 aml_append(scope, 1479 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1480 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1481 aml_append(field, aml_named_field("DBGB", 8)); 1482 aml_append(scope, field); 1483 1484 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1485 1486 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1487 aml_append(method, aml_to_buffer(buf, buf)); 1488 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1489 aml_append(method, aml_store(aml_int(0), idx)); 1490 1491 while_ctx = aml_while(aml_lless(idx, len)); 1492 aml_append(while_ctx, 1493 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1494 aml_append(while_ctx, aml_increment(idx)); 1495 aml_append(method, while_ctx); 1496 1497 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1498 aml_append(scope, method); 1499 1500 aml_append(table, scope); 1501 } 1502 1503 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1504 { 1505 Aml *dev; 1506 Aml *crs; 1507 Aml *method; 1508 uint32_t irqs[] = {5, 10, 11}; 1509 1510 dev = aml_device("%s", name); 1511 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1512 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1513 1514 crs = aml_resource_template(); 1515 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1516 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1517 aml_append(dev, aml_name_decl("_PRS", crs)); 1518 1519 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1520 aml_append(method, aml_return(aml_call1("IQST", reg))); 1521 aml_append(dev, method); 1522 1523 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1524 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1525 aml_append(dev, method); 1526 1527 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1528 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1529 aml_append(dev, method); 1530 1531 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1532 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1533 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1534 aml_append(dev, method); 1535 1536 return dev; 1537 } 1538 1539 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1540 { 1541 Aml *dev; 1542 Aml *crs; 1543 Aml *method; 1544 uint32_t irqs; 1545 1546 dev = aml_device("%s", name); 1547 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1548 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1549 1550 crs = aml_resource_template(); 1551 irqs = gsi; 1552 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1553 AML_SHARED, &irqs, 1)); 1554 aml_append(dev, aml_name_decl("_PRS", crs)); 1555 1556 aml_append(dev, aml_name_decl("_CRS", crs)); 1557 1558 /* 1559 * _DIS can be no-op because the interrupt cannot be disabled. 1560 */ 1561 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1562 aml_append(dev, method); 1563 1564 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1565 aml_append(dev, method); 1566 1567 return dev; 1568 } 1569 1570 /* _CRS method - get current settings */ 1571 static Aml *build_iqcr_method(bool is_piix4) 1572 { 1573 Aml *if_ctx; 1574 uint32_t irqs; 1575 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1576 Aml *crs = aml_resource_template(); 1577 1578 irqs = 0; 1579 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1580 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1581 aml_append(method, aml_name_decl("PRR0", crs)); 1582 1583 aml_append(method, 1584 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1585 1586 if (is_piix4) { 1587 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1588 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1589 aml_append(method, if_ctx); 1590 } else { 1591 aml_append(method, 1592 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1593 aml_name("PRRI"))); 1594 } 1595 1596 aml_append(method, aml_return(aml_name("PRR0"))); 1597 return method; 1598 } 1599 1600 /* _STA method - get status */ 1601 static Aml *build_irq_status_method(void) 1602 { 1603 Aml *if_ctx; 1604 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1605 1606 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1607 aml_append(if_ctx, aml_return(aml_int(0x09))); 1608 aml_append(method, if_ctx); 1609 aml_append(method, aml_return(aml_int(0x0B))); 1610 return method; 1611 } 1612 1613 static void build_piix4_pci0_int(Aml *table) 1614 { 1615 Aml *dev; 1616 Aml *crs; 1617 Aml *field; 1618 Aml *method; 1619 uint32_t irqs; 1620 Aml *sb_scope = aml_scope("_SB"); 1621 Aml *pci0_scope = aml_scope("PCI0"); 1622 1623 aml_append(pci0_scope, build_prt(true)); 1624 aml_append(sb_scope, pci0_scope); 1625 1626 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1627 aml_append(field, aml_named_field("PRQ0", 8)); 1628 aml_append(field, aml_named_field("PRQ1", 8)); 1629 aml_append(field, aml_named_field("PRQ2", 8)); 1630 aml_append(field, aml_named_field("PRQ3", 8)); 1631 aml_append(sb_scope, field); 1632 1633 aml_append(sb_scope, build_irq_status_method()); 1634 aml_append(sb_scope, build_iqcr_method(true)); 1635 1636 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1637 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1638 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1639 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1640 1641 dev = aml_device("LNKS"); 1642 { 1643 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1644 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1645 1646 crs = aml_resource_template(); 1647 irqs = 9; 1648 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1649 AML_ACTIVE_HIGH, AML_SHARED, 1650 &irqs, 1)); 1651 aml_append(dev, aml_name_decl("_PRS", crs)); 1652 1653 /* The SCI cannot be disabled and is always attached to GSI 9, 1654 * so these are no-ops. We only need this link to override the 1655 * polarity to active high and match the content of the MADT. 1656 */ 1657 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1658 aml_append(method, aml_return(aml_int(0x0b))); 1659 aml_append(dev, method); 1660 1661 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1662 aml_append(dev, method); 1663 1664 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1665 aml_append(method, aml_return(aml_name("_PRS"))); 1666 aml_append(dev, method); 1667 1668 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1669 aml_append(dev, method); 1670 } 1671 aml_append(sb_scope, dev); 1672 1673 aml_append(table, sb_scope); 1674 } 1675 1676 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1677 { 1678 int i; 1679 int head; 1680 Aml *pkg; 1681 char base = name[3] < 'E' ? 'A' : 'E'; 1682 char *s = g_strdup(name); 1683 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1684 1685 assert(strlen(s) == 4); 1686 1687 head = name[3] - base; 1688 for (i = 0; i < 4; i++) { 1689 if (head + i > 3) { 1690 head = i * -1; 1691 } 1692 s[3] = base + head + i; 1693 pkg = aml_package(4); 1694 aml_append(pkg, a_nr); 1695 aml_append(pkg, aml_int(i)); 1696 aml_append(pkg, aml_name("%s", s)); 1697 aml_append(pkg, aml_int(0)); 1698 aml_append(ctx, pkg); 1699 } 1700 g_free(s); 1701 } 1702 1703 static Aml *build_q35_routing_table(const char *str) 1704 { 1705 int i; 1706 Aml *pkg; 1707 char *name = g_strdup_printf("%s ", str); 1708 1709 pkg = aml_package(128); 1710 for (i = 0; i < 0x18; i++) { 1711 name[3] = 'E' + (i & 0x3); 1712 append_q35_prt_entry(pkg, i, name); 1713 } 1714 1715 name[3] = 'E'; 1716 append_q35_prt_entry(pkg, 0x18, name); 1717 1718 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1719 for (i = 0x0019; i < 0x1e; i++) { 1720 name[3] = 'A'; 1721 append_q35_prt_entry(pkg, i, name); 1722 } 1723 1724 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1725 name[3] = 'E'; 1726 append_q35_prt_entry(pkg, 0x1e, name); 1727 name[3] = 'A'; 1728 append_q35_prt_entry(pkg, 0x1f, name); 1729 1730 g_free(name); 1731 return pkg; 1732 } 1733 1734 static void build_q35_pci0_int(Aml *table) 1735 { 1736 Aml *field; 1737 Aml *method; 1738 Aml *sb_scope = aml_scope("_SB"); 1739 Aml *pci0_scope = aml_scope("PCI0"); 1740 1741 /* Zero => PIC mode, One => APIC Mode */ 1742 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1743 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1744 { 1745 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1746 } 1747 aml_append(table, method); 1748 1749 aml_append(pci0_scope, 1750 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1751 aml_append(pci0_scope, 1752 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1753 1754 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1755 { 1756 Aml *if_ctx; 1757 Aml *else_ctx; 1758 1759 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1760 section 6.2.8.1 */ 1761 /* Note: we provide the same info as the PCI routing 1762 table of the Bochs BIOS */ 1763 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1764 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1765 aml_append(method, if_ctx); 1766 else_ctx = aml_else(); 1767 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1768 aml_append(method, else_ctx); 1769 } 1770 aml_append(pci0_scope, method); 1771 aml_append(sb_scope, pci0_scope); 1772 1773 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1774 aml_append(field, aml_named_field("PRQA", 8)); 1775 aml_append(field, aml_named_field("PRQB", 8)); 1776 aml_append(field, aml_named_field("PRQC", 8)); 1777 aml_append(field, aml_named_field("PRQD", 8)); 1778 aml_append(field, aml_reserved_field(0x20)); 1779 aml_append(field, aml_named_field("PRQE", 8)); 1780 aml_append(field, aml_named_field("PRQF", 8)); 1781 aml_append(field, aml_named_field("PRQG", 8)); 1782 aml_append(field, aml_named_field("PRQH", 8)); 1783 aml_append(sb_scope, field); 1784 1785 aml_append(sb_scope, build_irq_status_method()); 1786 aml_append(sb_scope, build_iqcr_method(false)); 1787 1788 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1789 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1790 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1791 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1792 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1793 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1794 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1795 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1796 1797 /* 1798 * TODO: UID probably shouldn't be the same for GSIx devices 1799 * but that's how it was in original ASL so keep it for now 1800 */ 1801 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10)); 1802 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11)); 1803 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12)); 1804 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13)); 1805 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14)); 1806 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15)); 1807 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16)); 1808 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17)); 1809 1810 aml_append(table, sb_scope); 1811 } 1812 1813 static void build_q35_isa_bridge(Aml *table) 1814 { 1815 Aml *dev; 1816 Aml *scope; 1817 Aml *field; 1818 1819 scope = aml_scope("_SB.PCI0"); 1820 dev = aml_device("ISA"); 1821 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1822 1823 /* ICH9 PCI to ISA irq remapping */ 1824 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1825 aml_int(0x60), 0x0C)); 1826 1827 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1828 aml_int(0x80), 0x02)); 1829 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1830 aml_append(field, aml_named_field("COMA", 3)); 1831 aml_append(field, aml_reserved_field(1)); 1832 aml_append(field, aml_named_field("COMB", 3)); 1833 aml_append(field, aml_reserved_field(1)); 1834 aml_append(field, aml_named_field("LPTD", 2)); 1835 aml_append(dev, field); 1836 1837 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1838 aml_int(0x82), 0x02)); 1839 /* enable bits */ 1840 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1841 aml_append(field, aml_named_field("CAEN", 1)); 1842 aml_append(field, aml_named_field("CBEN", 1)); 1843 aml_append(field, aml_named_field("LPEN", 1)); 1844 aml_append(dev, field); 1845 1846 aml_append(scope, dev); 1847 aml_append(table, scope); 1848 } 1849 1850 static void build_piix4_pm(Aml *table) 1851 { 1852 Aml *dev; 1853 Aml *scope; 1854 1855 scope = aml_scope("_SB.PCI0"); 1856 dev = aml_device("PX13"); 1857 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1858 1859 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1860 aml_int(0x00), 0xff)); 1861 aml_append(scope, dev); 1862 aml_append(table, scope); 1863 } 1864 1865 static void build_piix4_isa_bridge(Aml *table) 1866 { 1867 Aml *dev; 1868 Aml *scope; 1869 Aml *field; 1870 1871 scope = aml_scope("_SB.PCI0"); 1872 dev = aml_device("ISA"); 1873 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1874 1875 /* PIIX PCI to ISA irq remapping */ 1876 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1877 aml_int(0x60), 0x04)); 1878 /* enable bits */ 1879 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1880 /* Offset(0x5f),, 7, */ 1881 aml_append(field, aml_reserved_field(0x2f8)); 1882 aml_append(field, aml_reserved_field(7)); 1883 aml_append(field, aml_named_field("LPEN", 1)); 1884 /* Offset(0x67),, 3, */ 1885 aml_append(field, aml_reserved_field(0x38)); 1886 aml_append(field, aml_reserved_field(3)); 1887 aml_append(field, aml_named_field("CAEN", 1)); 1888 aml_append(field, aml_reserved_field(3)); 1889 aml_append(field, aml_named_field("CBEN", 1)); 1890 aml_append(dev, field); 1891 1892 aml_append(scope, dev); 1893 aml_append(table, scope); 1894 } 1895 1896 static void build_piix4_pci_hotplug(Aml *table) 1897 { 1898 Aml *scope; 1899 Aml *field; 1900 Aml *method; 1901 1902 scope = aml_scope("_SB.PCI0"); 1903 1904 aml_append(scope, 1905 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1906 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1907 aml_append(field, aml_named_field("PCIU", 32)); 1908 aml_append(field, aml_named_field("PCID", 32)); 1909 aml_append(scope, field); 1910 1911 aml_append(scope, 1912 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1913 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1914 aml_append(field, aml_named_field("B0EJ", 32)); 1915 aml_append(scope, field); 1916 1917 aml_append(scope, 1918 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1919 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1920 aml_append(field, aml_named_field("BNUM", 32)); 1921 aml_append(scope, field); 1922 1923 aml_append(scope, aml_mutex("BLCK", 0)); 1924 1925 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1926 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1927 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1928 aml_append(method, 1929 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1930 aml_append(method, aml_release(aml_name("BLCK"))); 1931 aml_append(method, aml_return(aml_int(0))); 1932 aml_append(scope, method); 1933 1934 aml_append(table, scope); 1935 } 1936 1937 static Aml *build_q35_osc_method(void) 1938 { 1939 Aml *if_ctx; 1940 Aml *if_ctx2; 1941 Aml *else_ctx; 1942 Aml *method; 1943 Aml *a_cwd1 = aml_name("CDW1"); 1944 Aml *a_ctrl = aml_name("CTRL"); 1945 1946 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1947 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1948 1949 if_ctx = aml_if(aml_equal( 1950 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1951 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1952 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1953 1954 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 1955 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1956 1957 /* 1958 * Always allow native PME, AER (no dependencies) 1959 * Never allow SHPC (no SHPC controller in this system) 1960 */ 1961 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1962 1963 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1964 /* Unknown revision */ 1965 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1966 aml_append(if_ctx, if_ctx2); 1967 1968 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1969 /* Capabilities bits were masked */ 1970 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1971 aml_append(if_ctx, if_ctx2); 1972 1973 /* Update DWORD3 in the buffer */ 1974 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1975 aml_append(method, if_ctx); 1976 1977 else_ctx = aml_else(); 1978 /* Unrecognized UUID */ 1979 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1980 aml_append(method, else_ctx); 1981 1982 aml_append(method, aml_return(aml_arg(3))); 1983 return method; 1984 } 1985 1986 static void 1987 build_dsdt(GArray *table_data, GArray *linker, 1988 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 1989 PcPciInfo *pci) 1990 { 1991 CrsRangeEntry *entry; 1992 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1993 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1994 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1995 MachineState *machine = MACHINE(qdev_get_machine()); 1996 PCMachineState *pcms = PC_MACHINE(machine); 1997 uint32_t nr_mem = machine->ram_slots; 1998 int root_bus_limit = 0xFF; 1999 PCIBus *bus = NULL; 2000 int i; 2001 2002 dsdt = init_aml_allocator(); 2003 2004 /* Reserve space for header */ 2005 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 2006 2007 build_dbg_aml(dsdt); 2008 if (misc->is_piix4) { 2009 sb_scope = aml_scope("_SB"); 2010 dev = aml_device("PCI0"); 2011 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2012 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2013 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2014 aml_append(sb_scope, dev); 2015 aml_append(dsdt, sb_scope); 2016 2017 build_hpet_aml(dsdt); 2018 build_piix4_pm(dsdt); 2019 build_piix4_isa_bridge(dsdt); 2020 build_isa_devices_aml(dsdt); 2021 build_piix4_pci_hotplug(dsdt); 2022 build_piix4_pci0_int(dsdt); 2023 } else { 2024 sb_scope = aml_scope("_SB"); 2025 aml_append(sb_scope, 2026 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c)); 2027 aml_append(sb_scope, 2028 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01)); 2029 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 2030 aml_append(field, aml_named_field("PCIB", 8)); 2031 aml_append(sb_scope, field); 2032 aml_append(dsdt, sb_scope); 2033 2034 sb_scope = aml_scope("_SB"); 2035 dev = aml_device("PCI0"); 2036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 2037 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 2038 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2039 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2040 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 2041 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 2042 aml_append(dev, build_q35_osc_method()); 2043 aml_append(sb_scope, dev); 2044 aml_append(dsdt, sb_scope); 2045 2046 build_hpet_aml(dsdt); 2047 build_q35_isa_bridge(dsdt); 2048 build_isa_devices_aml(dsdt); 2049 build_q35_pci0_int(dsdt); 2050 } 2051 2052 build_cpu_hotplug_aml(dsdt); 2053 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, 2054 pm->mem_hp_io_len); 2055 2056 scope = aml_scope("_GPE"); 2057 { 2058 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 2059 2060 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); 2061 2062 if (misc->is_piix4) { 2063 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 2064 aml_append(method, 2065 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 2066 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 2067 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 2068 aml_append(scope, method); 2069 } else { 2070 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); 2071 } 2072 2073 method = aml_method("_E02", 0, AML_NOTSERIALIZED); 2074 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); 2075 aml_append(scope, method); 2076 2077 method = aml_method("_E03", 0, AML_NOTSERIALIZED); 2078 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); 2079 aml_append(scope, method); 2080 2081 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); 2082 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); 2083 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); 2084 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); 2085 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); 2086 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); 2087 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); 2088 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); 2089 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); 2090 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); 2091 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); 2092 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); 2093 } 2094 aml_append(dsdt, scope); 2095 2096 bus = PC_MACHINE(machine)->bus; 2097 if (bus) { 2098 QLIST_FOREACH(bus, &bus->child, sibling) { 2099 uint8_t bus_num = pci_bus_num(bus); 2100 uint8_t numa_node = pci_bus_numa_node(bus); 2101 2102 /* look only for expander root buses */ 2103 if (!pci_bus_is_root(bus)) { 2104 continue; 2105 } 2106 2107 if (bus_num < root_bus_limit) { 2108 root_bus_limit = bus_num - 1; 2109 } 2110 2111 scope = aml_scope("\\_SB"); 2112 dev = aml_device("PC%.02X", bus_num); 2113 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 2114 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2115 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 2116 2117 if (numa_node != NUMA_NODE_UNASSIGNED) { 2118 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 2119 } 2120 2121 aml_append(dev, build_prt(false)); 2122 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), 2123 io_ranges, mem_ranges); 2124 aml_append(dev, aml_name_decl("_CRS", crs)); 2125 aml_append(scope, dev); 2126 aml_append(dsdt, scope); 2127 } 2128 } 2129 2130 scope = aml_scope("\\_SB.PCI0"); 2131 /* build PCI0._CRS */ 2132 crs = aml_resource_template(); 2133 aml_append(crs, 2134 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 2135 0x0000, 0x0, root_bus_limit, 2136 0x0000, root_bus_limit + 1)); 2137 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2138 2139 aml_append(crs, 2140 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2141 AML_POS_DECODE, AML_ENTIRE_RANGE, 2142 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2143 2144 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); 2145 for (i = 0; i < io_ranges->len; i++) { 2146 entry = g_ptr_array_index(io_ranges, i); 2147 aml_append(crs, 2148 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2149 AML_POS_DECODE, AML_ENTIRE_RANGE, 2150 0x0000, entry->base, entry->limit, 2151 0x0000, entry->limit - entry->base + 1)); 2152 } 2153 2154 aml_append(crs, 2155 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2156 AML_CACHEABLE, AML_READ_WRITE, 2157 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2158 2159 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); 2160 for (i = 0; i < mem_ranges->len; i++) { 2161 entry = g_ptr_array_index(mem_ranges, i); 2162 aml_append(crs, 2163 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2164 AML_NON_CACHEABLE, AML_READ_WRITE, 2165 0, entry->base, entry->limit, 2166 0, entry->limit - entry->base + 1)); 2167 } 2168 2169 if (pci->w64.begin) { 2170 aml_append(crs, 2171 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2172 AML_CACHEABLE, AML_READ_WRITE, 2173 0, pci->w64.begin, pci->w64.end - 1, 0, 2174 pci->w64.end - pci->w64.begin)); 2175 } 2176 aml_append(scope, aml_name_decl("_CRS", crs)); 2177 2178 /* reserve GPE0 block resources */ 2179 dev = aml_device("GPE0"); 2180 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2181 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2182 /* device present, functioning, decoding, not shown in UI */ 2183 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2184 crs = aml_resource_template(); 2185 aml_append(crs, 2186 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2187 ); 2188 aml_append(dev, aml_name_decl("_CRS", crs)); 2189 aml_append(scope, dev); 2190 2191 g_ptr_array_free(io_ranges, true); 2192 g_ptr_array_free(mem_ranges, true); 2193 2194 /* reserve PCIHP resources */ 2195 if (pm->pcihp_io_len) { 2196 dev = aml_device("PHPR"); 2197 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2198 aml_append(dev, 2199 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2200 /* device present, functioning, decoding, not shown in UI */ 2201 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2202 crs = aml_resource_template(); 2203 aml_append(crs, 2204 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2205 pm->pcihp_io_len) 2206 ); 2207 aml_append(dev, aml_name_decl("_CRS", crs)); 2208 aml_append(scope, dev); 2209 } 2210 aml_append(dsdt, scope); 2211 2212 /* create S3_ / S4_ / S5_ packages if necessary */ 2213 scope = aml_scope("\\"); 2214 if (!pm->s3_disabled) { 2215 pkg = aml_package(4); 2216 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2217 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2218 aml_append(pkg, aml_int(0)); /* reserved */ 2219 aml_append(pkg, aml_int(0)); /* reserved */ 2220 aml_append(scope, aml_name_decl("_S3", pkg)); 2221 } 2222 2223 if (!pm->s4_disabled) { 2224 pkg = aml_package(4); 2225 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2226 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2227 aml_append(pkg, aml_int(pm->s4_val)); 2228 aml_append(pkg, aml_int(0)); /* reserved */ 2229 aml_append(pkg, aml_int(0)); /* reserved */ 2230 aml_append(scope, aml_name_decl("_S4", pkg)); 2231 } 2232 2233 pkg = aml_package(4); 2234 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2235 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2236 aml_append(pkg, aml_int(0)); /* reserved */ 2237 aml_append(pkg, aml_int(0)); /* reserved */ 2238 aml_append(scope, aml_name_decl("_S5", pkg)); 2239 aml_append(dsdt, scope); 2240 2241 /* create fw_cfg node, unconditionally */ 2242 { 2243 /* when using port i/o, the 8-bit data register *always* overlaps 2244 * with half of the 16-bit control register. Hence, the total size 2245 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2246 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2247 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2248 "dma_enabled", NULL) ? 2249 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2250 FW_CFG_CTL_SIZE; 2251 2252 scope = aml_scope("\\_SB.PCI0"); 2253 dev = aml_device("FWCF"); 2254 2255 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2256 2257 /* device present, functioning, decoding, not shown in UI */ 2258 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2259 2260 crs = aml_resource_template(); 2261 aml_append(crs, 2262 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2263 ); 2264 aml_append(dev, aml_name_decl("_CRS", crs)); 2265 2266 aml_append(scope, dev); 2267 aml_append(dsdt, scope); 2268 } 2269 2270 if (misc->applesmc_io_base) { 2271 scope = aml_scope("\\_SB.PCI0.ISA"); 2272 dev = aml_device("SMC"); 2273 2274 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2275 /* device present, functioning, decoding, not shown in UI */ 2276 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2277 2278 crs = aml_resource_template(); 2279 aml_append(crs, 2280 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2281 0x01, APPLESMC_MAX_DATA_LENGTH) 2282 ); 2283 aml_append(crs, aml_irq_no_flags(6)); 2284 aml_append(dev, aml_name_decl("_CRS", crs)); 2285 2286 aml_append(scope, dev); 2287 aml_append(dsdt, scope); 2288 } 2289 2290 if (misc->pvpanic_port) { 2291 scope = aml_scope("\\_SB.PCI0.ISA"); 2292 2293 dev = aml_device("PEVT"); 2294 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2295 2296 crs = aml_resource_template(); 2297 aml_append(crs, 2298 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2299 ); 2300 aml_append(dev, aml_name_decl("_CRS", crs)); 2301 2302 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2303 aml_int(misc->pvpanic_port), 1)); 2304 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2305 aml_append(field, aml_named_field("PEPT", 8)); 2306 aml_append(dev, field); 2307 2308 /* device present, functioning, decoding, shown in UI */ 2309 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2310 2311 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2312 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2313 aml_append(method, aml_return(aml_local(0))); 2314 aml_append(dev, method); 2315 2316 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2317 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2318 aml_append(dev, method); 2319 2320 aml_append(scope, dev); 2321 aml_append(dsdt, scope); 2322 } 2323 2324 sb_scope = aml_scope("\\_SB"); 2325 { 2326 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm); 2327 2328 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, 2329 pm->mem_hp_io_len); 2330 2331 { 2332 Object *pci_host; 2333 PCIBus *bus = NULL; 2334 2335 pci_host = acpi_get_i386_pci_host(); 2336 if (pci_host) { 2337 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2338 } 2339 2340 if (bus) { 2341 Aml *scope = aml_scope("PCI0"); 2342 /* Scan all PCI buses. Generate tables to support hotplug. */ 2343 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2344 2345 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2346 dev = aml_device("ISA.TPM"); 2347 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2348 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2349 crs = aml_resource_template(); 2350 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2351 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2352 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); 2353 aml_append(dev, aml_name_decl("_CRS", crs)); 2354 aml_append(scope, dev); 2355 } 2356 2357 aml_append(sb_scope, scope); 2358 } 2359 } 2360 aml_append(dsdt, sb_scope); 2361 } 2362 2363 /* copy AML table into ACPI tables blob and patch header there */ 2364 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2365 build_header(linker, table_data, 2366 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2367 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2368 free_aml_allocator(); 2369 } 2370 2371 static void 2372 build_hpet(GArray *table_data, GArray *linker) 2373 { 2374 Acpi20Hpet *hpet; 2375 2376 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2377 /* Note timer_block_id value must be kept in sync with value advertised by 2378 * emulated hpet 2379 */ 2380 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2381 hpet->addr.address = cpu_to_le64(HPET_BASE); 2382 build_header(linker, table_data, 2383 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2384 } 2385 2386 static void 2387 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 2388 { 2389 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2390 uint64_t log_area_start_address = acpi_data_len(tcpalog); 2391 2392 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2393 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2394 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 2395 2396 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 2397 false /* high memory */); 2398 2399 /* log area start address to be filled by Guest linker */ 2400 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2401 ACPI_BUILD_TPMLOG_FILE, 2402 table_data, &tcpa->log_area_start_address, 2403 sizeof(tcpa->log_area_start_address)); 2404 2405 build_header(linker, table_data, 2406 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2407 2408 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2409 } 2410 2411 static void 2412 build_tpm2(GArray *table_data, GArray *linker) 2413 { 2414 Acpi20TPM2 *tpm2_ptr; 2415 2416 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2417 2418 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2419 tpm2_ptr->control_area_address = cpu_to_le64(0); 2420 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2421 2422 build_header(linker, table_data, 2423 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2424 } 2425 2426 typedef enum { 2427 MEM_AFFINITY_NOFLAGS = 0, 2428 MEM_AFFINITY_ENABLED = (1 << 0), 2429 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 2430 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 2431 } MemoryAffinityFlags; 2432 2433 static void 2434 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 2435 uint64_t len, int node, MemoryAffinityFlags flags) 2436 { 2437 numamem->type = ACPI_SRAT_MEMORY; 2438 numamem->length = sizeof(*numamem); 2439 memset(numamem->proximity, 0, 4); 2440 numamem->proximity[0] = node; 2441 numamem->flags = cpu_to_le32(flags); 2442 numamem->base_addr = cpu_to_le64(base); 2443 numamem->range_length = cpu_to_le64(len); 2444 } 2445 2446 static void 2447 build_srat(GArray *table_data, GArray *linker) 2448 { 2449 AcpiSystemResourceAffinityTable *srat; 2450 AcpiSratProcessorAffinity *core; 2451 AcpiSratMemoryAffinity *numamem; 2452 2453 int i; 2454 uint64_t curnode; 2455 int srat_start, numa_start, slots; 2456 uint64_t mem_len, mem_base, next_base; 2457 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2458 ram_addr_t hotplugabble_address_space_size = 2459 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2460 NULL); 2461 2462 srat_start = table_data->len; 2463 2464 srat = acpi_data_push(table_data, sizeof *srat); 2465 srat->reserved1 = cpu_to_le32(1); 2466 core = (void *)(srat + 1); 2467 2468 for (i = 0; i < pcms->apic_id_limit; ++i) { 2469 core = acpi_data_push(table_data, sizeof *core); 2470 core->type = ACPI_SRAT_PROCESSOR; 2471 core->length = sizeof(*core); 2472 core->local_apic_id = i; 2473 curnode = pcms->node_cpu[i]; 2474 core->proximity_lo = curnode; 2475 memset(core->proximity_hi, 0, 3); 2476 core->local_sapic_eid = 0; 2477 core->flags = cpu_to_le32(1); 2478 } 2479 2480 2481 /* the memory map is a bit tricky, it contains at least one hole 2482 * from 640k-1M and possibly another one from 3.5G-4G. 2483 */ 2484 next_base = 0; 2485 numa_start = table_data->len; 2486 2487 numamem = acpi_data_push(table_data, sizeof *numamem); 2488 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 2489 next_base = 1024 * 1024; 2490 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2491 mem_base = next_base; 2492 mem_len = pcms->node_mem[i - 1]; 2493 if (i == 1) { 2494 mem_len -= 1024 * 1024; 2495 } 2496 next_base = mem_base + mem_len; 2497 2498 /* Cut out the ACPI_PCI hole */ 2499 if (mem_base <= pcms->below_4g_mem_size && 2500 next_base > pcms->below_4g_mem_size) { 2501 mem_len -= next_base - pcms->below_4g_mem_size; 2502 if (mem_len > 0) { 2503 numamem = acpi_data_push(table_data, sizeof *numamem); 2504 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2505 MEM_AFFINITY_ENABLED); 2506 } 2507 mem_base = 1ULL << 32; 2508 mem_len = next_base - pcms->below_4g_mem_size; 2509 next_base += (1ULL << 32) - pcms->below_4g_mem_size; 2510 } 2511 numamem = acpi_data_push(table_data, sizeof *numamem); 2512 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2513 MEM_AFFINITY_ENABLED); 2514 } 2515 slots = (table_data->len - numa_start) / sizeof *numamem; 2516 for (; slots < pcms->numa_nodes + 2; slots++) { 2517 numamem = acpi_data_push(table_data, sizeof *numamem); 2518 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2519 } 2520 2521 /* 2522 * Entry is required for Windows to enable memory hotplug in OS. 2523 * Memory devices may override proximity set by this entry, 2524 * providing _PXM method if necessary. 2525 */ 2526 if (hotplugabble_address_space_size) { 2527 numamem = acpi_data_push(table_data, sizeof *numamem); 2528 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, 2529 hotplugabble_address_space_size, 0, 2530 MEM_AFFINITY_HOTPLUGGABLE | 2531 MEM_AFFINITY_ENABLED); 2532 } 2533 2534 build_header(linker, table_data, 2535 (void *)(table_data->data + srat_start), 2536 "SRAT", 2537 table_data->len - srat_start, 1, NULL, NULL); 2538 } 2539 2540 static void 2541 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 2542 { 2543 AcpiTableMcfg *mcfg; 2544 const char *sig; 2545 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2546 2547 mcfg = acpi_data_push(table_data, len); 2548 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2549 /* Only a single allocation so no need to play with segments */ 2550 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2551 mcfg->allocation[0].start_bus_number = 0; 2552 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2553 2554 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2555 * To avoid table size changes (which create migration issues), 2556 * always create the table even if there are no allocations, 2557 * but set the signature to a reserved value in this case. 2558 * ACPI spec requires OSPMs to ignore such tables. 2559 */ 2560 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2561 /* Reserved signature: ignored by OSPM */ 2562 sig = "QEMU"; 2563 } else { 2564 sig = "MCFG"; 2565 } 2566 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2567 } 2568 2569 static void 2570 build_dmar_q35(GArray *table_data, GArray *linker) 2571 { 2572 int dmar_start = table_data->len; 2573 2574 AcpiTableDmar *dmar; 2575 AcpiDmarHardwareUnit *drhd; 2576 2577 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2578 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2579 dmar->flags = 0; /* No intr_remap for now */ 2580 2581 /* DMAR Remapping Hardware Unit Definition structure */ 2582 drhd = acpi_data_push(table_data, sizeof(*drhd)); 2583 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2584 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 2585 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2586 drhd->pci_segment = cpu_to_le16(0); 2587 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2588 2589 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2590 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2591 } 2592 2593 static GArray * 2594 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 2595 { 2596 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2597 2598 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 2599 true /* fseg memory */); 2600 2601 memcpy(&rsdp->signature, "RSD PTR ", 8); 2602 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2603 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 2604 /* Address to be filled by Guest linker */ 2605 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 2606 ACPI_BUILD_TABLE_FILE, 2607 rsdp_table, &rsdp->rsdt_physical_address, 2608 sizeof rsdp->rsdt_physical_address); 2609 rsdp->checksum = 0; 2610 /* Checksum to be filled by Guest linker */ 2611 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2612 rsdp_table, rsdp, sizeof *rsdp, 2613 &rsdp->checksum); 2614 2615 return rsdp_table; 2616 } 2617 2618 typedef 2619 struct AcpiBuildState { 2620 /* Copy of table in RAM (for patching). */ 2621 MemoryRegion *table_mr; 2622 /* Is table patched? */ 2623 uint8_t patched; 2624 void *rsdp; 2625 MemoryRegion *rsdp_mr; 2626 MemoryRegion *linker_mr; 2627 } AcpiBuildState; 2628 2629 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2630 { 2631 Object *pci_host; 2632 QObject *o; 2633 2634 pci_host = acpi_get_i386_pci_host(); 2635 g_assert(pci_host); 2636 2637 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2638 if (!o) { 2639 return false; 2640 } 2641 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 2642 qobject_decref(o); 2643 2644 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2645 assert(o); 2646 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 2647 qobject_decref(o); 2648 return true; 2649 } 2650 2651 static bool acpi_has_iommu(void) 2652 { 2653 bool ambiguous; 2654 Object *intel_iommu; 2655 2656 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 2657 &ambiguous); 2658 return intel_iommu && !ambiguous; 2659 } 2660 2661 static 2662 void acpi_build(AcpiBuildTables *tables) 2663 { 2664 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2665 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2666 GArray *table_offsets; 2667 unsigned facs, dsdt, rsdt, fadt; 2668 AcpiCpuInfo cpu; 2669 AcpiPmInfo pm; 2670 AcpiMiscInfo misc; 2671 AcpiMcfgInfo mcfg; 2672 PcPciInfo pci; 2673 uint8_t *u; 2674 size_t aml_len = 0; 2675 GArray *tables_blob = tables->table_data; 2676 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2677 2678 acpi_get_cpu_info(&cpu); 2679 acpi_get_pm_info(&pm); 2680 acpi_get_misc_info(&misc); 2681 acpi_get_pci_info(&pci); 2682 acpi_get_slic_oem(&slic_oem); 2683 2684 table_offsets = g_array_new(false, true /* clear */, 2685 sizeof(uint32_t)); 2686 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2687 2688 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 2689 64 /* Ensure FACS is aligned */, 2690 false /* high memory */); 2691 2692 /* 2693 * FACS is pointed to by FADT. 2694 * We place it first since it's the only table that has alignment 2695 * requirements. 2696 */ 2697 facs = tables_blob->len; 2698 build_facs(tables_blob, tables->linker); 2699 2700 /* DSDT is pointed to by FADT */ 2701 dsdt = tables_blob->len; 2702 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci); 2703 2704 /* Count the size of the DSDT and SSDT, we will need it for legacy 2705 * sizing of ACPI tables. 2706 */ 2707 aml_len += tables_blob->len - dsdt; 2708 2709 /* ACPI tables pointed to by RSDT */ 2710 fadt = tables_blob->len; 2711 acpi_add_table(table_offsets, tables_blob); 2712 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt, 2713 slic_oem.id, slic_oem.table_id); 2714 aml_len += tables_blob->len - fadt; 2715 2716 acpi_add_table(table_offsets, tables_blob); 2717 build_madt(tables_blob, tables->linker, &cpu); 2718 2719 if (misc.has_hpet) { 2720 acpi_add_table(table_offsets, tables_blob); 2721 build_hpet(tables_blob, tables->linker); 2722 } 2723 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2724 acpi_add_table(table_offsets, tables_blob); 2725 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2726 2727 if (misc.tpm_version == TPM_VERSION_2_0) { 2728 acpi_add_table(table_offsets, tables_blob); 2729 build_tpm2(tables_blob, tables->linker); 2730 } 2731 } 2732 if (pcms->numa_nodes) { 2733 acpi_add_table(table_offsets, tables_blob); 2734 build_srat(tables_blob, tables->linker); 2735 } 2736 if (acpi_get_mcfg(&mcfg)) { 2737 acpi_add_table(table_offsets, tables_blob); 2738 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2739 } 2740 if (acpi_has_iommu()) { 2741 acpi_add_table(table_offsets, tables_blob); 2742 build_dmar_q35(tables_blob, tables->linker); 2743 } 2744 2745 if (pcms->acpi_nvdimm_state.is_enabled) { 2746 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); 2747 } 2748 2749 /* Add tables supplied by user (if any) */ 2750 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2751 unsigned len = acpi_table_len(u); 2752 2753 acpi_add_table(table_offsets, tables_blob); 2754 g_array_append_vals(tables_blob, u, len); 2755 } 2756 2757 /* RSDT is pointed to by RSDP */ 2758 rsdt = tables_blob->len; 2759 build_rsdt(tables_blob, tables->linker, table_offsets, 2760 slic_oem.id, slic_oem.table_id); 2761 2762 /* RSDP is in FSEG memory, so allocate it separately */ 2763 build_rsdp(tables->rsdp, tables->linker, rsdt); 2764 2765 /* We'll expose it all to Guest so we want to reduce 2766 * chance of size changes. 2767 * 2768 * We used to align the tables to 4k, but of course this would 2769 * too simple to be enough. 4k turned out to be too small an 2770 * alignment very soon, and in fact it is almost impossible to 2771 * keep the table size stable for all (max_cpus, max_memory_slots) 2772 * combinations. So the table size is always 64k for pc-i440fx-2.1 2773 * and we give an error if the table grows beyond that limit. 2774 * 2775 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2776 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2777 * than 2.0 and we can always pad the smaller tables with zeros. We can 2778 * then use the exact size of the 2.0 tables. 2779 * 2780 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2781 */ 2782 if (pcmc->legacy_acpi_table_size) { 2783 /* Subtracting aml_len gives the size of fixed tables. Then add the 2784 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2785 */ 2786 int legacy_aml_len = 2787 pcmc->legacy_acpi_table_size + 2788 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 2789 int legacy_table_size = 2790 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2791 ACPI_BUILD_ALIGN_SIZE); 2792 if (tables_blob->len > legacy_table_size) { 2793 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2794 error_report("Warning: migration may not work."); 2795 } 2796 g_array_set_size(tables_blob, legacy_table_size); 2797 } else { 2798 /* Make sure we have a buffer in case we need to resize the tables. */ 2799 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2800 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2801 error_report("Warning: ACPI tables are larger than 64k."); 2802 error_report("Warning: migration may not work."); 2803 error_report("Warning: please remove CPUs, NUMA nodes, " 2804 "memory slots or PCI bridges."); 2805 } 2806 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2807 } 2808 2809 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 2810 2811 /* Cleanup memory that's no longer used. */ 2812 g_array_free(table_offsets, true); 2813 } 2814 2815 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2816 { 2817 uint32_t size = acpi_data_len(data); 2818 2819 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2820 memory_region_ram_resize(mr, size, &error_abort); 2821 2822 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2823 memory_region_set_dirty(mr, 0, size); 2824 } 2825 2826 static void acpi_build_update(void *build_opaque) 2827 { 2828 AcpiBuildState *build_state = build_opaque; 2829 AcpiBuildTables tables; 2830 2831 /* No state to update or already patched? Nothing to do. */ 2832 if (!build_state || build_state->patched) { 2833 return; 2834 } 2835 build_state->patched = 1; 2836 2837 acpi_build_tables_init(&tables); 2838 2839 acpi_build(&tables); 2840 2841 acpi_ram_update(build_state->table_mr, tables.table_data); 2842 2843 if (build_state->rsdp) { 2844 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2845 } else { 2846 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2847 } 2848 2849 acpi_ram_update(build_state->linker_mr, tables.linker); 2850 acpi_build_tables_cleanup(&tables, true); 2851 } 2852 2853 static void acpi_build_reset(void *build_opaque) 2854 { 2855 AcpiBuildState *build_state = build_opaque; 2856 build_state->patched = 0; 2857 } 2858 2859 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2860 GArray *blob, const char *name, 2861 uint64_t max_size) 2862 { 2863 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2864 name, acpi_build_update, build_state); 2865 } 2866 2867 static const VMStateDescription vmstate_acpi_build = { 2868 .name = "acpi_build", 2869 .version_id = 1, 2870 .minimum_version_id = 1, 2871 .fields = (VMStateField[]) { 2872 VMSTATE_UINT8(patched, AcpiBuildState), 2873 VMSTATE_END_OF_LIST() 2874 }, 2875 }; 2876 2877 void acpi_setup(void) 2878 { 2879 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2880 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2881 AcpiBuildTables tables; 2882 AcpiBuildState *build_state; 2883 2884 if (!pcms->fw_cfg) { 2885 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2886 return; 2887 } 2888 2889 if (!pcmc->has_acpi_build) { 2890 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2891 return; 2892 } 2893 2894 if (!acpi_enabled) { 2895 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2896 return; 2897 } 2898 2899 build_state = g_malloc0(sizeof *build_state); 2900 2901 acpi_set_pci_info(); 2902 2903 acpi_build_tables_init(&tables); 2904 acpi_build(&tables); 2905 2906 /* Now expose it all to Guest */ 2907 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2908 ACPI_BUILD_TABLE_FILE, 2909 ACPI_BUILD_TABLE_MAX_SIZE); 2910 assert(build_state->table_mr != NULL); 2911 2912 build_state->linker_mr = 2913 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 2914 2915 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2916 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2917 2918 if (!pcmc->rsdp_in_ram) { 2919 /* 2920 * Keep for compatibility with old machine types. 2921 * Though RSDP is small, its contents isn't immutable, so 2922 * we'll update it along with the rest of tables on guest access. 2923 */ 2924 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2925 2926 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2927 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2928 acpi_build_update, build_state, 2929 build_state->rsdp, rsdp_size); 2930 build_state->rsdp_mr = NULL; 2931 } else { 2932 build_state->rsdp = NULL; 2933 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2934 ACPI_BUILD_RSDP_FILE, 0); 2935 } 2936 2937 qemu_register_reset(acpi_build_reset, build_state); 2938 acpi_build_reset(build_state); 2939 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2940 2941 /* Cleanup tables but don't free the memory: we track it 2942 * in build_state. 2943 */ 2944 acpi_build_tables_cleanup(&tables, false); 2945 } 2946