xref: /qemu/hw/i386/kvm/apic.c (revision 2c7c4cf0) 
1 /*
2  * KVM in-kernel APIC support
3  *
4  * Copyright (c) 2011 Siemens AG
5  *
6  * Authors:
7  *  Jan Kiszka          <jan.kiszka@siemens.com>
8  *
9  * This work is licensed under the terms of the GNU GPL version 2.
10  * See the COPYING file in the top-level directory.
11  */
12 #include "qemu/osdep.h"
13 #include "qemu-common.h"
14 #include "cpu.h"
15 #include "hw/i386/apic_internal.h"
16 #include "hw/pci/msi.h"
17 #include "sysemu/kvm.h"
18 #include "target-i386/kvm_i386.h"
19 
20 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
21                                     int reg_id, uint32_t val)
22 {
23     *((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
24 }
25 
26 static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
27                                         int reg_id)
28 {
29     return *((uint32_t *)(kapic->regs + (reg_id << 4)));
30 }
31 
32 static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic)
33 {
34     int i;
35 
36     memset(kapic, 0, sizeof(*kapic));
37     kvm_apic_set_reg(kapic, 0x2, s->id << 24);
38     kvm_apic_set_reg(kapic, 0x8, s->tpr);
39     kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
40     kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
41     kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
42     for (i = 0; i < 8; i++) {
43         kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
44         kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
45         kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
46     }
47     kvm_apic_set_reg(kapic, 0x28, s->esr);
48     kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
49     kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
50     for (i = 0; i < APIC_LVT_NB; i++) {
51         kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
52     }
53     kvm_apic_set_reg(kapic, 0x38, s->initial_count);
54     kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
55 }
56 
57 void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
58 {
59     APICCommonState *s = APIC_COMMON(dev);
60     int i, v;
61 
62     s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
63     s->tpr = kvm_apic_get_reg(kapic, 0x8);
64     s->arb_id = kvm_apic_get_reg(kapic, 0x9);
65     s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
66     s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
67     s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
68     for (i = 0; i < 8; i++) {
69         s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
70         s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
71         s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
72     }
73     s->esr = kvm_apic_get_reg(kapic, 0x28);
74     s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
75     s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
76     for (i = 0; i < APIC_LVT_NB; i++) {
77         s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
78     }
79     s->initial_count = kvm_apic_get_reg(kapic, 0x38);
80     s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
81 
82     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
83     s->count_shift = (v + 1) & 7;
84 
85     s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
86     apic_next_timer(s, s->initial_count_load_time);
87 }
88 
89 static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
90 {
91     s->apicbase = val;
92 }
93 
94 static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
95 {
96     s->tpr = (val & 0x0f) << 4;
97 }
98 
99 static uint8_t kvm_apic_get_tpr(APICCommonState *s)
100 {
101     return s->tpr >> 4;
102 }
103 
104 static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
105 {
106     struct kvm_tpr_access_ctl ctl = {
107         .enabled = enable
108     };
109 
110     kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl);
111 }
112 
113 static void kvm_apic_vapic_base_update(APICCommonState *s)
114 {
115     struct kvm_vapic_addr vapid_addr = {
116         .vapic_addr = s->vapic_paddr,
117     };
118     int ret;
119 
120     ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr);
121     if (ret < 0) {
122         fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
123                 strerror(-ret));
124         abort();
125     }
126 }
127 
128 static void kvm_apic_put(void *data)
129 {
130     APICCommonState *s = data;
131     struct kvm_lapic_state kapic;
132     int ret;
133 
134     kvm_put_apicbase(s->cpu, s->apicbase);
135     kvm_put_apic_state(s, &kapic);
136 
137     ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic);
138     if (ret < 0) {
139         fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret));
140         abort();
141     }
142 }
143 
144 static void kvm_apic_post_load(APICCommonState *s)
145 {
146     run_on_cpu(CPU(s->cpu), kvm_apic_put, s);
147 }
148 
149 static void do_inject_external_nmi(void *data)
150 {
151     APICCommonState *s = data;
152     CPUState *cpu = CPU(s->cpu);
153     uint32_t lvt;
154     int ret;
155 
156     cpu_synchronize_state(cpu);
157 
158     lvt = s->lvt[APIC_LVT_LINT1];
159     if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
160         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
161         if (ret < 0) {
162             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
163                     strerror(-ret));
164         }
165     }
166 }
167 
168 static void kvm_apic_external_nmi(APICCommonState *s)
169 {
170     run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s);
171 }
172 
173 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
174                                   unsigned size)
175 {
176     return ~(uint64_t)0;
177 }
178 
179 static void kvm_apic_mem_write(void *opaque, hwaddr addr,
180                                uint64_t data, unsigned size)
181 {
182     MSIMessage msg = { .address = addr, .data = data };
183     int ret;
184 
185     ret = kvm_irqchip_send_msi(kvm_state, msg);
186     if (ret < 0) {
187         fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",
188                 strerror(-ret));
189     }
190 }
191 
192 static const MemoryRegionOps kvm_apic_io_ops = {
193     .read = kvm_apic_mem_read,
194     .write = kvm_apic_mem_write,
195     .endianness = DEVICE_NATIVE_ENDIAN,
196 };
197 
198 static void kvm_apic_reset(APICCommonState *s)
199 {
200     /* Not used by KVM, which uses the CPU mp_state instead.  */
201     s->wait_for_sipi = 0;
202 
203     run_on_cpu(CPU(s->cpu), kvm_apic_put, s);
204 }
205 
206 static void kvm_apic_realize(DeviceState *dev, Error **errp)
207 {
208     APICCommonState *s = APIC_COMMON(dev);
209 
210     memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
211                           "kvm-apic-msi", APIC_SPACE_SIZE);
212 
213     if (kvm_has_gsi_routing()) {
214         msi_nonbroken = true;
215     }
216 }
217 
218 static void kvm_apic_unrealize(DeviceState *dev, Error **errp)
219 {
220 }
221 
222 static void kvm_apic_class_init(ObjectClass *klass, void *data)
223 {
224     APICCommonClass *k = APIC_COMMON_CLASS(klass);
225 
226     k->realize = kvm_apic_realize;
227     k->unrealize = kvm_apic_unrealize;
228     k->reset = kvm_apic_reset;
229     k->set_base = kvm_apic_set_base;
230     k->set_tpr = kvm_apic_set_tpr;
231     k->get_tpr = kvm_apic_get_tpr;
232     k->post_load = kvm_apic_post_load;
233     k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting;
234     k->vapic_base_update = kvm_apic_vapic_base_update;
235     k->external_nmi = kvm_apic_external_nmi;
236 }
237 
238 static const TypeInfo kvm_apic_info = {
239     .name = "kvm-apic",
240     .parent = TYPE_APIC_COMMON,
241     .instance_size = sizeof(APICCommonState),
242     .class_init = kvm_apic_class_init,
243 };
244 
245 static void kvm_apic_register_types(void)
246 {
247     type_register_static(&kvm_apic_info);
248 }
249 
250 type_init(kvm_apic_register_types)
251