1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_9_0[] = { 82 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 83 }; 84 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 85 86 GlobalProperty pc_compat_8_2[] = {}; 87 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 88 89 GlobalProperty pc_compat_8_1[] = {}; 90 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 91 92 GlobalProperty pc_compat_8_0[] = { 93 { "virtio-mem", "unplugged-inaccessible", "auto" }, 94 }; 95 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 96 97 GlobalProperty pc_compat_7_2[] = { 98 { "ICH9-LPC", "noreboot", "true" }, 99 }; 100 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 101 102 GlobalProperty pc_compat_7_1[] = {}; 103 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 104 105 GlobalProperty pc_compat_7_0[] = {}; 106 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 107 108 GlobalProperty pc_compat_6_2[] = { 109 { "virtio-mem", "unplugged-inaccessible", "off" }, 110 }; 111 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 112 113 GlobalProperty pc_compat_6_1[] = { 114 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 115 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 116 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 117 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 118 }; 119 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 120 121 GlobalProperty pc_compat_6_0[] = { 122 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 123 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 124 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 125 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 126 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 127 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 128 }; 129 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 130 131 GlobalProperty pc_compat_5_2[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 133 }; 134 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 135 136 GlobalProperty pc_compat_5_1[] = { 137 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 138 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 139 }; 140 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 141 142 GlobalProperty pc_compat_5_0[] = { 143 }; 144 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 145 146 GlobalProperty pc_compat_4_2[] = { 147 { "mch", "smbase-smram", "off" }, 148 }; 149 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 150 151 GlobalProperty pc_compat_4_1[] = {}; 152 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 153 154 GlobalProperty pc_compat_4_0[] = {}; 155 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 156 157 GlobalProperty pc_compat_3_1[] = { 158 { "intel-iommu", "dma-drain", "off" }, 159 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 160 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 161 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 164 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 165 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 166 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 167 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 168 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 169 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 170 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 173 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 174 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 175 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 178 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 179 }; 180 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 181 182 GlobalProperty pc_compat_3_0[] = { 183 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 184 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 185 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 186 }; 187 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 188 189 GlobalProperty pc_compat_2_12[] = { 190 { TYPE_X86_CPU, "legacy-cache", "on" }, 191 { TYPE_X86_CPU, "topoext", "off" }, 192 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 193 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 194 }; 195 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 196 197 GlobalProperty pc_compat_2_11[] = { 198 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 199 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 200 }; 201 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 202 203 GlobalProperty pc_compat_2_10[] = { 204 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 205 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 206 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 207 }; 208 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 209 210 GlobalProperty pc_compat_2_9[] = { 211 { "mch", "extended-tseg-mbytes", "0" }, 212 }; 213 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 214 215 GlobalProperty pc_compat_2_8[] = { 216 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 217 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 218 { "ICH9-LPC", "x-smi-broadcast", "off" }, 219 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 220 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 221 }; 222 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 223 224 GlobalProperty pc_compat_2_7[] = { 225 { TYPE_X86_CPU, "l3-cache", "off" }, 226 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 227 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 228 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 229 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 230 { "isa-pcspk", "migrate", "off" }, 231 }; 232 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 233 234 GlobalProperty pc_compat_2_6[] = { 235 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 236 { "vmxnet3", "romfile", "" }, 237 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 238 { "apic-common", "legacy-instance-id", "on", } 239 }; 240 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 241 242 GlobalProperty pc_compat_2_5[] = {}; 243 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 244 245 GlobalProperty pc_compat_2_4[] = { 246 PC_CPU_MODEL_IDS("2.4.0") 247 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 248 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 249 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 250 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 251 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 252 { TYPE_X86_CPU, "check", "off" }, 253 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 254 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 255 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 256 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 257 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 258 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 259 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 260 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 261 }; 262 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 263 264 GlobalProperty pc_compat_2_3[] = { 265 PC_CPU_MODEL_IDS("2.3.0") 266 { TYPE_X86_CPU, "arat", "off" }, 267 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 269 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 270 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 272 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 273 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 274 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 281 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 282 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 283 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 284 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 285 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 286 }; 287 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 288 289 GlobalProperty pc_compat_2_2[] = { 290 PC_CPU_MODEL_IDS("2.2.0") 291 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 302 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 303 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 306 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 307 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 308 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 309 }; 310 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 311 312 GlobalProperty pc_compat_2_1[] = { 313 PC_CPU_MODEL_IDS("2.1.0") 314 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 315 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 316 }; 317 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 318 319 GlobalProperty pc_compat_2_0[] = { 320 PC_CPU_MODEL_IDS("2.0.0") 321 { "virtio-scsi-pci", "any_layout", "off" }, 322 { "PIIX4_PM", "memory-hotplug-support", "off" }, 323 { "apic", "version", "0x11" }, 324 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 325 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 326 { "pci-serial", "prog_if", "0" }, 327 { "pci-serial-2x", "prog_if", "0" }, 328 { "pci-serial-4x", "prog_if", "0" }, 329 { "virtio-net-pci", "guest_announce", "off" }, 330 { "ICH9-LPC", "memory-hotplug-support", "off" }, 331 }; 332 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 333 334 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 335 { 336 GSIState *s; 337 338 s = g_new0(GSIState, 1); 339 if (kvm_ioapic_in_kernel()) { 340 kvm_pc_setup_irq_routing(pci_enabled); 341 } 342 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 343 344 return s; 345 } 346 347 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 348 unsigned size) 349 { 350 } 351 352 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 353 { 354 return 0xffffffffffffffffULL; 355 } 356 357 /* MS-DOS compatibility mode FPU exception support */ 358 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 359 unsigned size) 360 { 361 if (tcg_enabled()) { 362 cpu_set_ignne(); 363 } 364 } 365 366 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 367 { 368 return 0xffffffffffffffffULL; 369 } 370 371 /* PC cmos mappings */ 372 373 #define REG_EQUIPMENT_BYTE 0x14 374 375 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 376 int16_t cylinders, int8_t heads, int8_t sectors) 377 { 378 mc146818rtc_set_cmos_data(s, type_ofs, 47); 379 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 380 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 381 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 382 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 383 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 384 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 385 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 386 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 387 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 388 } 389 390 /* convert boot_device letter to something recognizable by the bios */ 391 static int boot_device2nibble(char boot_device) 392 { 393 switch(boot_device) { 394 case 'a': 395 case 'b': 396 return 0x01; /* floppy boot */ 397 case 'c': 398 return 0x02; /* hard drive boot */ 399 case 'd': 400 return 0x03; /* CD-ROM boot */ 401 case 'n': 402 return 0x04; /* Network boot */ 403 } 404 return 0; 405 } 406 407 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 408 const char *boot_device, Error **errp) 409 { 410 #define PC_MAX_BOOT_DEVICES 3 411 int nbds, bds[3] = { 0, }; 412 int i; 413 414 nbds = strlen(boot_device); 415 if (nbds > PC_MAX_BOOT_DEVICES) { 416 error_setg(errp, "Too many boot devices for PC"); 417 return; 418 } 419 for (i = 0; i < nbds; i++) { 420 bds[i] = boot_device2nibble(boot_device[i]); 421 if (bds[i] == 0) { 422 error_setg(errp, "Invalid boot device for PC: '%c'", 423 boot_device[i]); 424 return; 425 } 426 } 427 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 428 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 429 } 430 431 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 432 { 433 PCMachineState *pcms = opaque; 434 X86MachineState *x86ms = X86_MACHINE(pcms); 435 436 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 437 } 438 439 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 440 { 441 int val, nb, i; 442 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 443 FLOPPY_DRIVE_TYPE_NONE }; 444 445 /* floppy type */ 446 if (floppy) { 447 for (i = 0; i < 2; i++) { 448 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 449 } 450 } 451 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 452 cmos_get_fd_drive_type(fd_type[1]); 453 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 454 455 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 456 nb = 0; 457 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 458 nb++; 459 } 460 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 461 nb++; 462 } 463 switch (nb) { 464 case 0: 465 break; 466 case 1: 467 val |= 0x01; /* 1 drive, ready for boot */ 468 break; 469 case 2: 470 val |= 0x41; /* 2 drives, ready for boot */ 471 break; 472 } 473 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 474 } 475 476 typedef struct check_fdc_state { 477 ISADevice *floppy; 478 bool multiple; 479 } CheckFdcState; 480 481 static int check_fdc(Object *obj, void *opaque) 482 { 483 CheckFdcState *state = opaque; 484 Object *fdc; 485 uint32_t iobase; 486 Error *local_err = NULL; 487 488 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 489 if (!fdc) { 490 return 0; 491 } 492 493 iobase = object_property_get_uint(obj, "iobase", &local_err); 494 if (local_err || iobase != 0x3f0) { 495 error_free(local_err); 496 return 0; 497 } 498 499 if (state->floppy) { 500 state->multiple = true; 501 } else { 502 state->floppy = ISA_DEVICE(obj); 503 } 504 return 0; 505 } 506 507 static const char * const fdc_container_path[] = { 508 "/unattached", "/peripheral", "/peripheral-anon" 509 }; 510 511 /* 512 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 513 * and ACPI objects. 514 */ 515 static ISADevice *pc_find_fdc0(void) 516 { 517 int i; 518 Object *container; 519 CheckFdcState state = { 0 }; 520 521 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 522 container = container_get(qdev_get_machine(), fdc_container_path[i]); 523 object_child_foreach(container, check_fdc, &state); 524 } 525 526 if (state.multiple) { 527 warn_report("multiple floppy disk controllers with " 528 "iobase=0x3f0 have been found"); 529 error_printf("the one being picked for CMOS setup might not reflect " 530 "your intent"); 531 } 532 533 return state.floppy; 534 } 535 536 static void pc_cmos_init_late(PCMachineState *pcms) 537 { 538 X86MachineState *x86ms = X86_MACHINE(pcms); 539 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 540 int16_t cylinders; 541 int8_t heads, sectors; 542 int val; 543 int i, trans; 544 545 val = 0; 546 if (pcms->idebus[0] && 547 ide_get_geometry(pcms->idebus[0], 0, 548 &cylinders, &heads, §ors) >= 0) { 549 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 550 val |= 0xf0; 551 } 552 if (pcms->idebus[0] && 553 ide_get_geometry(pcms->idebus[0], 1, 554 &cylinders, &heads, §ors) >= 0) { 555 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 556 val |= 0x0f; 557 } 558 mc146818rtc_set_cmos_data(s, 0x12, val); 559 560 val = 0; 561 for (i = 0; i < 4; i++) { 562 /* NOTE: ide_get_geometry() returns the physical 563 geometry. It is always such that: 1 <= sects <= 63, 1 564 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 565 geometry can be different if a translation is done. */ 566 BusState *idebus = pcms->idebus[i / 2]; 567 if (idebus && 568 ide_get_geometry(idebus, i % 2, 569 &cylinders, &heads, §ors) >= 0) { 570 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 571 assert((trans & ~3) == 0); 572 val |= trans << (i * 2); 573 } 574 } 575 mc146818rtc_set_cmos_data(s, 0x39, val); 576 577 pc_cmos_init_floppy(s, pc_find_fdc0()); 578 579 /* various important CMOS locations needed by PC/Bochs bios */ 580 581 /* memory size */ 582 /* base memory (first MiB) */ 583 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 584 mc146818rtc_set_cmos_data(s, 0x15, val); 585 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 586 /* extended memory (next 64MiB) */ 587 if (x86ms->below_4g_mem_size > 1 * MiB) { 588 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 589 } else { 590 val = 0; 591 } 592 if (val > 65535) 593 val = 65535; 594 mc146818rtc_set_cmos_data(s, 0x17, val); 595 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 596 mc146818rtc_set_cmos_data(s, 0x30, val); 597 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 598 /* memory between 16MiB and 4GiB */ 599 if (x86ms->below_4g_mem_size > 16 * MiB) { 600 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 601 } else { 602 val = 0; 603 } 604 if (val > 65535) 605 val = 65535; 606 mc146818rtc_set_cmos_data(s, 0x34, val); 607 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 608 /* memory above 4GiB */ 609 val = x86ms->above_4g_mem_size / 65536; 610 mc146818rtc_set_cmos_data(s, 0x5b, val); 611 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 612 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 613 614 val = 0; 615 val |= 0x02; /* FPU is there */ 616 val |= 0x04; /* PS/2 mouse installed */ 617 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 618 } 619 620 static void handle_a20_line_change(void *opaque, int irq, int level) 621 { 622 X86CPU *cpu = opaque; 623 624 /* XXX: send to all CPUs ? */ 625 /* XXX: add logic to handle multiple A20 line sources */ 626 x86_cpu_set_a20(cpu, level); 627 } 628 629 #define NE2000_NB_MAX 6 630 631 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 632 0x280, 0x380 }; 633 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 634 635 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 636 { 637 static int nb_ne2k = 0; 638 639 if (nb_ne2k == NE2000_NB_MAX) { 640 error_setg(errp, 641 "maximum number of ISA NE2000 devices exceeded"); 642 return false; 643 } 644 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 645 ne2000_irq[nb_ne2k], nd); 646 nb_ne2k++; 647 return true; 648 } 649 650 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 651 { 652 X86CPU *cpu = opaque; 653 654 if (level) { 655 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 656 } 657 } 658 659 static 660 void pc_machine_done(Notifier *notifier, void *data) 661 { 662 PCMachineState *pcms = container_of(notifier, 663 PCMachineState, machine_done); 664 X86MachineState *x86ms = X86_MACHINE(pcms); 665 666 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 667 &error_fatal); 668 669 if (pcms->cxl_devices_state.is_enabled) { 670 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 671 } 672 673 /* set the number of CPUs */ 674 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 675 676 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 677 678 acpi_setup(); 679 if (x86ms->fw_cfg) { 680 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 681 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 682 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 683 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 684 } 685 686 pc_cmos_init_late(pcms); 687 } 688 689 /* setup pci memory address space mapping into system address space */ 690 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 691 MemoryRegion *pci_address_space) 692 { 693 /* Set to lower priority than RAM */ 694 memory_region_add_subregion_overlap(system_memory, 0x0, 695 pci_address_space, -1); 696 } 697 698 void xen_load_linux(PCMachineState *pcms) 699 { 700 int i; 701 FWCfgState *fw_cfg; 702 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 703 X86MachineState *x86ms = X86_MACHINE(pcms); 704 705 assert(MACHINE(pcms)->kernel_filename != NULL); 706 707 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 708 &address_space_memory); 709 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 710 rom_set_fw(fw_cfg); 711 712 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 713 pcmc->pvh_enabled); 714 for (i = 0; i < nb_option_roms; i++) { 715 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 716 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 717 !strcmp(option_rom[i].name, "pvh.bin") || 718 !strcmp(option_rom[i].name, "multiboot.bin") || 719 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 720 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 721 } 722 x86ms->fw_cfg = fw_cfg; 723 } 724 725 #define PC_ROM_MIN_VGA 0xc0000 726 #define PC_ROM_MIN_OPTION 0xc8000 727 #define PC_ROM_MAX 0xe0000 728 #define PC_ROM_ALIGN 0x800 729 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 730 731 static hwaddr pc_above_4g_end(PCMachineState *pcms) 732 { 733 X86MachineState *x86ms = X86_MACHINE(pcms); 734 735 if (pcms->sgx_epc.size != 0) { 736 return sgx_epc_above_4g_end(&pcms->sgx_epc); 737 } 738 739 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 740 } 741 742 static void pc_get_device_memory_range(PCMachineState *pcms, 743 hwaddr *base, 744 ram_addr_t *device_mem_size) 745 { 746 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 747 MachineState *machine = MACHINE(pcms); 748 ram_addr_t size; 749 hwaddr addr; 750 751 size = machine->maxram_size - machine->ram_size; 752 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 753 754 if (pcmc->enforce_aligned_dimm) { 755 /* size device region assuming 1G page max alignment per slot */ 756 size += (1 * GiB) * machine->ram_slots; 757 } 758 759 *base = addr; 760 *device_mem_size = size; 761 } 762 763 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 764 { 765 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 766 MachineState *ms = MACHINE(pcms); 767 hwaddr cxl_base; 768 ram_addr_t size; 769 770 if (pcmc->has_reserved_memory && 771 (ms->ram_size < ms->maxram_size)) { 772 pc_get_device_memory_range(pcms, &cxl_base, &size); 773 cxl_base += size; 774 } else { 775 cxl_base = pc_above_4g_end(pcms); 776 } 777 778 return cxl_base; 779 } 780 781 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 782 { 783 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 784 785 if (pcms->cxl_devices_state.fixed_windows) { 786 GList *it; 787 788 start = ROUND_UP(start, 256 * MiB); 789 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 790 CXLFixedWindow *fw = it->data; 791 start += fw->size; 792 } 793 } 794 795 return start; 796 } 797 798 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 799 { 800 X86CPU *cpu = X86_CPU(first_cpu); 801 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 802 MachineState *ms = MACHINE(pcms); 803 804 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 805 /* 64-bit systems */ 806 return pc_pci_hole64_start() + pci_hole64_size - 1; 807 } 808 809 /* 32-bit systems */ 810 if (pcmc->broken_32bit_mem_addr_check) { 811 /* old value for compatibility reasons */ 812 return ((hwaddr)1 << cpu->phys_bits) - 1; 813 } 814 815 /* 816 * 32-bit systems don't have hole64 but they might have a region for 817 * memory devices. Even if additional hotplugged memory devices might 818 * not be usable by most guest OSes, we need to still consider them for 819 * calculating the highest possible GPA so that we can properly report 820 * if someone configures them on a CPU that cannot possibly address them. 821 */ 822 if (pcmc->has_reserved_memory && 823 (ms->ram_size < ms->maxram_size)) { 824 hwaddr devmem_start; 825 ram_addr_t devmem_size; 826 827 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 828 devmem_start += devmem_size; 829 return devmem_start - 1; 830 } 831 832 /* configuration without any memory hotplug */ 833 return pc_above_4g_end(pcms) - 1; 834 } 835 836 /* 837 * AMD systems with an IOMMU have an additional hole close to the 838 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 839 * on kernel version, VFIO may or may not let you DMA map those ranges. 840 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 841 * with certain memory sizes. It's also wrong to use those IOVA ranges 842 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 843 * The ranges reserved for Hyper-Transport are: 844 * 845 * FD_0000_0000h - FF_FFFF_FFFFh 846 * 847 * The ranges represent the following: 848 * 849 * Base Address Top Address Use 850 * 851 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 852 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 853 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 854 * FD_F910_0000h FD_F91F_FFFFh System Management 855 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 856 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 857 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 858 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 859 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 860 * FE_2000_0000h FF_FFFF_FFFFh Reserved 861 * 862 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 863 * Table 3: Special Address Controls (GPA) for more information. 864 */ 865 #define AMD_HT_START 0xfd00000000UL 866 #define AMD_HT_END 0xffffffffffUL 867 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 868 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 869 870 void pc_memory_init(PCMachineState *pcms, 871 MemoryRegion *system_memory, 872 MemoryRegion *rom_memory, 873 uint64_t pci_hole64_size) 874 { 875 int linux_boot, i; 876 MemoryRegion *option_rom_mr; 877 MemoryRegion *ram_below_4g, *ram_above_4g; 878 FWCfgState *fw_cfg; 879 MachineState *machine = MACHINE(pcms); 880 MachineClass *mc = MACHINE_GET_CLASS(machine); 881 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 882 X86MachineState *x86ms = X86_MACHINE(pcms); 883 hwaddr maxphysaddr, maxusedaddr; 884 hwaddr cxl_base, cxl_resv_end = 0; 885 X86CPU *cpu = X86_CPU(first_cpu); 886 887 assert(machine->ram_size == x86ms->below_4g_mem_size + 888 x86ms->above_4g_mem_size); 889 890 linux_boot = (machine->kernel_filename != NULL); 891 892 /* 893 * The HyperTransport range close to the 1T boundary is unique to AMD 894 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 895 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 896 * older machine types (<= 7.0) for compatibility purposes. 897 */ 898 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 899 /* Bail out if max possible address does not cross HT range */ 900 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 901 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 902 } 903 904 /* 905 * Advertise the HT region if address space covers the reserved 906 * region or if we relocate. 907 */ 908 if (cpu->phys_bits >= 40) { 909 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 910 } 911 } 912 913 /* 914 * phys-bits is required to be appropriately configured 915 * to make sure max used GPA is reachable. 916 */ 917 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 918 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 919 if (maxphysaddr < maxusedaddr) { 920 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 921 " phys-bits too low (%u)", 922 maxphysaddr, maxusedaddr, cpu->phys_bits); 923 exit(EXIT_FAILURE); 924 } 925 926 /* 927 * Split single memory region and use aliases to address portions of it, 928 * done for backwards compatibility with older qemus. 929 */ 930 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 931 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 932 0, x86ms->below_4g_mem_size); 933 memory_region_add_subregion(system_memory, 0, ram_below_4g); 934 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 935 if (x86ms->above_4g_mem_size > 0) { 936 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 937 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 938 machine->ram, 939 x86ms->below_4g_mem_size, 940 x86ms->above_4g_mem_size); 941 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 942 ram_above_4g); 943 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 944 E820_RAM); 945 } 946 947 if (pcms->sgx_epc.size != 0) { 948 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 949 } 950 951 if (!pcmc->has_reserved_memory && 952 (machine->ram_slots || 953 (machine->maxram_size > machine->ram_size))) { 954 955 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 956 mc->name); 957 exit(EXIT_FAILURE); 958 } 959 960 /* initialize device memory address space */ 961 if (pcmc->has_reserved_memory && 962 (machine->ram_size < machine->maxram_size)) { 963 ram_addr_t device_mem_size; 964 hwaddr device_mem_base; 965 966 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 967 error_report("unsupported amount of memory slots: %"PRIu64, 968 machine->ram_slots); 969 exit(EXIT_FAILURE); 970 } 971 972 if (QEMU_ALIGN_UP(machine->maxram_size, 973 TARGET_PAGE_SIZE) != machine->maxram_size) { 974 error_report("maximum memory size must by aligned to multiple of " 975 "%d bytes", TARGET_PAGE_SIZE); 976 exit(EXIT_FAILURE); 977 } 978 979 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 980 981 if (device_mem_base + device_mem_size < device_mem_size) { 982 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 983 machine->maxram_size); 984 exit(EXIT_FAILURE); 985 } 986 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 987 } 988 989 if (pcms->cxl_devices_state.is_enabled) { 990 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 991 hwaddr cxl_size = MiB; 992 993 cxl_base = pc_get_cxl_range_start(pcms); 994 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 995 memory_region_add_subregion(system_memory, cxl_base, mr); 996 cxl_resv_end = cxl_base + cxl_size; 997 if (pcms->cxl_devices_state.fixed_windows) { 998 hwaddr cxl_fmw_base; 999 GList *it; 1000 1001 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1002 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1003 CXLFixedWindow *fw = it->data; 1004 1005 fw->base = cxl_fmw_base; 1006 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1007 "cxl-fixed-memory-region", fw->size); 1008 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1009 cxl_fmw_base += fw->size; 1010 cxl_resv_end = cxl_fmw_base; 1011 } 1012 } 1013 } 1014 1015 /* Initialize PC system firmware */ 1016 pc_system_firmware_init(pcms, rom_memory); 1017 1018 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1019 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1020 &error_fatal); 1021 if (pcmc->pci_enabled) { 1022 memory_region_set_readonly(option_rom_mr, true); 1023 } 1024 memory_region_add_subregion_overlap(rom_memory, 1025 PC_ROM_MIN_VGA, 1026 option_rom_mr, 1027 1); 1028 1029 fw_cfg = fw_cfg_arch_create(machine, 1030 x86ms->boot_cpus, x86ms->apic_id_limit); 1031 1032 rom_set_fw(fw_cfg); 1033 1034 if (machine->device_memory) { 1035 uint64_t *val = g_malloc(sizeof(*val)); 1036 uint64_t res_mem_end = machine->device_memory->base; 1037 1038 if (!pcmc->broken_reserved_end) { 1039 res_mem_end += memory_region_size(&machine->device_memory->mr); 1040 } 1041 1042 if (pcms->cxl_devices_state.is_enabled) { 1043 res_mem_end = cxl_resv_end; 1044 } 1045 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1046 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1047 } 1048 1049 if (linux_boot) { 1050 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1051 pcmc->pvh_enabled); 1052 } 1053 1054 for (i = 0; i < nb_option_roms; i++) { 1055 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1056 } 1057 x86ms->fw_cfg = fw_cfg; 1058 1059 /* Init default IOAPIC address space */ 1060 x86ms->ioapic_as = &address_space_memory; 1061 1062 /* Init ACPI memory hotplug IO base address */ 1063 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1064 } 1065 1066 /* 1067 * The 64bit pci hole starts after "above 4G RAM" and 1068 * potentially the space reserved for memory hotplug. 1069 */ 1070 uint64_t pc_pci_hole64_start(void) 1071 { 1072 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1073 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1074 MachineState *ms = MACHINE(pcms); 1075 uint64_t hole64_start = 0; 1076 ram_addr_t size = 0; 1077 1078 if (pcms->cxl_devices_state.is_enabled) { 1079 hole64_start = pc_get_cxl_range_end(pcms); 1080 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1081 pc_get_device_memory_range(pcms, &hole64_start, &size); 1082 if (!pcmc->broken_reserved_end) { 1083 hole64_start += size; 1084 } 1085 } else { 1086 hole64_start = pc_above_4g_end(pcms); 1087 } 1088 1089 return ROUND_UP(hole64_start, 1 * GiB); 1090 } 1091 1092 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1093 { 1094 DeviceState *dev = NULL; 1095 1096 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1097 if (pci_bus) { 1098 PCIDevice *pcidev = pci_vga_init(pci_bus); 1099 dev = pcidev ? &pcidev->qdev : NULL; 1100 } else if (isa_bus) { 1101 ISADevice *isadev = isa_vga_init(isa_bus); 1102 dev = isadev ? DEVICE(isadev) : NULL; 1103 } 1104 rom_reset_order_override(); 1105 return dev; 1106 } 1107 1108 static const MemoryRegionOps ioport80_io_ops = { 1109 .write = ioport80_write, 1110 .read = ioport80_read, 1111 .endianness = DEVICE_NATIVE_ENDIAN, 1112 .impl = { 1113 .min_access_size = 1, 1114 .max_access_size = 1, 1115 }, 1116 }; 1117 1118 static const MemoryRegionOps ioportF0_io_ops = { 1119 .write = ioportF0_write, 1120 .read = ioportF0_read, 1121 .endianness = DEVICE_NATIVE_ENDIAN, 1122 .impl = { 1123 .min_access_size = 1, 1124 .max_access_size = 1, 1125 }, 1126 }; 1127 1128 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1129 bool create_i8042, bool no_vmport) 1130 { 1131 int i; 1132 DriveInfo *fd[MAX_FD]; 1133 qemu_irq *a20_line; 1134 ISADevice *fdc, *i8042, *port92, *vmmouse; 1135 1136 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1137 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1138 1139 for (i = 0; i < MAX_FD; i++) { 1140 fd[i] = drive_get(IF_FLOPPY, 0, i); 1141 create_fdctrl |= !!fd[i]; 1142 } 1143 if (create_fdctrl) { 1144 fdc = isa_new(TYPE_ISA_FDC); 1145 if (fdc) { 1146 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1147 isa_fdc_init_drives(fdc, fd); 1148 } 1149 } 1150 1151 if (!create_i8042) { 1152 return; 1153 } 1154 1155 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1156 if (!no_vmport) { 1157 isa_create_simple(isa_bus, TYPE_VMPORT); 1158 vmmouse = isa_try_new("vmmouse"); 1159 } else { 1160 vmmouse = NULL; 1161 } 1162 if (vmmouse) { 1163 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1164 &error_abort); 1165 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1166 } 1167 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1168 1169 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1170 qdev_connect_gpio_out_named(DEVICE(i8042), 1171 I8042_A20_LINE, 0, a20_line[0]); 1172 qdev_connect_gpio_out_named(DEVICE(port92), 1173 PORT92_A20_LINE, 0, a20_line[1]); 1174 g_free(a20_line); 1175 } 1176 1177 void pc_basic_device_init(struct PCMachineState *pcms, 1178 ISABus *isa_bus, qemu_irq *gsi, 1179 ISADevice *rtc_state, 1180 bool create_fdctrl, 1181 uint32_t hpet_irqs) 1182 { 1183 int i; 1184 DeviceState *hpet = NULL; 1185 int pit_isa_irq = 0; 1186 qemu_irq pit_alt_irq = NULL; 1187 ISADevice *pit = NULL; 1188 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1189 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1190 X86MachineState *x86ms = X86_MACHINE(pcms); 1191 1192 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1193 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1194 1195 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1196 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1197 1198 /* 1199 * Check if an HPET shall be created. 1200 */ 1201 if (pcms->hpet_enabled) { 1202 qemu_irq rtc_irq; 1203 1204 hpet = qdev_try_new(TYPE_HPET); 1205 if (!hpet) { 1206 error_report("couldn't create HPET device"); 1207 exit(1); 1208 } 1209 /* 1210 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1211 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1212 * the property, use whatever mask they specified. 1213 */ 1214 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1215 HPET_INTCAP, NULL); 1216 if (!compat) { 1217 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1218 } 1219 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1220 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1221 1222 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1223 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1224 } 1225 pit_isa_irq = -1; 1226 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1227 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1228 1229 /* overwrite connection created by south bridge */ 1230 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1231 } 1232 1233 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1234 "date"); 1235 1236 #ifdef CONFIG_XEN_EMU 1237 if (xen_mode == XEN_EMULATE) { 1238 xen_overlay_create(); 1239 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1240 xen_gnttab_create(); 1241 xen_xenstore_create(); 1242 if (pcms->pcibus) { 1243 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1244 } 1245 xen_bus_init(); 1246 xen_be_init(); 1247 } 1248 #endif 1249 1250 qemu_register_boot_set(pc_boot_set, pcms); 1251 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1252 MACHINE(pcms)->boot_config.order, &error_fatal); 1253 1254 if (!xen_enabled() && 1255 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1256 if (kvm_pit_in_kernel()) { 1257 pit = kvm_pit_init(isa_bus, 0x40); 1258 } else { 1259 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1260 } 1261 if (hpet) { 1262 /* connect PIT to output control line of the HPET */ 1263 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1264 } 1265 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1266 OBJECT(pit), &error_fatal); 1267 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1268 } 1269 1270 /* Super I/O */ 1271 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1272 pcms->vmport != ON_OFF_AUTO_ON); 1273 } 1274 1275 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1276 { 1277 MachineClass *mc = MACHINE_CLASS(pcmc); 1278 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1279 NICInfo *nd; 1280 1281 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1282 1283 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1284 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1285 } 1286 1287 /* Anything remaining should be a PCI NIC */ 1288 pci_init_nic_devices(pci_bus, mc->default_nic); 1289 1290 rom_reset_order_override(); 1291 } 1292 1293 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1294 { 1295 qemu_irq *i8259; 1296 1297 if (kvm_pic_in_kernel()) { 1298 i8259 = kvm_i8259_init(isa_bus); 1299 } else if (xen_enabled()) { 1300 i8259 = xen_interrupt_controller_init(); 1301 } else { 1302 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1303 } 1304 1305 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1306 i8259_irqs[i] = i8259[i]; 1307 } 1308 1309 g_free(i8259); 1310 } 1311 1312 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1313 Error **errp) 1314 { 1315 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1316 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1317 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1318 const MachineState *ms = MACHINE(hotplug_dev); 1319 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1320 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1321 Error *local_err = NULL; 1322 1323 /* 1324 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1325 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1326 * addition to cover this case. 1327 */ 1328 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1329 error_setg(errp, 1330 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1331 return; 1332 } 1333 1334 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1335 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1336 return; 1337 } 1338 1339 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1340 if (local_err) { 1341 error_propagate(errp, local_err); 1342 return; 1343 } 1344 1345 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1346 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1347 } 1348 1349 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1350 DeviceState *dev, Error **errp) 1351 { 1352 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1353 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1354 MachineState *ms = MACHINE(hotplug_dev); 1355 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1356 1357 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1358 1359 if (is_nvdimm) { 1360 nvdimm_plug(ms->nvdimms_state); 1361 } 1362 1363 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1364 } 1365 1366 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1367 DeviceState *dev, Error **errp) 1368 { 1369 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1370 1371 /* 1372 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1373 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1374 * addition to cover this case. 1375 */ 1376 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1377 error_setg(errp, 1378 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1379 return; 1380 } 1381 1382 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1383 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1384 return; 1385 } 1386 1387 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1388 errp); 1389 } 1390 1391 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1392 DeviceState *dev, Error **errp) 1393 { 1394 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1395 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1396 Error *local_err = NULL; 1397 1398 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1399 if (local_err) { 1400 goto out; 1401 } 1402 1403 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1404 qdev_unrealize(dev); 1405 out: 1406 error_propagate(errp, local_err); 1407 } 1408 1409 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1410 DeviceState *dev, Error **errp) 1411 { 1412 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1413 g_assert(!dev->hotplugged); 1414 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1415 errp); 1416 } 1417 1418 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1419 DeviceState *dev, Error **errp) 1420 { 1421 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1422 } 1423 1424 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1425 DeviceState *dev, Error **errp) 1426 { 1427 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1428 pc_memory_pre_plug(hotplug_dev, dev, errp); 1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1430 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1432 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1433 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1434 /* Declare the APIC range as the reserved MSI region */ 1435 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1436 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1437 QList *reserved_regions = qlist_new(); 1438 1439 qlist_append_str(reserved_regions, resv_prop_str); 1440 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1441 1442 g_free(resv_prop_str); 1443 } 1444 1445 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1446 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1447 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1448 1449 if (pcms->iommu) { 1450 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1451 "for x86 yet."); 1452 return; 1453 } 1454 pcms->iommu = dev; 1455 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1456 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1457 } 1458 } 1459 1460 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1461 DeviceState *dev, Error **errp) 1462 { 1463 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1464 pc_memory_plug(hotplug_dev, dev, errp); 1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1466 x86_cpu_plug(hotplug_dev, dev, errp); 1467 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1468 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1469 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1470 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1471 } 1472 } 1473 1474 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1475 DeviceState *dev, Error **errp) 1476 { 1477 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1478 pc_memory_unplug_request(hotplug_dev, dev, errp); 1479 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1480 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1481 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1482 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1483 errp); 1484 } else { 1485 error_setg(errp, "acpi: device unplug request for not supported device" 1486 " type: %s", object_get_typename(OBJECT(dev))); 1487 } 1488 } 1489 1490 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1491 DeviceState *dev, Error **errp) 1492 { 1493 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1494 pc_memory_unplug(hotplug_dev, dev, errp); 1495 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1496 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1497 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1498 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1499 } else { 1500 error_setg(errp, "acpi: device unplug for not supported device" 1501 " type: %s", object_get_typename(OBJECT(dev))); 1502 } 1503 } 1504 1505 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1506 DeviceState *dev) 1507 { 1508 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1509 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1510 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1511 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1512 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1513 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1514 return HOTPLUG_HANDLER(machine); 1515 } 1516 1517 return NULL; 1518 } 1519 1520 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1521 void *opaque, Error **errp) 1522 { 1523 PCMachineState *pcms = PC_MACHINE(obj); 1524 OnOffAuto vmport = pcms->vmport; 1525 1526 visit_type_OnOffAuto(v, name, &vmport, errp); 1527 } 1528 1529 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1530 void *opaque, Error **errp) 1531 { 1532 PCMachineState *pcms = PC_MACHINE(obj); 1533 1534 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1535 } 1536 1537 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 1541 return pcms->fd_bootchk; 1542 } 1543 1544 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 1548 pcms->fd_bootchk = value; 1549 } 1550 1551 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1552 { 1553 PCMachineState *pcms = PC_MACHINE(obj); 1554 1555 return pcms->smbus_enabled; 1556 } 1557 1558 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1559 { 1560 PCMachineState *pcms = PC_MACHINE(obj); 1561 1562 pcms->smbus_enabled = value; 1563 } 1564 1565 static bool pc_machine_get_sata(Object *obj, Error **errp) 1566 { 1567 PCMachineState *pcms = PC_MACHINE(obj); 1568 1569 return pcms->sata_enabled; 1570 } 1571 1572 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 1576 pcms->sata_enabled = value; 1577 } 1578 1579 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 return pcms->hpet_enabled; 1584 } 1585 1586 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1587 { 1588 PCMachineState *pcms = PC_MACHINE(obj); 1589 1590 pcms->hpet_enabled = value; 1591 } 1592 1593 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1594 { 1595 PCMachineState *pcms = PC_MACHINE(obj); 1596 1597 return pcms->i8042_enabled; 1598 } 1599 1600 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1601 { 1602 PCMachineState *pcms = PC_MACHINE(obj); 1603 1604 pcms->i8042_enabled = value; 1605 } 1606 1607 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1608 { 1609 PCMachineState *pcms = PC_MACHINE(obj); 1610 1611 return pcms->default_bus_bypass_iommu; 1612 } 1613 1614 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1615 Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 1619 pcms->default_bus_bypass_iommu = value; 1620 } 1621 1622 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1623 void *opaque, Error **errp) 1624 { 1625 PCMachineState *pcms = PC_MACHINE(obj); 1626 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1627 1628 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1629 } 1630 1631 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1632 void *opaque, Error **errp) 1633 { 1634 PCMachineState *pcms = PC_MACHINE(obj); 1635 1636 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1637 } 1638 1639 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1640 const char *name, void *opaque, 1641 Error **errp) 1642 { 1643 PCMachineState *pcms = PC_MACHINE(obj); 1644 uint64_t value = pcms->max_ram_below_4g; 1645 1646 visit_type_size(v, name, &value, errp); 1647 } 1648 1649 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1650 const char *name, void *opaque, 1651 Error **errp) 1652 { 1653 PCMachineState *pcms = PC_MACHINE(obj); 1654 uint64_t value; 1655 1656 if (!visit_type_size(v, name, &value, errp)) { 1657 return; 1658 } 1659 if (value > 4 * GiB) { 1660 error_setg(errp, 1661 "Machine option 'max-ram-below-4g=%"PRIu64 1662 "' expects size less than or equal to 4G", value); 1663 return; 1664 } 1665 1666 if (value < 1 * MiB) { 1667 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1668 "BIOS may not work with less than 1MiB", value); 1669 } 1670 1671 pcms->max_ram_below_4g = value; 1672 } 1673 1674 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1675 const char *name, void *opaque, 1676 Error **errp) 1677 { 1678 PCMachineState *pcms = PC_MACHINE(obj); 1679 uint64_t value = pcms->max_fw_size; 1680 1681 visit_type_size(v, name, &value, errp); 1682 } 1683 1684 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1685 const char *name, void *opaque, 1686 Error **errp) 1687 { 1688 PCMachineState *pcms = PC_MACHINE(obj); 1689 uint64_t value; 1690 1691 if (!visit_type_size(v, name, &value, errp)) { 1692 return; 1693 } 1694 1695 /* 1696 * We don't have a theoretically justifiable exact lower bound on the base 1697 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1698 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1699 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1700 * 16MiB in size. 1701 */ 1702 if (value > 16 * MiB) { 1703 error_setg(errp, 1704 "User specified max allowed firmware size %" PRIu64 " is " 1705 "greater than 16MiB. If combined firmware size exceeds " 1706 "16MiB the system may not boot, or experience intermittent" 1707 "stability issues.", 1708 value); 1709 return; 1710 } 1711 1712 pcms->max_fw_size = value; 1713 } 1714 1715 1716 static void pc_machine_initfn(Object *obj) 1717 { 1718 PCMachineState *pcms = PC_MACHINE(obj); 1719 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1720 1721 #ifdef CONFIG_VMPORT 1722 pcms->vmport = ON_OFF_AUTO_AUTO; 1723 #else 1724 pcms->vmport = ON_OFF_AUTO_OFF; 1725 #endif /* CONFIG_VMPORT */ 1726 pcms->max_ram_below_4g = 0; /* use default */ 1727 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1728 pcms->south_bridge = pcmc->default_south_bridge; 1729 1730 /* acpi build is enabled by default if machine supports it */ 1731 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1732 pcms->smbus_enabled = true; 1733 pcms->sata_enabled = true; 1734 pcms->i8042_enabled = true; 1735 pcms->max_fw_size = 8 * MiB; 1736 #ifdef CONFIG_HPET 1737 pcms->hpet_enabled = true; 1738 #endif 1739 pcms->fd_bootchk = true; 1740 pcms->default_bus_bypass_iommu = false; 1741 1742 pc_system_flash_create(pcms); 1743 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1744 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1745 OBJECT(pcms->pcspk), "audiodev"); 1746 if (pcmc->pci_enabled) { 1747 cxl_machine_init(obj, &pcms->cxl_devices_state); 1748 } 1749 1750 pcms->machine_done.notify = pc_machine_done; 1751 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1752 } 1753 1754 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1755 { 1756 CPUState *cs; 1757 X86CPU *cpu; 1758 1759 qemu_devices_reset(reason); 1760 1761 /* Reset APIC after devices have been reset to cancel 1762 * any changes that qemu_devices_reset() might have done. 1763 */ 1764 CPU_FOREACH(cs) { 1765 cpu = X86_CPU(cs); 1766 1767 x86_cpu_after_reset(cpu); 1768 } 1769 } 1770 1771 static void pc_machine_wakeup(MachineState *machine) 1772 { 1773 cpu_synchronize_all_states(); 1774 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1775 cpu_synchronize_all_post_reset(); 1776 } 1777 1778 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1779 { 1780 X86IOMMUState *iommu = x86_iommu_get_default(); 1781 IntelIOMMUState *intel_iommu; 1782 1783 if (iommu && 1784 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1785 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1786 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1787 if (!intel_iommu->caching_mode) { 1788 error_setg(errp, "Device assignment is not allowed without " 1789 "enabling caching-mode=on for Intel IOMMU."); 1790 return false; 1791 } 1792 } 1793 1794 return true; 1795 } 1796 1797 static void pc_machine_class_init(ObjectClass *oc, void *data) 1798 { 1799 MachineClass *mc = MACHINE_CLASS(oc); 1800 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1801 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1802 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1803 1804 pcmc->pci_enabled = true; 1805 pcmc->has_acpi_build = true; 1806 pcmc->rsdp_in_ram = true; 1807 pcmc->smbios_defaults = true; 1808 pcmc->smbios_uuid_encoded = true; 1809 pcmc->gigabyte_align = true; 1810 pcmc->has_reserved_memory = true; 1811 pcmc->enforce_aligned_dimm = true; 1812 pcmc->enforce_amd_1tb_hole = true; 1813 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1814 * to be used at the moment, 32K should be enough for a while. */ 1815 pcmc->acpi_data_size = 0x20000 + 0x8000; 1816 pcmc->pvh_enabled = true; 1817 pcmc->kvmclock_create_always = true; 1818 pcmc->resizable_acpi_blob = true; 1819 x86mc->apic_xrupt_override = true; 1820 assert(!mc->get_hotplug_handler); 1821 mc->get_hotplug_handler = pc_get_hotplug_handler; 1822 mc->hotplug_allowed = pc_hotplug_allowed; 1823 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1824 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1825 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1826 mc->auto_enable_numa_with_memhp = true; 1827 mc->auto_enable_numa_with_memdev = true; 1828 mc->has_hotpluggable_cpus = true; 1829 mc->default_boot_order = "cad"; 1830 mc->block_default_type = IF_IDE; 1831 mc->max_cpus = 255; 1832 mc->reset = pc_machine_reset; 1833 mc->wakeup = pc_machine_wakeup; 1834 hc->pre_plug = pc_machine_device_pre_plug_cb; 1835 hc->plug = pc_machine_device_plug_cb; 1836 hc->unplug_request = pc_machine_device_unplug_request_cb; 1837 hc->unplug = pc_machine_device_unplug_cb; 1838 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1839 mc->nvdimm_supported = true; 1840 mc->smp_props.dies_supported = true; 1841 mc->default_ram_id = "pc.ram"; 1842 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1843 1844 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1845 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1846 NULL, NULL); 1847 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1848 "Maximum ram below the 4G boundary (32bit boundary)"); 1849 1850 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1851 pc_machine_get_vmport, pc_machine_set_vmport, 1852 NULL, NULL); 1853 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1854 "Enable vmport (pc & q35)"); 1855 1856 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1857 pc_machine_get_smbus, pc_machine_set_smbus); 1858 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1859 "Enable/disable system management bus"); 1860 1861 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1862 pc_machine_get_sata, pc_machine_set_sata); 1863 object_class_property_set_description(oc, PC_MACHINE_SATA, 1864 "Enable/disable Serial ATA bus"); 1865 1866 object_class_property_add_bool(oc, "hpet", 1867 pc_machine_get_hpet, pc_machine_set_hpet); 1868 object_class_property_set_description(oc, "hpet", 1869 "Enable/disable high precision event timer emulation"); 1870 1871 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1872 pc_machine_get_i8042, pc_machine_set_i8042); 1873 1874 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1875 pc_machine_get_default_bus_bypass_iommu, 1876 pc_machine_set_default_bus_bypass_iommu); 1877 1878 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1879 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1880 NULL, NULL); 1881 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1882 "Maximum combined firmware size"); 1883 1884 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1885 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1886 NULL, NULL); 1887 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1888 "SMBIOS Entry Point type [32, 64]"); 1889 1890 object_class_property_add_bool(oc, "fd-bootchk", 1891 pc_machine_get_fd_bootchk, 1892 pc_machine_set_fd_bootchk); 1893 } 1894 1895 static const TypeInfo pc_machine_info = { 1896 .name = TYPE_PC_MACHINE, 1897 .parent = TYPE_X86_MACHINE, 1898 .abstract = true, 1899 .instance_size = sizeof(PCMachineState), 1900 .instance_init = pc_machine_initfn, 1901 .class_size = sizeof(PCMachineClass), 1902 .class_init = pc_machine_class_init, 1903 .interfaces = (InterfaceInfo[]) { 1904 { TYPE_HOTPLUG_HANDLER }, 1905 { } 1906 }, 1907 }; 1908 1909 static void pc_machine_register_types(void) 1910 { 1911 type_register_static(&pc_machine_info); 1912 } 1913 1914 type_init(pc_machine_register_types) 1915