1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "sysemu/arch_init.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_0[] = { 98 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 99 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 100 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 101 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 102 }; 103 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 104 105 GlobalProperty pc_compat_5_2[] = { 106 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 107 }; 108 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 109 110 GlobalProperty pc_compat_5_1[] = { 111 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 112 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 113 }; 114 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 115 116 GlobalProperty pc_compat_5_0[] = { 117 }; 118 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 119 120 GlobalProperty pc_compat_4_2[] = { 121 { "mch", "smbase-smram", "off" }, 122 }; 123 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 124 125 GlobalProperty pc_compat_4_1[] = {}; 126 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 127 128 GlobalProperty pc_compat_4_0[] = {}; 129 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 130 131 GlobalProperty pc_compat_3_1[] = { 132 { "intel-iommu", "dma-drain", "off" }, 133 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 134 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 135 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 136 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 137 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 138 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 139 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 140 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 141 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 142 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 143 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 144 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 146 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 147 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 148 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 149 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 150 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 151 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 152 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 153 }; 154 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 155 156 GlobalProperty pc_compat_3_0[] = { 157 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 158 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 159 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 160 }; 161 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 162 163 GlobalProperty pc_compat_2_12[] = { 164 { TYPE_X86_CPU, "legacy-cache", "on" }, 165 { TYPE_X86_CPU, "topoext", "off" }, 166 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 167 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 168 }; 169 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 170 171 GlobalProperty pc_compat_2_11[] = { 172 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 173 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 174 }; 175 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 176 177 GlobalProperty pc_compat_2_10[] = { 178 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 179 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 180 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 181 }; 182 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 183 184 GlobalProperty pc_compat_2_9[] = { 185 { "mch", "extended-tseg-mbytes", "0" }, 186 }; 187 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 188 189 GlobalProperty pc_compat_2_8[] = { 190 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 191 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 192 { "ICH9-LPC", "x-smi-broadcast", "off" }, 193 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 194 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 195 }; 196 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 197 198 GlobalProperty pc_compat_2_7[] = { 199 { TYPE_X86_CPU, "l3-cache", "off" }, 200 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 201 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 202 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 203 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 204 { "isa-pcspk", "migrate", "off" }, 205 }; 206 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 207 208 GlobalProperty pc_compat_2_6[] = { 209 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 210 { "vmxnet3", "romfile", "" }, 211 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 212 { "apic-common", "legacy-instance-id", "on", } 213 }; 214 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 215 216 GlobalProperty pc_compat_2_5[] = {}; 217 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 218 219 GlobalProperty pc_compat_2_4[] = { 220 PC_CPU_MODEL_IDS("2.4.0") 221 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 222 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 223 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 224 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 225 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 226 { TYPE_X86_CPU, "check", "off" }, 227 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 228 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 229 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 230 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 231 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 232 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 233 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 234 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 235 }; 236 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 237 238 GlobalProperty pc_compat_2_3[] = { 239 PC_CPU_MODEL_IDS("2.3.0") 240 { TYPE_X86_CPU, "arat", "off" }, 241 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 242 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 243 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 244 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 245 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 246 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 247 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 248 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 255 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 256 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 257 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 258 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 259 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 260 }; 261 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 262 263 GlobalProperty pc_compat_2_2[] = { 264 PC_CPU_MODEL_IDS("2.2.0") 265 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 279 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 280 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 281 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 282 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 283 }; 284 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 285 286 GlobalProperty pc_compat_2_1[] = { 287 PC_CPU_MODEL_IDS("2.1.0") 288 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 289 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 290 }; 291 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 292 293 GlobalProperty pc_compat_2_0[] = { 294 PC_CPU_MODEL_IDS("2.0.0") 295 { "virtio-scsi-pci", "any_layout", "off" }, 296 { "PIIX4_PM", "memory-hotplug-support", "off" }, 297 { "apic", "version", "0x11" }, 298 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 299 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 300 { "pci-serial", "prog_if", "0" }, 301 { "pci-serial-2x", "prog_if", "0" }, 302 { "pci-serial-4x", "prog_if", "0" }, 303 { "virtio-net-pci", "guest_announce", "off" }, 304 { "ICH9-LPC", "memory-hotplug-support", "off" }, 305 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 306 { "ioh3420", COMPAT_PROP_PCP, "off" }, 307 }; 308 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 309 310 GlobalProperty pc_compat_1_7[] = { 311 PC_CPU_MODEL_IDS("1.7.0") 312 { TYPE_USB_DEVICE, "msos-desc", "no" }, 313 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 314 { "hpet", HPET_INTCAP, "4" }, 315 }; 316 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 317 318 GlobalProperty pc_compat_1_6[] = { 319 PC_CPU_MODEL_IDS("1.6.0") 320 { "e1000", "mitigation", "off" }, 321 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 322 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 323 { "i440FX-pcihost", "short_root_bus", "1" }, 324 { "q35-pcihost", "short_root_bus", "1" }, 325 }; 326 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 327 328 GlobalProperty pc_compat_1_5[] = { 329 PC_CPU_MODEL_IDS("1.5.0") 330 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 331 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 332 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 333 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 334 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 335 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 336 { "virtio-net-pci", "any_layout", "off" }, 337 { TYPE_X86_CPU, "pmu", "on" }, 338 { "i440FX-pcihost", "short_root_bus", "0" }, 339 { "q35-pcihost", "short_root_bus", "0" }, 340 }; 341 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 342 343 GlobalProperty pc_compat_1_4[] = { 344 PC_CPU_MODEL_IDS("1.4.0") 345 { "scsi-hd", "discard_granularity", "0" }, 346 { "scsi-cd", "discard_granularity", "0" }, 347 { "ide-hd", "discard_granularity", "0" }, 348 { "ide-cd", "discard_granularity", "0" }, 349 { "virtio-blk-pci", "discard_granularity", "0" }, 350 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 351 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 352 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 353 { "e1000", "romfile", "pxe-e1000.rom" }, 354 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 355 { "pcnet", "romfile", "pxe-pcnet.rom" }, 356 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 357 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 358 { "486-" TYPE_X86_CPU, "model", "0" }, 359 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 360 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 361 }; 362 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 363 364 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 365 { 366 GSIState *s; 367 368 s = g_new0(GSIState, 1); 369 if (kvm_ioapic_in_kernel()) { 370 kvm_pc_setup_irq_routing(pci_enabled); 371 } 372 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 373 374 return s; 375 } 376 377 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 378 unsigned size) 379 { 380 } 381 382 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 383 { 384 return 0xffffffffffffffffULL; 385 } 386 387 /* MSDOS compatibility mode FPU exception support */ 388 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 389 unsigned size) 390 { 391 if (tcg_enabled()) { 392 cpu_set_ignne(); 393 } 394 } 395 396 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 397 { 398 return 0xffffffffffffffffULL; 399 } 400 401 /* PC cmos mappings */ 402 403 #define REG_EQUIPMENT_BYTE 0x14 404 405 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 406 int16_t cylinders, int8_t heads, int8_t sectors) 407 { 408 rtc_set_memory(s, type_ofs, 47); 409 rtc_set_memory(s, info_ofs, cylinders); 410 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 411 rtc_set_memory(s, info_ofs + 2, heads); 412 rtc_set_memory(s, info_ofs + 3, 0xff); 413 rtc_set_memory(s, info_ofs + 4, 0xff); 414 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 415 rtc_set_memory(s, info_ofs + 6, cylinders); 416 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 417 rtc_set_memory(s, info_ofs + 8, sectors); 418 } 419 420 /* convert boot_device letter to something recognizable by the bios */ 421 static int boot_device2nibble(char boot_device) 422 { 423 switch(boot_device) { 424 case 'a': 425 case 'b': 426 return 0x01; /* floppy boot */ 427 case 'c': 428 return 0x02; /* hard drive boot */ 429 case 'd': 430 return 0x03; /* CD-ROM boot */ 431 case 'n': 432 return 0x04; /* Network boot */ 433 } 434 return 0; 435 } 436 437 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 438 { 439 #define PC_MAX_BOOT_DEVICES 3 440 int nbds, bds[3] = { 0, }; 441 int i; 442 443 nbds = strlen(boot_device); 444 if (nbds > PC_MAX_BOOT_DEVICES) { 445 error_setg(errp, "Too many boot devices for PC"); 446 return; 447 } 448 for (i = 0; i < nbds; i++) { 449 bds[i] = boot_device2nibble(boot_device[i]); 450 if (bds[i] == 0) { 451 error_setg(errp, "Invalid boot device for PC: '%c'", 452 boot_device[i]); 453 return; 454 } 455 } 456 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 457 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 458 } 459 460 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 461 { 462 set_boot_dev(opaque, boot_device, errp); 463 } 464 465 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 466 { 467 int val, nb, i; 468 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 469 FLOPPY_DRIVE_TYPE_NONE }; 470 471 /* floppy type */ 472 if (floppy) { 473 for (i = 0; i < 2; i++) { 474 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 475 } 476 } 477 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 478 cmos_get_fd_drive_type(fd_type[1]); 479 rtc_set_memory(rtc_state, 0x10, val); 480 481 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 482 nb = 0; 483 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 484 nb++; 485 } 486 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 487 nb++; 488 } 489 switch (nb) { 490 case 0: 491 break; 492 case 1: 493 val |= 0x01; /* 1 drive, ready for boot */ 494 break; 495 case 2: 496 val |= 0x41; /* 2 drives, ready for boot */ 497 break; 498 } 499 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 500 } 501 502 typedef struct pc_cmos_init_late_arg { 503 ISADevice *rtc_state; 504 BusState *idebus[2]; 505 } pc_cmos_init_late_arg; 506 507 typedef struct check_fdc_state { 508 ISADevice *floppy; 509 bool multiple; 510 } CheckFdcState; 511 512 static int check_fdc(Object *obj, void *opaque) 513 { 514 CheckFdcState *state = opaque; 515 Object *fdc; 516 uint32_t iobase; 517 Error *local_err = NULL; 518 519 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 520 if (!fdc) { 521 return 0; 522 } 523 524 iobase = object_property_get_uint(obj, "iobase", &local_err); 525 if (local_err || iobase != 0x3f0) { 526 error_free(local_err); 527 return 0; 528 } 529 530 if (state->floppy) { 531 state->multiple = true; 532 } else { 533 state->floppy = ISA_DEVICE(obj); 534 } 535 return 0; 536 } 537 538 static const char * const fdc_container_path[] = { 539 "/unattached", "/peripheral", "/peripheral-anon" 540 }; 541 542 /* 543 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 544 * and ACPI objects. 545 */ 546 ISADevice *pc_find_fdc0(void) 547 { 548 int i; 549 Object *container; 550 CheckFdcState state = { 0 }; 551 552 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 553 container = container_get(qdev_get_machine(), fdc_container_path[i]); 554 object_child_foreach(container, check_fdc, &state); 555 } 556 557 if (state.multiple) { 558 warn_report("multiple floppy disk controllers with " 559 "iobase=0x3f0 have been found"); 560 error_printf("the one being picked for CMOS setup might not reflect " 561 "your intent"); 562 } 563 564 return state.floppy; 565 } 566 567 static void pc_cmos_init_late(void *opaque) 568 { 569 pc_cmos_init_late_arg *arg = opaque; 570 ISADevice *s = arg->rtc_state; 571 int16_t cylinders; 572 int8_t heads, sectors; 573 int val; 574 int i, trans; 575 576 val = 0; 577 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 578 &cylinders, &heads, §ors) >= 0) { 579 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 580 val |= 0xf0; 581 } 582 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 583 &cylinders, &heads, §ors) >= 0) { 584 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 585 val |= 0x0f; 586 } 587 rtc_set_memory(s, 0x12, val); 588 589 val = 0; 590 for (i = 0; i < 4; i++) { 591 /* NOTE: ide_get_geometry() returns the physical 592 geometry. It is always such that: 1 <= sects <= 63, 1 593 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 594 geometry can be different if a translation is done. */ 595 if (arg->idebus[i / 2] && 596 ide_get_geometry(arg->idebus[i / 2], i % 2, 597 &cylinders, &heads, §ors) >= 0) { 598 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 599 assert((trans & ~3) == 0); 600 val |= trans << (i * 2); 601 } 602 } 603 rtc_set_memory(s, 0x39, val); 604 605 pc_cmos_init_floppy(s, pc_find_fdc0()); 606 607 qemu_unregister_reset(pc_cmos_init_late, opaque); 608 } 609 610 void pc_cmos_init(PCMachineState *pcms, 611 BusState *idebus0, BusState *idebus1, 612 ISADevice *s) 613 { 614 int val; 615 static pc_cmos_init_late_arg arg; 616 X86MachineState *x86ms = X86_MACHINE(pcms); 617 618 /* various important CMOS locations needed by PC/Bochs bios */ 619 620 /* memory size */ 621 /* base memory (first MiB) */ 622 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 623 rtc_set_memory(s, 0x15, val); 624 rtc_set_memory(s, 0x16, val >> 8); 625 /* extended memory (next 64MiB) */ 626 if (x86ms->below_4g_mem_size > 1 * MiB) { 627 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 628 } else { 629 val = 0; 630 } 631 if (val > 65535) 632 val = 65535; 633 rtc_set_memory(s, 0x17, val); 634 rtc_set_memory(s, 0x18, val >> 8); 635 rtc_set_memory(s, 0x30, val); 636 rtc_set_memory(s, 0x31, val >> 8); 637 /* memory between 16MiB and 4GiB */ 638 if (x86ms->below_4g_mem_size > 16 * MiB) { 639 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 640 } else { 641 val = 0; 642 } 643 if (val > 65535) 644 val = 65535; 645 rtc_set_memory(s, 0x34, val); 646 rtc_set_memory(s, 0x35, val >> 8); 647 /* memory above 4GiB */ 648 val = x86ms->above_4g_mem_size / 65536; 649 rtc_set_memory(s, 0x5b, val); 650 rtc_set_memory(s, 0x5c, val >> 8); 651 rtc_set_memory(s, 0x5d, val >> 16); 652 653 object_property_add_link(OBJECT(pcms), "rtc_state", 654 TYPE_ISA_DEVICE, 655 (Object **)&x86ms->rtc, 656 object_property_allow_set_link, 657 OBJ_PROP_LINK_STRONG); 658 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 659 &error_abort); 660 661 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 662 663 val = 0; 664 val |= 0x02; /* FPU is there */ 665 val |= 0x04; /* PS/2 mouse installed */ 666 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 667 668 /* hard drives and FDC */ 669 arg.rtc_state = s; 670 arg.idebus[0] = idebus0; 671 arg.idebus[1] = idebus1; 672 qemu_register_reset(pc_cmos_init_late, &arg); 673 } 674 675 static void handle_a20_line_change(void *opaque, int irq, int level) 676 { 677 X86CPU *cpu = opaque; 678 679 /* XXX: send to all CPUs ? */ 680 /* XXX: add logic to handle multiple A20 line sources */ 681 x86_cpu_set_a20(cpu, level); 682 } 683 684 #define NE2000_NB_MAX 6 685 686 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 687 0x280, 0x380 }; 688 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 689 690 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 691 { 692 static int nb_ne2k = 0; 693 694 if (nb_ne2k == NE2000_NB_MAX) 695 return; 696 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 697 ne2000_irq[nb_ne2k], nd); 698 nb_ne2k++; 699 } 700 701 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 702 { 703 X86CPU *cpu = opaque; 704 705 if (level) { 706 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 707 } 708 } 709 710 /* 711 * This function is very similar to smp_parse() 712 * in hw/core/machine.c but includes CPU die support. 713 */ 714 static void pc_smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp) 715 { 716 unsigned cpus = config->has_cpus ? config->cpus : 0; 717 unsigned sockets = config->has_sockets ? config->sockets : 0; 718 unsigned dies = config->has_dies ? config->dies : 1; 719 unsigned cores = config->has_cores ? config->cores : 0; 720 unsigned threads = config->has_threads ? config->threads : 0; 721 722 /* compute missing values, prefer sockets over cores over threads */ 723 if (cpus == 0 || sockets == 0) { 724 cores = cores > 0 ? cores : 1; 725 threads = threads > 0 ? threads : 1; 726 if (cpus == 0) { 727 sockets = sockets > 0 ? sockets : 1; 728 cpus = cores * threads * dies * sockets; 729 } else { 730 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 731 sockets = ms->smp.max_cpus / (cores * threads * dies); 732 } 733 } else if (cores == 0) { 734 threads = threads > 0 ? threads : 1; 735 cores = cpus / (sockets * dies * threads); 736 cores = cores > 0 ? cores : 1; 737 } else if (threads == 0) { 738 threads = cpus / (cores * dies * sockets); 739 threads = threads > 0 ? threads : 1; 740 } else if (sockets * dies * cores * threads < cpus) { 741 error_setg(errp, "cpu topology: " 742 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 743 "smp_cpus (%u)", 744 sockets, dies, cores, threads, cpus); 745 return; 746 } 747 748 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 749 750 if (ms->smp.max_cpus < cpus) { 751 error_setg(errp, "maxcpus must be equal to or greater than smp"); 752 return; 753 } 754 755 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 756 error_setg(errp, "Invalid CPU topology deprecated: " 757 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 758 "!= maxcpus (%u)", 759 sockets, dies, cores, threads, 760 ms->smp.max_cpus); 761 return; 762 } 763 764 ms->smp.cpus = cpus; 765 ms->smp.cores = cores; 766 ms->smp.threads = threads; 767 ms->smp.sockets = sockets; 768 ms->smp.dies = dies; 769 } 770 771 static 772 void pc_machine_done(Notifier *notifier, void *data) 773 { 774 PCMachineState *pcms = container_of(notifier, 775 PCMachineState, machine_done); 776 X86MachineState *x86ms = X86_MACHINE(pcms); 777 778 /* set the number of CPUs */ 779 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 780 781 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 782 783 acpi_setup(); 784 if (x86ms->fw_cfg) { 785 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 786 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 787 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 788 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 789 } 790 791 792 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 793 !kvm_irqchip_in_kernel()) { 794 error_report("current -smp configuration requires kernel " 795 "irqchip support."); 796 exit(EXIT_FAILURE); 797 } 798 } 799 800 void pc_guest_info_init(PCMachineState *pcms) 801 { 802 int i; 803 MachineState *ms = MACHINE(pcms); 804 X86MachineState *x86ms = X86_MACHINE(pcms); 805 806 x86ms->apic_xrupt_override = true; 807 pcms->numa_nodes = ms->numa_state->num_nodes; 808 pcms->node_mem = g_malloc0(pcms->numa_nodes * 809 sizeof *pcms->node_mem); 810 for (i = 0; i < ms->numa_state->num_nodes; i++) { 811 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 812 } 813 814 pcms->machine_done.notify = pc_machine_done; 815 qemu_add_machine_init_done_notifier(&pcms->machine_done); 816 } 817 818 /* setup pci memory address space mapping into system address space */ 819 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 820 MemoryRegion *pci_address_space) 821 { 822 /* Set to lower priority than RAM */ 823 memory_region_add_subregion_overlap(system_memory, 0x0, 824 pci_address_space, -1); 825 } 826 827 void xen_load_linux(PCMachineState *pcms) 828 { 829 int i; 830 FWCfgState *fw_cfg; 831 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 832 X86MachineState *x86ms = X86_MACHINE(pcms); 833 834 assert(MACHINE(pcms)->kernel_filename != NULL); 835 836 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 837 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 838 rom_set_fw(fw_cfg); 839 840 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 841 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 842 for (i = 0; i < nb_option_roms; i++) { 843 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 844 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 845 !strcmp(option_rom[i].name, "pvh.bin") || 846 !strcmp(option_rom[i].name, "multiboot.bin")); 847 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 848 } 849 x86ms->fw_cfg = fw_cfg; 850 } 851 852 void pc_memory_init(PCMachineState *pcms, 853 MemoryRegion *system_memory, 854 MemoryRegion *rom_memory, 855 MemoryRegion **ram_memory) 856 { 857 int linux_boot, i; 858 MemoryRegion *option_rom_mr; 859 MemoryRegion *ram_below_4g, *ram_above_4g; 860 FWCfgState *fw_cfg; 861 MachineState *machine = MACHINE(pcms); 862 MachineClass *mc = MACHINE_GET_CLASS(machine); 863 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 864 X86MachineState *x86ms = X86_MACHINE(pcms); 865 866 assert(machine->ram_size == x86ms->below_4g_mem_size + 867 x86ms->above_4g_mem_size); 868 869 linux_boot = (machine->kernel_filename != NULL); 870 871 /* 872 * Split single memory region and use aliases to address portions of it, 873 * done for backwards compatibility with older qemus. 874 */ 875 *ram_memory = machine->ram; 876 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 877 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 878 0, x86ms->below_4g_mem_size); 879 memory_region_add_subregion(system_memory, 0, ram_below_4g); 880 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 881 if (x86ms->above_4g_mem_size > 0) { 882 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 883 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 884 machine->ram, 885 x86ms->below_4g_mem_size, 886 x86ms->above_4g_mem_size); 887 memory_region_add_subregion(system_memory, 0x100000000ULL, 888 ram_above_4g); 889 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 890 } 891 892 if (!pcmc->has_reserved_memory && 893 (machine->ram_slots || 894 (machine->maxram_size > machine->ram_size))) { 895 896 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 897 mc->name); 898 exit(EXIT_FAILURE); 899 } 900 901 /* always allocate the device memory information */ 902 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 903 904 /* initialize device memory address space */ 905 if (pcmc->has_reserved_memory && 906 (machine->ram_size < machine->maxram_size)) { 907 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 908 909 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 910 error_report("unsupported amount of memory slots: %"PRIu64, 911 machine->ram_slots); 912 exit(EXIT_FAILURE); 913 } 914 915 if (QEMU_ALIGN_UP(machine->maxram_size, 916 TARGET_PAGE_SIZE) != machine->maxram_size) { 917 error_report("maximum memory size must by aligned to multiple of " 918 "%d bytes", TARGET_PAGE_SIZE); 919 exit(EXIT_FAILURE); 920 } 921 922 machine->device_memory->base = 923 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 924 925 if (pcmc->enforce_aligned_dimm) { 926 /* size device region assuming 1G page max alignment per slot */ 927 device_mem_size += (1 * GiB) * machine->ram_slots; 928 } 929 930 if ((machine->device_memory->base + device_mem_size) < 931 device_mem_size) { 932 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 933 machine->maxram_size); 934 exit(EXIT_FAILURE); 935 } 936 937 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 938 "device-memory", device_mem_size); 939 memory_region_add_subregion(system_memory, machine->device_memory->base, 940 &machine->device_memory->mr); 941 } 942 943 /* Initialize PC system firmware */ 944 pc_system_firmware_init(pcms, rom_memory); 945 946 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 947 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 948 &error_fatal); 949 if (pcmc->pci_enabled) { 950 memory_region_set_readonly(option_rom_mr, true); 951 } 952 memory_region_add_subregion_overlap(rom_memory, 953 PC_ROM_MIN_VGA, 954 option_rom_mr, 955 1); 956 957 fw_cfg = fw_cfg_arch_create(machine, 958 x86ms->boot_cpus, x86ms->apic_id_limit); 959 960 rom_set_fw(fw_cfg); 961 962 if (pcmc->has_reserved_memory && machine->device_memory->base) { 963 uint64_t *val = g_malloc(sizeof(*val)); 964 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 965 uint64_t res_mem_end = machine->device_memory->base; 966 967 if (!pcmc->broken_reserved_end) { 968 res_mem_end += memory_region_size(&machine->device_memory->mr); 969 } 970 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 971 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 972 } 973 974 if (linux_boot) { 975 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 976 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 977 } 978 979 for (i = 0; i < nb_option_roms; i++) { 980 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 981 } 982 x86ms->fw_cfg = fw_cfg; 983 984 /* Init default IOAPIC address space */ 985 x86ms->ioapic_as = &address_space_memory; 986 987 /* Init ACPI memory hotplug IO base address */ 988 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 989 } 990 991 /* 992 * The 64bit pci hole starts after "above 4G RAM" and 993 * potentially the space reserved for memory hotplug. 994 */ 995 uint64_t pc_pci_hole64_start(void) 996 { 997 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 998 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 999 MachineState *ms = MACHINE(pcms); 1000 X86MachineState *x86ms = X86_MACHINE(pcms); 1001 uint64_t hole64_start = 0; 1002 1003 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1004 hole64_start = ms->device_memory->base; 1005 if (!pcmc->broken_reserved_end) { 1006 hole64_start += memory_region_size(&ms->device_memory->mr); 1007 } 1008 } else { 1009 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1010 } 1011 1012 return ROUND_UP(hole64_start, 1 * GiB); 1013 } 1014 1015 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1016 { 1017 DeviceState *dev = NULL; 1018 1019 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1020 if (pci_bus) { 1021 PCIDevice *pcidev = pci_vga_init(pci_bus); 1022 dev = pcidev ? &pcidev->qdev : NULL; 1023 } else if (isa_bus) { 1024 ISADevice *isadev = isa_vga_init(isa_bus); 1025 dev = isadev ? DEVICE(isadev) : NULL; 1026 } 1027 rom_reset_order_override(); 1028 return dev; 1029 } 1030 1031 static const MemoryRegionOps ioport80_io_ops = { 1032 .write = ioport80_write, 1033 .read = ioport80_read, 1034 .endianness = DEVICE_NATIVE_ENDIAN, 1035 .impl = { 1036 .min_access_size = 1, 1037 .max_access_size = 1, 1038 }, 1039 }; 1040 1041 static const MemoryRegionOps ioportF0_io_ops = { 1042 .write = ioportF0_write, 1043 .read = ioportF0_read, 1044 .endianness = DEVICE_NATIVE_ENDIAN, 1045 .impl = { 1046 .min_access_size = 1, 1047 .max_access_size = 1, 1048 }, 1049 }; 1050 1051 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1052 { 1053 int i; 1054 DriveInfo *fd[MAX_FD]; 1055 qemu_irq *a20_line; 1056 ISADevice *fdc, *i8042, *port92, *vmmouse; 1057 1058 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1059 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1060 1061 for (i = 0; i < MAX_FD; i++) { 1062 fd[i] = drive_get(IF_FLOPPY, 0, i); 1063 create_fdctrl |= !!fd[i]; 1064 } 1065 if (create_fdctrl) { 1066 fdc = isa_new(TYPE_ISA_FDC); 1067 if (fdc) { 1068 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1069 isa_fdc_init_drives(fdc, fd); 1070 } 1071 } 1072 1073 i8042 = isa_create_simple(isa_bus, "i8042"); 1074 if (!no_vmport) { 1075 isa_create_simple(isa_bus, TYPE_VMPORT); 1076 vmmouse = isa_try_new("vmmouse"); 1077 } else { 1078 vmmouse = NULL; 1079 } 1080 if (vmmouse) { 1081 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1082 &error_abort); 1083 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1084 } 1085 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1086 1087 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1088 i8042_setup_a20_line(i8042, a20_line[0]); 1089 qdev_connect_gpio_out_named(DEVICE(port92), 1090 PORT92_A20_LINE, 0, a20_line[1]); 1091 g_free(a20_line); 1092 } 1093 1094 void pc_basic_device_init(struct PCMachineState *pcms, 1095 ISABus *isa_bus, qemu_irq *gsi, 1096 ISADevice **rtc_state, 1097 bool create_fdctrl, 1098 uint32_t hpet_irqs) 1099 { 1100 int i; 1101 DeviceState *hpet = NULL; 1102 int pit_isa_irq = 0; 1103 qemu_irq pit_alt_irq = NULL; 1104 qemu_irq rtc_irq = NULL; 1105 ISADevice *pit = NULL; 1106 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1107 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1108 1109 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1110 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1111 1112 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1113 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1114 1115 /* 1116 * Check if an HPET shall be created. 1117 * 1118 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1119 * when the HPET wants to take over. Thus we have to disable the latter. 1120 */ 1121 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1122 kvm_has_pit_state2())) { 1123 hpet = qdev_try_new(TYPE_HPET); 1124 if (!hpet) { 1125 error_report("couldn't create HPET device"); 1126 exit(1); 1127 } 1128 /* 1129 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1130 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1131 * IRQ2. 1132 */ 1133 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1134 HPET_INTCAP, NULL); 1135 if (!compat) { 1136 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1137 } 1138 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1139 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1140 1141 for (i = 0; i < GSI_NUM_PINS; i++) { 1142 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1143 } 1144 pit_isa_irq = -1; 1145 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1146 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1147 } 1148 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1149 1150 qemu_register_boot_set(pc_boot_set, *rtc_state); 1151 1152 if (!xen_enabled() && pcms->pit_enabled) { 1153 if (kvm_pit_in_kernel()) { 1154 pit = kvm_pit_init(isa_bus, 0x40); 1155 } else { 1156 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1157 } 1158 if (hpet) { 1159 /* connect PIT to output control line of the HPET */ 1160 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1161 } 1162 pcspk_init(pcms->pcspk, isa_bus, pit); 1163 } 1164 1165 i8257_dma_init(isa_bus, 0); 1166 1167 /* Super I/O */ 1168 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1169 } 1170 1171 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1172 { 1173 int i; 1174 1175 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1176 for (i = 0; i < nb_nics; i++) { 1177 NICInfo *nd = &nd_table[i]; 1178 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1179 1180 if (g_str_equal(model, "ne2k_isa")) { 1181 pc_init_ne2k_isa(isa_bus, nd); 1182 } else { 1183 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1184 } 1185 } 1186 rom_reset_order_override(); 1187 } 1188 1189 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1190 { 1191 qemu_irq *i8259; 1192 1193 if (kvm_pic_in_kernel()) { 1194 i8259 = kvm_i8259_init(isa_bus); 1195 } else if (xen_enabled()) { 1196 i8259 = xen_interrupt_controller_init(); 1197 } else { 1198 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1199 } 1200 1201 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1202 i8259_irqs[i] = i8259[i]; 1203 } 1204 1205 g_free(i8259); 1206 } 1207 1208 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1209 Error **errp) 1210 { 1211 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1212 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1213 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1214 const MachineState *ms = MACHINE(hotplug_dev); 1215 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1216 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1217 Error *local_err = NULL; 1218 1219 /* 1220 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1221 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1222 * addition to cover this case. 1223 */ 1224 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1225 error_setg(errp, 1226 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1227 return; 1228 } 1229 1230 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1231 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1232 return; 1233 } 1234 1235 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1236 if (local_err) { 1237 error_propagate(errp, local_err); 1238 return; 1239 } 1240 1241 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1242 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1243 } 1244 1245 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1246 DeviceState *dev, Error **errp) 1247 { 1248 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1249 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1250 MachineState *ms = MACHINE(hotplug_dev); 1251 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1252 1253 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1254 1255 if (is_nvdimm) { 1256 nvdimm_plug(ms->nvdimms_state); 1257 } 1258 1259 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1260 } 1261 1262 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1263 DeviceState *dev, Error **errp) 1264 { 1265 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1266 1267 /* 1268 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1269 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1270 * addition to cover this case. 1271 */ 1272 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1273 error_setg(errp, 1274 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1275 return; 1276 } 1277 1278 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1279 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1280 return; 1281 } 1282 1283 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1284 errp); 1285 } 1286 1287 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1288 DeviceState *dev, Error **errp) 1289 { 1290 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1291 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1292 Error *local_err = NULL; 1293 1294 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1295 if (local_err) { 1296 goto out; 1297 } 1298 1299 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1300 qdev_unrealize(dev); 1301 out: 1302 error_propagate(errp, local_err); 1303 } 1304 1305 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1306 DeviceState *dev, Error **errp) 1307 { 1308 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1309 Error *local_err = NULL; 1310 1311 if (!hotplug_dev2 && dev->hotplugged) { 1312 /* 1313 * Without a bus hotplug handler, we cannot control the plug/unplug 1314 * order. We should never reach this point when hotplugging on x86, 1315 * however, better add a safety net. 1316 */ 1317 error_setg(errp, "hotplug of virtio based memory devices not supported" 1318 " on this bus."); 1319 return; 1320 } 1321 /* 1322 * First, see if we can plug this memory device at all. If that 1323 * succeeds, branch of to the actual hotplug handler. 1324 */ 1325 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1326 &local_err); 1327 if (!local_err && hotplug_dev2) { 1328 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1329 } 1330 error_propagate(errp, local_err); 1331 } 1332 1333 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1334 DeviceState *dev, Error **errp) 1335 { 1336 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1337 Error *local_err = NULL; 1338 1339 /* 1340 * Plug the memory device first and then branch off to the actual 1341 * hotplug handler. If that one fails, we can easily undo the memory 1342 * device bits. 1343 */ 1344 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1345 if (hotplug_dev2) { 1346 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1347 if (local_err) { 1348 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1349 } 1350 } 1351 error_propagate(errp, local_err); 1352 } 1353 1354 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1355 DeviceState *dev, Error **errp) 1356 { 1357 /* We don't support hot unplug of virtio based memory devices */ 1358 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1359 } 1360 1361 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 /* We don't support hot unplug of virtio based memory devices */ 1365 } 1366 1367 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1371 pc_memory_pre_plug(hotplug_dev, dev, errp); 1372 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1373 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1374 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1375 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1376 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1377 } 1378 } 1379 1380 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1381 DeviceState *dev, Error **errp) 1382 { 1383 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1384 pc_memory_plug(hotplug_dev, dev, errp); 1385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1386 x86_cpu_plug(hotplug_dev, dev, errp); 1387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1388 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1389 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1390 } 1391 } 1392 1393 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1394 DeviceState *dev, Error **errp) 1395 { 1396 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1397 pc_memory_unplug_request(hotplug_dev, dev, errp); 1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1399 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1400 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1401 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1402 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1403 } else { 1404 error_setg(errp, "acpi: device unplug request for not supported device" 1405 " type: %s", object_get_typename(OBJECT(dev))); 1406 } 1407 } 1408 1409 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1410 DeviceState *dev, Error **errp) 1411 { 1412 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1413 pc_memory_unplug(hotplug_dev, dev, errp); 1414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1415 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1416 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1417 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1418 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1419 } else { 1420 error_setg(errp, "acpi: device unplug for not supported device" 1421 " type: %s", object_get_typename(OBJECT(dev))); 1422 } 1423 } 1424 1425 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1426 DeviceState *dev) 1427 { 1428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1429 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1430 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1431 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1432 return HOTPLUG_HANDLER(machine); 1433 } 1434 1435 return NULL; 1436 } 1437 1438 static void 1439 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1440 const char *name, void *opaque, 1441 Error **errp) 1442 { 1443 MachineState *ms = MACHINE(obj); 1444 int64_t value = 0; 1445 1446 if (ms->device_memory) { 1447 value = memory_region_size(&ms->device_memory->mr); 1448 } 1449 1450 visit_type_int(v, name, &value, errp); 1451 } 1452 1453 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1454 void *opaque, Error **errp) 1455 { 1456 PCMachineState *pcms = PC_MACHINE(obj); 1457 OnOffAuto vmport = pcms->vmport; 1458 1459 visit_type_OnOffAuto(v, name, &vmport, errp); 1460 } 1461 1462 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1463 void *opaque, Error **errp) 1464 { 1465 PCMachineState *pcms = PC_MACHINE(obj); 1466 1467 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1468 } 1469 1470 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1471 { 1472 PCMachineState *pcms = PC_MACHINE(obj); 1473 1474 return pcms->smbus_enabled; 1475 } 1476 1477 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1478 { 1479 PCMachineState *pcms = PC_MACHINE(obj); 1480 1481 pcms->smbus_enabled = value; 1482 } 1483 1484 static bool pc_machine_get_sata(Object *obj, Error **errp) 1485 { 1486 PCMachineState *pcms = PC_MACHINE(obj); 1487 1488 return pcms->sata_enabled; 1489 } 1490 1491 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1492 { 1493 PCMachineState *pcms = PC_MACHINE(obj); 1494 1495 pcms->sata_enabled = value; 1496 } 1497 1498 static bool pc_machine_get_pit(Object *obj, Error **errp) 1499 { 1500 PCMachineState *pcms = PC_MACHINE(obj); 1501 1502 return pcms->pit_enabled; 1503 } 1504 1505 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 pcms->pit_enabled = value; 1510 } 1511 1512 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 return pcms->hpet_enabled; 1517 } 1518 1519 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 pcms->hpet_enabled = value; 1524 } 1525 1526 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1527 const char *name, void *opaque, 1528 Error **errp) 1529 { 1530 PCMachineState *pcms = PC_MACHINE(obj); 1531 uint64_t value = pcms->max_ram_below_4g; 1532 1533 visit_type_size(v, name, &value, errp); 1534 } 1535 1536 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1537 const char *name, void *opaque, 1538 Error **errp) 1539 { 1540 PCMachineState *pcms = PC_MACHINE(obj); 1541 uint64_t value; 1542 1543 if (!visit_type_size(v, name, &value, errp)) { 1544 return; 1545 } 1546 if (value > 4 * GiB) { 1547 error_setg(errp, 1548 "Machine option 'max-ram-below-4g=%"PRIu64 1549 "' expects size less than or equal to 4G", value); 1550 return; 1551 } 1552 1553 if (value < 1 * MiB) { 1554 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1555 "BIOS may not work with less than 1MiB", value); 1556 } 1557 1558 pcms->max_ram_below_4g = value; 1559 } 1560 1561 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1562 const char *name, void *opaque, 1563 Error **errp) 1564 { 1565 PCMachineState *pcms = PC_MACHINE(obj); 1566 uint64_t value = pcms->max_fw_size; 1567 1568 visit_type_size(v, name, &value, errp); 1569 } 1570 1571 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1572 const char *name, void *opaque, 1573 Error **errp) 1574 { 1575 PCMachineState *pcms = PC_MACHINE(obj); 1576 Error *error = NULL; 1577 uint64_t value; 1578 1579 visit_type_size(v, name, &value, &error); 1580 if (error) { 1581 error_propagate(errp, error); 1582 return; 1583 } 1584 1585 /* 1586 * We don't have a theoretically justifiable exact lower bound on the base 1587 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1588 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1589 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1590 * size. 1591 */ 1592 if (value > 16 * MiB) { 1593 error_setg(errp, 1594 "User specified max allowed firmware size %" PRIu64 " is " 1595 "greater than 16MiB. If combined firwmare size exceeds " 1596 "16MiB the system may not boot, or experience intermittent" 1597 "stability issues.", 1598 value); 1599 return; 1600 } 1601 1602 pcms->max_fw_size = value; 1603 } 1604 1605 1606 static void pc_machine_initfn(Object *obj) 1607 { 1608 PCMachineState *pcms = PC_MACHINE(obj); 1609 1610 #ifdef CONFIG_VMPORT 1611 pcms->vmport = ON_OFF_AUTO_AUTO; 1612 #else 1613 pcms->vmport = ON_OFF_AUTO_OFF; 1614 #endif /* CONFIG_VMPORT */ 1615 pcms->max_ram_below_4g = 0; /* use default */ 1616 /* acpi build is enabled by default if machine supports it */ 1617 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1618 pcms->smbus_enabled = true; 1619 pcms->sata_enabled = true; 1620 pcms->pit_enabled = true; 1621 pcms->max_fw_size = 8 * MiB; 1622 #ifdef CONFIG_HPET 1623 pcms->hpet_enabled = true; 1624 #endif 1625 1626 pc_system_flash_create(pcms); 1627 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1628 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1629 OBJECT(pcms->pcspk), "audiodev"); 1630 } 1631 1632 static void pc_machine_reset(MachineState *machine) 1633 { 1634 CPUState *cs; 1635 X86CPU *cpu; 1636 1637 qemu_devices_reset(); 1638 1639 /* Reset APIC after devices have been reset to cancel 1640 * any changes that qemu_devices_reset() might have done. 1641 */ 1642 CPU_FOREACH(cs) { 1643 cpu = X86_CPU(cs); 1644 1645 if (cpu->apic_state) { 1646 device_legacy_reset(cpu->apic_state); 1647 } 1648 } 1649 } 1650 1651 static void pc_machine_wakeup(MachineState *machine) 1652 { 1653 cpu_synchronize_all_states(); 1654 pc_machine_reset(machine); 1655 cpu_synchronize_all_post_reset(); 1656 } 1657 1658 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1659 { 1660 X86IOMMUState *iommu = x86_iommu_get_default(); 1661 IntelIOMMUState *intel_iommu; 1662 1663 if (iommu && 1664 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1665 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1666 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1667 if (!intel_iommu->caching_mode) { 1668 error_setg(errp, "Device assignment is not allowed without " 1669 "enabling caching-mode=on for Intel IOMMU."); 1670 return false; 1671 } 1672 } 1673 1674 return true; 1675 } 1676 1677 static void pc_machine_class_init(ObjectClass *oc, void *data) 1678 { 1679 MachineClass *mc = MACHINE_CLASS(oc); 1680 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1681 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1682 1683 pcmc->pci_enabled = true; 1684 pcmc->has_acpi_build = true; 1685 pcmc->rsdp_in_ram = true; 1686 pcmc->smbios_defaults = true; 1687 pcmc->smbios_uuid_encoded = true; 1688 pcmc->gigabyte_align = true; 1689 pcmc->has_reserved_memory = true; 1690 pcmc->kvmclock_enabled = true; 1691 pcmc->enforce_aligned_dimm = true; 1692 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1693 * to be used at the moment, 32K should be enough for a while. */ 1694 pcmc->acpi_data_size = 0x20000 + 0x8000; 1695 pcmc->linuxboot_dma_enabled = true; 1696 pcmc->pvh_enabled = true; 1697 pcmc->kvmclock_create_always = true; 1698 assert(!mc->get_hotplug_handler); 1699 mc->get_hotplug_handler = pc_get_hotplug_handler; 1700 mc->hotplug_allowed = pc_hotplug_allowed; 1701 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1702 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1703 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1704 mc->auto_enable_numa_with_memhp = true; 1705 mc->auto_enable_numa_with_memdev = true; 1706 mc->has_hotpluggable_cpus = true; 1707 mc->default_boot_order = "cad"; 1708 mc->smp_parse = pc_smp_parse; 1709 mc->block_default_type = IF_IDE; 1710 mc->max_cpus = 255; 1711 mc->reset = pc_machine_reset; 1712 mc->wakeup = pc_machine_wakeup; 1713 hc->pre_plug = pc_machine_device_pre_plug_cb; 1714 hc->plug = pc_machine_device_plug_cb; 1715 hc->unplug_request = pc_machine_device_unplug_request_cb; 1716 hc->unplug = pc_machine_device_unplug_cb; 1717 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1718 mc->nvdimm_supported = true; 1719 mc->default_ram_id = "pc.ram"; 1720 1721 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1722 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1723 NULL, NULL); 1724 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1725 "Maximum ram below the 4G boundary (32bit boundary)"); 1726 1727 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1728 pc_machine_get_device_memory_region_size, NULL, 1729 NULL, NULL); 1730 1731 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1732 pc_machine_get_vmport, pc_machine_set_vmport, 1733 NULL, NULL); 1734 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1735 "Enable vmport (pc & q35)"); 1736 1737 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1738 pc_machine_get_smbus, pc_machine_set_smbus); 1739 1740 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1741 pc_machine_get_sata, pc_machine_set_sata); 1742 1743 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1744 pc_machine_get_pit, pc_machine_set_pit); 1745 1746 object_class_property_add_bool(oc, "hpet", 1747 pc_machine_get_hpet, pc_machine_set_hpet); 1748 1749 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1750 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1751 NULL, NULL); 1752 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1753 "Maximum combined firmware size"); 1754 } 1755 1756 static const TypeInfo pc_machine_info = { 1757 .name = TYPE_PC_MACHINE, 1758 .parent = TYPE_X86_MACHINE, 1759 .abstract = true, 1760 .instance_size = sizeof(PCMachineState), 1761 .instance_init = pc_machine_initfn, 1762 .class_size = sizeof(PCMachineClass), 1763 .class_init = pc_machine_class_init, 1764 .interfaces = (InterfaceInfo[]) { 1765 { TYPE_HOTPLUG_HANDLER }, 1766 { } 1767 }, 1768 }; 1769 1770 static void pc_machine_register_types(void) 1771 { 1772 type_register_static(&pc_machine_info); 1773 } 1774 1775 type_init(pc_machine_register_types) 1776