1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "exec/address-spaces.h" 69 #include "sysemu/arch_init.h" 70 #include "qemu/bitmap.h" 71 #include "qemu/config-file.h" 72 #include "qemu/error-report.h" 73 #include "qemu/option.h" 74 #include "qemu/cutils.h" 75 #include "hw/acpi/acpi.h" 76 #include "hw/acpi/cpu_hotplug.h" 77 #include "acpi-build.h" 78 #include "hw/mem/pc-dimm.h" 79 #include "hw/mem/nvdimm.h" 80 #include "qapi/error.h" 81 #include "qapi/qapi-visit-common.h" 82 #include "qapi/visitor.h" 83 #include "hw/core/cpu.h" 84 #include "hw/usb.h" 85 #include "hw/i386/intel_iommu.h" 86 #include "hw/net/ne2000-isa.h" 87 #include "standard-headers/asm-x86/bootparam.h" 88 #include "hw/virtio/virtio-pmem-pci.h" 89 #include "hw/virtio/virtio-mem-pci.h" 90 #include "hw/mem/memory-device.h" 91 #include "sysemu/replay.h" 92 #include "qapi/qmp/qerror.h" 93 #include "e820_memory_layout.h" 94 #include "fw_cfg.h" 95 #include "trace.h" 96 #include CONFIG_DEVICES 97 98 GlobalProperty pc_compat_6_0[] = {}; 99 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 100 101 GlobalProperty pc_compat_5_2[] = { 102 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 103 }; 104 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 105 106 GlobalProperty pc_compat_5_1[] = { 107 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 108 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 109 }; 110 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 111 112 GlobalProperty pc_compat_5_0[] = { 113 }; 114 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 115 116 GlobalProperty pc_compat_4_2[] = { 117 { "mch", "smbase-smram", "off" }, 118 }; 119 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 120 121 GlobalProperty pc_compat_4_1[] = {}; 122 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 123 124 GlobalProperty pc_compat_4_0[] = {}; 125 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 126 127 GlobalProperty pc_compat_3_1[] = { 128 { "intel-iommu", "dma-drain", "off" }, 129 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 130 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 131 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 132 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 133 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 134 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 135 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 136 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 137 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 138 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 139 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 140 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 141 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 142 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 143 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 144 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 146 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 147 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 148 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 149 }; 150 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 151 152 GlobalProperty pc_compat_3_0[] = { 153 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 154 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 155 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 156 }; 157 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 158 159 GlobalProperty pc_compat_2_12[] = { 160 { TYPE_X86_CPU, "legacy-cache", "on" }, 161 { TYPE_X86_CPU, "topoext", "off" }, 162 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 163 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 164 }; 165 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 166 167 GlobalProperty pc_compat_2_11[] = { 168 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 169 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 170 }; 171 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 172 173 GlobalProperty pc_compat_2_10[] = { 174 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 175 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 176 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 177 }; 178 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 179 180 GlobalProperty pc_compat_2_9[] = { 181 { "mch", "extended-tseg-mbytes", "0" }, 182 }; 183 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 184 185 GlobalProperty pc_compat_2_8[] = { 186 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 187 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 188 { "ICH9-LPC", "x-smi-broadcast", "off" }, 189 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 190 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 191 }; 192 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 193 194 GlobalProperty pc_compat_2_7[] = { 195 { TYPE_X86_CPU, "l3-cache", "off" }, 196 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 197 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 198 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 199 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 200 { "isa-pcspk", "migrate", "off" }, 201 }; 202 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 203 204 GlobalProperty pc_compat_2_6[] = { 205 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 206 { "vmxnet3", "romfile", "" }, 207 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 208 { "apic-common", "legacy-instance-id", "on", } 209 }; 210 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 211 212 GlobalProperty pc_compat_2_5[] = {}; 213 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 214 215 GlobalProperty pc_compat_2_4[] = { 216 PC_CPU_MODEL_IDS("2.4.0") 217 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 218 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 219 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 220 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 221 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 222 { TYPE_X86_CPU, "check", "off" }, 223 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 224 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 225 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 226 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 227 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 228 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 229 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 230 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 231 }; 232 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 233 234 GlobalProperty pc_compat_2_3[] = { 235 PC_CPU_MODEL_IDS("2.3.0") 236 { TYPE_X86_CPU, "arat", "off" }, 237 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 238 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 239 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 240 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 241 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 242 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 243 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 244 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 255 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 256 }; 257 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 258 259 GlobalProperty pc_compat_2_2[] = { 260 PC_CPU_MODEL_IDS("2.2.0") 261 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 276 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 277 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 279 }; 280 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 281 282 GlobalProperty pc_compat_2_1[] = { 283 PC_CPU_MODEL_IDS("2.1.0") 284 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 285 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 286 }; 287 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 288 289 GlobalProperty pc_compat_2_0[] = { 290 PC_CPU_MODEL_IDS("2.0.0") 291 { "virtio-scsi-pci", "any_layout", "off" }, 292 { "PIIX4_PM", "memory-hotplug-support", "off" }, 293 { "apic", "version", "0x11" }, 294 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 295 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 296 { "pci-serial", "prog_if", "0" }, 297 { "pci-serial-2x", "prog_if", "0" }, 298 { "pci-serial-4x", "prog_if", "0" }, 299 { "virtio-net-pci", "guest_announce", "off" }, 300 { "ICH9-LPC", "memory-hotplug-support", "off" }, 301 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 302 { "ioh3420", COMPAT_PROP_PCP, "off" }, 303 }; 304 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 305 306 GlobalProperty pc_compat_1_7[] = { 307 PC_CPU_MODEL_IDS("1.7.0") 308 { TYPE_USB_DEVICE, "msos-desc", "no" }, 309 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 310 { "hpet", HPET_INTCAP, "4" }, 311 }; 312 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 313 314 GlobalProperty pc_compat_1_6[] = { 315 PC_CPU_MODEL_IDS("1.6.0") 316 { "e1000", "mitigation", "off" }, 317 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 318 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 319 { "i440FX-pcihost", "short_root_bus", "1" }, 320 { "q35-pcihost", "short_root_bus", "1" }, 321 }; 322 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 323 324 GlobalProperty pc_compat_1_5[] = { 325 PC_CPU_MODEL_IDS("1.5.0") 326 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 327 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 328 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 329 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 330 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 331 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 332 { "virtio-net-pci", "any_layout", "off" }, 333 { TYPE_X86_CPU, "pmu", "on" }, 334 { "i440FX-pcihost", "short_root_bus", "0" }, 335 { "q35-pcihost", "short_root_bus", "0" }, 336 }; 337 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 338 339 GlobalProperty pc_compat_1_4[] = { 340 PC_CPU_MODEL_IDS("1.4.0") 341 { "scsi-hd", "discard_granularity", "0" }, 342 { "scsi-cd", "discard_granularity", "0" }, 343 { "ide-hd", "discard_granularity", "0" }, 344 { "ide-cd", "discard_granularity", "0" }, 345 { "virtio-blk-pci", "discard_granularity", "0" }, 346 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 347 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 348 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 349 { "e1000", "romfile", "pxe-e1000.rom" }, 350 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 351 { "pcnet", "romfile", "pxe-pcnet.rom" }, 352 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 353 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 354 { "486-" TYPE_X86_CPU, "model", "0" }, 355 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 356 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 357 }; 358 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 359 360 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 361 { 362 GSIState *s; 363 364 s = g_new0(GSIState, 1); 365 if (kvm_ioapic_in_kernel()) { 366 kvm_pc_setup_irq_routing(pci_enabled); 367 } 368 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 369 370 return s; 371 } 372 373 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 374 unsigned size) 375 { 376 } 377 378 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 379 { 380 return 0xffffffffffffffffULL; 381 } 382 383 /* MSDOS compatibility mode FPU exception support */ 384 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 385 unsigned size) 386 { 387 if (tcg_enabled()) { 388 cpu_set_ignne(); 389 } 390 } 391 392 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 393 { 394 return 0xffffffffffffffffULL; 395 } 396 397 /* PC cmos mappings */ 398 399 #define REG_EQUIPMENT_BYTE 0x14 400 401 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 402 int16_t cylinders, int8_t heads, int8_t sectors) 403 { 404 rtc_set_memory(s, type_ofs, 47); 405 rtc_set_memory(s, info_ofs, cylinders); 406 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 407 rtc_set_memory(s, info_ofs + 2, heads); 408 rtc_set_memory(s, info_ofs + 3, 0xff); 409 rtc_set_memory(s, info_ofs + 4, 0xff); 410 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 411 rtc_set_memory(s, info_ofs + 6, cylinders); 412 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 413 rtc_set_memory(s, info_ofs + 8, sectors); 414 } 415 416 /* convert boot_device letter to something recognizable by the bios */ 417 static int boot_device2nibble(char boot_device) 418 { 419 switch(boot_device) { 420 case 'a': 421 case 'b': 422 return 0x01; /* floppy boot */ 423 case 'c': 424 return 0x02; /* hard drive boot */ 425 case 'd': 426 return 0x03; /* CD-ROM boot */ 427 case 'n': 428 return 0x04; /* Network boot */ 429 } 430 return 0; 431 } 432 433 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 434 { 435 #define PC_MAX_BOOT_DEVICES 3 436 int nbds, bds[3] = { 0, }; 437 int i; 438 439 nbds = strlen(boot_device); 440 if (nbds > PC_MAX_BOOT_DEVICES) { 441 error_setg(errp, "Too many boot devices for PC"); 442 return; 443 } 444 for (i = 0; i < nbds; i++) { 445 bds[i] = boot_device2nibble(boot_device[i]); 446 if (bds[i] == 0) { 447 error_setg(errp, "Invalid boot device for PC: '%c'", 448 boot_device[i]); 449 return; 450 } 451 } 452 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 453 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 454 } 455 456 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 457 { 458 set_boot_dev(opaque, boot_device, errp); 459 } 460 461 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 462 { 463 int val, nb, i; 464 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 465 FLOPPY_DRIVE_TYPE_NONE }; 466 467 /* floppy type */ 468 if (floppy) { 469 for (i = 0; i < 2; i++) { 470 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 471 } 472 } 473 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 474 cmos_get_fd_drive_type(fd_type[1]); 475 rtc_set_memory(rtc_state, 0x10, val); 476 477 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 478 nb = 0; 479 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 480 nb++; 481 } 482 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 483 nb++; 484 } 485 switch (nb) { 486 case 0: 487 break; 488 case 1: 489 val |= 0x01; /* 1 drive, ready for boot */ 490 break; 491 case 2: 492 val |= 0x41; /* 2 drives, ready for boot */ 493 break; 494 } 495 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 496 } 497 498 typedef struct pc_cmos_init_late_arg { 499 ISADevice *rtc_state; 500 BusState *idebus[2]; 501 } pc_cmos_init_late_arg; 502 503 typedef struct check_fdc_state { 504 ISADevice *floppy; 505 bool multiple; 506 } CheckFdcState; 507 508 static int check_fdc(Object *obj, void *opaque) 509 { 510 CheckFdcState *state = opaque; 511 Object *fdc; 512 uint32_t iobase; 513 Error *local_err = NULL; 514 515 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 516 if (!fdc) { 517 return 0; 518 } 519 520 iobase = object_property_get_uint(obj, "iobase", &local_err); 521 if (local_err || iobase != 0x3f0) { 522 error_free(local_err); 523 return 0; 524 } 525 526 if (state->floppy) { 527 state->multiple = true; 528 } else { 529 state->floppy = ISA_DEVICE(obj); 530 } 531 return 0; 532 } 533 534 static const char * const fdc_container_path[] = { 535 "/unattached", "/peripheral", "/peripheral-anon" 536 }; 537 538 /* 539 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 540 * and ACPI objects. 541 */ 542 ISADevice *pc_find_fdc0(void) 543 { 544 int i; 545 Object *container; 546 CheckFdcState state = { 0 }; 547 548 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 549 container = container_get(qdev_get_machine(), fdc_container_path[i]); 550 object_child_foreach(container, check_fdc, &state); 551 } 552 553 if (state.multiple) { 554 warn_report("multiple floppy disk controllers with " 555 "iobase=0x3f0 have been found"); 556 error_printf("the one being picked for CMOS setup might not reflect " 557 "your intent"); 558 } 559 560 return state.floppy; 561 } 562 563 static void pc_cmos_init_late(void *opaque) 564 { 565 pc_cmos_init_late_arg *arg = opaque; 566 ISADevice *s = arg->rtc_state; 567 int16_t cylinders; 568 int8_t heads, sectors; 569 int val; 570 int i, trans; 571 572 val = 0; 573 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 574 &cylinders, &heads, §ors) >= 0) { 575 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 576 val |= 0xf0; 577 } 578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 579 &cylinders, &heads, §ors) >= 0) { 580 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 581 val |= 0x0f; 582 } 583 rtc_set_memory(s, 0x12, val); 584 585 val = 0; 586 for (i = 0; i < 4; i++) { 587 /* NOTE: ide_get_geometry() returns the physical 588 geometry. It is always such that: 1 <= sects <= 63, 1 589 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 590 geometry can be different if a translation is done. */ 591 if (arg->idebus[i / 2] && 592 ide_get_geometry(arg->idebus[i / 2], i % 2, 593 &cylinders, &heads, §ors) >= 0) { 594 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 595 assert((trans & ~3) == 0); 596 val |= trans << (i * 2); 597 } 598 } 599 rtc_set_memory(s, 0x39, val); 600 601 pc_cmos_init_floppy(s, pc_find_fdc0()); 602 603 qemu_unregister_reset(pc_cmos_init_late, opaque); 604 } 605 606 void pc_cmos_init(PCMachineState *pcms, 607 BusState *idebus0, BusState *idebus1, 608 ISADevice *s) 609 { 610 int val; 611 static pc_cmos_init_late_arg arg; 612 X86MachineState *x86ms = X86_MACHINE(pcms); 613 614 /* various important CMOS locations needed by PC/Bochs bios */ 615 616 /* memory size */ 617 /* base memory (first MiB) */ 618 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 619 rtc_set_memory(s, 0x15, val); 620 rtc_set_memory(s, 0x16, val >> 8); 621 /* extended memory (next 64MiB) */ 622 if (x86ms->below_4g_mem_size > 1 * MiB) { 623 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 624 } else { 625 val = 0; 626 } 627 if (val > 65535) 628 val = 65535; 629 rtc_set_memory(s, 0x17, val); 630 rtc_set_memory(s, 0x18, val >> 8); 631 rtc_set_memory(s, 0x30, val); 632 rtc_set_memory(s, 0x31, val >> 8); 633 /* memory between 16MiB and 4GiB */ 634 if (x86ms->below_4g_mem_size > 16 * MiB) { 635 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 636 } else { 637 val = 0; 638 } 639 if (val > 65535) 640 val = 65535; 641 rtc_set_memory(s, 0x34, val); 642 rtc_set_memory(s, 0x35, val >> 8); 643 /* memory above 4GiB */ 644 val = x86ms->above_4g_mem_size / 65536; 645 rtc_set_memory(s, 0x5b, val); 646 rtc_set_memory(s, 0x5c, val >> 8); 647 rtc_set_memory(s, 0x5d, val >> 16); 648 649 object_property_add_link(OBJECT(pcms), "rtc_state", 650 TYPE_ISA_DEVICE, 651 (Object **)&x86ms->rtc, 652 object_property_allow_set_link, 653 OBJ_PROP_LINK_STRONG); 654 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 655 &error_abort); 656 657 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 658 659 val = 0; 660 val |= 0x02; /* FPU is there */ 661 val |= 0x04; /* PS/2 mouse installed */ 662 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 663 664 /* hard drives and FDC */ 665 arg.rtc_state = s; 666 arg.idebus[0] = idebus0; 667 arg.idebus[1] = idebus1; 668 qemu_register_reset(pc_cmos_init_late, &arg); 669 } 670 671 static void handle_a20_line_change(void *opaque, int irq, int level) 672 { 673 X86CPU *cpu = opaque; 674 675 /* XXX: send to all CPUs ? */ 676 /* XXX: add logic to handle multiple A20 line sources */ 677 x86_cpu_set_a20(cpu, level); 678 } 679 680 #define NE2000_NB_MAX 6 681 682 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 683 0x280, 0x380 }; 684 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 685 686 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 687 { 688 static int nb_ne2k = 0; 689 690 if (nb_ne2k == NE2000_NB_MAX) 691 return; 692 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 693 ne2000_irq[nb_ne2k], nd); 694 nb_ne2k++; 695 } 696 697 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 698 { 699 X86CPU *cpu = opaque; 700 701 if (level) { 702 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 703 } 704 } 705 706 /* 707 * This function is very similar to smp_parse() 708 * in hw/core/machine.c but includes CPU die support. 709 */ 710 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 711 { 712 X86MachineState *x86ms = X86_MACHINE(ms); 713 714 if (opts) { 715 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 716 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 717 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 718 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 719 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 720 721 /* compute missing values, prefer sockets over cores over threads */ 722 if (cpus == 0 || sockets == 0) { 723 cores = cores > 0 ? cores : 1; 724 threads = threads > 0 ? threads : 1; 725 if (cpus == 0) { 726 sockets = sockets > 0 ? sockets : 1; 727 cpus = cores * threads * dies * sockets; 728 } else { 729 ms->smp.max_cpus = 730 qemu_opt_get_number(opts, "maxcpus", cpus); 731 sockets = ms->smp.max_cpus / (cores * threads * dies); 732 } 733 } else if (cores == 0) { 734 threads = threads > 0 ? threads : 1; 735 cores = cpus / (sockets * dies * threads); 736 cores = cores > 0 ? cores : 1; 737 } else if (threads == 0) { 738 threads = cpus / (cores * dies * sockets); 739 threads = threads > 0 ? threads : 1; 740 } else if (sockets * dies * cores * threads < cpus) { 741 error_report("cpu topology: " 742 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 743 "smp_cpus (%u)", 744 sockets, dies, cores, threads, cpus); 745 exit(1); 746 } 747 748 ms->smp.max_cpus = 749 qemu_opt_get_number(opts, "maxcpus", cpus); 750 751 if (ms->smp.max_cpus < cpus) { 752 error_report("maxcpus must be equal to or greater than smp"); 753 exit(1); 754 } 755 756 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 757 error_report("Invalid CPU topology deprecated: " 758 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 759 "!= maxcpus (%u)", 760 sockets, dies, cores, threads, 761 ms->smp.max_cpus); 762 exit(1); 763 } 764 765 ms->smp.cpus = cpus; 766 ms->smp.cores = cores; 767 ms->smp.threads = threads; 768 ms->smp.sockets = sockets; 769 x86ms->smp_dies = dies; 770 } 771 772 if (ms->smp.cpus > 1) { 773 Error *blocker = NULL; 774 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 775 replay_add_blocker(blocker); 776 } 777 } 778 779 static 780 void pc_machine_done(Notifier *notifier, void *data) 781 { 782 PCMachineState *pcms = container_of(notifier, 783 PCMachineState, machine_done); 784 X86MachineState *x86ms = X86_MACHINE(pcms); 785 786 /* set the number of CPUs */ 787 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 788 789 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 790 791 acpi_setup(); 792 if (x86ms->fw_cfg) { 793 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 794 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 795 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 796 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 797 } 798 799 800 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 801 !kvm_irqchip_in_kernel()) { 802 error_report("current -smp configuration requires kernel " 803 "irqchip support."); 804 exit(EXIT_FAILURE); 805 } 806 } 807 808 void pc_guest_info_init(PCMachineState *pcms) 809 { 810 int i; 811 MachineState *ms = MACHINE(pcms); 812 X86MachineState *x86ms = X86_MACHINE(pcms); 813 814 x86ms->apic_xrupt_override = true; 815 pcms->numa_nodes = ms->numa_state->num_nodes; 816 pcms->node_mem = g_malloc0(pcms->numa_nodes * 817 sizeof *pcms->node_mem); 818 for (i = 0; i < ms->numa_state->num_nodes; i++) { 819 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 820 } 821 822 pcms->machine_done.notify = pc_machine_done; 823 qemu_add_machine_init_done_notifier(&pcms->machine_done); 824 } 825 826 /* setup pci memory address space mapping into system address space */ 827 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 828 MemoryRegion *pci_address_space) 829 { 830 /* Set to lower priority than RAM */ 831 memory_region_add_subregion_overlap(system_memory, 0x0, 832 pci_address_space, -1); 833 } 834 835 void xen_load_linux(PCMachineState *pcms) 836 { 837 int i; 838 FWCfgState *fw_cfg; 839 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 840 X86MachineState *x86ms = X86_MACHINE(pcms); 841 842 assert(MACHINE(pcms)->kernel_filename != NULL); 843 844 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 845 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 846 rom_set_fw(fw_cfg); 847 848 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 849 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 850 for (i = 0; i < nb_option_roms; i++) { 851 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 852 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 853 !strcmp(option_rom[i].name, "pvh.bin") || 854 !strcmp(option_rom[i].name, "multiboot.bin")); 855 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 856 } 857 x86ms->fw_cfg = fw_cfg; 858 } 859 860 void pc_memory_init(PCMachineState *pcms, 861 MemoryRegion *system_memory, 862 MemoryRegion *rom_memory, 863 MemoryRegion **ram_memory) 864 { 865 int linux_boot, i; 866 MemoryRegion *option_rom_mr; 867 MemoryRegion *ram_below_4g, *ram_above_4g; 868 FWCfgState *fw_cfg; 869 MachineState *machine = MACHINE(pcms); 870 MachineClass *mc = MACHINE_GET_CLASS(machine); 871 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 872 X86MachineState *x86ms = X86_MACHINE(pcms); 873 874 assert(machine->ram_size == x86ms->below_4g_mem_size + 875 x86ms->above_4g_mem_size); 876 877 linux_boot = (machine->kernel_filename != NULL); 878 879 /* 880 * Split single memory region and use aliases to address portions of it, 881 * done for backwards compatibility with older qemus. 882 */ 883 *ram_memory = machine->ram; 884 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 885 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 886 0, x86ms->below_4g_mem_size); 887 memory_region_add_subregion(system_memory, 0, ram_below_4g); 888 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 889 if (x86ms->above_4g_mem_size > 0) { 890 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 891 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 892 machine->ram, 893 x86ms->below_4g_mem_size, 894 x86ms->above_4g_mem_size); 895 memory_region_add_subregion(system_memory, 0x100000000ULL, 896 ram_above_4g); 897 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 898 } 899 900 if (!pcmc->has_reserved_memory && 901 (machine->ram_slots || 902 (machine->maxram_size > machine->ram_size))) { 903 904 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 905 mc->name); 906 exit(EXIT_FAILURE); 907 } 908 909 /* always allocate the device memory information */ 910 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 911 912 /* initialize device memory address space */ 913 if (pcmc->has_reserved_memory && 914 (machine->ram_size < machine->maxram_size)) { 915 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 916 917 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 918 error_report("unsupported amount of memory slots: %"PRIu64, 919 machine->ram_slots); 920 exit(EXIT_FAILURE); 921 } 922 923 if (QEMU_ALIGN_UP(machine->maxram_size, 924 TARGET_PAGE_SIZE) != machine->maxram_size) { 925 error_report("maximum memory size must by aligned to multiple of " 926 "%d bytes", TARGET_PAGE_SIZE); 927 exit(EXIT_FAILURE); 928 } 929 930 machine->device_memory->base = 931 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 932 933 if (pcmc->enforce_aligned_dimm) { 934 /* size device region assuming 1G page max alignment per slot */ 935 device_mem_size += (1 * GiB) * machine->ram_slots; 936 } 937 938 if ((machine->device_memory->base + device_mem_size) < 939 device_mem_size) { 940 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 941 machine->maxram_size); 942 exit(EXIT_FAILURE); 943 } 944 945 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 946 "device-memory", device_mem_size); 947 memory_region_add_subregion(system_memory, machine->device_memory->base, 948 &machine->device_memory->mr); 949 } 950 951 /* Initialize PC system firmware */ 952 pc_system_firmware_init(pcms, rom_memory); 953 954 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 955 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 956 &error_fatal); 957 if (pcmc->pci_enabled) { 958 memory_region_set_readonly(option_rom_mr, true); 959 } 960 memory_region_add_subregion_overlap(rom_memory, 961 PC_ROM_MIN_VGA, 962 option_rom_mr, 963 1); 964 965 fw_cfg = fw_cfg_arch_create(machine, 966 x86ms->boot_cpus, x86ms->apic_id_limit); 967 968 rom_set_fw(fw_cfg); 969 970 if (pcmc->has_reserved_memory && machine->device_memory->base) { 971 uint64_t *val = g_malloc(sizeof(*val)); 972 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 973 uint64_t res_mem_end = machine->device_memory->base; 974 975 if (!pcmc->broken_reserved_end) { 976 res_mem_end += memory_region_size(&machine->device_memory->mr); 977 } 978 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 979 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 980 } 981 982 if (linux_boot) { 983 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 984 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 985 } 986 987 for (i = 0; i < nb_option_roms; i++) { 988 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 989 } 990 x86ms->fw_cfg = fw_cfg; 991 992 /* Init default IOAPIC address space */ 993 x86ms->ioapic_as = &address_space_memory; 994 995 /* Init ACPI memory hotplug IO base address */ 996 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 997 } 998 999 /* 1000 * The 64bit pci hole starts after "above 4G RAM" and 1001 * potentially the space reserved for memory hotplug. 1002 */ 1003 uint64_t pc_pci_hole64_start(void) 1004 { 1005 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1006 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1007 MachineState *ms = MACHINE(pcms); 1008 X86MachineState *x86ms = X86_MACHINE(pcms); 1009 uint64_t hole64_start = 0; 1010 1011 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1012 hole64_start = ms->device_memory->base; 1013 if (!pcmc->broken_reserved_end) { 1014 hole64_start += memory_region_size(&ms->device_memory->mr); 1015 } 1016 } else { 1017 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1018 } 1019 1020 return ROUND_UP(hole64_start, 1 * GiB); 1021 } 1022 1023 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1024 { 1025 DeviceState *dev = NULL; 1026 1027 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1028 if (pci_bus) { 1029 PCIDevice *pcidev = pci_vga_init(pci_bus); 1030 dev = pcidev ? &pcidev->qdev : NULL; 1031 } else if (isa_bus) { 1032 ISADevice *isadev = isa_vga_init(isa_bus); 1033 dev = isadev ? DEVICE(isadev) : NULL; 1034 } 1035 rom_reset_order_override(); 1036 return dev; 1037 } 1038 1039 static const MemoryRegionOps ioport80_io_ops = { 1040 .write = ioport80_write, 1041 .read = ioport80_read, 1042 .endianness = DEVICE_NATIVE_ENDIAN, 1043 .impl = { 1044 .min_access_size = 1, 1045 .max_access_size = 1, 1046 }, 1047 }; 1048 1049 static const MemoryRegionOps ioportF0_io_ops = { 1050 .write = ioportF0_write, 1051 .read = ioportF0_read, 1052 .endianness = DEVICE_NATIVE_ENDIAN, 1053 .impl = { 1054 .min_access_size = 1, 1055 .max_access_size = 1, 1056 }, 1057 }; 1058 1059 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1060 { 1061 int i; 1062 DriveInfo *fd[MAX_FD]; 1063 qemu_irq *a20_line; 1064 ISADevice *fdc, *i8042, *port92, *vmmouse; 1065 1066 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1067 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1068 1069 for (i = 0; i < MAX_FD; i++) { 1070 fd[i] = drive_get(IF_FLOPPY, 0, i); 1071 create_fdctrl |= !!fd[i]; 1072 } 1073 if (create_fdctrl) { 1074 fdc = isa_new(TYPE_ISA_FDC); 1075 if (fdc) { 1076 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1077 isa_fdc_init_drives(fdc, fd); 1078 } 1079 } 1080 1081 i8042 = isa_create_simple(isa_bus, "i8042"); 1082 if (!no_vmport) { 1083 isa_create_simple(isa_bus, TYPE_VMPORT); 1084 vmmouse = isa_try_new("vmmouse"); 1085 } else { 1086 vmmouse = NULL; 1087 } 1088 if (vmmouse) { 1089 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1090 &error_abort); 1091 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1092 } 1093 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1094 1095 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1096 i8042_setup_a20_line(i8042, a20_line[0]); 1097 qdev_connect_gpio_out_named(DEVICE(port92), 1098 PORT92_A20_LINE, 0, a20_line[1]); 1099 g_free(a20_line); 1100 } 1101 1102 void pc_basic_device_init(struct PCMachineState *pcms, 1103 ISABus *isa_bus, qemu_irq *gsi, 1104 ISADevice **rtc_state, 1105 bool create_fdctrl, 1106 uint32_t hpet_irqs) 1107 { 1108 int i; 1109 DeviceState *hpet = NULL; 1110 int pit_isa_irq = 0; 1111 qemu_irq pit_alt_irq = NULL; 1112 qemu_irq rtc_irq = NULL; 1113 ISADevice *pit = NULL; 1114 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1115 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1116 1117 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1118 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1119 1120 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1121 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1122 1123 /* 1124 * Check if an HPET shall be created. 1125 * 1126 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1127 * when the HPET wants to take over. Thus we have to disable the latter. 1128 */ 1129 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1130 kvm_has_pit_state2())) { 1131 hpet = qdev_try_new(TYPE_HPET); 1132 if (!hpet) { 1133 error_report("couldn't create HPET device"); 1134 exit(1); 1135 } 1136 /* 1137 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1138 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1139 * IRQ2. 1140 */ 1141 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1142 HPET_INTCAP, NULL); 1143 if (!compat) { 1144 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1145 } 1146 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1147 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1148 1149 for (i = 0; i < GSI_NUM_PINS; i++) { 1150 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1151 } 1152 pit_isa_irq = -1; 1153 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1154 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1155 } 1156 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1157 1158 qemu_register_boot_set(pc_boot_set, *rtc_state); 1159 1160 if (!xen_enabled() && pcms->pit_enabled) { 1161 if (kvm_pit_in_kernel()) { 1162 pit = kvm_pit_init(isa_bus, 0x40); 1163 } else { 1164 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1165 } 1166 if (hpet) { 1167 /* connect PIT to output control line of the HPET */ 1168 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1169 } 1170 pcspk_init(pcms->pcspk, isa_bus, pit); 1171 } 1172 1173 i8257_dma_init(isa_bus, 0); 1174 1175 /* Super I/O */ 1176 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1177 } 1178 1179 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1180 { 1181 int i; 1182 1183 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1184 for (i = 0; i < nb_nics; i++) { 1185 NICInfo *nd = &nd_table[i]; 1186 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1187 1188 if (g_str_equal(model, "ne2k_isa")) { 1189 pc_init_ne2k_isa(isa_bus, nd); 1190 } else { 1191 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1192 } 1193 } 1194 rom_reset_order_override(); 1195 } 1196 1197 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1198 { 1199 qemu_irq *i8259; 1200 1201 if (kvm_pic_in_kernel()) { 1202 i8259 = kvm_i8259_init(isa_bus); 1203 } else if (xen_enabled()) { 1204 i8259 = xen_interrupt_controller_init(); 1205 } else { 1206 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1207 } 1208 1209 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1210 i8259_irqs[i] = i8259[i]; 1211 } 1212 1213 g_free(i8259); 1214 } 1215 1216 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1217 Error **errp) 1218 { 1219 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1220 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1221 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1222 const MachineState *ms = MACHINE(hotplug_dev); 1223 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1224 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1225 Error *local_err = NULL; 1226 1227 /* 1228 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1229 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1230 * addition to cover this case. 1231 */ 1232 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1233 error_setg(errp, 1234 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1235 return; 1236 } 1237 1238 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1239 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1240 return; 1241 } 1242 1243 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1244 if (local_err) { 1245 error_propagate(errp, local_err); 1246 return; 1247 } 1248 1249 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1250 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1251 } 1252 1253 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1254 DeviceState *dev, Error **errp) 1255 { 1256 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1257 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1258 MachineState *ms = MACHINE(hotplug_dev); 1259 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1260 1261 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1262 1263 if (is_nvdimm) { 1264 nvdimm_plug(ms->nvdimms_state); 1265 } 1266 1267 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1268 } 1269 1270 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1271 DeviceState *dev, Error **errp) 1272 { 1273 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1274 1275 /* 1276 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1277 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1278 * addition to cover this case. 1279 */ 1280 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1281 error_setg(errp, 1282 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1283 return; 1284 } 1285 1286 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1287 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1288 return; 1289 } 1290 1291 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1292 errp); 1293 } 1294 1295 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1296 DeviceState *dev, Error **errp) 1297 { 1298 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1299 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1300 Error *local_err = NULL; 1301 1302 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1303 if (local_err) { 1304 goto out; 1305 } 1306 1307 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1308 qdev_unrealize(dev); 1309 out: 1310 error_propagate(errp, local_err); 1311 } 1312 1313 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1314 DeviceState *dev, Error **errp) 1315 { 1316 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1317 Error *local_err = NULL; 1318 1319 if (!hotplug_dev2 && dev->hotplugged) { 1320 /* 1321 * Without a bus hotplug handler, we cannot control the plug/unplug 1322 * order. We should never reach this point when hotplugging on x86, 1323 * however, better add a safety net. 1324 */ 1325 error_setg(errp, "hotplug of virtio based memory devices not supported" 1326 " on this bus."); 1327 return; 1328 } 1329 /* 1330 * First, see if we can plug this memory device at all. If that 1331 * succeeds, branch of to the actual hotplug handler. 1332 */ 1333 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1334 &local_err); 1335 if (!local_err && hotplug_dev2) { 1336 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1337 } 1338 error_propagate(errp, local_err); 1339 } 1340 1341 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1342 DeviceState *dev, Error **errp) 1343 { 1344 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1345 Error *local_err = NULL; 1346 1347 /* 1348 * Plug the memory device first and then branch off to the actual 1349 * hotplug handler. If that one fails, we can easily undo the memory 1350 * device bits. 1351 */ 1352 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1353 if (hotplug_dev2) { 1354 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1355 if (local_err) { 1356 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1357 } 1358 } 1359 error_propagate(errp, local_err); 1360 } 1361 1362 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1363 DeviceState *dev, Error **errp) 1364 { 1365 /* We don't support hot unplug of virtio based memory devices */ 1366 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1367 } 1368 1369 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1370 DeviceState *dev, Error **errp) 1371 { 1372 /* We don't support hot unplug of virtio based memory devices */ 1373 } 1374 1375 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1376 DeviceState *dev, Error **errp) 1377 { 1378 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1379 pc_memory_pre_plug(hotplug_dev, dev, errp); 1380 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1381 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1383 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1384 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1385 } 1386 } 1387 1388 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1389 DeviceState *dev, Error **errp) 1390 { 1391 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1392 pc_memory_plug(hotplug_dev, dev, errp); 1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1394 x86_cpu_plug(hotplug_dev, dev, errp); 1395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1396 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1397 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1398 } 1399 } 1400 1401 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1402 DeviceState *dev, Error **errp) 1403 { 1404 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1405 pc_memory_unplug_request(hotplug_dev, dev, errp); 1406 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1407 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1409 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1410 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1411 } else { 1412 error_setg(errp, "acpi: device unplug request for not supported device" 1413 " type: %s", object_get_typename(OBJECT(dev))); 1414 } 1415 } 1416 1417 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1418 DeviceState *dev, Error **errp) 1419 { 1420 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1421 pc_memory_unplug(hotplug_dev, dev, errp); 1422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1423 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1425 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1426 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1427 } else { 1428 error_setg(errp, "acpi: device unplug for not supported device" 1429 " type: %s", object_get_typename(OBJECT(dev))); 1430 } 1431 } 1432 1433 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1434 DeviceState *dev) 1435 { 1436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1437 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1438 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1439 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1440 return HOTPLUG_HANDLER(machine); 1441 } 1442 1443 return NULL; 1444 } 1445 1446 static void 1447 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1448 const char *name, void *opaque, 1449 Error **errp) 1450 { 1451 MachineState *ms = MACHINE(obj); 1452 int64_t value = 0; 1453 1454 if (ms->device_memory) { 1455 value = memory_region_size(&ms->device_memory->mr); 1456 } 1457 1458 visit_type_int(v, name, &value, errp); 1459 } 1460 1461 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1462 void *opaque, Error **errp) 1463 { 1464 PCMachineState *pcms = PC_MACHINE(obj); 1465 OnOffAuto vmport = pcms->vmport; 1466 1467 visit_type_OnOffAuto(v, name, &vmport, errp); 1468 } 1469 1470 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1471 void *opaque, Error **errp) 1472 { 1473 PCMachineState *pcms = PC_MACHINE(obj); 1474 1475 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1476 } 1477 1478 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1479 { 1480 PCMachineState *pcms = PC_MACHINE(obj); 1481 1482 return pcms->smbus_enabled; 1483 } 1484 1485 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1486 { 1487 PCMachineState *pcms = PC_MACHINE(obj); 1488 1489 pcms->smbus_enabled = value; 1490 } 1491 1492 static bool pc_machine_get_sata(Object *obj, Error **errp) 1493 { 1494 PCMachineState *pcms = PC_MACHINE(obj); 1495 1496 return pcms->sata_enabled; 1497 } 1498 1499 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1500 { 1501 PCMachineState *pcms = PC_MACHINE(obj); 1502 1503 pcms->sata_enabled = value; 1504 } 1505 1506 static bool pc_machine_get_pit(Object *obj, Error **errp) 1507 { 1508 PCMachineState *pcms = PC_MACHINE(obj); 1509 1510 return pcms->pit_enabled; 1511 } 1512 1513 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1514 { 1515 PCMachineState *pcms = PC_MACHINE(obj); 1516 1517 pcms->pit_enabled = value; 1518 } 1519 1520 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1521 { 1522 PCMachineState *pcms = PC_MACHINE(obj); 1523 1524 return pcms->hpet_enabled; 1525 } 1526 1527 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1528 { 1529 PCMachineState *pcms = PC_MACHINE(obj); 1530 1531 pcms->hpet_enabled = value; 1532 } 1533 1534 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1535 const char *name, void *opaque, 1536 Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 uint64_t value = pcms->max_ram_below_4g; 1540 1541 visit_type_size(v, name, &value, errp); 1542 } 1543 1544 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1545 const char *name, void *opaque, 1546 Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 uint64_t value; 1550 1551 if (!visit_type_size(v, name, &value, errp)) { 1552 return; 1553 } 1554 if (value > 4 * GiB) { 1555 error_setg(errp, 1556 "Machine option 'max-ram-below-4g=%"PRIu64 1557 "' expects size less than or equal to 4G", value); 1558 return; 1559 } 1560 1561 if (value < 1 * MiB) { 1562 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1563 "BIOS may not work with less than 1MiB", value); 1564 } 1565 1566 pcms->max_ram_below_4g = value; 1567 } 1568 1569 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1570 const char *name, void *opaque, 1571 Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 uint64_t value = pcms->max_fw_size; 1575 1576 visit_type_size(v, name, &value, errp); 1577 } 1578 1579 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1580 const char *name, void *opaque, 1581 Error **errp) 1582 { 1583 PCMachineState *pcms = PC_MACHINE(obj); 1584 Error *error = NULL; 1585 uint64_t value; 1586 1587 visit_type_size(v, name, &value, &error); 1588 if (error) { 1589 error_propagate(errp, error); 1590 return; 1591 } 1592 1593 /* 1594 * We don't have a theoretically justifiable exact lower bound on the base 1595 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1596 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1597 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1598 * size. 1599 */ 1600 if (value > 16 * MiB) { 1601 error_setg(errp, 1602 "User specified max allowed firmware size %" PRIu64 " is " 1603 "greater than 16MiB. If combined firwmare size exceeds " 1604 "16MiB the system may not boot, or experience intermittent" 1605 "stability issues.", 1606 value); 1607 return; 1608 } 1609 1610 pcms->max_fw_size = value; 1611 } 1612 1613 1614 static void pc_machine_initfn(Object *obj) 1615 { 1616 PCMachineState *pcms = PC_MACHINE(obj); 1617 1618 #ifdef CONFIG_VMPORT 1619 pcms->vmport = ON_OFF_AUTO_AUTO; 1620 #else 1621 pcms->vmport = ON_OFF_AUTO_OFF; 1622 #endif /* CONFIG_VMPORT */ 1623 pcms->max_ram_below_4g = 0; /* use default */ 1624 /* acpi build is enabled by default if machine supports it */ 1625 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1626 pcms->smbus_enabled = true; 1627 pcms->sata_enabled = true; 1628 pcms->pit_enabled = true; 1629 pcms->max_fw_size = 8 * MiB; 1630 #ifdef CONFIG_HPET 1631 pcms->hpet_enabled = true; 1632 #endif 1633 1634 pc_system_flash_create(pcms); 1635 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1636 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1637 OBJECT(pcms->pcspk), "audiodev"); 1638 } 1639 1640 static void pc_machine_reset(MachineState *machine) 1641 { 1642 CPUState *cs; 1643 X86CPU *cpu; 1644 1645 qemu_devices_reset(); 1646 1647 /* Reset APIC after devices have been reset to cancel 1648 * any changes that qemu_devices_reset() might have done. 1649 */ 1650 CPU_FOREACH(cs) { 1651 cpu = X86_CPU(cs); 1652 1653 if (cpu->apic_state) { 1654 device_legacy_reset(cpu->apic_state); 1655 } 1656 } 1657 } 1658 1659 static void pc_machine_wakeup(MachineState *machine) 1660 { 1661 cpu_synchronize_all_states(); 1662 pc_machine_reset(machine); 1663 cpu_synchronize_all_post_reset(); 1664 } 1665 1666 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1667 { 1668 X86IOMMUState *iommu = x86_iommu_get_default(); 1669 IntelIOMMUState *intel_iommu; 1670 1671 if (iommu && 1672 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1673 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1674 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1675 if (!intel_iommu->caching_mode) { 1676 error_setg(errp, "Device assignment is not allowed without " 1677 "enabling caching-mode=on for Intel IOMMU."); 1678 return false; 1679 } 1680 } 1681 1682 return true; 1683 } 1684 1685 static void pc_machine_class_init(ObjectClass *oc, void *data) 1686 { 1687 MachineClass *mc = MACHINE_CLASS(oc); 1688 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1689 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1690 1691 pcmc->pci_enabled = true; 1692 pcmc->has_acpi_build = true; 1693 pcmc->rsdp_in_ram = true; 1694 pcmc->smbios_defaults = true; 1695 pcmc->smbios_uuid_encoded = true; 1696 pcmc->gigabyte_align = true; 1697 pcmc->has_reserved_memory = true; 1698 pcmc->kvmclock_enabled = true; 1699 pcmc->enforce_aligned_dimm = true; 1700 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1701 * to be used at the moment, 32K should be enough for a while. */ 1702 pcmc->acpi_data_size = 0x20000 + 0x8000; 1703 pcmc->linuxboot_dma_enabled = true; 1704 pcmc->pvh_enabled = true; 1705 pcmc->kvmclock_create_always = true; 1706 assert(!mc->get_hotplug_handler); 1707 mc->get_hotplug_handler = pc_get_hotplug_handler; 1708 mc->hotplug_allowed = pc_hotplug_allowed; 1709 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1710 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1711 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1712 mc->auto_enable_numa_with_memhp = true; 1713 mc->auto_enable_numa_with_memdev = true; 1714 mc->has_hotpluggable_cpus = true; 1715 mc->default_boot_order = "cad"; 1716 mc->smp_parse = pc_smp_parse; 1717 mc->block_default_type = IF_IDE; 1718 mc->max_cpus = 255; 1719 mc->reset = pc_machine_reset; 1720 mc->wakeup = pc_machine_wakeup; 1721 hc->pre_plug = pc_machine_device_pre_plug_cb; 1722 hc->plug = pc_machine_device_plug_cb; 1723 hc->unplug_request = pc_machine_device_unplug_request_cb; 1724 hc->unplug = pc_machine_device_unplug_cb; 1725 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1726 mc->nvdimm_supported = true; 1727 mc->default_ram_id = "pc.ram"; 1728 1729 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1730 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1731 NULL, NULL); 1732 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1733 "Maximum ram below the 4G boundary (32bit boundary)"); 1734 1735 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1736 pc_machine_get_device_memory_region_size, NULL, 1737 NULL, NULL); 1738 1739 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1740 pc_machine_get_vmport, pc_machine_set_vmport, 1741 NULL, NULL); 1742 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1743 "Enable vmport (pc & q35)"); 1744 1745 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1746 pc_machine_get_smbus, pc_machine_set_smbus); 1747 1748 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1749 pc_machine_get_sata, pc_machine_set_sata); 1750 1751 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1752 pc_machine_get_pit, pc_machine_set_pit); 1753 1754 object_class_property_add_bool(oc, "hpet", 1755 pc_machine_get_hpet, pc_machine_set_hpet); 1756 1757 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1758 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1759 NULL, NULL); 1760 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1761 "Maximum combined firmware size"); 1762 } 1763 1764 static const TypeInfo pc_machine_info = { 1765 .name = TYPE_PC_MACHINE, 1766 .parent = TYPE_X86_MACHINE, 1767 .abstract = true, 1768 .instance_size = sizeof(PCMachineState), 1769 .instance_init = pc_machine_initfn, 1770 .class_size = sizeof(PCMachineClass), 1771 .class_init = pc_machine_class_init, 1772 .interfaces = (InterfaceInfo[]) { 1773 { TYPE_HOTPLUG_HANDLER }, 1774 { } 1775 }, 1776 }; 1777 1778 static void pc_machine_register_types(void) 1779 { 1780 type_register_static(&pc_machine_info); 1781 } 1782 1783 type_init(pc_machine_register_types) 1784