1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 #include "hw/nmi.h" 71 #include "hw/i386/intel_iommu.h" 72 73 /* debug PC/ISA interrupts */ 74 //#define DEBUG_IRQ 75 76 #ifdef DEBUG_IRQ 77 #define DPRINTF(fmt, ...) \ 78 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 79 #else 80 #define DPRINTF(fmt, ...) 81 #endif 82 83 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 84 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 85 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 86 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 87 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 88 89 #define E820_NR_ENTRIES 16 90 91 struct e820_entry { 92 uint64_t address; 93 uint64_t length; 94 uint32_t type; 95 } QEMU_PACKED __attribute((__aligned__(4))); 96 97 struct e820_table { 98 uint32_t count; 99 struct e820_entry entry[E820_NR_ENTRIES]; 100 } QEMU_PACKED __attribute((__aligned__(4))); 101 102 static struct e820_table e820_reserve; 103 static struct e820_entry *e820_table; 104 static unsigned e820_entries; 105 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 106 107 void gsi_handler(void *opaque, int n, int level) 108 { 109 GSIState *s = opaque; 110 111 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 112 if (n < ISA_NUM_IRQS) { 113 qemu_set_irq(s->i8259_irq[n], level); 114 } 115 qemu_set_irq(s->ioapic_irq[n], level); 116 } 117 118 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 119 unsigned size) 120 { 121 } 122 123 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 124 { 125 return 0xffffffffffffffffULL; 126 } 127 128 /* MSDOS compatibility mode FPU exception support */ 129 static qemu_irq ferr_irq; 130 131 void pc_register_ferr_irq(qemu_irq irq) 132 { 133 ferr_irq = irq; 134 } 135 136 /* XXX: add IGNNE support */ 137 void cpu_set_ferr(CPUX86State *s) 138 { 139 qemu_irq_raise(ferr_irq); 140 } 141 142 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 143 unsigned size) 144 { 145 qemu_irq_lower(ferr_irq); 146 } 147 148 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 149 { 150 return 0xffffffffffffffffULL; 151 } 152 153 /* TSC handling */ 154 uint64_t cpu_get_tsc(CPUX86State *env) 155 { 156 return cpu_get_ticks(); 157 } 158 159 /* IRQ handling */ 160 int cpu_get_pic_interrupt(CPUX86State *env) 161 { 162 X86CPU *cpu = x86_env_get_cpu(env); 163 int intno; 164 165 if (!kvm_irqchip_in_kernel()) { 166 intno = apic_get_interrupt(cpu->apic_state); 167 if (intno >= 0) { 168 return intno; 169 } 170 /* read the irq from the PIC */ 171 if (!apic_accept_pic_intr(cpu->apic_state)) { 172 return -1; 173 } 174 } 175 176 intno = pic_read_irq(isa_pic); 177 return intno; 178 } 179 180 static void pic_irq_request(void *opaque, int irq, int level) 181 { 182 CPUState *cs = first_cpu; 183 X86CPU *cpu = X86_CPU(cs); 184 185 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 186 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 187 CPU_FOREACH(cs) { 188 cpu = X86_CPU(cs); 189 if (apic_accept_pic_intr(cpu->apic_state)) { 190 apic_deliver_pic_intr(cpu->apic_state, level); 191 } 192 } 193 } else { 194 if (level) { 195 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 196 } else { 197 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 198 } 199 } 200 } 201 202 /* PC cmos mappings */ 203 204 #define REG_EQUIPMENT_BYTE 0x14 205 206 int cmos_get_fd_drive_type(FloppyDriveType fd0) 207 { 208 int val; 209 210 switch (fd0) { 211 case FLOPPY_DRIVE_TYPE_144: 212 /* 1.44 Mb 3"5 drive */ 213 val = 4; 214 break; 215 case FLOPPY_DRIVE_TYPE_288: 216 /* 2.88 Mb 3"5 drive */ 217 val = 5; 218 break; 219 case FLOPPY_DRIVE_TYPE_120: 220 /* 1.2 Mb 5"5 drive */ 221 val = 2; 222 break; 223 case FLOPPY_DRIVE_TYPE_NONE: 224 default: 225 val = 0; 226 break; 227 } 228 return val; 229 } 230 231 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 232 int16_t cylinders, int8_t heads, int8_t sectors) 233 { 234 rtc_set_memory(s, type_ofs, 47); 235 rtc_set_memory(s, info_ofs, cylinders); 236 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 237 rtc_set_memory(s, info_ofs + 2, heads); 238 rtc_set_memory(s, info_ofs + 3, 0xff); 239 rtc_set_memory(s, info_ofs + 4, 0xff); 240 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 241 rtc_set_memory(s, info_ofs + 6, cylinders); 242 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 243 rtc_set_memory(s, info_ofs + 8, sectors); 244 } 245 246 /* convert boot_device letter to something recognizable by the bios */ 247 static int boot_device2nibble(char boot_device) 248 { 249 switch(boot_device) { 250 case 'a': 251 case 'b': 252 return 0x01; /* floppy boot */ 253 case 'c': 254 return 0x02; /* hard drive boot */ 255 case 'd': 256 return 0x03; /* CD-ROM boot */ 257 case 'n': 258 return 0x04; /* Network boot */ 259 } 260 return 0; 261 } 262 263 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 264 { 265 #define PC_MAX_BOOT_DEVICES 3 266 int nbds, bds[3] = { 0, }; 267 int i; 268 269 nbds = strlen(boot_device); 270 if (nbds > PC_MAX_BOOT_DEVICES) { 271 error_setg(errp, "Too many boot devices for PC"); 272 return; 273 } 274 for (i = 0; i < nbds; i++) { 275 bds[i] = boot_device2nibble(boot_device[i]); 276 if (bds[i] == 0) { 277 error_setg(errp, "Invalid boot device for PC: '%c'", 278 boot_device[i]); 279 return; 280 } 281 } 282 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 283 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 284 } 285 286 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 287 { 288 set_boot_dev(opaque, boot_device, errp); 289 } 290 291 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 292 { 293 int val, nb, i; 294 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 295 FLOPPY_DRIVE_TYPE_NONE }; 296 297 /* floppy type */ 298 if (floppy) { 299 for (i = 0; i < 2; i++) { 300 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 301 } 302 } 303 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 304 cmos_get_fd_drive_type(fd_type[1]); 305 rtc_set_memory(rtc_state, 0x10, val); 306 307 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 308 nb = 0; 309 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 310 nb++; 311 } 312 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 313 nb++; 314 } 315 switch (nb) { 316 case 0: 317 break; 318 case 1: 319 val |= 0x01; /* 1 drive, ready for boot */ 320 break; 321 case 2: 322 val |= 0x41; /* 2 drives, ready for boot */ 323 break; 324 } 325 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 326 } 327 328 typedef struct pc_cmos_init_late_arg { 329 ISADevice *rtc_state; 330 BusState *idebus[2]; 331 } pc_cmos_init_late_arg; 332 333 typedef struct check_fdc_state { 334 ISADevice *floppy; 335 bool multiple; 336 } CheckFdcState; 337 338 static int check_fdc(Object *obj, void *opaque) 339 { 340 CheckFdcState *state = opaque; 341 Object *fdc; 342 uint32_t iobase; 343 Error *local_err = NULL; 344 345 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 346 if (!fdc) { 347 return 0; 348 } 349 350 iobase = object_property_get_int(obj, "iobase", &local_err); 351 if (local_err || iobase != 0x3f0) { 352 error_free(local_err); 353 return 0; 354 } 355 356 if (state->floppy) { 357 state->multiple = true; 358 } else { 359 state->floppy = ISA_DEVICE(obj); 360 } 361 return 0; 362 } 363 364 static const char * const fdc_container_path[] = { 365 "/unattached", "/peripheral", "/peripheral-anon" 366 }; 367 368 /* 369 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 370 * and ACPI objects. 371 */ 372 ISADevice *pc_find_fdc0(void) 373 { 374 int i; 375 Object *container; 376 CheckFdcState state = { 0 }; 377 378 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 379 container = container_get(qdev_get_machine(), fdc_container_path[i]); 380 object_child_foreach(container, check_fdc, &state); 381 } 382 383 if (state.multiple) { 384 error_report("warning: multiple floppy disk controllers with " 385 "iobase=0x3f0 have been found"); 386 error_printf("the one being picked for CMOS setup might not reflect " 387 "your intent\n"); 388 } 389 390 return state.floppy; 391 } 392 393 static void pc_cmos_init_late(void *opaque) 394 { 395 pc_cmos_init_late_arg *arg = opaque; 396 ISADevice *s = arg->rtc_state; 397 int16_t cylinders; 398 int8_t heads, sectors; 399 int val; 400 int i, trans; 401 402 val = 0; 403 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 404 &cylinders, &heads, §ors) >= 0) { 405 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 406 val |= 0xf0; 407 } 408 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 409 &cylinders, &heads, §ors) >= 0) { 410 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 411 val |= 0x0f; 412 } 413 rtc_set_memory(s, 0x12, val); 414 415 val = 0; 416 for (i = 0; i < 4; i++) { 417 /* NOTE: ide_get_geometry() returns the physical 418 geometry. It is always such that: 1 <= sects <= 63, 1 419 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 420 geometry can be different if a translation is done. */ 421 if (arg->idebus[i / 2] && 422 ide_get_geometry(arg->idebus[i / 2], i % 2, 423 &cylinders, &heads, §ors) >= 0) { 424 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 425 assert((trans & ~3) == 0); 426 val |= trans << (i * 2); 427 } 428 } 429 rtc_set_memory(s, 0x39, val); 430 431 pc_cmos_init_floppy(s, pc_find_fdc0()); 432 433 qemu_unregister_reset(pc_cmos_init_late, opaque); 434 } 435 436 void pc_cmos_init(PCMachineState *pcms, 437 BusState *idebus0, BusState *idebus1, 438 ISADevice *s) 439 { 440 int val; 441 static pc_cmos_init_late_arg arg; 442 443 /* various important CMOS locations needed by PC/Bochs bios */ 444 445 /* memory size */ 446 /* base memory (first MiB) */ 447 val = MIN(pcms->below_4g_mem_size / 1024, 640); 448 rtc_set_memory(s, 0x15, val); 449 rtc_set_memory(s, 0x16, val >> 8); 450 /* extended memory (next 64MiB) */ 451 if (pcms->below_4g_mem_size > 1024 * 1024) { 452 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 453 } else { 454 val = 0; 455 } 456 if (val > 65535) 457 val = 65535; 458 rtc_set_memory(s, 0x17, val); 459 rtc_set_memory(s, 0x18, val >> 8); 460 rtc_set_memory(s, 0x30, val); 461 rtc_set_memory(s, 0x31, val >> 8); 462 /* memory between 16MiB and 4GiB */ 463 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 464 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 465 } else { 466 val = 0; 467 } 468 if (val > 65535) 469 val = 65535; 470 rtc_set_memory(s, 0x34, val); 471 rtc_set_memory(s, 0x35, val >> 8); 472 /* memory above 4GiB */ 473 val = pcms->above_4g_mem_size / 65536; 474 rtc_set_memory(s, 0x5b, val); 475 rtc_set_memory(s, 0x5c, val >> 8); 476 rtc_set_memory(s, 0x5d, val >> 16); 477 478 object_property_add_link(OBJECT(pcms), "rtc_state", 479 TYPE_ISA_DEVICE, 480 (Object **)&pcms->rtc, 481 object_property_allow_set_link, 482 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 483 object_property_set_link(OBJECT(pcms), OBJECT(s), 484 "rtc_state", &error_abort); 485 486 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 487 488 val = 0; 489 val |= 0x02; /* FPU is there */ 490 val |= 0x04; /* PS/2 mouse installed */ 491 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 492 493 /* hard drives and FDC */ 494 arg.rtc_state = s; 495 arg.idebus[0] = idebus0; 496 arg.idebus[1] = idebus1; 497 qemu_register_reset(pc_cmos_init_late, &arg); 498 } 499 500 #define TYPE_PORT92 "port92" 501 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 502 503 /* port 92 stuff: could be split off */ 504 typedef struct Port92State { 505 ISADevice parent_obj; 506 507 MemoryRegion io; 508 uint8_t outport; 509 qemu_irq a20_out; 510 } Port92State; 511 512 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 513 unsigned size) 514 { 515 Port92State *s = opaque; 516 int oldval = s->outport; 517 518 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 519 s->outport = val; 520 qemu_set_irq(s->a20_out, (val >> 1) & 1); 521 if ((val & 1) && !(oldval & 1)) { 522 qemu_system_reset_request(); 523 } 524 } 525 526 static uint64_t port92_read(void *opaque, hwaddr addr, 527 unsigned size) 528 { 529 Port92State *s = opaque; 530 uint32_t ret; 531 532 ret = s->outport; 533 DPRINTF("port92: read 0x%02x\n", ret); 534 return ret; 535 } 536 537 static void port92_init(ISADevice *dev, qemu_irq a20_out) 538 { 539 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 540 } 541 542 static const VMStateDescription vmstate_port92_isa = { 543 .name = "port92", 544 .version_id = 1, 545 .minimum_version_id = 1, 546 .fields = (VMStateField[]) { 547 VMSTATE_UINT8(outport, Port92State), 548 VMSTATE_END_OF_LIST() 549 } 550 }; 551 552 static void port92_reset(DeviceState *d) 553 { 554 Port92State *s = PORT92(d); 555 556 s->outport &= ~1; 557 } 558 559 static const MemoryRegionOps port92_ops = { 560 .read = port92_read, 561 .write = port92_write, 562 .impl = { 563 .min_access_size = 1, 564 .max_access_size = 1, 565 }, 566 .endianness = DEVICE_LITTLE_ENDIAN, 567 }; 568 569 static void port92_initfn(Object *obj) 570 { 571 Port92State *s = PORT92(obj); 572 573 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 574 575 s->outport = 0; 576 577 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 578 } 579 580 static void port92_realizefn(DeviceState *dev, Error **errp) 581 { 582 ISADevice *isadev = ISA_DEVICE(dev); 583 Port92State *s = PORT92(dev); 584 585 isa_register_ioport(isadev, &s->io, 0x92); 586 } 587 588 static void port92_class_initfn(ObjectClass *klass, void *data) 589 { 590 DeviceClass *dc = DEVICE_CLASS(klass); 591 592 dc->realize = port92_realizefn; 593 dc->reset = port92_reset; 594 dc->vmsd = &vmstate_port92_isa; 595 /* 596 * Reason: unlike ordinary ISA devices, this one needs additional 597 * wiring: its A20 output line needs to be wired up by 598 * port92_init(). 599 */ 600 dc->cannot_instantiate_with_device_add_yet = true; 601 } 602 603 static const TypeInfo port92_info = { 604 .name = TYPE_PORT92, 605 .parent = TYPE_ISA_DEVICE, 606 .instance_size = sizeof(Port92State), 607 .instance_init = port92_initfn, 608 .class_init = port92_class_initfn, 609 }; 610 611 static void port92_register_types(void) 612 { 613 type_register_static(&port92_info); 614 } 615 616 type_init(port92_register_types) 617 618 static void handle_a20_line_change(void *opaque, int irq, int level) 619 { 620 X86CPU *cpu = opaque; 621 622 /* XXX: send to all CPUs ? */ 623 /* XXX: add logic to handle multiple A20 line sources */ 624 x86_cpu_set_a20(cpu, level); 625 } 626 627 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 628 { 629 int index = le32_to_cpu(e820_reserve.count); 630 struct e820_entry *entry; 631 632 if (type != E820_RAM) { 633 /* old FW_CFG_E820_TABLE entry -- reservations only */ 634 if (index >= E820_NR_ENTRIES) { 635 return -EBUSY; 636 } 637 entry = &e820_reserve.entry[index++]; 638 639 entry->address = cpu_to_le64(address); 640 entry->length = cpu_to_le64(length); 641 entry->type = cpu_to_le32(type); 642 643 e820_reserve.count = cpu_to_le32(index); 644 } 645 646 /* new "etc/e820" file -- include ram too */ 647 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 648 e820_table[e820_entries].address = cpu_to_le64(address); 649 e820_table[e820_entries].length = cpu_to_le64(length); 650 e820_table[e820_entries].type = cpu_to_le32(type); 651 e820_entries++; 652 653 return e820_entries; 654 } 655 656 int e820_get_num_entries(void) 657 { 658 return e820_entries; 659 } 660 661 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 662 { 663 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 664 *address = le64_to_cpu(e820_table[idx].address); 665 *length = le64_to_cpu(e820_table[idx].length); 666 return true; 667 } 668 return false; 669 } 670 671 /* Enables contiguous-apic-ID mode, for compatibility */ 672 static bool compat_apic_id_mode; 673 674 void enable_compat_apic_id_mode(void) 675 { 676 compat_apic_id_mode = true; 677 } 678 679 /* Calculates initial APIC ID for a specific CPU index 680 * 681 * Currently we need to be able to calculate the APIC ID from the CPU index 682 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 683 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 684 * all CPUs up to max_cpus. 685 */ 686 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 687 { 688 uint32_t correct_id; 689 static bool warned; 690 691 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 692 if (compat_apic_id_mode) { 693 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 694 error_report("APIC IDs set in compatibility mode, " 695 "CPU topology won't match the configuration"); 696 warned = true; 697 } 698 return cpu_index; 699 } else { 700 return correct_id; 701 } 702 } 703 704 static void pc_build_smbios(FWCfgState *fw_cfg) 705 { 706 uint8_t *smbios_tables, *smbios_anchor; 707 size_t smbios_tables_len, smbios_anchor_len; 708 struct smbios_phys_mem_area *mem_array; 709 unsigned i, array_count; 710 711 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 712 if (smbios_tables) { 713 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 714 smbios_tables, smbios_tables_len); 715 } 716 717 /* build the array of physical mem area from e820 table */ 718 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 719 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 720 uint64_t addr, len; 721 722 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 723 mem_array[array_count].address = addr; 724 mem_array[array_count].length = len; 725 array_count++; 726 } 727 } 728 smbios_get_tables(mem_array, array_count, 729 &smbios_tables, &smbios_tables_len, 730 &smbios_anchor, &smbios_anchor_len); 731 g_free(mem_array); 732 733 if (smbios_anchor) { 734 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 735 smbios_tables, smbios_tables_len); 736 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 737 smbios_anchor, smbios_anchor_len); 738 } 739 } 740 741 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 742 { 743 FWCfgState *fw_cfg; 744 uint64_t *numa_fw_cfg; 745 int i, j; 746 747 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 748 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 749 750 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 751 * 752 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 753 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 754 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 755 * for CPU hotplug also uses APIC ID and not "CPU index". 756 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 757 * but the "limit to the APIC ID values SeaBIOS may see". 758 * 759 * So for compatibility reasons with old BIOSes we are stuck with 760 * "etc/max-cpus" actually being apic_id_limit 761 */ 762 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 763 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 764 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 765 acpi_tables, acpi_tables_len); 766 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 767 768 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 769 &e820_reserve, sizeof(e820_reserve)); 770 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 771 sizeof(struct e820_entry) * e820_entries); 772 773 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 774 /* allocate memory for the NUMA channel: one (64bit) word for the number 775 * of nodes, one word for each VCPU->node and one word for each node to 776 * hold the amount of memory. 777 */ 778 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 779 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 780 for (i = 0; i < max_cpus; i++) { 781 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 782 assert(apic_id < pcms->apic_id_limit); 783 j = numa_get_node_for_cpu(i); 784 if (j < nb_numa_nodes) { 785 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 786 } 787 } 788 for (i = 0; i < nb_numa_nodes; i++) { 789 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 790 cpu_to_le64(numa_info[i].node_mem); 791 } 792 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 793 (1 + pcms->apic_id_limit + nb_numa_nodes) * 794 sizeof(*numa_fw_cfg)); 795 796 return fw_cfg; 797 } 798 799 static long get_file_size(FILE *f) 800 { 801 long where, size; 802 803 /* XXX: on Unix systems, using fstat() probably makes more sense */ 804 805 where = ftell(f); 806 fseek(f, 0, SEEK_END); 807 size = ftell(f); 808 fseek(f, where, SEEK_SET); 809 810 return size; 811 } 812 813 /* setup_data types */ 814 #define SETUP_NONE 0 815 #define SETUP_E820_EXT 1 816 #define SETUP_DTB 2 817 #define SETUP_PCI 3 818 #define SETUP_EFI 4 819 820 struct setup_data { 821 uint64_t next; 822 uint32_t type; 823 uint32_t len; 824 uint8_t data[0]; 825 } __attribute__((packed)); 826 827 static void load_linux(PCMachineState *pcms, 828 FWCfgState *fw_cfg) 829 { 830 uint16_t protocol; 831 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 832 int dtb_size, setup_data_offset; 833 uint32_t initrd_max; 834 uint8_t header[8192], *setup, *kernel, *initrd_data; 835 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 836 FILE *f; 837 char *vmode; 838 MachineState *machine = MACHINE(pcms); 839 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 840 struct setup_data *setup_data; 841 const char *kernel_filename = machine->kernel_filename; 842 const char *initrd_filename = machine->initrd_filename; 843 const char *dtb_filename = machine->dtb; 844 const char *kernel_cmdline = machine->kernel_cmdline; 845 846 /* Align to 16 bytes as a paranoia measure */ 847 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 848 849 /* load the kernel header */ 850 f = fopen(kernel_filename, "rb"); 851 if (!f || !(kernel_size = get_file_size(f)) || 852 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 853 MIN(ARRAY_SIZE(header), kernel_size)) { 854 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 855 kernel_filename, strerror(errno)); 856 exit(1); 857 } 858 859 /* kernel protocol version */ 860 #if 0 861 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 862 #endif 863 if (ldl_p(header+0x202) == 0x53726448) { 864 protocol = lduw_p(header+0x206); 865 } else { 866 /* This looks like a multiboot kernel. If it is, let's stop 867 treating it like a Linux kernel. */ 868 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 869 kernel_cmdline, kernel_size, header)) { 870 return; 871 } 872 protocol = 0; 873 } 874 875 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 876 /* Low kernel */ 877 real_addr = 0x90000; 878 cmdline_addr = 0x9a000 - cmdline_size; 879 prot_addr = 0x10000; 880 } else if (protocol < 0x202) { 881 /* High but ancient kernel */ 882 real_addr = 0x90000; 883 cmdline_addr = 0x9a000 - cmdline_size; 884 prot_addr = 0x100000; 885 } else { 886 /* High and recent kernel */ 887 real_addr = 0x10000; 888 cmdline_addr = 0x20000; 889 prot_addr = 0x100000; 890 } 891 892 #if 0 893 fprintf(stderr, 894 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 895 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 896 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 897 real_addr, 898 cmdline_addr, 899 prot_addr); 900 #endif 901 902 /* highest address for loading the initrd */ 903 if (protocol >= 0x203) { 904 initrd_max = ldl_p(header+0x22c); 905 } else { 906 initrd_max = 0x37ffffff; 907 } 908 909 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 910 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 911 } 912 913 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 914 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 915 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 916 917 if (protocol >= 0x202) { 918 stl_p(header+0x228, cmdline_addr); 919 } else { 920 stw_p(header+0x20, 0xA33F); 921 stw_p(header+0x22, cmdline_addr-real_addr); 922 } 923 924 /* handle vga= parameter */ 925 vmode = strstr(kernel_cmdline, "vga="); 926 if (vmode) { 927 unsigned int video_mode; 928 /* skip "vga=" */ 929 vmode += 4; 930 if (!strncmp(vmode, "normal", 6)) { 931 video_mode = 0xffff; 932 } else if (!strncmp(vmode, "ext", 3)) { 933 video_mode = 0xfffe; 934 } else if (!strncmp(vmode, "ask", 3)) { 935 video_mode = 0xfffd; 936 } else { 937 video_mode = strtol(vmode, NULL, 0); 938 } 939 stw_p(header+0x1fa, video_mode); 940 } 941 942 /* loader type */ 943 /* High nybble = B reserved for QEMU; low nybble is revision number. 944 If this code is substantially changed, you may want to consider 945 incrementing the revision. */ 946 if (protocol >= 0x200) { 947 header[0x210] = 0xB0; 948 } 949 /* heap */ 950 if (protocol >= 0x201) { 951 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 952 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 953 } 954 955 /* load initrd */ 956 if (initrd_filename) { 957 if (protocol < 0x200) { 958 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 959 exit(1); 960 } 961 962 initrd_size = get_image_size(initrd_filename); 963 if (initrd_size < 0) { 964 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 965 initrd_filename, strerror(errno)); 966 exit(1); 967 } 968 969 initrd_addr = (initrd_max-initrd_size) & ~4095; 970 971 initrd_data = g_malloc(initrd_size); 972 load_image(initrd_filename, initrd_data); 973 974 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 975 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 976 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 977 978 stl_p(header+0x218, initrd_addr); 979 stl_p(header+0x21c, initrd_size); 980 } 981 982 /* load kernel and setup */ 983 setup_size = header[0x1f1]; 984 if (setup_size == 0) { 985 setup_size = 4; 986 } 987 setup_size = (setup_size+1)*512; 988 if (setup_size > kernel_size) { 989 fprintf(stderr, "qemu: invalid kernel header\n"); 990 exit(1); 991 } 992 kernel_size -= setup_size; 993 994 setup = g_malloc(setup_size); 995 kernel = g_malloc(kernel_size); 996 fseek(f, 0, SEEK_SET); 997 if (fread(setup, 1, setup_size, f) != setup_size) { 998 fprintf(stderr, "fread() failed\n"); 999 exit(1); 1000 } 1001 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1002 fprintf(stderr, "fread() failed\n"); 1003 exit(1); 1004 } 1005 fclose(f); 1006 1007 /* append dtb to kernel */ 1008 if (dtb_filename) { 1009 if (protocol < 0x209) { 1010 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1011 exit(1); 1012 } 1013 1014 dtb_size = get_image_size(dtb_filename); 1015 if (dtb_size <= 0) { 1016 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1017 dtb_filename, strerror(errno)); 1018 exit(1); 1019 } 1020 1021 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1022 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1023 kernel = g_realloc(kernel, kernel_size); 1024 1025 stq_p(header+0x250, prot_addr + setup_data_offset); 1026 1027 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1028 setup_data->next = 0; 1029 setup_data->type = cpu_to_le32(SETUP_DTB); 1030 setup_data->len = cpu_to_le32(dtb_size); 1031 1032 load_image_size(dtb_filename, setup_data->data, dtb_size); 1033 } 1034 1035 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1036 1037 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1039 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1040 1041 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1042 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1043 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1044 1045 if (fw_cfg_dma_enabled(fw_cfg)) { 1046 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1047 option_rom[nb_option_roms].bootindex = 0; 1048 } else { 1049 option_rom[nb_option_roms].name = "linuxboot.bin"; 1050 option_rom[nb_option_roms].bootindex = 0; 1051 } 1052 nb_option_roms++; 1053 } 1054 1055 #define NE2000_NB_MAX 6 1056 1057 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1058 0x280, 0x380 }; 1059 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1060 1061 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1062 { 1063 static int nb_ne2k = 0; 1064 1065 if (nb_ne2k == NE2000_NB_MAX) 1066 return; 1067 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1068 ne2000_irq[nb_ne2k], nd); 1069 nb_ne2k++; 1070 } 1071 1072 DeviceState *cpu_get_current_apic(void) 1073 { 1074 if (current_cpu) { 1075 X86CPU *cpu = X86_CPU(current_cpu); 1076 return cpu->apic_state; 1077 } else { 1078 return NULL; 1079 } 1080 } 1081 1082 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1083 { 1084 X86CPU *cpu = opaque; 1085 1086 if (level) { 1087 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1088 } 1089 } 1090 1091 static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id, 1092 Error **errp) 1093 { 1094 X86CPU *cpu = NULL; 1095 Error *local_err = NULL; 1096 1097 cpu = X86_CPU(object_new(typename)); 1098 1099 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1100 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1101 1102 if (local_err) { 1103 error_propagate(errp, local_err); 1104 object_unref(OBJECT(cpu)); 1105 cpu = NULL; 1106 } 1107 return cpu; 1108 } 1109 1110 void pc_hot_add_cpu(const int64_t id, Error **errp) 1111 { 1112 X86CPU *cpu; 1113 ObjectClass *oc; 1114 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1115 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1116 Error *local_err = NULL; 1117 1118 if (id < 0) { 1119 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1120 return; 1121 } 1122 1123 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1124 error_setg(errp, "Unable to add CPU: %" PRIi64 1125 ", resulting APIC ID (%" PRIi64 ") is too large", 1126 id, apic_id); 1127 return; 1128 } 1129 1130 assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */ 1131 oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu)); 1132 cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); 1133 if (local_err) { 1134 error_propagate(errp, local_err); 1135 return; 1136 } 1137 object_unref(OBJECT(cpu)); 1138 } 1139 1140 void pc_cpus_init(PCMachineState *pcms) 1141 { 1142 int i; 1143 CPUClass *cc; 1144 ObjectClass *oc; 1145 const char *typename; 1146 gchar **model_pieces; 1147 X86CPU *cpu = NULL; 1148 MachineState *machine = MACHINE(pcms); 1149 1150 /* init CPUs */ 1151 if (machine->cpu_model == NULL) { 1152 #ifdef TARGET_X86_64 1153 machine->cpu_model = "qemu64"; 1154 #else 1155 machine->cpu_model = "qemu32"; 1156 #endif 1157 } 1158 1159 model_pieces = g_strsplit(machine->cpu_model, ",", 2); 1160 if (!model_pieces[0]) { 1161 error_report("Invalid/empty CPU model name"); 1162 exit(1); 1163 } 1164 1165 oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); 1166 if (oc == NULL) { 1167 error_report("Unable to find CPU definition: %s", model_pieces[0]); 1168 exit(1); 1169 } 1170 typename = object_class_get_name(oc); 1171 cc = CPU_CLASS(oc); 1172 cc->parse_features(typename, model_pieces[1], &error_fatal); 1173 g_strfreev(model_pieces); 1174 1175 /* Calculates the limit to CPU APIC ID values 1176 * 1177 * Limit for the APIC ID value, so that all 1178 * CPU APIC IDs are < pcms->apic_id_limit. 1179 * 1180 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1181 */ 1182 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1183 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1184 sizeof(CPUArchId) * max_cpus); 1185 for (i = 0; i < max_cpus; i++) { 1186 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 1187 pcms->possible_cpus->len++; 1188 if (i < smp_cpus) { 1189 cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), 1190 &error_fatal); 1191 object_unref(OBJECT(cpu)); 1192 } 1193 } 1194 1195 /* tell smbios about cpuid version and features */ 1196 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1197 } 1198 1199 static void pc_build_feature_control_file(PCMachineState *pcms) 1200 { 1201 X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); 1202 CPUX86State *env = &cpu->env; 1203 uint32_t unused, ecx, edx; 1204 uint64_t feature_control_bits = 0; 1205 uint64_t *val; 1206 1207 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1208 if (ecx & CPUID_EXT_VMX) { 1209 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1210 } 1211 1212 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1213 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1214 (env->mcg_cap & MCG_LMCE_P)) { 1215 feature_control_bits |= FEATURE_CONTROL_LMCE; 1216 } 1217 1218 if (!feature_control_bits) { 1219 return; 1220 } 1221 1222 val = g_malloc(sizeof(*val)); 1223 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1224 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1225 } 1226 1227 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1228 { 1229 if (cpus_count > 0xff) { 1230 /* If the number of CPUs can't be represented in 8 bits, the 1231 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1232 * to make old BIOSes fail more predictably. 1233 */ 1234 rtc_set_memory(rtc, 0x5f, 0); 1235 } else { 1236 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1237 } 1238 } 1239 1240 static 1241 void pc_machine_done(Notifier *notifier, void *data) 1242 { 1243 PCMachineState *pcms = container_of(notifier, 1244 PCMachineState, machine_done); 1245 PCIBus *bus = pcms->bus; 1246 1247 /* set the number of CPUs */ 1248 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1249 1250 if (bus) { 1251 int extra_hosts = 0; 1252 1253 QLIST_FOREACH(bus, &bus->child, sibling) { 1254 /* look for expander root buses */ 1255 if (pci_bus_is_root(bus)) { 1256 extra_hosts++; 1257 } 1258 } 1259 if (extra_hosts && pcms->fw_cfg) { 1260 uint64_t *val = g_malloc(sizeof(*val)); 1261 *val = cpu_to_le64(extra_hosts); 1262 fw_cfg_add_file(pcms->fw_cfg, 1263 "etc/extra-pci-roots", val, sizeof(*val)); 1264 } 1265 } 1266 1267 acpi_setup(); 1268 if (pcms->fw_cfg) { 1269 pc_build_smbios(pcms->fw_cfg); 1270 pc_build_feature_control_file(pcms); 1271 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1272 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1273 } 1274 1275 if (pcms->apic_id_limit > 255) { 1276 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1277 1278 if (!iommu || !iommu->x86_iommu.intr_supported || 1279 iommu->intr_eim != ON_OFF_AUTO_ON) { 1280 error_report("current -smp configuration requires " 1281 "Extended Interrupt Mode enabled. " 1282 "You can add an IOMMU using: " 1283 "-device intel-iommu,intremap=on,eim=on"); 1284 exit(EXIT_FAILURE); 1285 } 1286 } 1287 } 1288 1289 void pc_guest_info_init(PCMachineState *pcms) 1290 { 1291 int i; 1292 1293 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1294 pcms->numa_nodes = nb_numa_nodes; 1295 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1296 sizeof *pcms->node_mem); 1297 for (i = 0; i < nb_numa_nodes; i++) { 1298 pcms->node_mem[i] = numa_info[i].node_mem; 1299 } 1300 1301 pcms->machine_done.notify = pc_machine_done; 1302 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1303 } 1304 1305 /* setup pci memory address space mapping into system address space */ 1306 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1307 MemoryRegion *pci_address_space) 1308 { 1309 /* Set to lower priority than RAM */ 1310 memory_region_add_subregion_overlap(system_memory, 0x0, 1311 pci_address_space, -1); 1312 } 1313 1314 void pc_acpi_init(const char *default_dsdt) 1315 { 1316 char *filename; 1317 1318 if (acpi_tables != NULL) { 1319 /* manually set via -acpitable, leave it alone */ 1320 return; 1321 } 1322 1323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1324 if (filename == NULL) { 1325 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1326 } else { 1327 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1328 &error_abort); 1329 Error *err = NULL; 1330 1331 qemu_opt_set(opts, "file", filename, &error_abort); 1332 1333 acpi_table_add_builtin(opts, &err); 1334 if (err) { 1335 error_reportf_err(err, "WARNING: failed to load %s: ", 1336 filename); 1337 } 1338 g_free(filename); 1339 } 1340 } 1341 1342 void xen_load_linux(PCMachineState *pcms) 1343 { 1344 int i; 1345 FWCfgState *fw_cfg; 1346 1347 assert(MACHINE(pcms)->kernel_filename != NULL); 1348 1349 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1350 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1351 rom_set_fw(fw_cfg); 1352 1353 load_linux(pcms, fw_cfg); 1354 for (i = 0; i < nb_option_roms; i++) { 1355 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1356 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1357 !strcmp(option_rom[i].name, "multiboot.bin")); 1358 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1359 } 1360 pcms->fw_cfg = fw_cfg; 1361 } 1362 1363 void pc_memory_init(PCMachineState *pcms, 1364 MemoryRegion *system_memory, 1365 MemoryRegion *rom_memory, 1366 MemoryRegion **ram_memory) 1367 { 1368 int linux_boot, i; 1369 MemoryRegion *ram, *option_rom_mr; 1370 MemoryRegion *ram_below_4g, *ram_above_4g; 1371 FWCfgState *fw_cfg; 1372 MachineState *machine = MACHINE(pcms); 1373 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1374 1375 assert(machine->ram_size == pcms->below_4g_mem_size + 1376 pcms->above_4g_mem_size); 1377 1378 linux_boot = (machine->kernel_filename != NULL); 1379 1380 /* Allocate RAM. We allocate it as a single memory region and use 1381 * aliases to address portions of it, mostly for backwards compatibility 1382 * with older qemus that used qemu_ram_alloc(). 1383 */ 1384 ram = g_malloc(sizeof(*ram)); 1385 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1386 machine->ram_size); 1387 *ram_memory = ram; 1388 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1389 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1390 0, pcms->below_4g_mem_size); 1391 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1392 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1393 if (pcms->above_4g_mem_size > 0) { 1394 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1395 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1396 pcms->below_4g_mem_size, 1397 pcms->above_4g_mem_size); 1398 memory_region_add_subregion(system_memory, 0x100000000ULL, 1399 ram_above_4g); 1400 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1401 } 1402 1403 if (!pcmc->has_reserved_memory && 1404 (machine->ram_slots || 1405 (machine->maxram_size > machine->ram_size))) { 1406 MachineClass *mc = MACHINE_GET_CLASS(machine); 1407 1408 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1409 mc->name); 1410 exit(EXIT_FAILURE); 1411 } 1412 1413 /* initialize hotplug memory address space */ 1414 if (pcmc->has_reserved_memory && 1415 (machine->ram_size < machine->maxram_size)) { 1416 ram_addr_t hotplug_mem_size = 1417 machine->maxram_size - machine->ram_size; 1418 1419 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1420 error_report("unsupported amount of memory slots: %"PRIu64, 1421 machine->ram_slots); 1422 exit(EXIT_FAILURE); 1423 } 1424 1425 if (QEMU_ALIGN_UP(machine->maxram_size, 1426 TARGET_PAGE_SIZE) != machine->maxram_size) { 1427 error_report("maximum memory size must by aligned to multiple of " 1428 "%d bytes", TARGET_PAGE_SIZE); 1429 exit(EXIT_FAILURE); 1430 } 1431 1432 pcms->hotplug_memory.base = 1433 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1434 1435 if (pcmc->enforce_aligned_dimm) { 1436 /* size hotplug region assuming 1G page max alignment per slot */ 1437 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1438 } 1439 1440 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1441 hotplug_mem_size) { 1442 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1443 machine->maxram_size); 1444 exit(EXIT_FAILURE); 1445 } 1446 1447 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1448 "hotplug-memory", hotplug_mem_size); 1449 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1450 &pcms->hotplug_memory.mr); 1451 } 1452 1453 /* Initialize PC system firmware */ 1454 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1455 1456 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1457 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1458 &error_fatal); 1459 vmstate_register_ram_global(option_rom_mr); 1460 memory_region_add_subregion_overlap(rom_memory, 1461 PC_ROM_MIN_VGA, 1462 option_rom_mr, 1463 1); 1464 1465 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1466 1467 rom_set_fw(fw_cfg); 1468 1469 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { 1470 uint64_t *val = g_malloc(sizeof(*val)); 1471 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1472 uint64_t res_mem_end = pcms->hotplug_memory.base; 1473 1474 if (!pcmc->broken_reserved_end) { 1475 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1476 } 1477 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1478 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1479 } 1480 1481 if (linux_boot) { 1482 load_linux(pcms, fw_cfg); 1483 } 1484 1485 for (i = 0; i < nb_option_roms; i++) { 1486 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1487 } 1488 pcms->fw_cfg = fw_cfg; 1489 1490 /* Init default IOAPIC address space */ 1491 pcms->ioapic_as = &address_space_memory; 1492 } 1493 1494 qemu_irq pc_allocate_cpu_irq(void) 1495 { 1496 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1497 } 1498 1499 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1500 { 1501 DeviceState *dev = NULL; 1502 1503 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1504 if (pci_bus) { 1505 PCIDevice *pcidev = pci_vga_init(pci_bus); 1506 dev = pcidev ? &pcidev->qdev : NULL; 1507 } else if (isa_bus) { 1508 ISADevice *isadev = isa_vga_init(isa_bus); 1509 dev = isadev ? DEVICE(isadev) : NULL; 1510 } 1511 rom_reset_order_override(); 1512 return dev; 1513 } 1514 1515 static const MemoryRegionOps ioport80_io_ops = { 1516 .write = ioport80_write, 1517 .read = ioport80_read, 1518 .endianness = DEVICE_NATIVE_ENDIAN, 1519 .impl = { 1520 .min_access_size = 1, 1521 .max_access_size = 1, 1522 }, 1523 }; 1524 1525 static const MemoryRegionOps ioportF0_io_ops = { 1526 .write = ioportF0_write, 1527 .read = ioportF0_read, 1528 .endianness = DEVICE_NATIVE_ENDIAN, 1529 .impl = { 1530 .min_access_size = 1, 1531 .max_access_size = 1, 1532 }, 1533 }; 1534 1535 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1536 ISADevice **rtc_state, 1537 bool create_fdctrl, 1538 bool no_vmport, 1539 bool has_pit, 1540 uint32_t hpet_irqs) 1541 { 1542 int i; 1543 DriveInfo *fd[MAX_FD]; 1544 DeviceState *hpet = NULL; 1545 int pit_isa_irq = 0; 1546 qemu_irq pit_alt_irq = NULL; 1547 qemu_irq rtc_irq = NULL; 1548 qemu_irq *a20_line; 1549 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1550 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1551 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1552 1553 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1554 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1555 1556 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1557 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1558 1559 /* 1560 * Check if an HPET shall be created. 1561 * 1562 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1563 * when the HPET wants to take over. Thus we have to disable the latter. 1564 */ 1565 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1566 /* In order to set property, here not using sysbus_try_create_simple */ 1567 hpet = qdev_try_create(NULL, TYPE_HPET); 1568 if (hpet) { 1569 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1570 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1571 * IRQ8 and IRQ2. 1572 */ 1573 uint8_t compat = object_property_get_int(OBJECT(hpet), 1574 HPET_INTCAP, NULL); 1575 if (!compat) { 1576 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1577 } 1578 qdev_init_nofail(hpet); 1579 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1580 1581 for (i = 0; i < GSI_NUM_PINS; i++) { 1582 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1583 } 1584 pit_isa_irq = -1; 1585 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1586 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1587 } 1588 } 1589 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1590 1591 qemu_register_boot_set(pc_boot_set, *rtc_state); 1592 1593 if (!xen_enabled() && has_pit) { 1594 if (kvm_pit_in_kernel()) { 1595 pit = kvm_pit_init(isa_bus, 0x40); 1596 } else { 1597 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1598 } 1599 if (hpet) { 1600 /* connect PIT to output control line of the HPET */ 1601 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1602 } 1603 pcspk_init(isa_bus, pit); 1604 } 1605 1606 serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); 1607 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1608 1609 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1610 i8042 = isa_create_simple(isa_bus, "i8042"); 1611 i8042_setup_a20_line(i8042, a20_line[0]); 1612 if (!no_vmport) { 1613 vmport_init(isa_bus); 1614 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1615 } else { 1616 vmmouse = NULL; 1617 } 1618 if (vmmouse) { 1619 DeviceState *dev = DEVICE(vmmouse); 1620 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1621 qdev_init_nofail(dev); 1622 } 1623 port92 = isa_create_simple(isa_bus, "port92"); 1624 port92_init(port92, a20_line[1]); 1625 g_free(a20_line); 1626 1627 DMA_init(isa_bus, 0); 1628 1629 for(i = 0; i < MAX_FD; i++) { 1630 fd[i] = drive_get(IF_FLOPPY, 0, i); 1631 create_fdctrl |= !!fd[i]; 1632 } 1633 if (create_fdctrl) { 1634 fdctrl_init_isa(isa_bus, fd); 1635 } 1636 } 1637 1638 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1639 { 1640 int i; 1641 1642 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1643 for (i = 0; i < nb_nics; i++) { 1644 NICInfo *nd = &nd_table[i]; 1645 1646 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1647 pc_init_ne2k_isa(isa_bus, nd); 1648 } else { 1649 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1650 } 1651 } 1652 rom_reset_order_override(); 1653 } 1654 1655 void pc_pci_device_init(PCIBus *pci_bus) 1656 { 1657 int max_bus; 1658 int bus; 1659 1660 max_bus = drive_get_max_bus(IF_SCSI); 1661 for (bus = 0; bus <= max_bus; bus++) { 1662 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1663 } 1664 } 1665 1666 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1667 { 1668 DeviceState *dev; 1669 SysBusDevice *d; 1670 unsigned int i; 1671 1672 if (kvm_ioapic_in_kernel()) { 1673 dev = qdev_create(NULL, "kvm-ioapic"); 1674 } else { 1675 dev = qdev_create(NULL, "ioapic"); 1676 } 1677 if (parent_name) { 1678 object_property_add_child(object_resolve_path(parent_name, NULL), 1679 "ioapic", OBJECT(dev), NULL); 1680 } 1681 qdev_init_nofail(dev); 1682 d = SYS_BUS_DEVICE(dev); 1683 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1684 1685 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1686 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1687 } 1688 } 1689 1690 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1691 DeviceState *dev, Error **errp) 1692 { 1693 HotplugHandlerClass *hhc; 1694 Error *local_err = NULL; 1695 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1696 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1697 PCDIMMDevice *dimm = PC_DIMM(dev); 1698 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1699 MemoryRegion *mr = ddc->get_memory_region(dimm); 1700 uint64_t align = TARGET_PAGE_SIZE; 1701 1702 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1703 align = memory_region_get_alignment(mr); 1704 } 1705 1706 if (!pcms->acpi_dev) { 1707 error_setg(&local_err, 1708 "memory hotplug is not enabled: missing acpi device"); 1709 goto out; 1710 } 1711 1712 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1713 if (local_err) { 1714 goto out; 1715 } 1716 1717 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1718 nvdimm_plug(&pcms->acpi_nvdimm_state); 1719 } 1720 1721 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1722 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1723 out: 1724 error_propagate(errp, local_err); 1725 } 1726 1727 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1728 DeviceState *dev, Error **errp) 1729 { 1730 HotplugHandlerClass *hhc; 1731 Error *local_err = NULL; 1732 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1733 1734 if (!pcms->acpi_dev) { 1735 error_setg(&local_err, 1736 "memory hotplug is not enabled: missing acpi device"); 1737 goto out; 1738 } 1739 1740 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1741 error_setg(&local_err, 1742 "nvdimm device hot unplug is not supported yet."); 1743 goto out; 1744 } 1745 1746 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1747 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1748 1749 out: 1750 error_propagate(errp, local_err); 1751 } 1752 1753 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1754 DeviceState *dev, Error **errp) 1755 { 1756 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1757 PCDIMMDevice *dimm = PC_DIMM(dev); 1758 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1759 MemoryRegion *mr = ddc->get_memory_region(dimm); 1760 HotplugHandlerClass *hhc; 1761 Error *local_err = NULL; 1762 1763 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1764 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1765 1766 if (local_err) { 1767 goto out; 1768 } 1769 1770 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1771 object_unparent(OBJECT(dev)); 1772 1773 out: 1774 error_propagate(errp, local_err); 1775 } 1776 1777 static int pc_apic_cmp(const void *a, const void *b) 1778 { 1779 CPUArchId *apic_a = (CPUArchId *)a; 1780 CPUArchId *apic_b = (CPUArchId *)b; 1781 1782 return apic_a->arch_id - apic_b->arch_id; 1783 } 1784 1785 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1786 * in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no 1787 * entry correponding to CPU's apic_id returns NULL. 1788 */ 1789 static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu, 1790 int *idx) 1791 { 1792 CPUClass *cc = CPU_GET_CLASS(cpu); 1793 CPUArchId apic_id, *found_cpu; 1794 1795 apic_id.arch_id = cc->get_arch_id(CPU(cpu)); 1796 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, 1797 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), 1798 pc_apic_cmp); 1799 if (found_cpu && idx) { 1800 *idx = found_cpu - pcms->possible_cpus->cpus; 1801 } 1802 return found_cpu; 1803 } 1804 1805 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1806 DeviceState *dev, Error **errp) 1807 { 1808 CPUArchId *found_cpu; 1809 HotplugHandlerClass *hhc; 1810 Error *local_err = NULL; 1811 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1812 1813 if (pcms->acpi_dev) { 1814 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1815 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1816 if (local_err) { 1817 goto out; 1818 } 1819 } 1820 1821 /* increment the number of CPUs */ 1822 pcms->boot_cpus++; 1823 if (dev->hotplugged) { 1824 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1825 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1826 } 1827 1828 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); 1829 found_cpu->cpu = CPU(dev); 1830 out: 1831 error_propagate(errp, local_err); 1832 } 1833 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1834 DeviceState *dev, Error **errp) 1835 { 1836 int idx = -1; 1837 HotplugHandlerClass *hhc; 1838 Error *local_err = NULL; 1839 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1840 1841 pc_find_cpu_slot(pcms, CPU(dev), &idx); 1842 assert(idx != -1); 1843 if (idx == 0) { 1844 error_setg(&local_err, "Boot CPU is unpluggable"); 1845 goto out; 1846 } 1847 1848 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1849 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1850 1851 if (local_err) { 1852 goto out; 1853 } 1854 1855 out: 1856 error_propagate(errp, local_err); 1857 1858 } 1859 1860 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1861 DeviceState *dev, Error **errp) 1862 { 1863 CPUArchId *found_cpu; 1864 HotplugHandlerClass *hhc; 1865 Error *local_err = NULL; 1866 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1867 1868 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1869 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1870 1871 if (local_err) { 1872 goto out; 1873 } 1874 1875 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); 1876 found_cpu->cpu = NULL; 1877 object_unparent(OBJECT(dev)); 1878 1879 /* decrement the number of CPUs */ 1880 pcms->boot_cpus--; 1881 /* Update the number of CPUs in CMOS */ 1882 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1883 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1884 out: 1885 error_propagate(errp, local_err); 1886 } 1887 1888 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1889 DeviceState *dev, Error **errp) 1890 { 1891 int idx; 1892 CPUState *cs; 1893 CPUArchId *cpu_slot; 1894 X86CPUTopoInfo topo; 1895 X86CPU *cpu = X86_CPU(dev); 1896 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1897 1898 /* if APIC ID is not set, set it based on socket/core/thread properties */ 1899 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1900 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 1901 1902 if (cpu->socket_id < 0) { 1903 error_setg(errp, "CPU socket-id is not set"); 1904 return; 1905 } else if (cpu->socket_id > max_socket) { 1906 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1907 cpu->socket_id, max_socket); 1908 return; 1909 } 1910 if (cpu->core_id < 0) { 1911 error_setg(errp, "CPU core-id is not set"); 1912 return; 1913 } else if (cpu->core_id > (smp_cores - 1)) { 1914 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1915 cpu->core_id, smp_cores - 1); 1916 return; 1917 } 1918 if (cpu->thread_id < 0) { 1919 error_setg(errp, "CPU thread-id is not set"); 1920 return; 1921 } else if (cpu->thread_id > (smp_threads - 1)) { 1922 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1923 cpu->thread_id, smp_threads - 1); 1924 return; 1925 } 1926 1927 topo.pkg_id = cpu->socket_id; 1928 topo.core_id = cpu->core_id; 1929 topo.smt_id = cpu->thread_id; 1930 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 1931 } 1932 1933 cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx); 1934 if (!cpu_slot) { 1935 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1936 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 1937 " APIC ID %" PRIu32 ", valid index range 0:%d", 1938 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 1939 pcms->possible_cpus->len - 1); 1940 return; 1941 } 1942 1943 if (cpu_slot->cpu) { 1944 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1945 idx, cpu->apic_id); 1946 return; 1947 } 1948 1949 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1950 * so that query_hotpluggable_cpus would show correct values 1951 */ 1952 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1953 * once -smp refactoring is complete and there will be CPU private 1954 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1955 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1956 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1957 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1958 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1959 return; 1960 } 1961 cpu->socket_id = topo.pkg_id; 1962 1963 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1964 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1965 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1966 return; 1967 } 1968 cpu->core_id = topo.core_id; 1969 1970 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1971 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1972 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1973 return; 1974 } 1975 cpu->thread_id = topo.smt_id; 1976 1977 cs = CPU(cpu); 1978 cs->cpu_index = idx; 1979 } 1980 1981 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1982 DeviceState *dev, Error **errp) 1983 { 1984 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1985 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1986 } 1987 } 1988 1989 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1990 DeviceState *dev, Error **errp) 1991 { 1992 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1993 pc_dimm_plug(hotplug_dev, dev, errp); 1994 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1995 pc_cpu_plug(hotplug_dev, dev, errp); 1996 } 1997 } 1998 1999 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2000 DeviceState *dev, Error **errp) 2001 { 2002 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2003 pc_dimm_unplug_request(hotplug_dev, dev, errp); 2004 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2005 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2006 } else { 2007 error_setg(errp, "acpi: device unplug request for not supported device" 2008 " type: %s", object_get_typename(OBJECT(dev))); 2009 } 2010 } 2011 2012 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2013 DeviceState *dev, Error **errp) 2014 { 2015 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2016 pc_dimm_unplug(hotplug_dev, dev, errp); 2017 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2018 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2019 } else { 2020 error_setg(errp, "acpi: device unplug for not supported device" 2021 " type: %s", object_get_typename(OBJECT(dev))); 2022 } 2023 } 2024 2025 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 2026 DeviceState *dev) 2027 { 2028 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 2029 2030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2031 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2032 return HOTPLUG_HANDLER(machine); 2033 } 2034 2035 return pcmc->get_hotplug_handler ? 2036 pcmc->get_hotplug_handler(machine, dev) : NULL; 2037 } 2038 2039 static void 2040 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, 2041 const char *name, void *opaque, 2042 Error **errp) 2043 { 2044 PCMachineState *pcms = PC_MACHINE(obj); 2045 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 2046 2047 visit_type_int(v, name, &value, errp); 2048 } 2049 2050 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2051 const char *name, void *opaque, 2052 Error **errp) 2053 { 2054 PCMachineState *pcms = PC_MACHINE(obj); 2055 uint64_t value = pcms->max_ram_below_4g; 2056 2057 visit_type_size(v, name, &value, errp); 2058 } 2059 2060 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2061 const char *name, void *opaque, 2062 Error **errp) 2063 { 2064 PCMachineState *pcms = PC_MACHINE(obj); 2065 Error *error = NULL; 2066 uint64_t value; 2067 2068 visit_type_size(v, name, &value, &error); 2069 if (error) { 2070 error_propagate(errp, error); 2071 return; 2072 } 2073 if (value > (1ULL << 32)) { 2074 error_setg(&error, 2075 "Machine option 'max-ram-below-4g=%"PRIu64 2076 "' expects size less than or equal to 4G", value); 2077 error_propagate(errp, error); 2078 return; 2079 } 2080 2081 if (value < (1ULL << 20)) { 2082 error_report("Warning: small max_ram_below_4g(%"PRIu64 2083 ") less than 1M. BIOS may not work..", 2084 value); 2085 } 2086 2087 pcms->max_ram_below_4g = value; 2088 } 2089 2090 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2091 void *opaque, Error **errp) 2092 { 2093 PCMachineState *pcms = PC_MACHINE(obj); 2094 OnOffAuto vmport = pcms->vmport; 2095 2096 visit_type_OnOffAuto(v, name, &vmport, errp); 2097 } 2098 2099 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2100 void *opaque, Error **errp) 2101 { 2102 PCMachineState *pcms = PC_MACHINE(obj); 2103 2104 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2105 } 2106 2107 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2108 { 2109 bool smm_available = false; 2110 2111 if (pcms->smm == ON_OFF_AUTO_OFF) { 2112 return false; 2113 } 2114 2115 if (tcg_enabled() || qtest_enabled()) { 2116 smm_available = true; 2117 } else if (kvm_enabled()) { 2118 smm_available = kvm_has_smm(); 2119 } 2120 2121 if (smm_available) { 2122 return true; 2123 } 2124 2125 if (pcms->smm == ON_OFF_AUTO_ON) { 2126 error_report("System Management Mode not supported by this hypervisor."); 2127 exit(1); 2128 } 2129 return false; 2130 } 2131 2132 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2133 void *opaque, Error **errp) 2134 { 2135 PCMachineState *pcms = PC_MACHINE(obj); 2136 OnOffAuto smm = pcms->smm; 2137 2138 visit_type_OnOffAuto(v, name, &smm, errp); 2139 } 2140 2141 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2142 void *opaque, Error **errp) 2143 { 2144 PCMachineState *pcms = PC_MACHINE(obj); 2145 2146 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2147 } 2148 2149 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2150 { 2151 PCMachineState *pcms = PC_MACHINE(obj); 2152 2153 return pcms->acpi_nvdimm_state.is_enabled; 2154 } 2155 2156 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2157 { 2158 PCMachineState *pcms = PC_MACHINE(obj); 2159 2160 pcms->acpi_nvdimm_state.is_enabled = value; 2161 } 2162 2163 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2164 { 2165 PCMachineState *pcms = PC_MACHINE(obj); 2166 2167 return pcms->smbus; 2168 } 2169 2170 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2171 { 2172 PCMachineState *pcms = PC_MACHINE(obj); 2173 2174 pcms->smbus = value; 2175 } 2176 2177 static bool pc_machine_get_sata(Object *obj, Error **errp) 2178 { 2179 PCMachineState *pcms = PC_MACHINE(obj); 2180 2181 return pcms->sata; 2182 } 2183 2184 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2185 { 2186 PCMachineState *pcms = PC_MACHINE(obj); 2187 2188 pcms->sata = value; 2189 } 2190 2191 static bool pc_machine_get_pit(Object *obj, Error **errp) 2192 { 2193 PCMachineState *pcms = PC_MACHINE(obj); 2194 2195 return pcms->pit; 2196 } 2197 2198 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2199 { 2200 PCMachineState *pcms = PC_MACHINE(obj); 2201 2202 pcms->pit = value; 2203 } 2204 2205 static void pc_machine_initfn(Object *obj) 2206 { 2207 PCMachineState *pcms = PC_MACHINE(obj); 2208 2209 pcms->max_ram_below_4g = 0; /* use default */ 2210 pcms->smm = ON_OFF_AUTO_AUTO; 2211 pcms->vmport = ON_OFF_AUTO_AUTO; 2212 /* nvdimm is disabled on default. */ 2213 pcms->acpi_nvdimm_state.is_enabled = false; 2214 /* acpi build is enabled by default if machine supports it */ 2215 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2216 pcms->smbus = true; 2217 pcms->sata = true; 2218 pcms->pit = true; 2219 } 2220 2221 static void pc_machine_reset(void) 2222 { 2223 CPUState *cs; 2224 X86CPU *cpu; 2225 2226 qemu_devices_reset(); 2227 2228 /* Reset APIC after devices have been reset to cancel 2229 * any changes that qemu_devices_reset() might have done. 2230 */ 2231 CPU_FOREACH(cs) { 2232 cpu = X86_CPU(cs); 2233 2234 if (cpu->apic_state) { 2235 device_reset(cpu->apic_state); 2236 } 2237 } 2238 } 2239 2240 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 2241 { 2242 X86CPUTopoInfo topo; 2243 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 2244 &topo); 2245 return topo.pkg_id; 2246 } 2247 2248 static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) 2249 { 2250 PCMachineState *pcms = PC_MACHINE(machine); 2251 int len = sizeof(CPUArchIdList) + 2252 sizeof(CPUArchId) * (pcms->possible_cpus->len); 2253 CPUArchIdList *list = g_malloc(len); 2254 2255 memcpy(list, pcms->possible_cpus, len); 2256 return list; 2257 } 2258 2259 static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine) 2260 { 2261 int i; 2262 CPUState *cpu; 2263 HotpluggableCPUList *head = NULL; 2264 PCMachineState *pcms = PC_MACHINE(machine); 2265 const char *cpu_type; 2266 2267 cpu = pcms->possible_cpus->cpus[0].cpu; 2268 assert(cpu); /* BSP is always present */ 2269 cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu))); 2270 2271 for (i = 0; i < pcms->possible_cpus->len; i++) { 2272 X86CPUTopoInfo topo; 2273 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2274 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2275 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2276 const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id; 2277 2278 x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo); 2279 2280 cpu_item->type = g_strdup(cpu_type); 2281 cpu_item->vcpus_count = 1; 2282 cpu_props->has_socket_id = true; 2283 cpu_props->socket_id = topo.pkg_id; 2284 cpu_props->has_core_id = true; 2285 cpu_props->core_id = topo.core_id; 2286 cpu_props->has_thread_id = true; 2287 cpu_props->thread_id = topo.smt_id; 2288 cpu_item->props = cpu_props; 2289 2290 cpu = pcms->possible_cpus->cpus[i].cpu; 2291 if (cpu) { 2292 cpu_item->has_qom_path = true; 2293 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 2294 } 2295 2296 list_item->value = cpu_item; 2297 list_item->next = head; 2298 head = list_item; 2299 } 2300 return head; 2301 } 2302 2303 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2304 { 2305 /* cpu index isn't used */ 2306 CPUState *cs; 2307 2308 CPU_FOREACH(cs) { 2309 X86CPU *cpu = X86_CPU(cs); 2310 2311 if (!cpu->apic_state) { 2312 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2313 } else { 2314 apic_deliver_nmi(cpu->apic_state); 2315 } 2316 } 2317 } 2318 2319 static void pc_machine_class_init(ObjectClass *oc, void *data) 2320 { 2321 MachineClass *mc = MACHINE_CLASS(oc); 2322 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2323 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2324 NMIClass *nc = NMI_CLASS(oc); 2325 2326 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 2327 pcmc->pci_enabled = true; 2328 pcmc->has_acpi_build = true; 2329 pcmc->rsdp_in_ram = true; 2330 pcmc->smbios_defaults = true; 2331 pcmc->smbios_uuid_encoded = true; 2332 pcmc->gigabyte_align = true; 2333 pcmc->has_reserved_memory = true; 2334 pcmc->kvmclock_enabled = true; 2335 pcmc->enforce_aligned_dimm = true; 2336 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2337 * to be used at the moment, 32K should be enough for a while. */ 2338 pcmc->acpi_data_size = 0x20000 + 0x8000; 2339 pcmc->save_tsc_khz = true; 2340 mc->get_hotplug_handler = pc_get_hotpug_handler; 2341 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 2342 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2343 mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus; 2344 mc->default_boot_order = "cad"; 2345 mc->hot_add_cpu = pc_hot_add_cpu; 2346 mc->max_cpus = 255; 2347 mc->reset = pc_machine_reset; 2348 hc->pre_plug = pc_machine_device_pre_plug_cb; 2349 hc->plug = pc_machine_device_plug_cb; 2350 hc->unplug_request = pc_machine_device_unplug_request_cb; 2351 hc->unplug = pc_machine_device_unplug_cb; 2352 nc->nmi_monitor_handler = x86_nmi; 2353 2354 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", 2355 pc_machine_get_hotplug_memory_region_size, NULL, 2356 NULL, NULL, &error_abort); 2357 2358 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2359 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2360 NULL, NULL, &error_abort); 2361 2362 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2363 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2364 2365 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2366 pc_machine_get_smm, pc_machine_set_smm, 2367 NULL, NULL, &error_abort); 2368 object_class_property_set_description(oc, PC_MACHINE_SMM, 2369 "Enable SMM (pc & q35)", &error_abort); 2370 2371 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2372 pc_machine_get_vmport, pc_machine_set_vmport, 2373 NULL, NULL, &error_abort); 2374 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2375 "Enable vmport (pc & q35)", &error_abort); 2376 2377 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, 2378 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); 2379 2380 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2381 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2382 2383 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2384 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2385 2386 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2387 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2388 } 2389 2390 static const TypeInfo pc_machine_info = { 2391 .name = TYPE_PC_MACHINE, 2392 .parent = TYPE_MACHINE, 2393 .abstract = true, 2394 .instance_size = sizeof(PCMachineState), 2395 .instance_init = pc_machine_initfn, 2396 .class_size = sizeof(PCMachineClass), 2397 .class_init = pc_machine_class_init, 2398 .interfaces = (InterfaceInfo[]) { 2399 { TYPE_HOTPLUG_HANDLER }, 2400 { TYPE_NMI }, 2401 { } 2402 }, 2403 }; 2404 2405 static void pc_machine_register_types(void) 2406 { 2407 type_register_static(&pc_machine_info); 2408 } 2409 2410 type_init(pc_machine_register_types) 2411