1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/cpu/icc_bus.h" 57 #include "hw/boards.h" 58 #include "hw/pci/pci_host.h" 59 #include "acpi-build.h" 60 61 /* debug PC/ISA interrupts */ 62 //#define DEBUG_IRQ 63 64 #ifdef DEBUG_IRQ 65 #define DPRINTF(fmt, ...) \ 66 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 67 #else 68 #define DPRINTF(fmt, ...) 69 #endif 70 71 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 72 #define ACPI_DATA_SIZE 0x10000 73 #define BIOS_CFG_IOPORT 0x510 74 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 75 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 76 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 77 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 78 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 79 80 #define E820_NR_ENTRIES 16 81 82 struct e820_entry { 83 uint64_t address; 84 uint64_t length; 85 uint32_t type; 86 } QEMU_PACKED __attribute((__aligned__(4))); 87 88 struct e820_table { 89 uint32_t count; 90 struct e820_entry entry[E820_NR_ENTRIES]; 91 } QEMU_PACKED __attribute((__aligned__(4))); 92 93 static struct e820_table e820_reserve; 94 static struct e820_entry *e820_table; 95 static unsigned e820_entries; 96 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 97 98 void gsi_handler(void *opaque, int n, int level) 99 { 100 GSIState *s = opaque; 101 102 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 103 if (n < ISA_NUM_IRQS) { 104 qemu_set_irq(s->i8259_irq[n], level); 105 } 106 qemu_set_irq(s->ioapic_irq[n], level); 107 } 108 109 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 110 unsigned size) 111 { 112 } 113 114 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 115 { 116 return 0xffffffffffffffffULL; 117 } 118 119 /* MSDOS compatibility mode FPU exception support */ 120 static qemu_irq ferr_irq; 121 122 void pc_register_ferr_irq(qemu_irq irq) 123 { 124 ferr_irq = irq; 125 } 126 127 /* XXX: add IGNNE support */ 128 void cpu_set_ferr(CPUX86State *s) 129 { 130 qemu_irq_raise(ferr_irq); 131 } 132 133 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 134 unsigned size) 135 { 136 qemu_irq_lower(ferr_irq); 137 } 138 139 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 140 { 141 return 0xffffffffffffffffULL; 142 } 143 144 /* TSC handling */ 145 uint64_t cpu_get_tsc(CPUX86State *env) 146 { 147 return cpu_get_ticks(); 148 } 149 150 /* SMM support */ 151 152 static cpu_set_smm_t smm_set; 153 static void *smm_arg; 154 155 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 156 { 157 assert(smm_set == NULL); 158 assert(smm_arg == NULL); 159 smm_set = callback; 160 smm_arg = arg; 161 } 162 163 void cpu_smm_update(CPUX86State *env) 164 { 165 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 166 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 167 } 168 } 169 170 171 /* IRQ handling */ 172 int cpu_get_pic_interrupt(CPUX86State *env) 173 { 174 int intno; 175 176 intno = apic_get_interrupt(env->apic_state); 177 if (intno >= 0) { 178 return intno; 179 } 180 /* read the irq from the PIC */ 181 if (!apic_accept_pic_intr(env->apic_state)) { 182 return -1; 183 } 184 185 intno = pic_read_irq(isa_pic); 186 return intno; 187 } 188 189 static void pic_irq_request(void *opaque, int irq, int level) 190 { 191 CPUState *cs = first_cpu; 192 X86CPU *cpu = X86_CPU(cs); 193 CPUX86State *env = &cpu->env; 194 195 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 196 if (env->apic_state) { 197 CPU_FOREACH(cs) { 198 cpu = X86_CPU(cs); 199 env = &cpu->env; 200 if (apic_accept_pic_intr(env->apic_state)) { 201 apic_deliver_pic_intr(env->apic_state, level); 202 } 203 } 204 } else { 205 if (level) { 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } else { 208 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 209 } 210 } 211 } 212 213 /* PC cmos mappings */ 214 215 #define REG_EQUIPMENT_BYTE 0x14 216 217 static int cmos_get_fd_drive_type(FDriveType fd0) 218 { 219 int val; 220 221 switch (fd0) { 222 case FDRIVE_DRV_144: 223 /* 1.44 Mb 3"5 drive */ 224 val = 4; 225 break; 226 case FDRIVE_DRV_288: 227 /* 2.88 Mb 3"5 drive */ 228 val = 5; 229 break; 230 case FDRIVE_DRV_120: 231 /* 1.2 Mb 5"5 drive */ 232 val = 2; 233 break; 234 case FDRIVE_DRV_NONE: 235 default: 236 val = 0; 237 break; 238 } 239 return val; 240 } 241 242 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 243 int16_t cylinders, int8_t heads, int8_t sectors) 244 { 245 rtc_set_memory(s, type_ofs, 47); 246 rtc_set_memory(s, info_ofs, cylinders); 247 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 2, heads); 249 rtc_set_memory(s, info_ofs + 3, 0xff); 250 rtc_set_memory(s, info_ofs + 4, 0xff); 251 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 252 rtc_set_memory(s, info_ofs + 6, cylinders); 253 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 254 rtc_set_memory(s, info_ofs + 8, sectors); 255 } 256 257 /* convert boot_device letter to something recognizable by the bios */ 258 static int boot_device2nibble(char boot_device) 259 { 260 switch(boot_device) { 261 case 'a': 262 case 'b': 263 return 0x01; /* floppy boot */ 264 case 'c': 265 return 0x02; /* hard drive boot */ 266 case 'd': 267 return 0x03; /* CD-ROM boot */ 268 case 'n': 269 return 0x04; /* Network boot */ 270 } 271 return 0; 272 } 273 274 static int set_boot_dev(ISADevice *s, const char *boot_device) 275 { 276 #define PC_MAX_BOOT_DEVICES 3 277 int nbds, bds[3] = { 0, }; 278 int i; 279 280 nbds = strlen(boot_device); 281 if (nbds > PC_MAX_BOOT_DEVICES) { 282 error_report("Too many boot devices for PC"); 283 return(1); 284 } 285 for (i = 0; i < nbds; i++) { 286 bds[i] = boot_device2nibble(boot_device[i]); 287 if (bds[i] == 0) { 288 error_report("Invalid boot device for PC: '%c'", 289 boot_device[i]); 290 return(1); 291 } 292 } 293 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 294 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 295 return(0); 296 } 297 298 static int pc_boot_set(void *opaque, const char *boot_device) 299 { 300 return set_boot_dev(opaque, boot_device); 301 } 302 303 typedef struct pc_cmos_init_late_arg { 304 ISADevice *rtc_state; 305 BusState *idebus[2]; 306 } pc_cmos_init_late_arg; 307 308 static void pc_cmos_init_late(void *opaque) 309 { 310 pc_cmos_init_late_arg *arg = opaque; 311 ISADevice *s = arg->rtc_state; 312 int16_t cylinders; 313 int8_t heads, sectors; 314 int val; 315 int i, trans; 316 317 val = 0; 318 if (ide_get_geometry(arg->idebus[0], 0, 319 &cylinders, &heads, §ors) >= 0) { 320 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 321 val |= 0xf0; 322 } 323 if (ide_get_geometry(arg->idebus[0], 1, 324 &cylinders, &heads, §ors) >= 0) { 325 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 326 val |= 0x0f; 327 } 328 rtc_set_memory(s, 0x12, val); 329 330 val = 0; 331 for (i = 0; i < 4; i++) { 332 /* NOTE: ide_get_geometry() returns the physical 333 geometry. It is always such that: 1 <= sects <= 63, 1 334 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 335 geometry can be different if a translation is done. */ 336 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 337 &cylinders, &heads, §ors) >= 0) { 338 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 339 assert((trans & ~3) == 0); 340 val |= trans << (i * 2); 341 } 342 } 343 rtc_set_memory(s, 0x39, val); 344 345 qemu_unregister_reset(pc_cmos_init_late, opaque); 346 } 347 348 typedef struct RTCCPUHotplugArg { 349 Notifier cpu_added_notifier; 350 ISADevice *rtc_state; 351 } RTCCPUHotplugArg; 352 353 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 354 { 355 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 356 cpu_added_notifier); 357 ISADevice *s = arg->rtc_state; 358 359 /* increment the number of CPUs */ 360 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 361 } 362 363 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 364 const char *boot_device, 365 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 366 ISADevice *s) 367 { 368 int val, nb, i; 369 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 370 static pc_cmos_init_late_arg arg; 371 static RTCCPUHotplugArg cpu_hotplug_cb; 372 373 /* various important CMOS locations needed by PC/Bochs bios */ 374 375 /* memory size */ 376 /* base memory (first MiB) */ 377 val = MIN(ram_size / 1024, 640); 378 rtc_set_memory(s, 0x15, val); 379 rtc_set_memory(s, 0x16, val >> 8); 380 /* extended memory (next 64MiB) */ 381 if (ram_size > 1024 * 1024) { 382 val = (ram_size - 1024 * 1024) / 1024; 383 } else { 384 val = 0; 385 } 386 if (val > 65535) 387 val = 65535; 388 rtc_set_memory(s, 0x17, val); 389 rtc_set_memory(s, 0x18, val >> 8); 390 rtc_set_memory(s, 0x30, val); 391 rtc_set_memory(s, 0x31, val >> 8); 392 /* memory between 16MiB and 4GiB */ 393 if (ram_size > 16 * 1024 * 1024) { 394 val = (ram_size - 16 * 1024 * 1024) / 65536; 395 } else { 396 val = 0; 397 } 398 if (val > 65535) 399 val = 65535; 400 rtc_set_memory(s, 0x34, val); 401 rtc_set_memory(s, 0x35, val >> 8); 402 /* memory above 4GiB */ 403 val = above_4g_mem_size / 65536; 404 rtc_set_memory(s, 0x5b, val); 405 rtc_set_memory(s, 0x5c, val >> 8); 406 rtc_set_memory(s, 0x5d, val >> 16); 407 408 /* set the number of CPU */ 409 rtc_set_memory(s, 0x5f, smp_cpus - 1); 410 /* init CPU hotplug notifier */ 411 cpu_hotplug_cb.rtc_state = s; 412 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 413 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 414 415 if (set_boot_dev(s, boot_device)) { 416 exit(1); 417 } 418 419 /* floppy type */ 420 if (floppy) { 421 for (i = 0; i < 2; i++) { 422 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 423 } 424 } 425 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 426 cmos_get_fd_drive_type(fd_type[1]); 427 rtc_set_memory(s, 0x10, val); 428 429 val = 0; 430 nb = 0; 431 if (fd_type[0] < FDRIVE_DRV_NONE) { 432 nb++; 433 } 434 if (fd_type[1] < FDRIVE_DRV_NONE) { 435 nb++; 436 } 437 switch (nb) { 438 case 0: 439 break; 440 case 1: 441 val |= 0x01; /* 1 drive, ready for boot */ 442 break; 443 case 2: 444 val |= 0x41; /* 2 drives, ready for boot */ 445 break; 446 } 447 val |= 0x02; /* FPU is there */ 448 val |= 0x04; /* PS/2 mouse installed */ 449 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 450 451 /* hard drives */ 452 arg.rtc_state = s; 453 arg.idebus[0] = idebus0; 454 arg.idebus[1] = idebus1; 455 qemu_register_reset(pc_cmos_init_late, &arg); 456 } 457 458 #define TYPE_PORT92 "port92" 459 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 460 461 /* port 92 stuff: could be split off */ 462 typedef struct Port92State { 463 ISADevice parent_obj; 464 465 MemoryRegion io; 466 uint8_t outport; 467 qemu_irq *a20_out; 468 } Port92State; 469 470 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 471 unsigned size) 472 { 473 Port92State *s = opaque; 474 475 DPRINTF("port92: write 0x%02x\n", val); 476 s->outport = val; 477 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 478 if (val & 1) { 479 qemu_system_reset_request(); 480 } 481 } 482 483 static uint64_t port92_read(void *opaque, hwaddr addr, 484 unsigned size) 485 { 486 Port92State *s = opaque; 487 uint32_t ret; 488 489 ret = s->outport; 490 DPRINTF("port92: read 0x%02x\n", ret); 491 return ret; 492 } 493 494 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 495 { 496 Port92State *s = PORT92(dev); 497 498 s->a20_out = a20_out; 499 } 500 501 static const VMStateDescription vmstate_port92_isa = { 502 .name = "port92", 503 .version_id = 1, 504 .minimum_version_id = 1, 505 .minimum_version_id_old = 1, 506 .fields = (VMStateField []) { 507 VMSTATE_UINT8(outport, Port92State), 508 VMSTATE_END_OF_LIST() 509 } 510 }; 511 512 static void port92_reset(DeviceState *d) 513 { 514 Port92State *s = PORT92(d); 515 516 s->outport &= ~1; 517 } 518 519 static const MemoryRegionOps port92_ops = { 520 .read = port92_read, 521 .write = port92_write, 522 .impl = { 523 .min_access_size = 1, 524 .max_access_size = 1, 525 }, 526 .endianness = DEVICE_LITTLE_ENDIAN, 527 }; 528 529 static void port92_initfn(Object *obj) 530 { 531 Port92State *s = PORT92(obj); 532 533 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 534 535 s->outport = 0; 536 } 537 538 static void port92_realizefn(DeviceState *dev, Error **errp) 539 { 540 ISADevice *isadev = ISA_DEVICE(dev); 541 Port92State *s = PORT92(dev); 542 543 isa_register_ioport(isadev, &s->io, 0x92); 544 } 545 546 static void port92_class_initfn(ObjectClass *klass, void *data) 547 { 548 DeviceClass *dc = DEVICE_CLASS(klass); 549 550 dc->no_user = 1; 551 dc->realize = port92_realizefn; 552 dc->reset = port92_reset; 553 dc->vmsd = &vmstate_port92_isa; 554 } 555 556 static const TypeInfo port92_info = { 557 .name = TYPE_PORT92, 558 .parent = TYPE_ISA_DEVICE, 559 .instance_size = sizeof(Port92State), 560 .instance_init = port92_initfn, 561 .class_init = port92_class_initfn, 562 }; 563 564 static void port92_register_types(void) 565 { 566 type_register_static(&port92_info); 567 } 568 569 type_init(port92_register_types) 570 571 static void handle_a20_line_change(void *opaque, int irq, int level) 572 { 573 X86CPU *cpu = opaque; 574 575 /* XXX: send to all CPUs ? */ 576 /* XXX: add logic to handle multiple A20 line sources */ 577 x86_cpu_set_a20(cpu, level); 578 } 579 580 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 581 { 582 int index = le32_to_cpu(e820_reserve.count); 583 struct e820_entry *entry; 584 585 if (type != E820_RAM) { 586 /* old FW_CFG_E820_TABLE entry -- reservations only */ 587 if (index >= E820_NR_ENTRIES) { 588 return -EBUSY; 589 } 590 entry = &e820_reserve.entry[index++]; 591 592 entry->address = cpu_to_le64(address); 593 entry->length = cpu_to_le64(length); 594 entry->type = cpu_to_le32(type); 595 596 e820_reserve.count = cpu_to_le32(index); 597 } 598 599 /* new "etc/e820" file -- include ram too */ 600 e820_table = g_realloc(e820_table, 601 sizeof(struct e820_entry) * (e820_entries+1)); 602 e820_table[e820_entries].address = cpu_to_le64(address); 603 e820_table[e820_entries].length = cpu_to_le64(length); 604 e820_table[e820_entries].type = cpu_to_le32(type); 605 e820_entries++; 606 607 return e820_entries; 608 } 609 610 /* Calculates the limit to CPU APIC ID values 611 * 612 * This function returns the limit for the APIC ID value, so that all 613 * CPU APIC IDs are < pc_apic_id_limit(). 614 * 615 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 616 */ 617 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 618 { 619 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 620 } 621 622 static FWCfgState *bochs_bios_init(void) 623 { 624 FWCfgState *fw_cfg; 625 uint8_t *smbios_table; 626 size_t smbios_len; 627 uint64_t *numa_fw_cfg; 628 int i, j; 629 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 630 631 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 632 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 633 * 634 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 635 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 636 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 637 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 638 * may see". 639 * 640 * So, this means we must not use max_cpus, here, but the maximum possible 641 * APIC ID value, plus one. 642 * 643 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 644 * the APIC ID, not the "CPU index" 645 */ 646 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 647 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 648 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 649 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 650 acpi_tables, acpi_tables_len); 651 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 652 653 smbios_table = smbios_get_table(&smbios_len); 654 if (smbios_table) 655 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 656 smbios_table, smbios_len); 657 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 658 &e820_reserve, sizeof(e820_reserve)); 659 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 660 sizeof(struct e820_entry) * e820_entries); 661 662 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 663 /* allocate memory for the NUMA channel: one (64bit) word for the number 664 * of nodes, one word for each VCPU->node and one word for each node to 665 * hold the amount of memory. 666 */ 667 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 668 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 669 for (i = 0; i < max_cpus; i++) { 670 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 671 assert(apic_id < apic_id_limit); 672 for (j = 0; j < nb_numa_nodes; j++) { 673 if (test_bit(i, node_cpumask[j])) { 674 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 675 break; 676 } 677 } 678 } 679 for (i = 0; i < nb_numa_nodes; i++) { 680 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 681 } 682 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 683 (1 + apic_id_limit + nb_numa_nodes) * 684 sizeof(*numa_fw_cfg)); 685 686 return fw_cfg; 687 } 688 689 static long get_file_size(FILE *f) 690 { 691 long where, size; 692 693 /* XXX: on Unix systems, using fstat() probably makes more sense */ 694 695 where = ftell(f); 696 fseek(f, 0, SEEK_END); 697 size = ftell(f); 698 fseek(f, where, SEEK_SET); 699 700 return size; 701 } 702 703 static void load_linux(FWCfgState *fw_cfg, 704 const char *kernel_filename, 705 const char *initrd_filename, 706 const char *kernel_cmdline, 707 hwaddr max_ram_size) 708 { 709 uint16_t protocol; 710 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 711 uint32_t initrd_max; 712 uint8_t header[8192], *setup, *kernel, *initrd_data; 713 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 714 FILE *f; 715 char *vmode; 716 717 /* Align to 16 bytes as a paranoia measure */ 718 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 719 720 /* load the kernel header */ 721 f = fopen(kernel_filename, "rb"); 722 if (!f || !(kernel_size = get_file_size(f)) || 723 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 724 MIN(ARRAY_SIZE(header), kernel_size)) { 725 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 726 kernel_filename, strerror(errno)); 727 exit(1); 728 } 729 730 /* kernel protocol version */ 731 #if 0 732 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 733 #endif 734 if (ldl_p(header+0x202) == 0x53726448) { 735 protocol = lduw_p(header+0x206); 736 } else { 737 /* This looks like a multiboot kernel. If it is, let's stop 738 treating it like a Linux kernel. */ 739 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 740 kernel_cmdline, kernel_size, header)) { 741 return; 742 } 743 protocol = 0; 744 } 745 746 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 747 /* Low kernel */ 748 real_addr = 0x90000; 749 cmdline_addr = 0x9a000 - cmdline_size; 750 prot_addr = 0x10000; 751 } else if (protocol < 0x202) { 752 /* High but ancient kernel */ 753 real_addr = 0x90000; 754 cmdline_addr = 0x9a000 - cmdline_size; 755 prot_addr = 0x100000; 756 } else { 757 /* High and recent kernel */ 758 real_addr = 0x10000; 759 cmdline_addr = 0x20000; 760 prot_addr = 0x100000; 761 } 762 763 #if 0 764 fprintf(stderr, 765 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 766 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 767 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 768 real_addr, 769 cmdline_addr, 770 prot_addr); 771 #endif 772 773 /* highest address for loading the initrd */ 774 if (protocol >= 0x203) { 775 initrd_max = ldl_p(header+0x22c); 776 } else { 777 initrd_max = 0x37ffffff; 778 } 779 780 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 781 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 782 783 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 784 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 785 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 786 787 if (protocol >= 0x202) { 788 stl_p(header+0x228, cmdline_addr); 789 } else { 790 stw_p(header+0x20, 0xA33F); 791 stw_p(header+0x22, cmdline_addr-real_addr); 792 } 793 794 /* handle vga= parameter */ 795 vmode = strstr(kernel_cmdline, "vga="); 796 if (vmode) { 797 unsigned int video_mode; 798 /* skip "vga=" */ 799 vmode += 4; 800 if (!strncmp(vmode, "normal", 6)) { 801 video_mode = 0xffff; 802 } else if (!strncmp(vmode, "ext", 3)) { 803 video_mode = 0xfffe; 804 } else if (!strncmp(vmode, "ask", 3)) { 805 video_mode = 0xfffd; 806 } else { 807 video_mode = strtol(vmode, NULL, 0); 808 } 809 stw_p(header+0x1fa, video_mode); 810 } 811 812 /* loader type */ 813 /* High nybble = B reserved for QEMU; low nybble is revision number. 814 If this code is substantially changed, you may want to consider 815 incrementing the revision. */ 816 if (protocol >= 0x200) { 817 header[0x210] = 0xB0; 818 } 819 /* heap */ 820 if (protocol >= 0x201) { 821 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 822 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 823 } 824 825 /* load initrd */ 826 if (initrd_filename) { 827 if (protocol < 0x200) { 828 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 829 exit(1); 830 } 831 832 initrd_size = get_image_size(initrd_filename); 833 if (initrd_size < 0) { 834 fprintf(stderr, "qemu: error reading initrd %s\n", 835 initrd_filename); 836 exit(1); 837 } 838 839 initrd_addr = (initrd_max-initrd_size) & ~4095; 840 841 initrd_data = g_malloc(initrd_size); 842 load_image(initrd_filename, initrd_data); 843 844 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 845 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 846 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 847 848 stl_p(header+0x218, initrd_addr); 849 stl_p(header+0x21c, initrd_size); 850 } 851 852 /* load kernel and setup */ 853 setup_size = header[0x1f1]; 854 if (setup_size == 0) { 855 setup_size = 4; 856 } 857 setup_size = (setup_size+1)*512; 858 kernel_size -= setup_size; 859 860 setup = g_malloc(setup_size); 861 kernel = g_malloc(kernel_size); 862 fseek(f, 0, SEEK_SET); 863 if (fread(setup, 1, setup_size, f) != setup_size) { 864 fprintf(stderr, "fread() failed\n"); 865 exit(1); 866 } 867 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 868 fprintf(stderr, "fread() failed\n"); 869 exit(1); 870 } 871 fclose(f); 872 memcpy(setup, header, MIN(sizeof(header), setup_size)); 873 874 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 875 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 876 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 877 878 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 879 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 880 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 881 882 option_rom[nb_option_roms].name = "linuxboot.bin"; 883 option_rom[nb_option_roms].bootindex = 0; 884 nb_option_roms++; 885 } 886 887 #define NE2000_NB_MAX 6 888 889 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 890 0x280, 0x380 }; 891 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 892 893 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 894 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 895 896 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 897 { 898 static int nb_ne2k = 0; 899 900 if (nb_ne2k == NE2000_NB_MAX) 901 return; 902 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 903 ne2000_irq[nb_ne2k], nd); 904 nb_ne2k++; 905 } 906 907 DeviceState *cpu_get_current_apic(void) 908 { 909 if (current_cpu) { 910 X86CPU *cpu = X86_CPU(current_cpu); 911 return cpu->env.apic_state; 912 } else { 913 return NULL; 914 } 915 } 916 917 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 918 { 919 X86CPU *cpu = opaque; 920 921 if (level) { 922 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 923 } 924 } 925 926 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 927 DeviceState *icc_bridge, Error **errp) 928 { 929 X86CPU *cpu; 930 Error *local_err = NULL; 931 932 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 933 if (local_err != NULL) { 934 error_propagate(errp, local_err); 935 return NULL; 936 } 937 938 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 939 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 940 941 if (local_err) { 942 error_propagate(errp, local_err); 943 object_unref(OBJECT(cpu)); 944 cpu = NULL; 945 } 946 return cpu; 947 } 948 949 static const char *current_cpu_model; 950 951 void pc_hot_add_cpu(const int64_t id, Error **errp) 952 { 953 DeviceState *icc_bridge; 954 int64_t apic_id = x86_cpu_apic_id_from_index(id); 955 956 if (id < 0) { 957 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 958 return; 959 } 960 961 if (cpu_exists(apic_id)) { 962 error_setg(errp, "Unable to add CPU: %" PRIi64 963 ", it already exists", id); 964 return; 965 } 966 967 if (id >= max_cpus) { 968 error_setg(errp, "Unable to add CPU: %" PRIi64 969 ", max allowed: %d", id, max_cpus - 1); 970 return; 971 } 972 973 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 974 TYPE_ICC_BRIDGE, NULL)); 975 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 976 } 977 978 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 979 { 980 int i; 981 X86CPU *cpu = NULL; 982 Error *error = NULL; 983 984 /* init CPUs */ 985 if (cpu_model == NULL) { 986 #ifdef TARGET_X86_64 987 cpu_model = "qemu64"; 988 #else 989 cpu_model = "qemu32"; 990 #endif 991 } 992 current_cpu_model = cpu_model; 993 994 for (i = 0; i < smp_cpus; i++) { 995 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 996 icc_bridge, &error); 997 if (error) { 998 error_report("%s", error_get_pretty(error)); 999 error_free(error); 1000 exit(1); 1001 } 1002 } 1003 1004 /* map APIC MMIO area if CPU has APIC */ 1005 if (cpu && cpu->env.apic_state) { 1006 /* XXX: what if the base changes? */ 1007 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1008 APIC_DEFAULT_ADDRESS, 0x1000); 1009 } 1010 } 1011 1012 /* pci-info ROM file. Little endian format */ 1013 typedef struct PcRomPciInfo { 1014 uint64_t w32_min; 1015 uint64_t w32_max; 1016 uint64_t w64_min; 1017 uint64_t w64_max; 1018 } PcRomPciInfo; 1019 1020 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info) 1021 { 1022 PcRomPciInfo *info; 1023 Object *pci_info; 1024 bool ambiguous = false; 1025 1026 if (!guest_info->has_pci_info || !guest_info->fw_cfg) { 1027 return; 1028 } 1029 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1030 g_assert(!ambiguous); 1031 if (!pci_info) { 1032 return; 1033 } 1034 1035 info = g_malloc(sizeof *info); 1036 info->w32_min = cpu_to_le64(object_property_get_int(pci_info, 1037 PCI_HOST_PROP_PCI_HOLE_START, NULL)); 1038 info->w32_max = cpu_to_le64(object_property_get_int(pci_info, 1039 PCI_HOST_PROP_PCI_HOLE_END, NULL)); 1040 info->w64_min = cpu_to_le64(object_property_get_int(pci_info, 1041 PCI_HOST_PROP_PCI_HOLE64_START, NULL)); 1042 info->w64_max = cpu_to_le64(object_property_get_int(pci_info, 1043 PCI_HOST_PROP_PCI_HOLE64_END, NULL)); 1044 /* Pass PCI hole info to guest via a side channel. 1045 * Required so guest PCI enumeration does the right thing. */ 1046 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info); 1047 } 1048 1049 typedef struct PcGuestInfoState { 1050 PcGuestInfo info; 1051 Notifier machine_done; 1052 } PcGuestInfoState; 1053 1054 static 1055 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1056 { 1057 PcGuestInfoState *guest_info_state = container_of(notifier, 1058 PcGuestInfoState, 1059 machine_done); 1060 pc_fw_cfg_guest_info(&guest_info_state->info); 1061 acpi_setup(&guest_info_state->info); 1062 } 1063 1064 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1065 ram_addr_t above_4g_mem_size) 1066 { 1067 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1068 PcGuestInfo *guest_info = &guest_info_state->info; 1069 int i, j; 1070 1071 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1072 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1073 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1074 guest_info->numa_nodes = nb_numa_nodes; 1075 guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes * 1076 sizeof *guest_info->node_mem); 1077 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1078 sizeof *guest_info->node_cpu); 1079 1080 for (i = 0; i < max_cpus; i++) { 1081 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1082 assert(apic_id < guest_info->apic_id_limit); 1083 for (j = 0; j < nb_numa_nodes; j++) { 1084 if (test_bit(i, node_cpumask[j])) { 1085 guest_info->node_cpu[apic_id] = j; 1086 break; 1087 } 1088 } 1089 } 1090 1091 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1092 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1093 return guest_info; 1094 } 1095 1096 /* setup pci memory address space mapping into system address space */ 1097 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1098 MemoryRegion *pci_address_space) 1099 { 1100 /* Set to lower priority than RAM */ 1101 memory_region_add_subregion_overlap(system_memory, 0x0, 1102 pci_address_space, -1); 1103 } 1104 1105 void pc_acpi_init(const char *default_dsdt) 1106 { 1107 char *filename; 1108 1109 if (acpi_tables != NULL) { 1110 /* manually set via -acpitable, leave it alone */ 1111 return; 1112 } 1113 1114 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1115 if (filename == NULL) { 1116 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1117 } else { 1118 char *arg; 1119 QemuOpts *opts; 1120 Error *err = NULL; 1121 1122 arg = g_strdup_printf("file=%s", filename); 1123 1124 /* creates a deep copy of "arg" */ 1125 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1126 g_assert(opts != NULL); 1127 1128 acpi_table_add_builtin(opts, &err); 1129 if (err) { 1130 error_report("WARNING: failed to load %s: %s", filename, 1131 error_get_pretty(err)); 1132 error_free(err); 1133 } 1134 g_free(arg); 1135 g_free(filename); 1136 } 1137 } 1138 1139 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 1140 const char *kernel_filename, 1141 const char *kernel_cmdline, 1142 const char *initrd_filename, 1143 ram_addr_t below_4g_mem_size, 1144 ram_addr_t above_4g_mem_size, 1145 MemoryRegion *rom_memory, 1146 MemoryRegion **ram_memory, 1147 PcGuestInfo *guest_info) 1148 { 1149 int linux_boot, i; 1150 MemoryRegion *ram, *option_rom_mr; 1151 MemoryRegion *ram_below_4g, *ram_above_4g; 1152 FWCfgState *fw_cfg; 1153 1154 linux_boot = (kernel_filename != NULL); 1155 1156 /* Allocate RAM. We allocate it as a single memory region and use 1157 * aliases to address portions of it, mostly for backwards compatibility 1158 * with older qemus that used qemu_ram_alloc(). 1159 */ 1160 ram = g_malloc(sizeof(*ram)); 1161 memory_region_init_ram(ram, NULL, "pc.ram", 1162 below_4g_mem_size + above_4g_mem_size); 1163 vmstate_register_ram_global(ram); 1164 *ram_memory = ram; 1165 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1166 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1167 0, below_4g_mem_size); 1168 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1169 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1170 if (above_4g_mem_size > 0) { 1171 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1172 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1173 below_4g_mem_size, above_4g_mem_size); 1174 memory_region_add_subregion(system_memory, 0x100000000ULL, 1175 ram_above_4g); 1176 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1177 } 1178 1179 1180 /* Initialize PC system firmware */ 1181 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1182 1183 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1184 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); 1185 vmstate_register_ram_global(option_rom_mr); 1186 memory_region_add_subregion_overlap(rom_memory, 1187 PC_ROM_MIN_VGA, 1188 option_rom_mr, 1189 1); 1190 1191 fw_cfg = bochs_bios_init(); 1192 rom_set_fw(fw_cfg); 1193 1194 if (linux_boot) { 1195 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1196 } 1197 1198 for (i = 0; i < nb_option_roms; i++) { 1199 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1200 } 1201 guest_info->fw_cfg = fw_cfg; 1202 return fw_cfg; 1203 } 1204 1205 qemu_irq *pc_allocate_cpu_irq(void) 1206 { 1207 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1208 } 1209 1210 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1211 { 1212 DeviceState *dev = NULL; 1213 1214 if (pci_bus) { 1215 PCIDevice *pcidev = pci_vga_init(pci_bus); 1216 dev = pcidev ? &pcidev->qdev : NULL; 1217 } else if (isa_bus) { 1218 ISADevice *isadev = isa_vga_init(isa_bus); 1219 dev = isadev ? DEVICE(isadev) : NULL; 1220 } 1221 return dev; 1222 } 1223 1224 static void cpu_request_exit(void *opaque, int irq, int level) 1225 { 1226 CPUState *cpu = current_cpu; 1227 1228 if (cpu && level) { 1229 cpu_exit(cpu); 1230 } 1231 } 1232 1233 static const MemoryRegionOps ioport80_io_ops = { 1234 .write = ioport80_write, 1235 .read = ioport80_read, 1236 .endianness = DEVICE_NATIVE_ENDIAN, 1237 .impl = { 1238 .min_access_size = 1, 1239 .max_access_size = 1, 1240 }, 1241 }; 1242 1243 static const MemoryRegionOps ioportF0_io_ops = { 1244 .write = ioportF0_write, 1245 .read = ioportF0_read, 1246 .endianness = DEVICE_NATIVE_ENDIAN, 1247 .impl = { 1248 .min_access_size = 1, 1249 .max_access_size = 1, 1250 }, 1251 }; 1252 1253 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1254 ISADevice **rtc_state, 1255 ISADevice **floppy, 1256 bool no_vmport, 1257 uint32 hpet_irqs) 1258 { 1259 int i; 1260 DriveInfo *fd[MAX_FD]; 1261 DeviceState *hpet = NULL; 1262 int pit_isa_irq = 0; 1263 qemu_irq pit_alt_irq = NULL; 1264 qemu_irq rtc_irq = NULL; 1265 qemu_irq *a20_line; 1266 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1267 qemu_irq *cpu_exit_irq; 1268 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1269 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1270 1271 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1272 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1273 1274 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1275 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1276 1277 /* 1278 * Check if an HPET shall be created. 1279 * 1280 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1281 * when the HPET wants to take over. Thus we have to disable the latter. 1282 */ 1283 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1284 /* In order to set property, here not using sysbus_try_create_simple */ 1285 hpet = qdev_try_create(NULL, TYPE_HPET); 1286 if (hpet) { 1287 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1288 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1289 * IRQ8 and IRQ2. 1290 */ 1291 uint8_t compat = object_property_get_int(OBJECT(hpet), 1292 HPET_INTCAP, NULL); 1293 if (!compat) { 1294 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1295 } 1296 qdev_init_nofail(hpet); 1297 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1298 1299 for (i = 0; i < GSI_NUM_PINS; i++) { 1300 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1301 } 1302 pit_isa_irq = -1; 1303 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1304 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1305 } 1306 } 1307 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1308 1309 qemu_register_boot_set(pc_boot_set, *rtc_state); 1310 1311 if (!xen_enabled()) { 1312 if (kvm_irqchip_in_kernel()) { 1313 pit = kvm_pit_init(isa_bus, 0x40); 1314 } else { 1315 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1316 } 1317 if (hpet) { 1318 /* connect PIT to output control line of the HPET */ 1319 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1320 } 1321 pcspk_init(isa_bus, pit); 1322 } 1323 1324 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1325 if (serial_hds[i]) { 1326 serial_isa_init(isa_bus, i, serial_hds[i]); 1327 } 1328 } 1329 1330 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1331 if (parallel_hds[i]) { 1332 parallel_init(isa_bus, i, parallel_hds[i]); 1333 } 1334 } 1335 1336 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1337 i8042 = isa_create_simple(isa_bus, "i8042"); 1338 i8042_setup_a20_line(i8042, &a20_line[0]); 1339 if (!no_vmport) { 1340 vmport_init(isa_bus); 1341 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1342 } else { 1343 vmmouse = NULL; 1344 } 1345 if (vmmouse) { 1346 DeviceState *dev = DEVICE(vmmouse); 1347 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1348 qdev_init_nofail(dev); 1349 } 1350 port92 = isa_create_simple(isa_bus, "port92"); 1351 port92_init(port92, &a20_line[1]); 1352 1353 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1354 DMA_init(0, cpu_exit_irq); 1355 1356 for(i = 0; i < MAX_FD; i++) { 1357 fd[i] = drive_get(IF_FLOPPY, 0, i); 1358 } 1359 *floppy = fdctrl_init_isa(isa_bus, fd); 1360 } 1361 1362 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1363 { 1364 int i; 1365 1366 for (i = 0; i < nb_nics; i++) { 1367 NICInfo *nd = &nd_table[i]; 1368 1369 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1370 pc_init_ne2k_isa(isa_bus, nd); 1371 } else { 1372 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1373 } 1374 } 1375 } 1376 1377 void pc_pci_device_init(PCIBus *pci_bus) 1378 { 1379 int max_bus; 1380 int bus; 1381 1382 max_bus = drive_get_max_bus(IF_SCSI); 1383 for (bus = 0; bus <= max_bus; bus++) { 1384 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1385 } 1386 } 1387 1388 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1389 { 1390 DeviceState *dev; 1391 SysBusDevice *d; 1392 unsigned int i; 1393 1394 if (kvm_irqchip_in_kernel()) { 1395 dev = qdev_create(NULL, "kvm-ioapic"); 1396 } else { 1397 dev = qdev_create(NULL, "ioapic"); 1398 } 1399 if (parent_name) { 1400 object_property_add_child(object_resolve_path(parent_name, NULL), 1401 "ioapic", OBJECT(dev), NULL); 1402 } 1403 qdev_init_nofail(dev); 1404 d = SYS_BUS_DEVICE(dev); 1405 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1406 1407 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1408 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1409 } 1410 } 1411