1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/smbios/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/cpu/icc_bus.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 81 * (128K) and other BIOS datastructures (less than 4K reported to be used at 82 * the moment, 32K should be enough for a while). */ 83 static unsigned acpi_data_size = 0x20000 + 0x8000; 84 void pc_set_legacy_acpi_data_size(void) 85 { 86 acpi_data_size = 0x10000; 87 } 88 89 #define BIOS_CFG_IOPORT 0x510 90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 95 96 #define E820_NR_ENTRIES 16 97 98 struct e820_entry { 99 uint64_t address; 100 uint64_t length; 101 uint32_t type; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 struct e820_table { 105 uint32_t count; 106 struct e820_entry entry[E820_NR_ENTRIES]; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 static struct e820_table e820_reserve; 110 static struct e820_entry *e820_table; 111 static unsigned e820_entries; 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 113 114 void gsi_handler(void *opaque, int n, int level) 115 { 116 GSIState *s = opaque; 117 118 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 119 if (n < ISA_NUM_IRQS) { 120 qemu_set_irq(s->i8259_irq[n], level); 121 } 122 qemu_set_irq(s->ioapic_irq[n], level); 123 } 124 125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 126 unsigned size) 127 { 128 } 129 130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 131 { 132 return 0xffffffffffffffffULL; 133 } 134 135 /* MSDOS compatibility mode FPU exception support */ 136 static qemu_irq ferr_irq; 137 138 void pc_register_ferr_irq(qemu_irq irq) 139 { 140 ferr_irq = irq; 141 } 142 143 /* XXX: add IGNNE support */ 144 void cpu_set_ferr(CPUX86State *s) 145 { 146 qemu_irq_raise(ferr_irq); 147 } 148 149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 150 unsigned size) 151 { 152 qemu_irq_lower(ferr_irq); 153 } 154 155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 156 { 157 return 0xffffffffffffffffULL; 158 } 159 160 /* TSC handling */ 161 uint64_t cpu_get_tsc(CPUX86State *env) 162 { 163 return cpu_get_ticks(); 164 } 165 166 /* IRQ handling */ 167 int cpu_get_pic_interrupt(CPUX86State *env) 168 { 169 X86CPU *cpu = x86_env_get_cpu(env); 170 int intno; 171 172 intno = apic_get_interrupt(cpu->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(cpu->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUState *cs = first_cpu; 188 X86CPU *cpu = X86_CPU(cs); 189 190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 191 if (cpu->apic_state) { 192 CPU_FOREACH(cs) { 193 cpu = X86_CPU(cs); 194 if (apic_accept_pic_intr(cpu->apic_state)) { 195 apic_deliver_pic_intr(cpu->apic_state, level); 196 } 197 } 198 } else { 199 if (level) { 200 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 201 } else { 202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 203 } 204 } 205 } 206 207 /* PC cmos mappings */ 208 209 #define REG_EQUIPMENT_BYTE 0x14 210 211 static int cmos_get_fd_drive_type(FDriveType fd0) 212 { 213 int val; 214 215 switch (fd0) { 216 case FDRIVE_DRV_144: 217 /* 1.44 Mb 3"5 drive */ 218 val = 4; 219 break; 220 case FDRIVE_DRV_288: 221 /* 2.88 Mb 3"5 drive */ 222 val = 5; 223 break; 224 case FDRIVE_DRV_120: 225 /* 1.2 Mb 5"5 drive */ 226 val = 2; 227 break; 228 case FDRIVE_DRV_NONE: 229 default: 230 val = 0; 231 break; 232 } 233 return val; 234 } 235 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 237 int16_t cylinders, int8_t heads, int8_t sectors) 238 { 239 rtc_set_memory(s, type_ofs, 47); 240 rtc_set_memory(s, info_ofs, cylinders); 241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 2, heads); 243 rtc_set_memory(s, info_ofs + 3, 0xff); 244 rtc_set_memory(s, info_ofs + 4, 0xff); 245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 246 rtc_set_memory(s, info_ofs + 6, cylinders); 247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 8, sectors); 249 } 250 251 /* convert boot_device letter to something recognizable by the bios */ 252 static int boot_device2nibble(char boot_device) 253 { 254 switch(boot_device) { 255 case 'a': 256 case 'b': 257 return 0x01; /* floppy boot */ 258 case 'c': 259 return 0x02; /* hard drive boot */ 260 case 'd': 261 return 0x03; /* CD-ROM boot */ 262 case 'n': 263 return 0x04; /* Network boot */ 264 } 265 return 0; 266 } 267 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 269 { 270 #define PC_MAX_BOOT_DEVICES 3 271 int nbds, bds[3] = { 0, }; 272 int i; 273 274 nbds = strlen(boot_device); 275 if (nbds > PC_MAX_BOOT_DEVICES) { 276 error_setg(errp, "Too many boot devices for PC"); 277 return; 278 } 279 for (i = 0; i < nbds; i++) { 280 bds[i] = boot_device2nibble(boot_device[i]); 281 if (bds[i] == 0) { 282 error_setg(errp, "Invalid boot device for PC: '%c'", 283 boot_device[i]); 284 return; 285 } 286 } 287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 289 } 290 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 292 { 293 set_boot_dev(opaque, boot_device, errp); 294 } 295 296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 297 { 298 int val, nb, i; 299 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 300 301 /* floppy type */ 302 if (floppy) { 303 for (i = 0; i < 2; i++) { 304 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 305 } 306 } 307 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 308 cmos_get_fd_drive_type(fd_type[1]); 309 rtc_set_memory(rtc_state, 0x10, val); 310 311 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 312 nb = 0; 313 if (fd_type[0] < FDRIVE_DRV_NONE) { 314 nb++; 315 } 316 if (fd_type[1] < FDRIVE_DRV_NONE) { 317 nb++; 318 } 319 switch (nb) { 320 case 0: 321 break; 322 case 1: 323 val |= 0x01; /* 1 drive, ready for boot */ 324 break; 325 case 2: 326 val |= 0x41; /* 2 drives, ready for boot */ 327 break; 328 } 329 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 330 } 331 332 typedef struct pc_cmos_init_late_arg { 333 ISADevice *rtc_state; 334 BusState *idebus[2]; 335 } pc_cmos_init_late_arg; 336 337 typedef struct check_fdc_state { 338 ISADevice *floppy; 339 bool multiple; 340 } CheckFdcState; 341 342 static int check_fdc(Object *obj, void *opaque) 343 { 344 CheckFdcState *state = opaque; 345 Object *fdc; 346 uint32_t iobase; 347 Error *local_err = NULL; 348 349 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 350 if (!fdc) { 351 return 0; 352 } 353 354 iobase = object_property_get_int(obj, "iobase", &local_err); 355 if (local_err || iobase != 0x3f0) { 356 error_free(local_err); 357 return 0; 358 } 359 360 if (state->floppy) { 361 state->multiple = true; 362 } else { 363 state->floppy = ISA_DEVICE(obj); 364 } 365 return 0; 366 } 367 368 static const char * const fdc_container_path[] = { 369 "/unattached", "/peripheral", "/peripheral-anon" 370 }; 371 372 static void pc_cmos_init_late(void *opaque) 373 { 374 pc_cmos_init_late_arg *arg = opaque; 375 ISADevice *s = arg->rtc_state; 376 int16_t cylinders; 377 int8_t heads, sectors; 378 int val; 379 int i, trans; 380 Object *container; 381 CheckFdcState state = { 0 }; 382 383 val = 0; 384 if (ide_get_geometry(arg->idebus[0], 0, 385 &cylinders, &heads, §ors) >= 0) { 386 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 387 val |= 0xf0; 388 } 389 if (ide_get_geometry(arg->idebus[0], 1, 390 &cylinders, &heads, §ors) >= 0) { 391 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 392 val |= 0x0f; 393 } 394 rtc_set_memory(s, 0x12, val); 395 396 val = 0; 397 for (i = 0; i < 4; i++) { 398 /* NOTE: ide_get_geometry() returns the physical 399 geometry. It is always such that: 1 <= sects <= 63, 1 400 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 401 geometry can be different if a translation is done. */ 402 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 403 &cylinders, &heads, §ors) >= 0) { 404 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 405 assert((trans & ~3) == 0); 406 val |= trans << (i * 2); 407 } 408 } 409 rtc_set_memory(s, 0x39, val); 410 411 /* 412 * Locate the FDC at IO address 0x3f0, and configure the CMOS registers 413 * accordingly. 414 */ 415 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 416 container = container_get(qdev_get_machine(), fdc_container_path[i]); 417 object_child_foreach(container, check_fdc, &state); 418 } 419 420 if (state.multiple) { 421 error_report("warning: multiple floppy disk controllers with " 422 "iobase=0x3f0 have been found;\n" 423 "the one being picked for CMOS setup might not reflect " 424 "your intent"); 425 } 426 pc_cmos_init_floppy(s, state.floppy); 427 428 qemu_unregister_reset(pc_cmos_init_late, opaque); 429 } 430 431 void pc_cmos_init(PCMachineState *pcms, 432 BusState *idebus0, BusState *idebus1, 433 ISADevice *s) 434 { 435 int val; 436 static pc_cmos_init_late_arg arg; 437 Error *local_err = NULL; 438 439 /* various important CMOS locations needed by PC/Bochs bios */ 440 441 /* memory size */ 442 /* base memory (first MiB) */ 443 val = MIN(pcms->below_4g_mem_size / 1024, 640); 444 rtc_set_memory(s, 0x15, val); 445 rtc_set_memory(s, 0x16, val >> 8); 446 /* extended memory (next 64MiB) */ 447 if (pcms->below_4g_mem_size > 1024 * 1024) { 448 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 449 } else { 450 val = 0; 451 } 452 if (val > 65535) 453 val = 65535; 454 rtc_set_memory(s, 0x17, val); 455 rtc_set_memory(s, 0x18, val >> 8); 456 rtc_set_memory(s, 0x30, val); 457 rtc_set_memory(s, 0x31, val >> 8); 458 /* memory between 16MiB and 4GiB */ 459 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 460 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 461 } else { 462 val = 0; 463 } 464 if (val > 65535) 465 val = 65535; 466 rtc_set_memory(s, 0x34, val); 467 rtc_set_memory(s, 0x35, val >> 8); 468 /* memory above 4GiB */ 469 val = pcms->above_4g_mem_size / 65536; 470 rtc_set_memory(s, 0x5b, val); 471 rtc_set_memory(s, 0x5c, val >> 8); 472 rtc_set_memory(s, 0x5d, val >> 16); 473 474 /* set the number of CPU */ 475 rtc_set_memory(s, 0x5f, smp_cpus - 1); 476 477 object_property_add_link(OBJECT(pcms), "rtc_state", 478 TYPE_ISA_DEVICE, 479 (Object **)&pcms->rtc, 480 object_property_allow_set_link, 481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 482 object_property_set_link(OBJECT(pcms), OBJECT(s), 483 "rtc_state", &error_abort); 484 485 set_boot_dev(s, MACHINE(pcms)->boot_order, &local_err); 486 if (local_err) { 487 error_report_err(local_err); 488 exit(1); 489 } 490 491 val = 0; 492 val |= 0x02; /* FPU is there */ 493 val |= 0x04; /* PS/2 mouse installed */ 494 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 495 496 /* hard drives and FDC */ 497 arg.rtc_state = s; 498 arg.idebus[0] = idebus0; 499 arg.idebus[1] = idebus1; 500 qemu_register_reset(pc_cmos_init_late, &arg); 501 } 502 503 #define TYPE_PORT92 "port92" 504 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 505 506 /* port 92 stuff: could be split off */ 507 typedef struct Port92State { 508 ISADevice parent_obj; 509 510 MemoryRegion io; 511 uint8_t outport; 512 qemu_irq *a20_out; 513 } Port92State; 514 515 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 516 unsigned size) 517 { 518 Port92State *s = opaque; 519 int oldval = s->outport; 520 521 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 522 s->outport = val; 523 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 524 if ((val & 1) && !(oldval & 1)) { 525 qemu_system_reset_request(); 526 } 527 } 528 529 static uint64_t port92_read(void *opaque, hwaddr addr, 530 unsigned size) 531 { 532 Port92State *s = opaque; 533 uint32_t ret; 534 535 ret = s->outport; 536 DPRINTF("port92: read 0x%02x\n", ret); 537 return ret; 538 } 539 540 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 541 { 542 Port92State *s = PORT92(dev); 543 544 s->a20_out = a20_out; 545 } 546 547 static const VMStateDescription vmstate_port92_isa = { 548 .name = "port92", 549 .version_id = 1, 550 .minimum_version_id = 1, 551 .fields = (VMStateField[]) { 552 VMSTATE_UINT8(outport, Port92State), 553 VMSTATE_END_OF_LIST() 554 } 555 }; 556 557 static void port92_reset(DeviceState *d) 558 { 559 Port92State *s = PORT92(d); 560 561 s->outport &= ~1; 562 } 563 564 static const MemoryRegionOps port92_ops = { 565 .read = port92_read, 566 .write = port92_write, 567 .impl = { 568 .min_access_size = 1, 569 .max_access_size = 1, 570 }, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 }; 573 574 static void port92_initfn(Object *obj) 575 { 576 Port92State *s = PORT92(obj); 577 578 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 579 580 s->outport = 0; 581 } 582 583 static void port92_realizefn(DeviceState *dev, Error **errp) 584 { 585 ISADevice *isadev = ISA_DEVICE(dev); 586 Port92State *s = PORT92(dev); 587 588 isa_register_ioport(isadev, &s->io, 0x92); 589 } 590 591 static void port92_class_initfn(ObjectClass *klass, void *data) 592 { 593 DeviceClass *dc = DEVICE_CLASS(klass); 594 595 dc->realize = port92_realizefn; 596 dc->reset = port92_reset; 597 dc->vmsd = &vmstate_port92_isa; 598 /* 599 * Reason: unlike ordinary ISA devices, this one needs additional 600 * wiring: its A20 output line needs to be wired up by 601 * port92_init(). 602 */ 603 dc->cannot_instantiate_with_device_add_yet = true; 604 } 605 606 static const TypeInfo port92_info = { 607 .name = TYPE_PORT92, 608 .parent = TYPE_ISA_DEVICE, 609 .instance_size = sizeof(Port92State), 610 .instance_init = port92_initfn, 611 .class_init = port92_class_initfn, 612 }; 613 614 static void port92_register_types(void) 615 { 616 type_register_static(&port92_info); 617 } 618 619 type_init(port92_register_types) 620 621 static void handle_a20_line_change(void *opaque, int irq, int level) 622 { 623 X86CPU *cpu = opaque; 624 625 /* XXX: send to all CPUs ? */ 626 /* XXX: add logic to handle multiple A20 line sources */ 627 x86_cpu_set_a20(cpu, level); 628 } 629 630 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 631 { 632 int index = le32_to_cpu(e820_reserve.count); 633 struct e820_entry *entry; 634 635 if (type != E820_RAM) { 636 /* old FW_CFG_E820_TABLE entry -- reservations only */ 637 if (index >= E820_NR_ENTRIES) { 638 return -EBUSY; 639 } 640 entry = &e820_reserve.entry[index++]; 641 642 entry->address = cpu_to_le64(address); 643 entry->length = cpu_to_le64(length); 644 entry->type = cpu_to_le32(type); 645 646 e820_reserve.count = cpu_to_le32(index); 647 } 648 649 /* new "etc/e820" file -- include ram too */ 650 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 651 e820_table[e820_entries].address = cpu_to_le64(address); 652 e820_table[e820_entries].length = cpu_to_le64(length); 653 e820_table[e820_entries].type = cpu_to_le32(type); 654 e820_entries++; 655 656 return e820_entries; 657 } 658 659 int e820_get_num_entries(void) 660 { 661 return e820_entries; 662 } 663 664 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 665 { 666 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 667 *address = le64_to_cpu(e820_table[idx].address); 668 *length = le64_to_cpu(e820_table[idx].length); 669 return true; 670 } 671 return false; 672 } 673 674 /* Enables contiguous-apic-ID mode, for compatibility */ 675 static bool compat_apic_id_mode; 676 677 void enable_compat_apic_id_mode(void) 678 { 679 compat_apic_id_mode = true; 680 } 681 682 /* Calculates initial APIC ID for a specific CPU index 683 * 684 * Currently we need to be able to calculate the APIC ID from the CPU index 685 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 686 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 687 * all CPUs up to max_cpus. 688 */ 689 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 690 { 691 uint32_t correct_id; 692 static bool warned; 693 694 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 695 if (compat_apic_id_mode) { 696 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 697 error_report("APIC IDs set in compatibility mode, " 698 "CPU topology won't match the configuration"); 699 warned = true; 700 } 701 return cpu_index; 702 } else { 703 return correct_id; 704 } 705 } 706 707 /* Calculates the limit to CPU APIC ID values 708 * 709 * This function returns the limit for the APIC ID value, so that all 710 * CPU APIC IDs are < pc_apic_id_limit(). 711 * 712 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 713 */ 714 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 715 { 716 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 717 } 718 719 static void pc_build_smbios(FWCfgState *fw_cfg) 720 { 721 uint8_t *smbios_tables, *smbios_anchor; 722 size_t smbios_tables_len, smbios_anchor_len; 723 struct smbios_phys_mem_area *mem_array; 724 unsigned i, array_count; 725 726 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 727 if (smbios_tables) { 728 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 729 smbios_tables, smbios_tables_len); 730 } 731 732 /* build the array of physical mem area from e820 table */ 733 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 734 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 735 uint64_t addr, len; 736 737 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 738 mem_array[array_count].address = addr; 739 mem_array[array_count].length = len; 740 array_count++; 741 } 742 } 743 smbios_get_tables(mem_array, array_count, 744 &smbios_tables, &smbios_tables_len, 745 &smbios_anchor, &smbios_anchor_len); 746 g_free(mem_array); 747 748 if (smbios_anchor) { 749 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 750 smbios_tables, smbios_tables_len); 751 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 752 smbios_anchor, smbios_anchor_len); 753 } 754 } 755 756 static FWCfgState *bochs_bios_init(void) 757 { 758 FWCfgState *fw_cfg; 759 uint64_t *numa_fw_cfg; 760 int i, j; 761 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 762 763 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 764 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 765 * 766 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 767 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 768 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 769 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 770 * may see". 771 * 772 * So, this means we must not use max_cpus, here, but the maximum possible 773 * APIC ID value, plus one. 774 * 775 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 776 * the APIC ID, not the "CPU index" 777 */ 778 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 779 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 780 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 781 acpi_tables, acpi_tables_len); 782 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 783 784 pc_build_smbios(fw_cfg); 785 786 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 787 &e820_reserve, sizeof(e820_reserve)); 788 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 789 sizeof(struct e820_entry) * e820_entries); 790 791 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 792 /* allocate memory for the NUMA channel: one (64bit) word for the number 793 * of nodes, one word for each VCPU->node and one word for each node to 794 * hold the amount of memory. 795 */ 796 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 797 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 798 for (i = 0; i < max_cpus; i++) { 799 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 800 assert(apic_id < apic_id_limit); 801 for (j = 0; j < nb_numa_nodes; j++) { 802 if (test_bit(i, numa_info[j].node_cpu)) { 803 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 804 break; 805 } 806 } 807 } 808 for (i = 0; i < nb_numa_nodes; i++) { 809 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 810 } 811 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 812 (1 + apic_id_limit + nb_numa_nodes) * 813 sizeof(*numa_fw_cfg)); 814 815 return fw_cfg; 816 } 817 818 static long get_file_size(FILE *f) 819 { 820 long where, size; 821 822 /* XXX: on Unix systems, using fstat() probably makes more sense */ 823 824 where = ftell(f); 825 fseek(f, 0, SEEK_END); 826 size = ftell(f); 827 fseek(f, where, SEEK_SET); 828 829 return size; 830 } 831 832 static void load_linux(PCMachineState *pcms, 833 FWCfgState *fw_cfg) 834 { 835 uint16_t protocol; 836 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 837 uint32_t initrd_max; 838 uint8_t header[8192], *setup, *kernel, *initrd_data; 839 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 840 FILE *f; 841 char *vmode; 842 MachineState *machine = MACHINE(pcms); 843 const char *kernel_filename = machine->kernel_filename; 844 const char *initrd_filename = machine->initrd_filename; 845 const char *kernel_cmdline = machine->kernel_cmdline; 846 847 /* Align to 16 bytes as a paranoia measure */ 848 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 849 850 /* load the kernel header */ 851 f = fopen(kernel_filename, "rb"); 852 if (!f || !(kernel_size = get_file_size(f)) || 853 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 854 MIN(ARRAY_SIZE(header), kernel_size)) { 855 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 856 kernel_filename, strerror(errno)); 857 exit(1); 858 } 859 860 /* kernel protocol version */ 861 #if 0 862 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 863 #endif 864 if (ldl_p(header+0x202) == 0x53726448) { 865 protocol = lduw_p(header+0x206); 866 } else { 867 /* This looks like a multiboot kernel. If it is, let's stop 868 treating it like a Linux kernel. */ 869 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 870 kernel_cmdline, kernel_size, header)) { 871 return; 872 } 873 protocol = 0; 874 } 875 876 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 877 /* Low kernel */ 878 real_addr = 0x90000; 879 cmdline_addr = 0x9a000 - cmdline_size; 880 prot_addr = 0x10000; 881 } else if (protocol < 0x202) { 882 /* High but ancient kernel */ 883 real_addr = 0x90000; 884 cmdline_addr = 0x9a000 - cmdline_size; 885 prot_addr = 0x100000; 886 } else { 887 /* High and recent kernel */ 888 real_addr = 0x10000; 889 cmdline_addr = 0x20000; 890 prot_addr = 0x100000; 891 } 892 893 #if 0 894 fprintf(stderr, 895 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 896 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 897 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 898 real_addr, 899 cmdline_addr, 900 prot_addr); 901 #endif 902 903 /* highest address for loading the initrd */ 904 if (protocol >= 0x203) { 905 initrd_max = ldl_p(header+0x22c); 906 } else { 907 initrd_max = 0x37ffffff; 908 } 909 910 if (initrd_max >= pcms->below_4g_mem_size - acpi_data_size) { 911 initrd_max = pcms->below_4g_mem_size - acpi_data_size - 1; 912 } 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 916 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 917 918 if (protocol >= 0x202) { 919 stl_p(header+0x228, cmdline_addr); 920 } else { 921 stw_p(header+0x20, 0xA33F); 922 stw_p(header+0x22, cmdline_addr-real_addr); 923 } 924 925 /* handle vga= parameter */ 926 vmode = strstr(kernel_cmdline, "vga="); 927 if (vmode) { 928 unsigned int video_mode; 929 /* skip "vga=" */ 930 vmode += 4; 931 if (!strncmp(vmode, "normal", 6)) { 932 video_mode = 0xffff; 933 } else if (!strncmp(vmode, "ext", 3)) { 934 video_mode = 0xfffe; 935 } else if (!strncmp(vmode, "ask", 3)) { 936 video_mode = 0xfffd; 937 } else { 938 video_mode = strtol(vmode, NULL, 0); 939 } 940 stw_p(header+0x1fa, video_mode); 941 } 942 943 /* loader type */ 944 /* High nybble = B reserved for QEMU; low nybble is revision number. 945 If this code is substantially changed, you may want to consider 946 incrementing the revision. */ 947 if (protocol >= 0x200) { 948 header[0x210] = 0xB0; 949 } 950 /* heap */ 951 if (protocol >= 0x201) { 952 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 953 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 954 } 955 956 /* load initrd */ 957 if (initrd_filename) { 958 if (protocol < 0x200) { 959 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 960 exit(1); 961 } 962 963 initrd_size = get_image_size(initrd_filename); 964 if (initrd_size < 0) { 965 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 966 initrd_filename, strerror(errno)); 967 exit(1); 968 } 969 970 initrd_addr = (initrd_max-initrd_size) & ~4095; 971 972 initrd_data = g_malloc(initrd_size); 973 load_image(initrd_filename, initrd_data); 974 975 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 976 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 977 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 978 979 stl_p(header+0x218, initrd_addr); 980 stl_p(header+0x21c, initrd_size); 981 } 982 983 /* load kernel and setup */ 984 setup_size = header[0x1f1]; 985 if (setup_size == 0) { 986 setup_size = 4; 987 } 988 setup_size = (setup_size+1)*512; 989 kernel_size -= setup_size; 990 991 setup = g_malloc(setup_size); 992 kernel = g_malloc(kernel_size); 993 fseek(f, 0, SEEK_SET); 994 if (fread(setup, 1, setup_size, f) != setup_size) { 995 fprintf(stderr, "fread() failed\n"); 996 exit(1); 997 } 998 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 999 fprintf(stderr, "fread() failed\n"); 1000 exit(1); 1001 } 1002 fclose(f); 1003 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1004 1005 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1006 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1007 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1008 1009 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1010 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1011 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1012 1013 option_rom[nb_option_roms].name = "linuxboot.bin"; 1014 option_rom[nb_option_roms].bootindex = 0; 1015 nb_option_roms++; 1016 } 1017 1018 #define NE2000_NB_MAX 6 1019 1020 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1021 0x280, 0x380 }; 1022 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1023 1024 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1025 { 1026 static int nb_ne2k = 0; 1027 1028 if (nb_ne2k == NE2000_NB_MAX) 1029 return; 1030 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1031 ne2000_irq[nb_ne2k], nd); 1032 nb_ne2k++; 1033 } 1034 1035 DeviceState *cpu_get_current_apic(void) 1036 { 1037 if (current_cpu) { 1038 X86CPU *cpu = X86_CPU(current_cpu); 1039 return cpu->apic_state; 1040 } else { 1041 return NULL; 1042 } 1043 } 1044 1045 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1046 { 1047 X86CPU *cpu = opaque; 1048 1049 if (level) { 1050 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1051 } 1052 } 1053 1054 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1055 DeviceState *icc_bridge, Error **errp) 1056 { 1057 X86CPU *cpu = NULL; 1058 Error *local_err = NULL; 1059 1060 if (icc_bridge == NULL) { 1061 error_setg(&local_err, "Invalid icc-bridge value"); 1062 goto out; 1063 } 1064 1065 cpu = cpu_x86_create(cpu_model, &local_err); 1066 if (local_err != NULL) { 1067 goto out; 1068 } 1069 1070 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); 1071 1072 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1073 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1074 1075 out: 1076 if (local_err) { 1077 error_propagate(errp, local_err); 1078 object_unref(OBJECT(cpu)); 1079 cpu = NULL; 1080 } 1081 return cpu; 1082 } 1083 1084 static const char *current_cpu_model; 1085 1086 void pc_hot_add_cpu(const int64_t id, Error **errp) 1087 { 1088 DeviceState *icc_bridge; 1089 X86CPU *cpu; 1090 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1091 Error *local_err = NULL; 1092 1093 if (id < 0) { 1094 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1095 return; 1096 } 1097 1098 if (cpu_exists(apic_id)) { 1099 error_setg(errp, "Unable to add CPU: %" PRIi64 1100 ", it already exists", id); 1101 return; 1102 } 1103 1104 if (id >= max_cpus) { 1105 error_setg(errp, "Unable to add CPU: %" PRIi64 1106 ", max allowed: %d", id, max_cpus - 1); 1107 return; 1108 } 1109 1110 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1111 error_setg(errp, "Unable to add CPU: %" PRIi64 1112 ", resulting APIC ID (%" PRIi64 ") is too large", 1113 id, apic_id); 1114 return; 1115 } 1116 1117 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1118 TYPE_ICC_BRIDGE, NULL)); 1119 cpu = pc_new_cpu(current_cpu_model, apic_id, icc_bridge, &local_err); 1120 if (local_err) { 1121 error_propagate(errp, local_err); 1122 return; 1123 } 1124 object_unref(OBJECT(cpu)); 1125 } 1126 1127 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1128 { 1129 int i; 1130 X86CPU *cpu = NULL; 1131 Error *error = NULL; 1132 unsigned long apic_id_limit; 1133 1134 /* init CPUs */ 1135 if (cpu_model == NULL) { 1136 #ifdef TARGET_X86_64 1137 cpu_model = "qemu64"; 1138 #else 1139 cpu_model = "qemu32"; 1140 #endif 1141 } 1142 current_cpu_model = cpu_model; 1143 1144 apic_id_limit = pc_apic_id_limit(max_cpus); 1145 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1146 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1147 apic_id_limit - 1); 1148 exit(1); 1149 } 1150 1151 for (i = 0; i < smp_cpus; i++) { 1152 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1153 icc_bridge, &error); 1154 if (error) { 1155 error_report_err(error); 1156 exit(1); 1157 } 1158 object_unref(OBJECT(cpu)); 1159 } 1160 1161 /* map APIC MMIO area if CPU has APIC */ 1162 if (cpu && cpu->apic_state) { 1163 /* XXX: what if the base changes? */ 1164 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1165 APIC_DEFAULT_ADDRESS, 0x1000); 1166 } 1167 1168 /* tell smbios about cpuid version and features */ 1169 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1170 } 1171 1172 /* pci-info ROM file. Little endian format */ 1173 typedef struct PcRomPciInfo { 1174 uint64_t w32_min; 1175 uint64_t w32_max; 1176 uint64_t w64_min; 1177 uint64_t w64_max; 1178 } PcRomPciInfo; 1179 1180 typedef struct PcGuestInfoState { 1181 PcGuestInfo info; 1182 Notifier machine_done; 1183 } PcGuestInfoState; 1184 1185 static 1186 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1187 { 1188 PcGuestInfoState *guest_info_state = container_of(notifier, 1189 PcGuestInfoState, 1190 machine_done); 1191 PCIBus *bus = find_i440fx(); 1192 1193 if (bus) { 1194 int extra_hosts = 0; 1195 1196 QLIST_FOREACH(bus, &bus->child, sibling) { 1197 /* look for expander root buses */ 1198 if (pci_bus_is_root(bus)) { 1199 extra_hosts++; 1200 } 1201 } 1202 if (extra_hosts && guest_info_state->info.fw_cfg) { 1203 uint64_t *val = g_malloc(sizeof(*val)); 1204 *val = cpu_to_le64(extra_hosts); 1205 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1206 "etc/extra-pci-roots", val, sizeof(*val)); 1207 } 1208 } 1209 1210 acpi_setup(&guest_info_state->info); 1211 } 1212 1213 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1214 { 1215 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1216 PcGuestInfo *guest_info = &guest_info_state->info; 1217 int i, j; 1218 1219 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1220 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1221 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1222 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1223 guest_info->numa_nodes = nb_numa_nodes; 1224 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1225 sizeof *guest_info->node_mem); 1226 for (i = 0; i < nb_numa_nodes; i++) { 1227 guest_info->node_mem[i] = numa_info[i].node_mem; 1228 } 1229 1230 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1231 sizeof *guest_info->node_cpu); 1232 1233 for (i = 0; i < max_cpus; i++) { 1234 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1235 assert(apic_id < guest_info->apic_id_limit); 1236 for (j = 0; j < nb_numa_nodes; j++) { 1237 if (test_bit(i, numa_info[j].node_cpu)) { 1238 guest_info->node_cpu[apic_id] = j; 1239 break; 1240 } 1241 } 1242 } 1243 1244 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1245 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1246 return guest_info; 1247 } 1248 1249 /* setup pci memory address space mapping into system address space */ 1250 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1251 MemoryRegion *pci_address_space) 1252 { 1253 /* Set to lower priority than RAM */ 1254 memory_region_add_subregion_overlap(system_memory, 0x0, 1255 pci_address_space, -1); 1256 } 1257 1258 void pc_acpi_init(const char *default_dsdt) 1259 { 1260 char *filename; 1261 1262 if (acpi_tables != NULL) { 1263 /* manually set via -acpitable, leave it alone */ 1264 return; 1265 } 1266 1267 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1268 if (filename == NULL) { 1269 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1270 } else { 1271 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1272 &error_abort); 1273 Error *err = NULL; 1274 1275 qemu_opt_set(opts, "file", filename, &error_abort); 1276 1277 acpi_table_add_builtin(opts, &err); 1278 if (err) { 1279 error_report("WARNING: failed to load %s: %s", filename, 1280 error_get_pretty(err)); 1281 error_free(err); 1282 } 1283 g_free(filename); 1284 } 1285 } 1286 1287 FWCfgState *xen_load_linux(PCMachineState *pcms, 1288 PcGuestInfo *guest_info) 1289 { 1290 int i; 1291 FWCfgState *fw_cfg; 1292 1293 assert(MACHINE(pcms)->kernel_filename != NULL); 1294 1295 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1296 rom_set_fw(fw_cfg); 1297 1298 load_linux(pcms, fw_cfg); 1299 for (i = 0; i < nb_option_roms; i++) { 1300 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1301 !strcmp(option_rom[i].name, "multiboot.bin")); 1302 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1303 } 1304 guest_info->fw_cfg = fw_cfg; 1305 return fw_cfg; 1306 } 1307 1308 FWCfgState *pc_memory_init(PCMachineState *pcms, 1309 MemoryRegion *system_memory, 1310 MemoryRegion *rom_memory, 1311 MemoryRegion **ram_memory, 1312 PcGuestInfo *guest_info) 1313 { 1314 int linux_boot, i; 1315 MemoryRegion *ram, *option_rom_mr; 1316 MemoryRegion *ram_below_4g, *ram_above_4g; 1317 FWCfgState *fw_cfg; 1318 MachineState *machine = MACHINE(pcms); 1319 1320 assert(machine->ram_size == pcms->below_4g_mem_size + 1321 pcms->above_4g_mem_size); 1322 1323 linux_boot = (machine->kernel_filename != NULL); 1324 1325 /* Allocate RAM. We allocate it as a single memory region and use 1326 * aliases to address portions of it, mostly for backwards compatibility 1327 * with older qemus that used qemu_ram_alloc(). 1328 */ 1329 ram = g_malloc(sizeof(*ram)); 1330 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1331 machine->ram_size); 1332 *ram_memory = ram; 1333 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1334 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1335 0, pcms->below_4g_mem_size); 1336 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1337 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1338 if (pcms->above_4g_mem_size > 0) { 1339 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1340 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1341 pcms->below_4g_mem_size, 1342 pcms->above_4g_mem_size); 1343 memory_region_add_subregion(system_memory, 0x100000000ULL, 1344 ram_above_4g); 1345 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1346 } 1347 1348 if (!guest_info->has_reserved_memory && 1349 (machine->ram_slots || 1350 (machine->maxram_size > machine->ram_size))) { 1351 MachineClass *mc = MACHINE_GET_CLASS(machine); 1352 1353 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1354 mc->name); 1355 exit(EXIT_FAILURE); 1356 } 1357 1358 /* initialize hotplug memory address space */ 1359 if (guest_info->has_reserved_memory && 1360 (machine->ram_size < machine->maxram_size)) { 1361 ram_addr_t hotplug_mem_size = 1362 machine->maxram_size - machine->ram_size; 1363 1364 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1365 error_report("unsupported amount of memory slots: %"PRIu64, 1366 machine->ram_slots); 1367 exit(EXIT_FAILURE); 1368 } 1369 1370 if (QEMU_ALIGN_UP(machine->maxram_size, 1371 TARGET_PAGE_SIZE) != machine->maxram_size) { 1372 error_report("maximum memory size must by aligned to multiple of " 1373 "%d bytes", TARGET_PAGE_SIZE); 1374 exit(EXIT_FAILURE); 1375 } 1376 1377 pcms->hotplug_memory.base = 1378 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1379 1380 if (pcms->enforce_aligned_dimm) { 1381 /* size hotplug region assuming 1G page max alignment per slot */ 1382 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1383 } 1384 1385 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1386 hotplug_mem_size) { 1387 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1388 machine->maxram_size); 1389 exit(EXIT_FAILURE); 1390 } 1391 1392 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1393 "hotplug-memory", hotplug_mem_size); 1394 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1395 &pcms->hotplug_memory.mr); 1396 } 1397 1398 /* Initialize PC system firmware */ 1399 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1400 1401 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1402 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1403 &error_abort); 1404 vmstate_register_ram_global(option_rom_mr); 1405 memory_region_add_subregion_overlap(rom_memory, 1406 PC_ROM_MIN_VGA, 1407 option_rom_mr, 1408 1); 1409 1410 fw_cfg = bochs_bios_init(); 1411 rom_set_fw(fw_cfg); 1412 1413 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1414 uint64_t *val = g_malloc(sizeof(*val)); 1415 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1416 uint64_t res_mem_end = pcms->hotplug_memory.base; 1417 1418 if (!pcmc->broken_reserved_end) { 1419 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1420 } 1421 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1422 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1423 } 1424 1425 if (linux_boot) { 1426 load_linux(pcms, fw_cfg); 1427 } 1428 1429 for (i = 0; i < nb_option_roms; i++) { 1430 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1431 } 1432 guest_info->fw_cfg = fw_cfg; 1433 return fw_cfg; 1434 } 1435 1436 qemu_irq pc_allocate_cpu_irq(void) 1437 { 1438 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1439 } 1440 1441 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1442 { 1443 DeviceState *dev = NULL; 1444 1445 if (pci_bus) { 1446 PCIDevice *pcidev = pci_vga_init(pci_bus); 1447 dev = pcidev ? &pcidev->qdev : NULL; 1448 } else if (isa_bus) { 1449 ISADevice *isadev = isa_vga_init(isa_bus); 1450 dev = isadev ? DEVICE(isadev) : NULL; 1451 } 1452 return dev; 1453 } 1454 1455 static void cpu_request_exit(void *opaque, int irq, int level) 1456 { 1457 CPUState *cpu = current_cpu; 1458 1459 if (cpu && level) { 1460 cpu_exit(cpu); 1461 } 1462 } 1463 1464 static const MemoryRegionOps ioport80_io_ops = { 1465 .write = ioport80_write, 1466 .read = ioport80_read, 1467 .endianness = DEVICE_NATIVE_ENDIAN, 1468 .impl = { 1469 .min_access_size = 1, 1470 .max_access_size = 1, 1471 }, 1472 }; 1473 1474 static const MemoryRegionOps ioportF0_io_ops = { 1475 .write = ioportF0_write, 1476 .read = ioportF0_read, 1477 .endianness = DEVICE_NATIVE_ENDIAN, 1478 .impl = { 1479 .min_access_size = 1, 1480 .max_access_size = 1, 1481 }, 1482 }; 1483 1484 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1485 ISADevice **rtc_state, 1486 bool create_fdctrl, 1487 bool no_vmport, 1488 uint32 hpet_irqs) 1489 { 1490 int i; 1491 DriveInfo *fd[MAX_FD]; 1492 DeviceState *hpet = NULL; 1493 int pit_isa_irq = 0; 1494 qemu_irq pit_alt_irq = NULL; 1495 qemu_irq rtc_irq = NULL; 1496 qemu_irq *a20_line; 1497 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1498 qemu_irq *cpu_exit_irq; 1499 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1500 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1501 1502 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1503 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1504 1505 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1506 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1507 1508 /* 1509 * Check if an HPET shall be created. 1510 * 1511 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1512 * when the HPET wants to take over. Thus we have to disable the latter. 1513 */ 1514 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1515 /* In order to set property, here not using sysbus_try_create_simple */ 1516 hpet = qdev_try_create(NULL, TYPE_HPET); 1517 if (hpet) { 1518 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1519 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1520 * IRQ8 and IRQ2. 1521 */ 1522 uint8_t compat = object_property_get_int(OBJECT(hpet), 1523 HPET_INTCAP, NULL); 1524 if (!compat) { 1525 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1526 } 1527 qdev_init_nofail(hpet); 1528 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1529 1530 for (i = 0; i < GSI_NUM_PINS; i++) { 1531 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1532 } 1533 pit_isa_irq = -1; 1534 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1535 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1536 } 1537 } 1538 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1539 1540 qemu_register_boot_set(pc_boot_set, *rtc_state); 1541 1542 if (!xen_enabled()) { 1543 if (kvm_irqchip_in_kernel()) { 1544 pit = kvm_pit_init(isa_bus, 0x40); 1545 } else { 1546 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1547 } 1548 if (hpet) { 1549 /* connect PIT to output control line of the HPET */ 1550 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1551 } 1552 pcspk_init(isa_bus, pit); 1553 } 1554 1555 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1556 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1557 1558 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1559 i8042 = isa_create_simple(isa_bus, "i8042"); 1560 i8042_setup_a20_line(i8042, &a20_line[0]); 1561 if (!no_vmport) { 1562 vmport_init(isa_bus); 1563 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1564 } else { 1565 vmmouse = NULL; 1566 } 1567 if (vmmouse) { 1568 DeviceState *dev = DEVICE(vmmouse); 1569 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1570 qdev_init_nofail(dev); 1571 } 1572 port92 = isa_create_simple(isa_bus, "port92"); 1573 port92_init(port92, &a20_line[1]); 1574 1575 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1576 DMA_init(0, cpu_exit_irq); 1577 1578 for(i = 0; i < MAX_FD; i++) { 1579 fd[i] = drive_get(IF_FLOPPY, 0, i); 1580 create_fdctrl |= !!fd[i]; 1581 } 1582 if (create_fdctrl) { 1583 fdctrl_init_isa(isa_bus, fd); 1584 } 1585 } 1586 1587 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1588 { 1589 int i; 1590 1591 for (i = 0; i < nb_nics; i++) { 1592 NICInfo *nd = &nd_table[i]; 1593 1594 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1595 pc_init_ne2k_isa(isa_bus, nd); 1596 } else { 1597 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1598 } 1599 } 1600 } 1601 1602 void pc_pci_device_init(PCIBus *pci_bus) 1603 { 1604 int max_bus; 1605 int bus; 1606 1607 max_bus = drive_get_max_bus(IF_SCSI); 1608 for (bus = 0; bus <= max_bus; bus++) { 1609 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1610 } 1611 } 1612 1613 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1614 { 1615 DeviceState *dev; 1616 SysBusDevice *d; 1617 unsigned int i; 1618 1619 if (kvm_irqchip_in_kernel()) { 1620 dev = qdev_create(NULL, "kvm-ioapic"); 1621 } else { 1622 dev = qdev_create(NULL, "ioapic"); 1623 } 1624 if (parent_name) { 1625 object_property_add_child(object_resolve_path(parent_name, NULL), 1626 "ioapic", OBJECT(dev), NULL); 1627 } 1628 qdev_init_nofail(dev); 1629 d = SYS_BUS_DEVICE(dev); 1630 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1631 1632 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1633 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1634 } 1635 } 1636 1637 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1638 DeviceState *dev, Error **errp) 1639 { 1640 HotplugHandlerClass *hhc; 1641 Error *local_err = NULL; 1642 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1643 PCDIMMDevice *dimm = PC_DIMM(dev); 1644 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1645 MemoryRegion *mr = ddc->get_memory_region(dimm); 1646 uint64_t align = TARGET_PAGE_SIZE; 1647 1648 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1649 align = memory_region_get_alignment(mr); 1650 } 1651 1652 if (!pcms->acpi_dev) { 1653 error_setg(&local_err, 1654 "memory hotplug is not enabled: missing acpi device"); 1655 goto out; 1656 } 1657 1658 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1659 if (local_err) { 1660 goto out; 1661 } 1662 1663 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1664 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1665 out: 1666 error_propagate(errp, local_err); 1667 } 1668 1669 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1670 DeviceState *dev, Error **errp) 1671 { 1672 HotplugHandlerClass *hhc; 1673 Error *local_err = NULL; 1674 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1675 1676 if (!pcms->acpi_dev) { 1677 error_setg(&local_err, 1678 "memory hotplug is not enabled: missing acpi device"); 1679 goto out; 1680 } 1681 1682 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1683 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1684 1685 out: 1686 error_propagate(errp, local_err); 1687 } 1688 1689 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1690 DeviceState *dev, Error **errp) 1691 { 1692 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1693 PCDIMMDevice *dimm = PC_DIMM(dev); 1694 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1695 MemoryRegion *mr = ddc->get_memory_region(dimm); 1696 HotplugHandlerClass *hhc; 1697 Error *local_err = NULL; 1698 1699 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1700 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1701 1702 if (local_err) { 1703 goto out; 1704 } 1705 1706 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1707 object_unparent(OBJECT(dev)); 1708 1709 out: 1710 error_propagate(errp, local_err); 1711 } 1712 1713 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1714 DeviceState *dev, Error **errp) 1715 { 1716 HotplugHandlerClass *hhc; 1717 Error *local_err = NULL; 1718 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1719 1720 if (!dev->hotplugged) { 1721 goto out; 1722 } 1723 1724 if (!pcms->acpi_dev) { 1725 error_setg(&local_err, 1726 "cpu hotplug is not enabled: missing acpi device"); 1727 goto out; 1728 } 1729 1730 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1731 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1732 if (local_err) { 1733 goto out; 1734 } 1735 1736 /* increment the number of CPUs */ 1737 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1738 out: 1739 error_propagate(errp, local_err); 1740 } 1741 1742 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1743 DeviceState *dev, Error **errp) 1744 { 1745 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1746 pc_dimm_plug(hotplug_dev, dev, errp); 1747 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1748 pc_cpu_plug(hotplug_dev, dev, errp); 1749 } 1750 } 1751 1752 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1753 DeviceState *dev, Error **errp) 1754 { 1755 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1756 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1757 } else { 1758 error_setg(errp, "acpi: device unplug request for not supported device" 1759 " type: %s", object_get_typename(OBJECT(dev))); 1760 } 1761 } 1762 1763 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1764 DeviceState *dev, Error **errp) 1765 { 1766 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1767 pc_dimm_unplug(hotplug_dev, dev, errp); 1768 } else { 1769 error_setg(errp, "acpi: device unplug for not supported device" 1770 " type: %s", object_get_typename(OBJECT(dev))); 1771 } 1772 } 1773 1774 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1775 DeviceState *dev) 1776 { 1777 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1778 1779 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1780 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1781 return HOTPLUG_HANDLER(machine); 1782 } 1783 1784 return pcmc->get_hotplug_handler ? 1785 pcmc->get_hotplug_handler(machine, dev) : NULL; 1786 } 1787 1788 static void 1789 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1790 const char *name, Error **errp) 1791 { 1792 PCMachineState *pcms = PC_MACHINE(obj); 1793 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1794 1795 visit_type_int(v, &value, name, errp); 1796 } 1797 1798 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1799 void *opaque, const char *name, 1800 Error **errp) 1801 { 1802 PCMachineState *pcms = PC_MACHINE(obj); 1803 uint64_t value = pcms->max_ram_below_4g; 1804 1805 visit_type_size(v, &value, name, errp); 1806 } 1807 1808 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1809 void *opaque, const char *name, 1810 Error **errp) 1811 { 1812 PCMachineState *pcms = PC_MACHINE(obj); 1813 Error *error = NULL; 1814 uint64_t value; 1815 1816 visit_type_size(v, &value, name, &error); 1817 if (error) { 1818 error_propagate(errp, error); 1819 return; 1820 } 1821 if (value > (1ULL << 32)) { 1822 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1823 "Machine option 'max-ram-below-4g=%"PRIu64 1824 "' expects size less than or equal to 4G", value); 1825 error_propagate(errp, error); 1826 return; 1827 } 1828 1829 if (value < (1ULL << 20)) { 1830 error_report("Warning: small max_ram_below_4g(%"PRIu64 1831 ") less than 1M. BIOS may not work..", 1832 value); 1833 } 1834 1835 pcms->max_ram_below_4g = value; 1836 } 1837 1838 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1839 const char *name, Error **errp) 1840 { 1841 PCMachineState *pcms = PC_MACHINE(obj); 1842 OnOffAuto vmport = pcms->vmport; 1843 1844 visit_type_OnOffAuto(v, &vmport, name, errp); 1845 } 1846 1847 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1848 const char *name, Error **errp) 1849 { 1850 PCMachineState *pcms = PC_MACHINE(obj); 1851 1852 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1853 } 1854 1855 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1856 { 1857 bool smm_available = false; 1858 1859 if (pcms->smm == ON_OFF_AUTO_OFF) { 1860 return false; 1861 } 1862 1863 if (tcg_enabled() || qtest_enabled()) { 1864 smm_available = true; 1865 } else if (kvm_enabled()) { 1866 smm_available = kvm_has_smm(); 1867 } 1868 1869 if (smm_available) { 1870 return true; 1871 } 1872 1873 if (pcms->smm == ON_OFF_AUTO_ON) { 1874 error_report("System Management Mode not supported by this hypervisor."); 1875 exit(1); 1876 } 1877 return false; 1878 } 1879 1880 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1881 const char *name, Error **errp) 1882 { 1883 PCMachineState *pcms = PC_MACHINE(obj); 1884 OnOffAuto smm = pcms->smm; 1885 1886 visit_type_OnOffAuto(v, &smm, name, errp); 1887 } 1888 1889 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1890 const char *name, Error **errp) 1891 { 1892 PCMachineState *pcms = PC_MACHINE(obj); 1893 1894 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1895 } 1896 1897 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1898 { 1899 PCMachineState *pcms = PC_MACHINE(obj); 1900 1901 return pcms->enforce_aligned_dimm; 1902 } 1903 1904 static void pc_machine_initfn(Object *obj) 1905 { 1906 PCMachineState *pcms = PC_MACHINE(obj); 1907 1908 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1909 pc_machine_get_hotplug_memory_region_size, 1910 NULL, NULL, NULL, &error_abort); 1911 1912 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1913 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1914 pc_machine_get_max_ram_below_4g, 1915 pc_machine_set_max_ram_below_4g, 1916 NULL, NULL, &error_abort); 1917 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1918 "Maximum ram below the 4G boundary (32bit boundary)", 1919 &error_abort); 1920 1921 pcms->smm = ON_OFF_AUTO_AUTO; 1922 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1923 pc_machine_get_smm, 1924 pc_machine_set_smm, 1925 NULL, NULL, &error_abort); 1926 object_property_set_description(obj, PC_MACHINE_SMM, 1927 "Enable SMM (pc & q35)", 1928 &error_abort); 1929 1930 pcms->vmport = ON_OFF_AUTO_AUTO; 1931 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1932 pc_machine_get_vmport, 1933 pc_machine_set_vmport, 1934 NULL, NULL, &error_abort); 1935 object_property_set_description(obj, PC_MACHINE_VMPORT, 1936 "Enable vmport (pc & q35)", 1937 &error_abort); 1938 1939 pcms->enforce_aligned_dimm = true; 1940 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1941 pc_machine_get_aligned_dimm, 1942 NULL, &error_abort); 1943 } 1944 1945 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1946 { 1947 unsigned pkg_id, core_id, smt_id; 1948 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1949 &pkg_id, &core_id, &smt_id); 1950 return pkg_id; 1951 } 1952 1953 static void pc_machine_class_init(ObjectClass *oc, void *data) 1954 { 1955 MachineClass *mc = MACHINE_CLASS(oc); 1956 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1957 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1958 1959 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1960 mc->get_hotplug_handler = pc_get_hotpug_handler; 1961 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1962 mc->default_boot_order = "cad"; 1963 mc->hot_add_cpu = pc_hot_add_cpu; 1964 mc->max_cpus = 255; 1965 hc->plug = pc_machine_device_plug_cb; 1966 hc->unplug_request = pc_machine_device_unplug_request_cb; 1967 hc->unplug = pc_machine_device_unplug_cb; 1968 } 1969 1970 static const TypeInfo pc_machine_info = { 1971 .name = TYPE_PC_MACHINE, 1972 .parent = TYPE_MACHINE, 1973 .abstract = true, 1974 .instance_size = sizeof(PCMachineState), 1975 .instance_init = pc_machine_initfn, 1976 .class_size = sizeof(PCMachineClass), 1977 .class_init = pc_machine_class_init, 1978 .interfaces = (InterfaceInfo[]) { 1979 { TYPE_HOTPLUG_HANDLER }, 1980 { } 1981 }, 1982 }; 1983 1984 static void pc_machine_register_types(void) 1985 { 1986 type_register_static(&pc_machine_info); 1987 } 1988 1989 type_init(pc_machine_register_types) 1990