1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 71 /* debug PC/ISA interrupts */ 72 //#define DEBUG_IRQ 73 74 #ifdef DEBUG_IRQ 75 #define DPRINTF(fmt, ...) \ 76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 77 #else 78 #define DPRINTF(fmt, ...) 79 #endif 80 81 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 82 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 83 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 84 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 85 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 86 87 #define E820_NR_ENTRIES 16 88 89 struct e820_entry { 90 uint64_t address; 91 uint64_t length; 92 uint32_t type; 93 } QEMU_PACKED __attribute((__aligned__(4))); 94 95 struct e820_table { 96 uint32_t count; 97 struct e820_entry entry[E820_NR_ENTRIES]; 98 } QEMU_PACKED __attribute((__aligned__(4))); 99 100 static struct e820_table e820_reserve; 101 static struct e820_entry *e820_table; 102 static unsigned e820_entries; 103 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 104 105 void gsi_handler(void *opaque, int n, int level) 106 { 107 GSIState *s = opaque; 108 109 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 110 if (n < ISA_NUM_IRQS) { 111 qemu_set_irq(s->i8259_irq[n], level); 112 } 113 qemu_set_irq(s->ioapic_irq[n], level); 114 } 115 116 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 117 unsigned size) 118 { 119 } 120 121 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 122 { 123 return 0xffffffffffffffffULL; 124 } 125 126 /* MSDOS compatibility mode FPU exception support */ 127 static qemu_irq ferr_irq; 128 129 void pc_register_ferr_irq(qemu_irq irq) 130 { 131 ferr_irq = irq; 132 } 133 134 /* XXX: add IGNNE support */ 135 void cpu_set_ferr(CPUX86State *s) 136 { 137 qemu_irq_raise(ferr_irq); 138 } 139 140 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 141 unsigned size) 142 { 143 qemu_irq_lower(ferr_irq); 144 } 145 146 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 147 { 148 return 0xffffffffffffffffULL; 149 } 150 151 /* TSC handling */ 152 uint64_t cpu_get_tsc(CPUX86State *env) 153 { 154 return cpu_get_ticks(); 155 } 156 157 /* IRQ handling */ 158 int cpu_get_pic_interrupt(CPUX86State *env) 159 { 160 X86CPU *cpu = x86_env_get_cpu(env); 161 int intno; 162 163 intno = apic_get_interrupt(cpu->apic_state); 164 if (intno >= 0) { 165 return intno; 166 } 167 /* read the irq from the PIC */ 168 if (!apic_accept_pic_intr(cpu->apic_state)) { 169 return -1; 170 } 171 172 intno = pic_read_irq(isa_pic); 173 return intno; 174 } 175 176 static void pic_irq_request(void *opaque, int irq, int level) 177 { 178 CPUState *cs = first_cpu; 179 X86CPU *cpu = X86_CPU(cs); 180 181 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 182 if (cpu->apic_state) { 183 CPU_FOREACH(cs) { 184 cpu = X86_CPU(cs); 185 if (apic_accept_pic_intr(cpu->apic_state)) { 186 apic_deliver_pic_intr(cpu->apic_state, level); 187 } 188 } 189 } else { 190 if (level) { 191 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 192 } else { 193 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 194 } 195 } 196 } 197 198 /* PC cmos mappings */ 199 200 #define REG_EQUIPMENT_BYTE 0x14 201 202 int cmos_get_fd_drive_type(FloppyDriveType fd0) 203 { 204 int val; 205 206 switch (fd0) { 207 case FLOPPY_DRIVE_TYPE_144: 208 /* 1.44 Mb 3"5 drive */ 209 val = 4; 210 break; 211 case FLOPPY_DRIVE_TYPE_288: 212 /* 2.88 Mb 3"5 drive */ 213 val = 5; 214 break; 215 case FLOPPY_DRIVE_TYPE_120: 216 /* 1.2 Mb 5"5 drive */ 217 val = 2; 218 break; 219 case FLOPPY_DRIVE_TYPE_NONE: 220 default: 221 val = 0; 222 break; 223 } 224 return val; 225 } 226 227 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 228 int16_t cylinders, int8_t heads, int8_t sectors) 229 { 230 rtc_set_memory(s, type_ofs, 47); 231 rtc_set_memory(s, info_ofs, cylinders); 232 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 233 rtc_set_memory(s, info_ofs + 2, heads); 234 rtc_set_memory(s, info_ofs + 3, 0xff); 235 rtc_set_memory(s, info_ofs + 4, 0xff); 236 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 237 rtc_set_memory(s, info_ofs + 6, cylinders); 238 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 239 rtc_set_memory(s, info_ofs + 8, sectors); 240 } 241 242 /* convert boot_device letter to something recognizable by the bios */ 243 static int boot_device2nibble(char boot_device) 244 { 245 switch(boot_device) { 246 case 'a': 247 case 'b': 248 return 0x01; /* floppy boot */ 249 case 'c': 250 return 0x02; /* hard drive boot */ 251 case 'd': 252 return 0x03; /* CD-ROM boot */ 253 case 'n': 254 return 0x04; /* Network boot */ 255 } 256 return 0; 257 } 258 259 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 260 { 261 #define PC_MAX_BOOT_DEVICES 3 262 int nbds, bds[3] = { 0, }; 263 int i; 264 265 nbds = strlen(boot_device); 266 if (nbds > PC_MAX_BOOT_DEVICES) { 267 error_setg(errp, "Too many boot devices for PC"); 268 return; 269 } 270 for (i = 0; i < nbds; i++) { 271 bds[i] = boot_device2nibble(boot_device[i]); 272 if (bds[i] == 0) { 273 error_setg(errp, "Invalid boot device for PC: '%c'", 274 boot_device[i]); 275 return; 276 } 277 } 278 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 279 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 280 } 281 282 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 283 { 284 set_boot_dev(opaque, boot_device, errp); 285 } 286 287 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 288 { 289 int val, nb, i; 290 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 291 FLOPPY_DRIVE_TYPE_NONE }; 292 293 /* floppy type */ 294 if (floppy) { 295 for (i = 0; i < 2; i++) { 296 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 297 } 298 } 299 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 300 cmos_get_fd_drive_type(fd_type[1]); 301 rtc_set_memory(rtc_state, 0x10, val); 302 303 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 304 nb = 0; 305 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 306 nb++; 307 } 308 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 309 nb++; 310 } 311 switch (nb) { 312 case 0: 313 break; 314 case 1: 315 val |= 0x01; /* 1 drive, ready for boot */ 316 break; 317 case 2: 318 val |= 0x41; /* 2 drives, ready for boot */ 319 break; 320 } 321 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 322 } 323 324 typedef struct pc_cmos_init_late_arg { 325 ISADevice *rtc_state; 326 BusState *idebus[2]; 327 } pc_cmos_init_late_arg; 328 329 typedef struct check_fdc_state { 330 ISADevice *floppy; 331 bool multiple; 332 } CheckFdcState; 333 334 static int check_fdc(Object *obj, void *opaque) 335 { 336 CheckFdcState *state = opaque; 337 Object *fdc; 338 uint32_t iobase; 339 Error *local_err = NULL; 340 341 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 342 if (!fdc) { 343 return 0; 344 } 345 346 iobase = object_property_get_int(obj, "iobase", &local_err); 347 if (local_err || iobase != 0x3f0) { 348 error_free(local_err); 349 return 0; 350 } 351 352 if (state->floppy) { 353 state->multiple = true; 354 } else { 355 state->floppy = ISA_DEVICE(obj); 356 } 357 return 0; 358 } 359 360 static const char * const fdc_container_path[] = { 361 "/unattached", "/peripheral", "/peripheral-anon" 362 }; 363 364 /* 365 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 366 * and ACPI objects. 367 */ 368 ISADevice *pc_find_fdc0(void) 369 { 370 int i; 371 Object *container; 372 CheckFdcState state = { 0 }; 373 374 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 375 container = container_get(qdev_get_machine(), fdc_container_path[i]); 376 object_child_foreach(container, check_fdc, &state); 377 } 378 379 if (state.multiple) { 380 error_report("warning: multiple floppy disk controllers with " 381 "iobase=0x3f0 have been found"); 382 error_printf("the one being picked for CMOS setup might not reflect " 383 "your intent"); 384 } 385 386 return state.floppy; 387 } 388 389 static void pc_cmos_init_late(void *opaque) 390 { 391 pc_cmos_init_late_arg *arg = opaque; 392 ISADevice *s = arg->rtc_state; 393 int16_t cylinders; 394 int8_t heads, sectors; 395 int val; 396 int i, trans; 397 398 val = 0; 399 if (ide_get_geometry(arg->idebus[0], 0, 400 &cylinders, &heads, §ors) >= 0) { 401 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 402 val |= 0xf0; 403 } 404 if (ide_get_geometry(arg->idebus[0], 1, 405 &cylinders, &heads, §ors) >= 0) { 406 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 407 val |= 0x0f; 408 } 409 rtc_set_memory(s, 0x12, val); 410 411 val = 0; 412 for (i = 0; i < 4; i++) { 413 /* NOTE: ide_get_geometry() returns the physical 414 geometry. It is always such that: 1 <= sects <= 63, 1 415 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 416 geometry can be different if a translation is done. */ 417 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 418 &cylinders, &heads, §ors) >= 0) { 419 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 420 assert((trans & ~3) == 0); 421 val |= trans << (i * 2); 422 } 423 } 424 rtc_set_memory(s, 0x39, val); 425 426 pc_cmos_init_floppy(s, pc_find_fdc0()); 427 428 qemu_unregister_reset(pc_cmos_init_late, opaque); 429 } 430 431 void pc_cmos_init(PCMachineState *pcms, 432 BusState *idebus0, BusState *idebus1, 433 ISADevice *s) 434 { 435 int val; 436 static pc_cmos_init_late_arg arg; 437 438 /* various important CMOS locations needed by PC/Bochs bios */ 439 440 /* memory size */ 441 /* base memory (first MiB) */ 442 val = MIN(pcms->below_4g_mem_size / 1024, 640); 443 rtc_set_memory(s, 0x15, val); 444 rtc_set_memory(s, 0x16, val >> 8); 445 /* extended memory (next 64MiB) */ 446 if (pcms->below_4g_mem_size > 1024 * 1024) { 447 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 448 } else { 449 val = 0; 450 } 451 if (val > 65535) 452 val = 65535; 453 rtc_set_memory(s, 0x17, val); 454 rtc_set_memory(s, 0x18, val >> 8); 455 rtc_set_memory(s, 0x30, val); 456 rtc_set_memory(s, 0x31, val >> 8); 457 /* memory between 16MiB and 4GiB */ 458 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 459 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 460 } else { 461 val = 0; 462 } 463 if (val > 65535) 464 val = 65535; 465 rtc_set_memory(s, 0x34, val); 466 rtc_set_memory(s, 0x35, val >> 8); 467 /* memory above 4GiB */ 468 val = pcms->above_4g_mem_size / 65536; 469 rtc_set_memory(s, 0x5b, val); 470 rtc_set_memory(s, 0x5c, val >> 8); 471 rtc_set_memory(s, 0x5d, val >> 16); 472 473 /* set the number of CPU */ 474 rtc_set_memory(s, 0x5f, smp_cpus - 1); 475 476 object_property_add_link(OBJECT(pcms), "rtc_state", 477 TYPE_ISA_DEVICE, 478 (Object **)&pcms->rtc, 479 object_property_allow_set_link, 480 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 481 object_property_set_link(OBJECT(pcms), OBJECT(s), 482 "rtc_state", &error_abort); 483 484 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 485 486 val = 0; 487 val |= 0x02; /* FPU is there */ 488 val |= 0x04; /* PS/2 mouse installed */ 489 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 490 491 /* hard drives and FDC */ 492 arg.rtc_state = s; 493 arg.idebus[0] = idebus0; 494 arg.idebus[1] = idebus1; 495 qemu_register_reset(pc_cmos_init_late, &arg); 496 } 497 498 #define TYPE_PORT92 "port92" 499 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 500 501 /* port 92 stuff: could be split off */ 502 typedef struct Port92State { 503 ISADevice parent_obj; 504 505 MemoryRegion io; 506 uint8_t outport; 507 qemu_irq *a20_out; 508 } Port92State; 509 510 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 511 unsigned size) 512 { 513 Port92State *s = opaque; 514 int oldval = s->outport; 515 516 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 517 s->outport = val; 518 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 519 if ((val & 1) && !(oldval & 1)) { 520 qemu_system_reset_request(); 521 } 522 } 523 524 static uint64_t port92_read(void *opaque, hwaddr addr, 525 unsigned size) 526 { 527 Port92State *s = opaque; 528 uint32_t ret; 529 530 ret = s->outport; 531 DPRINTF("port92: read 0x%02x\n", ret); 532 return ret; 533 } 534 535 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 536 { 537 Port92State *s = PORT92(dev); 538 539 s->a20_out = a20_out; 540 } 541 542 static const VMStateDescription vmstate_port92_isa = { 543 .name = "port92", 544 .version_id = 1, 545 .minimum_version_id = 1, 546 .fields = (VMStateField[]) { 547 VMSTATE_UINT8(outport, Port92State), 548 VMSTATE_END_OF_LIST() 549 } 550 }; 551 552 static void port92_reset(DeviceState *d) 553 { 554 Port92State *s = PORT92(d); 555 556 s->outport &= ~1; 557 } 558 559 static const MemoryRegionOps port92_ops = { 560 .read = port92_read, 561 .write = port92_write, 562 .impl = { 563 .min_access_size = 1, 564 .max_access_size = 1, 565 }, 566 .endianness = DEVICE_LITTLE_ENDIAN, 567 }; 568 569 static void port92_initfn(Object *obj) 570 { 571 Port92State *s = PORT92(obj); 572 573 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 574 575 s->outport = 0; 576 } 577 578 static void port92_realizefn(DeviceState *dev, Error **errp) 579 { 580 ISADevice *isadev = ISA_DEVICE(dev); 581 Port92State *s = PORT92(dev); 582 583 isa_register_ioport(isadev, &s->io, 0x92); 584 } 585 586 static void port92_class_initfn(ObjectClass *klass, void *data) 587 { 588 DeviceClass *dc = DEVICE_CLASS(klass); 589 590 dc->realize = port92_realizefn; 591 dc->reset = port92_reset; 592 dc->vmsd = &vmstate_port92_isa; 593 /* 594 * Reason: unlike ordinary ISA devices, this one needs additional 595 * wiring: its A20 output line needs to be wired up by 596 * port92_init(). 597 */ 598 dc->cannot_instantiate_with_device_add_yet = true; 599 } 600 601 static const TypeInfo port92_info = { 602 .name = TYPE_PORT92, 603 .parent = TYPE_ISA_DEVICE, 604 .instance_size = sizeof(Port92State), 605 .instance_init = port92_initfn, 606 .class_init = port92_class_initfn, 607 }; 608 609 static void port92_register_types(void) 610 { 611 type_register_static(&port92_info); 612 } 613 614 type_init(port92_register_types) 615 616 static void handle_a20_line_change(void *opaque, int irq, int level) 617 { 618 X86CPU *cpu = opaque; 619 620 /* XXX: send to all CPUs ? */ 621 /* XXX: add logic to handle multiple A20 line sources */ 622 x86_cpu_set_a20(cpu, level); 623 } 624 625 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 626 { 627 int index = le32_to_cpu(e820_reserve.count); 628 struct e820_entry *entry; 629 630 if (type != E820_RAM) { 631 /* old FW_CFG_E820_TABLE entry -- reservations only */ 632 if (index >= E820_NR_ENTRIES) { 633 return -EBUSY; 634 } 635 entry = &e820_reserve.entry[index++]; 636 637 entry->address = cpu_to_le64(address); 638 entry->length = cpu_to_le64(length); 639 entry->type = cpu_to_le32(type); 640 641 e820_reserve.count = cpu_to_le32(index); 642 } 643 644 /* new "etc/e820" file -- include ram too */ 645 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 646 e820_table[e820_entries].address = cpu_to_le64(address); 647 e820_table[e820_entries].length = cpu_to_le64(length); 648 e820_table[e820_entries].type = cpu_to_le32(type); 649 e820_entries++; 650 651 return e820_entries; 652 } 653 654 int e820_get_num_entries(void) 655 { 656 return e820_entries; 657 } 658 659 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 660 { 661 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 662 *address = le64_to_cpu(e820_table[idx].address); 663 *length = le64_to_cpu(e820_table[idx].length); 664 return true; 665 } 666 return false; 667 } 668 669 /* Enables contiguous-apic-ID mode, for compatibility */ 670 static bool compat_apic_id_mode; 671 672 void enable_compat_apic_id_mode(void) 673 { 674 compat_apic_id_mode = true; 675 } 676 677 /* Calculates initial APIC ID for a specific CPU index 678 * 679 * Currently we need to be able to calculate the APIC ID from the CPU index 680 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 681 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 682 * all CPUs up to max_cpus. 683 */ 684 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 685 { 686 uint32_t correct_id; 687 static bool warned; 688 689 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 690 if (compat_apic_id_mode) { 691 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 692 error_report("APIC IDs set in compatibility mode, " 693 "CPU topology won't match the configuration"); 694 warned = true; 695 } 696 return cpu_index; 697 } else { 698 return correct_id; 699 } 700 } 701 702 static void pc_build_smbios(FWCfgState *fw_cfg) 703 { 704 uint8_t *smbios_tables, *smbios_anchor; 705 size_t smbios_tables_len, smbios_anchor_len; 706 struct smbios_phys_mem_area *mem_array; 707 unsigned i, array_count; 708 709 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 710 if (smbios_tables) { 711 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 712 smbios_tables, smbios_tables_len); 713 } 714 715 /* build the array of physical mem area from e820 table */ 716 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 717 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 718 uint64_t addr, len; 719 720 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 721 mem_array[array_count].address = addr; 722 mem_array[array_count].length = len; 723 array_count++; 724 } 725 } 726 smbios_get_tables(mem_array, array_count, 727 &smbios_tables, &smbios_tables_len, 728 &smbios_anchor, &smbios_anchor_len); 729 g_free(mem_array); 730 731 if (smbios_anchor) { 732 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 733 smbios_tables, smbios_tables_len); 734 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 735 smbios_anchor, smbios_anchor_len); 736 } 737 } 738 739 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 740 { 741 FWCfgState *fw_cfg; 742 uint64_t *numa_fw_cfg; 743 int i, j; 744 745 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 746 747 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 748 * 749 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 750 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 751 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 752 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 753 * may see". 754 * 755 * So, this means we must not use max_cpus, here, but the maximum possible 756 * APIC ID value, plus one. 757 * 758 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 759 * the APIC ID, not the "CPU index" 760 */ 761 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 762 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 763 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 764 acpi_tables, acpi_tables_len); 765 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 766 767 pc_build_smbios(fw_cfg); 768 769 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 770 &e820_reserve, sizeof(e820_reserve)); 771 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 772 sizeof(struct e820_entry) * e820_entries); 773 774 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 775 /* allocate memory for the NUMA channel: one (64bit) word for the number 776 * of nodes, one word for each VCPU->node and one word for each node to 777 * hold the amount of memory. 778 */ 779 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 780 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 781 for (i = 0; i < max_cpus; i++) { 782 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 783 assert(apic_id < pcms->apic_id_limit); 784 for (j = 0; j < nb_numa_nodes; j++) { 785 if (test_bit(i, numa_info[j].node_cpu)) { 786 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 787 break; 788 } 789 } 790 } 791 for (i = 0; i < nb_numa_nodes; i++) { 792 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 793 cpu_to_le64(numa_info[i].node_mem); 794 } 795 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 796 (1 + pcms->apic_id_limit + nb_numa_nodes) * 797 sizeof(*numa_fw_cfg)); 798 799 return fw_cfg; 800 } 801 802 static long get_file_size(FILE *f) 803 { 804 long where, size; 805 806 /* XXX: on Unix systems, using fstat() probably makes more sense */ 807 808 where = ftell(f); 809 fseek(f, 0, SEEK_END); 810 size = ftell(f); 811 fseek(f, where, SEEK_SET); 812 813 return size; 814 } 815 816 static void load_linux(PCMachineState *pcms, 817 FWCfgState *fw_cfg) 818 { 819 uint16_t protocol; 820 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 821 uint32_t initrd_max; 822 uint8_t header[8192], *setup, *kernel, *initrd_data; 823 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 824 FILE *f; 825 char *vmode; 826 MachineState *machine = MACHINE(pcms); 827 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 828 const char *kernel_filename = machine->kernel_filename; 829 const char *initrd_filename = machine->initrd_filename; 830 const char *kernel_cmdline = machine->kernel_cmdline; 831 832 /* Align to 16 bytes as a paranoia measure */ 833 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 834 835 /* load the kernel header */ 836 f = fopen(kernel_filename, "rb"); 837 if (!f || !(kernel_size = get_file_size(f)) || 838 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 839 MIN(ARRAY_SIZE(header), kernel_size)) { 840 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 841 kernel_filename, strerror(errno)); 842 exit(1); 843 } 844 845 /* kernel protocol version */ 846 #if 0 847 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 848 #endif 849 if (ldl_p(header+0x202) == 0x53726448) { 850 protocol = lduw_p(header+0x206); 851 } else { 852 /* This looks like a multiboot kernel. If it is, let's stop 853 treating it like a Linux kernel. */ 854 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 855 kernel_cmdline, kernel_size, header)) { 856 return; 857 } 858 protocol = 0; 859 } 860 861 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 862 /* Low kernel */ 863 real_addr = 0x90000; 864 cmdline_addr = 0x9a000 - cmdline_size; 865 prot_addr = 0x10000; 866 } else if (protocol < 0x202) { 867 /* High but ancient kernel */ 868 real_addr = 0x90000; 869 cmdline_addr = 0x9a000 - cmdline_size; 870 prot_addr = 0x100000; 871 } else { 872 /* High and recent kernel */ 873 real_addr = 0x10000; 874 cmdline_addr = 0x20000; 875 prot_addr = 0x100000; 876 } 877 878 #if 0 879 fprintf(stderr, 880 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 881 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 882 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 883 real_addr, 884 cmdline_addr, 885 prot_addr); 886 #endif 887 888 /* highest address for loading the initrd */ 889 if (protocol >= 0x203) { 890 initrd_max = ldl_p(header+0x22c); 891 } else { 892 initrd_max = 0x37ffffff; 893 } 894 895 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 896 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 897 } 898 899 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 900 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 901 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 902 903 if (protocol >= 0x202) { 904 stl_p(header+0x228, cmdline_addr); 905 } else { 906 stw_p(header+0x20, 0xA33F); 907 stw_p(header+0x22, cmdline_addr-real_addr); 908 } 909 910 /* handle vga= parameter */ 911 vmode = strstr(kernel_cmdline, "vga="); 912 if (vmode) { 913 unsigned int video_mode; 914 /* skip "vga=" */ 915 vmode += 4; 916 if (!strncmp(vmode, "normal", 6)) { 917 video_mode = 0xffff; 918 } else if (!strncmp(vmode, "ext", 3)) { 919 video_mode = 0xfffe; 920 } else if (!strncmp(vmode, "ask", 3)) { 921 video_mode = 0xfffd; 922 } else { 923 video_mode = strtol(vmode, NULL, 0); 924 } 925 stw_p(header+0x1fa, video_mode); 926 } 927 928 /* loader type */ 929 /* High nybble = B reserved for QEMU; low nybble is revision number. 930 If this code is substantially changed, you may want to consider 931 incrementing the revision. */ 932 if (protocol >= 0x200) { 933 header[0x210] = 0xB0; 934 } 935 /* heap */ 936 if (protocol >= 0x201) { 937 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 938 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 939 } 940 941 /* load initrd */ 942 if (initrd_filename) { 943 if (protocol < 0x200) { 944 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 945 exit(1); 946 } 947 948 initrd_size = get_image_size(initrd_filename); 949 if (initrd_size < 0) { 950 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 951 initrd_filename, strerror(errno)); 952 exit(1); 953 } 954 955 initrd_addr = (initrd_max-initrd_size) & ~4095; 956 957 initrd_data = g_malloc(initrd_size); 958 load_image(initrd_filename, initrd_data); 959 960 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 961 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 962 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 963 964 stl_p(header+0x218, initrd_addr); 965 stl_p(header+0x21c, initrd_size); 966 } 967 968 /* load kernel and setup */ 969 setup_size = header[0x1f1]; 970 if (setup_size == 0) { 971 setup_size = 4; 972 } 973 setup_size = (setup_size+1)*512; 974 if (setup_size > kernel_size) { 975 fprintf(stderr, "qemu: invalid kernel header\n"); 976 exit(1); 977 } 978 kernel_size -= setup_size; 979 980 setup = g_malloc(setup_size); 981 kernel = g_malloc(kernel_size); 982 fseek(f, 0, SEEK_SET); 983 if (fread(setup, 1, setup_size, f) != setup_size) { 984 fprintf(stderr, "fread() failed\n"); 985 exit(1); 986 } 987 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 988 fprintf(stderr, "fread() failed\n"); 989 exit(1); 990 } 991 fclose(f); 992 memcpy(setup, header, MIN(sizeof(header), setup_size)); 993 994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 995 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 996 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 997 998 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 999 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1000 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1001 1002 option_rom[nb_option_roms].name = "linuxboot.bin"; 1003 option_rom[nb_option_roms].bootindex = 0; 1004 nb_option_roms++; 1005 } 1006 1007 #define NE2000_NB_MAX 6 1008 1009 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1010 0x280, 0x380 }; 1011 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1012 1013 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1014 { 1015 static int nb_ne2k = 0; 1016 1017 if (nb_ne2k == NE2000_NB_MAX) 1018 return; 1019 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1020 ne2000_irq[nb_ne2k], nd); 1021 nb_ne2k++; 1022 } 1023 1024 DeviceState *cpu_get_current_apic(void) 1025 { 1026 if (current_cpu) { 1027 X86CPU *cpu = X86_CPU(current_cpu); 1028 return cpu->apic_state; 1029 } else { 1030 return NULL; 1031 } 1032 } 1033 1034 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1035 { 1036 X86CPU *cpu = opaque; 1037 1038 if (level) { 1039 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1040 } 1041 } 1042 1043 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1044 Error **errp) 1045 { 1046 X86CPU *cpu = NULL; 1047 Error *local_err = NULL; 1048 1049 cpu = cpu_x86_create(cpu_model, &local_err); 1050 if (local_err != NULL) { 1051 goto out; 1052 } 1053 1054 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1055 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1056 1057 out: 1058 if (local_err) { 1059 error_propagate(errp, local_err); 1060 object_unref(OBJECT(cpu)); 1061 cpu = NULL; 1062 } 1063 return cpu; 1064 } 1065 1066 void pc_hot_add_cpu(const int64_t id, Error **errp) 1067 { 1068 X86CPU *cpu; 1069 MachineState *machine = MACHINE(qdev_get_machine()); 1070 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1071 Error *local_err = NULL; 1072 1073 if (id < 0) { 1074 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1075 return; 1076 } 1077 1078 if (cpu_exists(apic_id)) { 1079 error_setg(errp, "Unable to add CPU: %" PRIi64 1080 ", it already exists", id); 1081 return; 1082 } 1083 1084 if (id >= max_cpus) { 1085 error_setg(errp, "Unable to add CPU: %" PRIi64 1086 ", max allowed: %d", id, max_cpus - 1); 1087 return; 1088 } 1089 1090 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1091 error_setg(errp, "Unable to add CPU: %" PRIi64 1092 ", resulting APIC ID (%" PRIi64 ") is too large", 1093 id, apic_id); 1094 return; 1095 } 1096 1097 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1098 if (local_err) { 1099 error_propagate(errp, local_err); 1100 return; 1101 } 1102 object_unref(OBJECT(cpu)); 1103 } 1104 1105 void pc_cpus_init(PCMachineState *pcms) 1106 { 1107 int i; 1108 X86CPU *cpu = NULL; 1109 MachineState *machine = MACHINE(pcms); 1110 1111 /* init CPUs */ 1112 if (machine->cpu_model == NULL) { 1113 #ifdef TARGET_X86_64 1114 machine->cpu_model = "qemu64"; 1115 #else 1116 machine->cpu_model = "qemu32"; 1117 #endif 1118 } 1119 1120 /* Calculates the limit to CPU APIC ID values 1121 * 1122 * Limit for the APIC ID value, so that all 1123 * CPU APIC IDs are < pcms->apic_id_limit. 1124 * 1125 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1126 */ 1127 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1128 if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1129 error_report("max_cpus is too large. APIC ID of last CPU is %u", 1130 pcms->apic_id_limit - 1); 1131 exit(1); 1132 } 1133 1134 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1135 sizeof(CPUArchId) * max_cpus); 1136 for (i = 0; i < max_cpus; i++) { 1137 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 1138 pcms->possible_cpus->len++; 1139 if (i < smp_cpus) { 1140 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1141 &error_fatal); 1142 pcms->possible_cpus->cpus[i].cpu = CPU(cpu); 1143 object_unref(OBJECT(cpu)); 1144 } 1145 } 1146 1147 /* tell smbios about cpuid version and features */ 1148 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1149 } 1150 1151 /* pci-info ROM file. Little endian format */ 1152 typedef struct PcRomPciInfo { 1153 uint64_t w32_min; 1154 uint64_t w32_max; 1155 uint64_t w64_min; 1156 uint64_t w64_max; 1157 } PcRomPciInfo; 1158 1159 static 1160 void pc_machine_done(Notifier *notifier, void *data) 1161 { 1162 PCMachineState *pcms = container_of(notifier, 1163 PCMachineState, machine_done); 1164 PCIBus *bus = pcms->bus; 1165 1166 if (bus) { 1167 int extra_hosts = 0; 1168 1169 QLIST_FOREACH(bus, &bus->child, sibling) { 1170 /* look for expander root buses */ 1171 if (pci_bus_is_root(bus)) { 1172 extra_hosts++; 1173 } 1174 } 1175 if (extra_hosts && pcms->fw_cfg) { 1176 uint64_t *val = g_malloc(sizeof(*val)); 1177 *val = cpu_to_le64(extra_hosts); 1178 fw_cfg_add_file(pcms->fw_cfg, 1179 "etc/extra-pci-roots", val, sizeof(*val)); 1180 } 1181 } 1182 1183 acpi_setup(); 1184 } 1185 1186 void pc_guest_info_init(PCMachineState *pcms) 1187 { 1188 int i, j; 1189 1190 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1191 pcms->numa_nodes = nb_numa_nodes; 1192 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1193 sizeof *pcms->node_mem); 1194 for (i = 0; i < nb_numa_nodes; i++) { 1195 pcms->node_mem[i] = numa_info[i].node_mem; 1196 } 1197 1198 pcms->node_cpu = g_malloc0(pcms->apic_id_limit * 1199 sizeof *pcms->node_cpu); 1200 1201 for (i = 0; i < max_cpus; i++) { 1202 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1203 assert(apic_id < pcms->apic_id_limit); 1204 for (j = 0; j < nb_numa_nodes; j++) { 1205 if (test_bit(i, numa_info[j].node_cpu)) { 1206 pcms->node_cpu[apic_id] = j; 1207 break; 1208 } 1209 } 1210 } 1211 1212 pcms->machine_done.notify = pc_machine_done; 1213 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1214 } 1215 1216 /* setup pci memory address space mapping into system address space */ 1217 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1218 MemoryRegion *pci_address_space) 1219 { 1220 /* Set to lower priority than RAM */ 1221 memory_region_add_subregion_overlap(system_memory, 0x0, 1222 pci_address_space, -1); 1223 } 1224 1225 void pc_acpi_init(const char *default_dsdt) 1226 { 1227 char *filename; 1228 1229 if (acpi_tables != NULL) { 1230 /* manually set via -acpitable, leave it alone */ 1231 return; 1232 } 1233 1234 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1235 if (filename == NULL) { 1236 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1237 } else { 1238 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1239 &error_abort); 1240 Error *err = NULL; 1241 1242 qemu_opt_set(opts, "file", filename, &error_abort); 1243 1244 acpi_table_add_builtin(opts, &err); 1245 if (err) { 1246 error_reportf_err(err, "WARNING: failed to load %s: ", 1247 filename); 1248 } 1249 g_free(filename); 1250 } 1251 } 1252 1253 void xen_load_linux(PCMachineState *pcms) 1254 { 1255 int i; 1256 FWCfgState *fw_cfg; 1257 1258 assert(MACHINE(pcms)->kernel_filename != NULL); 1259 1260 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1261 rom_set_fw(fw_cfg); 1262 1263 load_linux(pcms, fw_cfg); 1264 for (i = 0; i < nb_option_roms; i++) { 1265 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1266 !strcmp(option_rom[i].name, "multiboot.bin")); 1267 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1268 } 1269 pcms->fw_cfg = fw_cfg; 1270 } 1271 1272 void pc_memory_init(PCMachineState *pcms, 1273 MemoryRegion *system_memory, 1274 MemoryRegion *rom_memory, 1275 MemoryRegion **ram_memory) 1276 { 1277 int linux_boot, i; 1278 MemoryRegion *ram, *option_rom_mr; 1279 MemoryRegion *ram_below_4g, *ram_above_4g; 1280 FWCfgState *fw_cfg; 1281 MachineState *machine = MACHINE(pcms); 1282 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1283 1284 assert(machine->ram_size == pcms->below_4g_mem_size + 1285 pcms->above_4g_mem_size); 1286 1287 linux_boot = (machine->kernel_filename != NULL); 1288 1289 /* Allocate RAM. We allocate it as a single memory region and use 1290 * aliases to address portions of it, mostly for backwards compatibility 1291 * with older qemus that used qemu_ram_alloc(). 1292 */ 1293 ram = g_malloc(sizeof(*ram)); 1294 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1295 machine->ram_size); 1296 *ram_memory = ram; 1297 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1298 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1299 0, pcms->below_4g_mem_size); 1300 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1301 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1302 if (pcms->above_4g_mem_size > 0) { 1303 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1304 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1305 pcms->below_4g_mem_size, 1306 pcms->above_4g_mem_size); 1307 memory_region_add_subregion(system_memory, 0x100000000ULL, 1308 ram_above_4g); 1309 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1310 } 1311 1312 if (!pcmc->has_reserved_memory && 1313 (machine->ram_slots || 1314 (machine->maxram_size > machine->ram_size))) { 1315 MachineClass *mc = MACHINE_GET_CLASS(machine); 1316 1317 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1318 mc->name); 1319 exit(EXIT_FAILURE); 1320 } 1321 1322 /* initialize hotplug memory address space */ 1323 if (pcmc->has_reserved_memory && 1324 (machine->ram_size < machine->maxram_size)) { 1325 ram_addr_t hotplug_mem_size = 1326 machine->maxram_size - machine->ram_size; 1327 1328 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1329 error_report("unsupported amount of memory slots: %"PRIu64, 1330 machine->ram_slots); 1331 exit(EXIT_FAILURE); 1332 } 1333 1334 if (QEMU_ALIGN_UP(machine->maxram_size, 1335 TARGET_PAGE_SIZE) != machine->maxram_size) { 1336 error_report("maximum memory size must by aligned to multiple of " 1337 "%d bytes", TARGET_PAGE_SIZE); 1338 exit(EXIT_FAILURE); 1339 } 1340 1341 pcms->hotplug_memory.base = 1342 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1343 1344 if (pcmc->enforce_aligned_dimm) { 1345 /* size hotplug region assuming 1G page max alignment per slot */ 1346 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1347 } 1348 1349 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1350 hotplug_mem_size) { 1351 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1352 machine->maxram_size); 1353 exit(EXIT_FAILURE); 1354 } 1355 1356 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1357 "hotplug-memory", hotplug_mem_size); 1358 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1359 &pcms->hotplug_memory.mr); 1360 } 1361 1362 /* Initialize PC system firmware */ 1363 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1364 1365 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1366 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1367 &error_fatal); 1368 vmstate_register_ram_global(option_rom_mr); 1369 memory_region_add_subregion_overlap(rom_memory, 1370 PC_ROM_MIN_VGA, 1371 option_rom_mr, 1372 1); 1373 1374 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1375 1376 rom_set_fw(fw_cfg); 1377 1378 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { 1379 uint64_t *val = g_malloc(sizeof(*val)); 1380 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1381 uint64_t res_mem_end = pcms->hotplug_memory.base; 1382 1383 if (!pcmc->broken_reserved_end) { 1384 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1385 } 1386 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1387 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1388 } 1389 1390 if (linux_boot) { 1391 load_linux(pcms, fw_cfg); 1392 } 1393 1394 for (i = 0; i < nb_option_roms; i++) { 1395 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1396 } 1397 pcms->fw_cfg = fw_cfg; 1398 } 1399 1400 qemu_irq pc_allocate_cpu_irq(void) 1401 { 1402 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1403 } 1404 1405 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1406 { 1407 DeviceState *dev = NULL; 1408 1409 if (pci_bus) { 1410 PCIDevice *pcidev = pci_vga_init(pci_bus); 1411 dev = pcidev ? &pcidev->qdev : NULL; 1412 } else if (isa_bus) { 1413 ISADevice *isadev = isa_vga_init(isa_bus); 1414 dev = isadev ? DEVICE(isadev) : NULL; 1415 } 1416 return dev; 1417 } 1418 1419 static const MemoryRegionOps ioport80_io_ops = { 1420 .write = ioport80_write, 1421 .read = ioport80_read, 1422 .endianness = DEVICE_NATIVE_ENDIAN, 1423 .impl = { 1424 .min_access_size = 1, 1425 .max_access_size = 1, 1426 }, 1427 }; 1428 1429 static const MemoryRegionOps ioportF0_io_ops = { 1430 .write = ioportF0_write, 1431 .read = ioportF0_read, 1432 .endianness = DEVICE_NATIVE_ENDIAN, 1433 .impl = { 1434 .min_access_size = 1, 1435 .max_access_size = 1, 1436 }, 1437 }; 1438 1439 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1440 ISADevice **rtc_state, 1441 bool create_fdctrl, 1442 bool no_vmport, 1443 uint32_t hpet_irqs) 1444 { 1445 int i; 1446 DriveInfo *fd[MAX_FD]; 1447 DeviceState *hpet = NULL; 1448 int pit_isa_irq = 0; 1449 qemu_irq pit_alt_irq = NULL; 1450 qemu_irq rtc_irq = NULL; 1451 qemu_irq *a20_line; 1452 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1453 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1454 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1455 1456 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1457 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1458 1459 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1460 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1461 1462 /* 1463 * Check if an HPET shall be created. 1464 * 1465 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1466 * when the HPET wants to take over. Thus we have to disable the latter. 1467 */ 1468 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1469 /* In order to set property, here not using sysbus_try_create_simple */ 1470 hpet = qdev_try_create(NULL, TYPE_HPET); 1471 if (hpet) { 1472 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1473 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1474 * IRQ8 and IRQ2. 1475 */ 1476 uint8_t compat = object_property_get_int(OBJECT(hpet), 1477 HPET_INTCAP, NULL); 1478 if (!compat) { 1479 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1480 } 1481 qdev_init_nofail(hpet); 1482 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1483 1484 for (i = 0; i < GSI_NUM_PINS; i++) { 1485 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1486 } 1487 pit_isa_irq = -1; 1488 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1489 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1490 } 1491 } 1492 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1493 1494 qemu_register_boot_set(pc_boot_set, *rtc_state); 1495 1496 if (!xen_enabled()) { 1497 if (kvm_pit_in_kernel()) { 1498 pit = kvm_pit_init(isa_bus, 0x40); 1499 } else { 1500 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1501 } 1502 if (hpet) { 1503 /* connect PIT to output control line of the HPET */ 1504 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1505 } 1506 pcspk_init(isa_bus, pit); 1507 } 1508 1509 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1510 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1511 1512 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1513 i8042 = isa_create_simple(isa_bus, "i8042"); 1514 i8042_setup_a20_line(i8042, &a20_line[0]); 1515 if (!no_vmport) { 1516 vmport_init(isa_bus); 1517 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1518 } else { 1519 vmmouse = NULL; 1520 } 1521 if (vmmouse) { 1522 DeviceState *dev = DEVICE(vmmouse); 1523 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1524 qdev_init_nofail(dev); 1525 } 1526 port92 = isa_create_simple(isa_bus, "port92"); 1527 port92_init(port92, &a20_line[1]); 1528 1529 DMA_init(isa_bus, 0); 1530 1531 for(i = 0; i < MAX_FD; i++) { 1532 fd[i] = drive_get(IF_FLOPPY, 0, i); 1533 create_fdctrl |= !!fd[i]; 1534 } 1535 if (create_fdctrl) { 1536 fdctrl_init_isa(isa_bus, fd); 1537 } 1538 } 1539 1540 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1541 { 1542 int i; 1543 1544 for (i = 0; i < nb_nics; i++) { 1545 NICInfo *nd = &nd_table[i]; 1546 1547 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1548 pc_init_ne2k_isa(isa_bus, nd); 1549 } else { 1550 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1551 } 1552 } 1553 } 1554 1555 void pc_pci_device_init(PCIBus *pci_bus) 1556 { 1557 int max_bus; 1558 int bus; 1559 1560 max_bus = drive_get_max_bus(IF_SCSI); 1561 for (bus = 0; bus <= max_bus; bus++) { 1562 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1563 } 1564 } 1565 1566 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1567 { 1568 DeviceState *dev; 1569 SysBusDevice *d; 1570 unsigned int i; 1571 1572 if (kvm_ioapic_in_kernel()) { 1573 dev = qdev_create(NULL, "kvm-ioapic"); 1574 } else { 1575 dev = qdev_create(NULL, "ioapic"); 1576 } 1577 if (parent_name) { 1578 object_property_add_child(object_resolve_path(parent_name, NULL), 1579 "ioapic", OBJECT(dev), NULL); 1580 } 1581 qdev_init_nofail(dev); 1582 d = SYS_BUS_DEVICE(dev); 1583 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1584 1585 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1586 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1587 } 1588 } 1589 1590 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1591 DeviceState *dev, Error **errp) 1592 { 1593 HotplugHandlerClass *hhc; 1594 Error *local_err = NULL; 1595 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1596 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1597 PCDIMMDevice *dimm = PC_DIMM(dev); 1598 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1599 MemoryRegion *mr = ddc->get_memory_region(dimm); 1600 uint64_t align = TARGET_PAGE_SIZE; 1601 1602 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1603 align = memory_region_get_alignment(mr); 1604 } 1605 1606 if (!pcms->acpi_dev) { 1607 error_setg(&local_err, 1608 "memory hotplug is not enabled: missing acpi device"); 1609 goto out; 1610 } 1611 1612 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1613 if (local_err) { 1614 goto out; 1615 } 1616 1617 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1618 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1619 out: 1620 error_propagate(errp, local_err); 1621 } 1622 1623 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1624 DeviceState *dev, Error **errp) 1625 { 1626 HotplugHandlerClass *hhc; 1627 Error *local_err = NULL; 1628 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1629 1630 if (!pcms->acpi_dev) { 1631 error_setg(&local_err, 1632 "memory hotplug is not enabled: missing acpi device"); 1633 goto out; 1634 } 1635 1636 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1637 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1638 1639 out: 1640 error_propagate(errp, local_err); 1641 } 1642 1643 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1644 DeviceState *dev, Error **errp) 1645 { 1646 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1647 PCDIMMDevice *dimm = PC_DIMM(dev); 1648 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1649 MemoryRegion *mr = ddc->get_memory_region(dimm); 1650 HotplugHandlerClass *hhc; 1651 Error *local_err = NULL; 1652 1653 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1654 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1655 1656 if (local_err) { 1657 goto out; 1658 } 1659 1660 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1661 object_unparent(OBJECT(dev)); 1662 1663 out: 1664 error_propagate(errp, local_err); 1665 } 1666 1667 static int pc_apic_cmp(const void *a, const void *b) 1668 { 1669 CPUArchId *apic_a = (CPUArchId *)a; 1670 CPUArchId *apic_b = (CPUArchId *)b; 1671 1672 return apic_a->arch_id - apic_b->arch_id; 1673 } 1674 1675 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1676 DeviceState *dev, Error **errp) 1677 { 1678 CPUClass *cc = CPU_GET_CLASS(dev); 1679 CPUArchId apic_id, *found_cpu; 1680 HotplugHandlerClass *hhc; 1681 Error *local_err = NULL; 1682 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1683 1684 if (!dev->hotplugged) { 1685 goto out; 1686 } 1687 1688 if (!pcms->acpi_dev) { 1689 error_setg(&local_err, 1690 "cpu hotplug is not enabled: missing acpi device"); 1691 goto out; 1692 } 1693 1694 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1695 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1696 if (local_err) { 1697 goto out; 1698 } 1699 1700 /* increment the number of CPUs */ 1701 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1702 1703 apic_id.arch_id = cc->get_arch_id(CPU(dev)); 1704 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, 1705 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), 1706 pc_apic_cmp); 1707 assert(found_cpu); 1708 found_cpu->cpu = CPU(dev); 1709 out: 1710 error_propagate(errp, local_err); 1711 } 1712 1713 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1714 DeviceState *dev, Error **errp) 1715 { 1716 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1717 pc_dimm_plug(hotplug_dev, dev, errp); 1718 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1719 pc_cpu_plug(hotplug_dev, dev, errp); 1720 } 1721 } 1722 1723 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1724 DeviceState *dev, Error **errp) 1725 { 1726 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1727 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1728 } else { 1729 error_setg(errp, "acpi: device unplug request for not supported device" 1730 " type: %s", object_get_typename(OBJECT(dev))); 1731 } 1732 } 1733 1734 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1735 DeviceState *dev, Error **errp) 1736 { 1737 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1738 pc_dimm_unplug(hotplug_dev, dev, errp); 1739 } else { 1740 error_setg(errp, "acpi: device unplug for not supported device" 1741 " type: %s", object_get_typename(OBJECT(dev))); 1742 } 1743 } 1744 1745 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1746 DeviceState *dev) 1747 { 1748 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1749 1750 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1751 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1752 return HOTPLUG_HANDLER(machine); 1753 } 1754 1755 return pcmc->get_hotplug_handler ? 1756 pcmc->get_hotplug_handler(machine, dev) : NULL; 1757 } 1758 1759 static void 1760 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, 1761 const char *name, void *opaque, 1762 Error **errp) 1763 { 1764 PCMachineState *pcms = PC_MACHINE(obj); 1765 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1766 1767 visit_type_int(v, name, &value, errp); 1768 } 1769 1770 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1771 const char *name, void *opaque, 1772 Error **errp) 1773 { 1774 PCMachineState *pcms = PC_MACHINE(obj); 1775 uint64_t value = pcms->max_ram_below_4g; 1776 1777 visit_type_size(v, name, &value, errp); 1778 } 1779 1780 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1781 const char *name, void *opaque, 1782 Error **errp) 1783 { 1784 PCMachineState *pcms = PC_MACHINE(obj); 1785 Error *error = NULL; 1786 uint64_t value; 1787 1788 visit_type_size(v, name, &value, &error); 1789 if (error) { 1790 error_propagate(errp, error); 1791 return; 1792 } 1793 if (value > (1ULL << 32)) { 1794 error_setg(&error, 1795 "Machine option 'max-ram-below-4g=%"PRIu64 1796 "' expects size less than or equal to 4G", value); 1797 error_propagate(errp, error); 1798 return; 1799 } 1800 1801 if (value < (1ULL << 20)) { 1802 error_report("Warning: small max_ram_below_4g(%"PRIu64 1803 ") less than 1M. BIOS may not work..", 1804 value); 1805 } 1806 1807 pcms->max_ram_below_4g = value; 1808 } 1809 1810 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1811 void *opaque, Error **errp) 1812 { 1813 PCMachineState *pcms = PC_MACHINE(obj); 1814 OnOffAuto vmport = pcms->vmport; 1815 1816 visit_type_OnOffAuto(v, name, &vmport, errp); 1817 } 1818 1819 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1820 void *opaque, Error **errp) 1821 { 1822 PCMachineState *pcms = PC_MACHINE(obj); 1823 1824 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1825 } 1826 1827 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1828 { 1829 bool smm_available = false; 1830 1831 if (pcms->smm == ON_OFF_AUTO_OFF) { 1832 return false; 1833 } 1834 1835 if (tcg_enabled() || qtest_enabled()) { 1836 smm_available = true; 1837 } else if (kvm_enabled()) { 1838 smm_available = kvm_has_smm(); 1839 } 1840 1841 if (smm_available) { 1842 return true; 1843 } 1844 1845 if (pcms->smm == ON_OFF_AUTO_ON) { 1846 error_report("System Management Mode not supported by this hypervisor."); 1847 exit(1); 1848 } 1849 return false; 1850 } 1851 1852 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 1853 void *opaque, Error **errp) 1854 { 1855 PCMachineState *pcms = PC_MACHINE(obj); 1856 OnOffAuto smm = pcms->smm; 1857 1858 visit_type_OnOffAuto(v, name, &smm, errp); 1859 } 1860 1861 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 1862 void *opaque, Error **errp) 1863 { 1864 PCMachineState *pcms = PC_MACHINE(obj); 1865 1866 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 1867 } 1868 1869 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 1870 { 1871 PCMachineState *pcms = PC_MACHINE(obj); 1872 1873 return pcms->acpi_nvdimm_state.is_enabled; 1874 } 1875 1876 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 1877 { 1878 PCMachineState *pcms = PC_MACHINE(obj); 1879 1880 pcms->acpi_nvdimm_state.is_enabled = value; 1881 } 1882 1883 static void pc_machine_initfn(Object *obj) 1884 { 1885 PCMachineState *pcms = PC_MACHINE(obj); 1886 1887 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1888 pc_machine_get_hotplug_memory_region_size, 1889 NULL, NULL, NULL, &error_abort); 1890 1891 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1892 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1893 pc_machine_get_max_ram_below_4g, 1894 pc_machine_set_max_ram_below_4g, 1895 NULL, NULL, &error_abort); 1896 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1897 "Maximum ram below the 4G boundary (32bit boundary)", 1898 &error_abort); 1899 1900 pcms->smm = ON_OFF_AUTO_AUTO; 1901 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1902 pc_machine_get_smm, 1903 pc_machine_set_smm, 1904 NULL, NULL, &error_abort); 1905 object_property_set_description(obj, PC_MACHINE_SMM, 1906 "Enable SMM (pc & q35)", 1907 &error_abort); 1908 1909 pcms->vmport = ON_OFF_AUTO_AUTO; 1910 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1911 pc_machine_get_vmport, 1912 pc_machine_set_vmport, 1913 NULL, NULL, &error_abort); 1914 object_property_set_description(obj, PC_MACHINE_VMPORT, 1915 "Enable vmport (pc & q35)", 1916 &error_abort); 1917 1918 /* nvdimm is disabled on default. */ 1919 pcms->acpi_nvdimm_state.is_enabled = false; 1920 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 1921 pc_machine_set_nvdimm, &error_abort); 1922 } 1923 1924 static void pc_machine_reset(void) 1925 { 1926 CPUState *cs; 1927 X86CPU *cpu; 1928 1929 qemu_devices_reset(); 1930 1931 /* Reset APIC after devices have been reset to cancel 1932 * any changes that qemu_devices_reset() might have done. 1933 */ 1934 CPU_FOREACH(cs) { 1935 cpu = X86_CPU(cs); 1936 1937 if (cpu->apic_state) { 1938 device_reset(cpu->apic_state); 1939 } 1940 } 1941 } 1942 1943 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1944 { 1945 X86CPUTopoInfo topo; 1946 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1947 &topo); 1948 return topo.pkg_id; 1949 } 1950 1951 static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) 1952 { 1953 PCMachineState *pcms = PC_MACHINE(machine); 1954 int len = sizeof(CPUArchIdList) + 1955 sizeof(CPUArchId) * (pcms->possible_cpus->len); 1956 CPUArchIdList *list = g_malloc(len); 1957 1958 memcpy(list, pcms->possible_cpus, len); 1959 return list; 1960 } 1961 1962 static void pc_machine_class_init(ObjectClass *oc, void *data) 1963 { 1964 MachineClass *mc = MACHINE_CLASS(oc); 1965 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1966 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1967 1968 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1969 pcmc->pci_enabled = true; 1970 pcmc->has_acpi_build = true; 1971 pcmc->rsdp_in_ram = true; 1972 pcmc->smbios_defaults = true; 1973 pcmc->smbios_uuid_encoded = true; 1974 pcmc->gigabyte_align = true; 1975 pcmc->has_reserved_memory = true; 1976 pcmc->kvmclock_enabled = true; 1977 pcmc->enforce_aligned_dimm = true; 1978 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1979 * to be used at the moment, 32K should be enough for a while. */ 1980 pcmc->acpi_data_size = 0x20000 + 0x8000; 1981 pcmc->save_tsc_khz = true; 1982 mc->get_hotplug_handler = pc_get_hotpug_handler; 1983 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1984 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 1985 mc->default_boot_order = "cad"; 1986 mc->hot_add_cpu = pc_hot_add_cpu; 1987 mc->max_cpus = 255; 1988 mc->reset = pc_machine_reset; 1989 hc->plug = pc_machine_device_plug_cb; 1990 hc->unplug_request = pc_machine_device_unplug_request_cb; 1991 hc->unplug = pc_machine_device_unplug_cb; 1992 } 1993 1994 static const TypeInfo pc_machine_info = { 1995 .name = TYPE_PC_MACHINE, 1996 .parent = TYPE_MACHINE, 1997 .abstract = true, 1998 .instance_size = sizeof(PCMachineState), 1999 .instance_init = pc_machine_initfn, 2000 .class_size = sizeof(PCMachineClass), 2001 .class_init = pc_machine_class_init, 2002 .interfaces = (InterfaceInfo[]) { 2003 { TYPE_HOTPLUG_HANDLER }, 2004 { } 2005 }, 2006 }; 2007 2008 static void pc_machine_register_types(void) 2009 { 2010 type_register_static(&pc_machine_info); 2011 } 2012 2013 type_init(pc_machine_register_types) 2014