1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/visitor.h" 81 #include "hw/core/cpu.h" 82 #include "hw/usb.h" 83 #include "hw/i386/intel_iommu.h" 84 #include "hw/net/ne2000-isa.h" 85 #include "standard-headers/asm-x86/bootparam.h" 86 #include "hw/virtio/virtio-iommu.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_1[] = { 98 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 99 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 100 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 101 }; 102 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 103 104 GlobalProperty pc_compat_6_0[] = { 105 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 106 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 107 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 108 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 109 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 110 }; 111 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 112 113 GlobalProperty pc_compat_5_2[] = { 114 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 115 }; 116 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 117 118 GlobalProperty pc_compat_5_1[] = { 119 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 120 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 121 }; 122 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 123 124 GlobalProperty pc_compat_5_0[] = { 125 }; 126 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 127 128 GlobalProperty pc_compat_4_2[] = { 129 { "mch", "smbase-smram", "off" }, 130 }; 131 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 132 133 GlobalProperty pc_compat_4_1[] = {}; 134 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 135 136 GlobalProperty pc_compat_4_0[] = {}; 137 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 138 139 GlobalProperty pc_compat_3_1[] = { 140 { "intel-iommu", "dma-drain", "off" }, 141 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 142 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 143 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 144 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 145 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 146 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 147 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 148 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 149 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 150 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 151 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 152 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 153 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 154 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 155 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 156 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 157 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 158 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 159 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 160 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 161 }; 162 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 163 164 GlobalProperty pc_compat_3_0[] = { 165 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 166 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 167 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 168 }; 169 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 170 171 GlobalProperty pc_compat_2_12[] = { 172 { TYPE_X86_CPU, "legacy-cache", "on" }, 173 { TYPE_X86_CPU, "topoext", "off" }, 174 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 175 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 176 }; 177 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 178 179 GlobalProperty pc_compat_2_11[] = { 180 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 181 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 182 }; 183 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 184 185 GlobalProperty pc_compat_2_10[] = { 186 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 187 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 188 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 189 }; 190 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 191 192 GlobalProperty pc_compat_2_9[] = { 193 { "mch", "extended-tseg-mbytes", "0" }, 194 }; 195 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 196 197 GlobalProperty pc_compat_2_8[] = { 198 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 199 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 200 { "ICH9-LPC", "x-smi-broadcast", "off" }, 201 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 202 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 203 }; 204 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 205 206 GlobalProperty pc_compat_2_7[] = { 207 { TYPE_X86_CPU, "l3-cache", "off" }, 208 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 209 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 210 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 211 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 212 { "isa-pcspk", "migrate", "off" }, 213 }; 214 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 215 216 GlobalProperty pc_compat_2_6[] = { 217 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 218 { "vmxnet3", "romfile", "" }, 219 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 220 { "apic-common", "legacy-instance-id", "on", } 221 }; 222 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 223 224 GlobalProperty pc_compat_2_5[] = {}; 225 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 226 227 GlobalProperty pc_compat_2_4[] = { 228 PC_CPU_MODEL_IDS("2.4.0") 229 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 230 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 231 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 232 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 233 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 234 { TYPE_X86_CPU, "check", "off" }, 235 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 236 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 237 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 238 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 239 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 240 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 241 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 242 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 243 }; 244 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 245 246 GlobalProperty pc_compat_2_3[] = { 247 PC_CPU_MODEL_IDS("2.3.0") 248 { TYPE_X86_CPU, "arat", "off" }, 249 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 250 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 251 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 252 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 253 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 254 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 255 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 256 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 257 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 258 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 259 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 260 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 261 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 262 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 263 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 264 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 265 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 266 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 267 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 268 }; 269 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 270 271 GlobalProperty pc_compat_2_2[] = { 272 PC_CPU_MODEL_IDS("2.2.0") 273 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 279 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 280 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 281 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 282 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 283 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 284 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 285 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 288 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 289 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 290 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 291 }; 292 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 293 294 GlobalProperty pc_compat_2_1[] = { 295 PC_CPU_MODEL_IDS("2.1.0") 296 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 297 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 298 }; 299 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 300 301 GlobalProperty pc_compat_2_0[] = { 302 PC_CPU_MODEL_IDS("2.0.0") 303 { "virtio-scsi-pci", "any_layout", "off" }, 304 { "PIIX4_PM", "memory-hotplug-support", "off" }, 305 { "apic", "version", "0x11" }, 306 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 307 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 308 { "pci-serial", "prog_if", "0" }, 309 { "pci-serial-2x", "prog_if", "0" }, 310 { "pci-serial-4x", "prog_if", "0" }, 311 { "virtio-net-pci", "guest_announce", "off" }, 312 { "ICH9-LPC", "memory-hotplug-support", "off" }, 313 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 314 { "ioh3420", COMPAT_PROP_PCP, "off" }, 315 }; 316 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 317 318 GlobalProperty pc_compat_1_7[] = { 319 PC_CPU_MODEL_IDS("1.7.0") 320 { TYPE_USB_DEVICE, "msos-desc", "no" }, 321 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 322 { "hpet", HPET_INTCAP, "4" }, 323 }; 324 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 325 326 GlobalProperty pc_compat_1_6[] = { 327 PC_CPU_MODEL_IDS("1.6.0") 328 { "e1000", "mitigation", "off" }, 329 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 330 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 331 { "i440FX-pcihost", "short_root_bus", "1" }, 332 { "q35-pcihost", "short_root_bus", "1" }, 333 }; 334 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 335 336 GlobalProperty pc_compat_1_5[] = { 337 PC_CPU_MODEL_IDS("1.5.0") 338 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 339 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 340 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 341 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 342 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 343 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 344 { "virtio-net-pci", "any_layout", "off" }, 345 { TYPE_X86_CPU, "pmu", "on" }, 346 { "i440FX-pcihost", "short_root_bus", "0" }, 347 { "q35-pcihost", "short_root_bus", "0" }, 348 }; 349 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 350 351 GlobalProperty pc_compat_1_4[] = { 352 PC_CPU_MODEL_IDS("1.4.0") 353 { "scsi-hd", "discard_granularity", "0" }, 354 { "scsi-cd", "discard_granularity", "0" }, 355 { "ide-hd", "discard_granularity", "0" }, 356 { "ide-cd", "discard_granularity", "0" }, 357 { "virtio-blk-pci", "discard_granularity", "0" }, 358 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 359 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 360 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 361 { "e1000", "romfile", "pxe-e1000.rom" }, 362 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 363 { "pcnet", "romfile", "pxe-pcnet.rom" }, 364 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 365 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 366 { "486-" TYPE_X86_CPU, "model", "0" }, 367 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 368 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 369 }; 370 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 371 372 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 373 { 374 GSIState *s; 375 376 s = g_new0(GSIState, 1); 377 if (kvm_ioapic_in_kernel()) { 378 kvm_pc_setup_irq_routing(pci_enabled); 379 } 380 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 381 382 return s; 383 } 384 385 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 386 unsigned size) 387 { 388 } 389 390 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 391 { 392 return 0xffffffffffffffffULL; 393 } 394 395 /* MSDOS compatibility mode FPU exception support */ 396 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 397 unsigned size) 398 { 399 if (tcg_enabled()) { 400 cpu_set_ignne(); 401 } 402 } 403 404 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 405 { 406 return 0xffffffffffffffffULL; 407 } 408 409 /* PC cmos mappings */ 410 411 #define REG_EQUIPMENT_BYTE 0x14 412 413 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 414 int16_t cylinders, int8_t heads, int8_t sectors) 415 { 416 rtc_set_memory(s, type_ofs, 47); 417 rtc_set_memory(s, info_ofs, cylinders); 418 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 419 rtc_set_memory(s, info_ofs + 2, heads); 420 rtc_set_memory(s, info_ofs + 3, 0xff); 421 rtc_set_memory(s, info_ofs + 4, 0xff); 422 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 423 rtc_set_memory(s, info_ofs + 6, cylinders); 424 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 425 rtc_set_memory(s, info_ofs + 8, sectors); 426 } 427 428 /* convert boot_device letter to something recognizable by the bios */ 429 static int boot_device2nibble(char boot_device) 430 { 431 switch(boot_device) { 432 case 'a': 433 case 'b': 434 return 0x01; /* floppy boot */ 435 case 'c': 436 return 0x02; /* hard drive boot */ 437 case 'd': 438 return 0x03; /* CD-ROM boot */ 439 case 'n': 440 return 0x04; /* Network boot */ 441 } 442 return 0; 443 } 444 445 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 446 { 447 #define PC_MAX_BOOT_DEVICES 3 448 int nbds, bds[3] = { 0, }; 449 int i; 450 451 nbds = strlen(boot_device); 452 if (nbds > PC_MAX_BOOT_DEVICES) { 453 error_setg(errp, "Too many boot devices for PC"); 454 return; 455 } 456 for (i = 0; i < nbds; i++) { 457 bds[i] = boot_device2nibble(boot_device[i]); 458 if (bds[i] == 0) { 459 error_setg(errp, "Invalid boot device for PC: '%c'", 460 boot_device[i]); 461 return; 462 } 463 } 464 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 465 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 466 } 467 468 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 469 { 470 set_boot_dev(opaque, boot_device, errp); 471 } 472 473 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 474 { 475 int val, nb, i; 476 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 477 FLOPPY_DRIVE_TYPE_NONE }; 478 479 /* floppy type */ 480 if (floppy) { 481 for (i = 0; i < 2; i++) { 482 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 483 } 484 } 485 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 486 cmos_get_fd_drive_type(fd_type[1]); 487 rtc_set_memory(rtc_state, 0x10, val); 488 489 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 490 nb = 0; 491 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 492 nb++; 493 } 494 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 495 nb++; 496 } 497 switch (nb) { 498 case 0: 499 break; 500 case 1: 501 val |= 0x01; /* 1 drive, ready for boot */ 502 break; 503 case 2: 504 val |= 0x41; /* 2 drives, ready for boot */ 505 break; 506 } 507 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 508 } 509 510 typedef struct pc_cmos_init_late_arg { 511 ISADevice *rtc_state; 512 BusState *idebus[2]; 513 } pc_cmos_init_late_arg; 514 515 typedef struct check_fdc_state { 516 ISADevice *floppy; 517 bool multiple; 518 } CheckFdcState; 519 520 static int check_fdc(Object *obj, void *opaque) 521 { 522 CheckFdcState *state = opaque; 523 Object *fdc; 524 uint32_t iobase; 525 Error *local_err = NULL; 526 527 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 528 if (!fdc) { 529 return 0; 530 } 531 532 iobase = object_property_get_uint(obj, "iobase", &local_err); 533 if (local_err || iobase != 0x3f0) { 534 error_free(local_err); 535 return 0; 536 } 537 538 if (state->floppy) { 539 state->multiple = true; 540 } else { 541 state->floppy = ISA_DEVICE(obj); 542 } 543 return 0; 544 } 545 546 static const char * const fdc_container_path[] = { 547 "/unattached", "/peripheral", "/peripheral-anon" 548 }; 549 550 /* 551 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 552 * and ACPI objects. 553 */ 554 ISADevice *pc_find_fdc0(void) 555 { 556 int i; 557 Object *container; 558 CheckFdcState state = { 0 }; 559 560 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 561 container = container_get(qdev_get_machine(), fdc_container_path[i]); 562 object_child_foreach(container, check_fdc, &state); 563 } 564 565 if (state.multiple) { 566 warn_report("multiple floppy disk controllers with " 567 "iobase=0x3f0 have been found"); 568 error_printf("the one being picked for CMOS setup might not reflect " 569 "your intent"); 570 } 571 572 return state.floppy; 573 } 574 575 static void pc_cmos_init_late(void *opaque) 576 { 577 pc_cmos_init_late_arg *arg = opaque; 578 ISADevice *s = arg->rtc_state; 579 int16_t cylinders; 580 int8_t heads, sectors; 581 int val; 582 int i, trans; 583 584 val = 0; 585 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 586 &cylinders, &heads, §ors) >= 0) { 587 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 588 val |= 0xf0; 589 } 590 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 591 &cylinders, &heads, §ors) >= 0) { 592 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 593 val |= 0x0f; 594 } 595 rtc_set_memory(s, 0x12, val); 596 597 val = 0; 598 for (i = 0; i < 4; i++) { 599 /* NOTE: ide_get_geometry() returns the physical 600 geometry. It is always such that: 1 <= sects <= 63, 1 601 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 602 geometry can be different if a translation is done. */ 603 if (arg->idebus[i / 2] && 604 ide_get_geometry(arg->idebus[i / 2], i % 2, 605 &cylinders, &heads, §ors) >= 0) { 606 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 607 assert((trans & ~3) == 0); 608 val |= trans << (i * 2); 609 } 610 } 611 rtc_set_memory(s, 0x39, val); 612 613 pc_cmos_init_floppy(s, pc_find_fdc0()); 614 615 qemu_unregister_reset(pc_cmos_init_late, opaque); 616 } 617 618 void pc_cmos_init(PCMachineState *pcms, 619 BusState *idebus0, BusState *idebus1, 620 ISADevice *s) 621 { 622 int val; 623 static pc_cmos_init_late_arg arg; 624 X86MachineState *x86ms = X86_MACHINE(pcms); 625 626 /* various important CMOS locations needed by PC/Bochs bios */ 627 628 /* memory size */ 629 /* base memory (first MiB) */ 630 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 631 rtc_set_memory(s, 0x15, val); 632 rtc_set_memory(s, 0x16, val >> 8); 633 /* extended memory (next 64MiB) */ 634 if (x86ms->below_4g_mem_size > 1 * MiB) { 635 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 636 } else { 637 val = 0; 638 } 639 if (val > 65535) 640 val = 65535; 641 rtc_set_memory(s, 0x17, val); 642 rtc_set_memory(s, 0x18, val >> 8); 643 rtc_set_memory(s, 0x30, val); 644 rtc_set_memory(s, 0x31, val >> 8); 645 /* memory between 16MiB and 4GiB */ 646 if (x86ms->below_4g_mem_size > 16 * MiB) { 647 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 648 } else { 649 val = 0; 650 } 651 if (val > 65535) 652 val = 65535; 653 rtc_set_memory(s, 0x34, val); 654 rtc_set_memory(s, 0x35, val >> 8); 655 /* memory above 4GiB */ 656 val = x86ms->above_4g_mem_size / 65536; 657 rtc_set_memory(s, 0x5b, val); 658 rtc_set_memory(s, 0x5c, val >> 8); 659 rtc_set_memory(s, 0x5d, val >> 16); 660 661 object_property_add_link(OBJECT(pcms), "rtc_state", 662 TYPE_ISA_DEVICE, 663 (Object **)&x86ms->rtc, 664 object_property_allow_set_link, 665 OBJ_PROP_LINK_STRONG); 666 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 667 &error_abort); 668 669 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 670 671 val = 0; 672 val |= 0x02; /* FPU is there */ 673 val |= 0x04; /* PS/2 mouse installed */ 674 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 675 676 /* hard drives and FDC */ 677 arg.rtc_state = s; 678 arg.idebus[0] = idebus0; 679 arg.idebus[1] = idebus1; 680 qemu_register_reset(pc_cmos_init_late, &arg); 681 } 682 683 static void handle_a20_line_change(void *opaque, int irq, int level) 684 { 685 X86CPU *cpu = opaque; 686 687 /* XXX: send to all CPUs ? */ 688 /* XXX: add logic to handle multiple A20 line sources */ 689 x86_cpu_set_a20(cpu, level); 690 } 691 692 #define NE2000_NB_MAX 6 693 694 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 695 0x280, 0x380 }; 696 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 697 698 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 699 { 700 static int nb_ne2k = 0; 701 702 if (nb_ne2k == NE2000_NB_MAX) 703 return; 704 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 705 ne2000_irq[nb_ne2k], nd); 706 nb_ne2k++; 707 } 708 709 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 710 { 711 X86CPU *cpu = opaque; 712 713 if (level) { 714 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 715 } 716 } 717 718 static 719 void pc_machine_done(Notifier *notifier, void *data) 720 { 721 PCMachineState *pcms = container_of(notifier, 722 PCMachineState, machine_done); 723 X86MachineState *x86ms = X86_MACHINE(pcms); 724 725 /* set the number of CPUs */ 726 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 727 728 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 729 730 acpi_setup(); 731 if (x86ms->fw_cfg) { 732 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 733 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 734 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 735 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 736 } 737 738 739 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 740 !kvm_irqchip_in_kernel()) { 741 error_report("current -smp configuration requires kernel " 742 "irqchip support."); 743 exit(EXIT_FAILURE); 744 } 745 } 746 747 void pc_guest_info_init(PCMachineState *pcms) 748 { 749 X86MachineState *x86ms = X86_MACHINE(pcms); 750 751 x86ms->apic_xrupt_override = true; 752 pcms->machine_done.notify = pc_machine_done; 753 qemu_add_machine_init_done_notifier(&pcms->machine_done); 754 } 755 756 /* setup pci memory address space mapping into system address space */ 757 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 758 MemoryRegion *pci_address_space) 759 { 760 /* Set to lower priority than RAM */ 761 memory_region_add_subregion_overlap(system_memory, 0x0, 762 pci_address_space, -1); 763 } 764 765 void xen_load_linux(PCMachineState *pcms) 766 { 767 int i; 768 FWCfgState *fw_cfg; 769 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 770 X86MachineState *x86ms = X86_MACHINE(pcms); 771 772 assert(MACHINE(pcms)->kernel_filename != NULL); 773 774 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 775 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 776 rom_set_fw(fw_cfg); 777 778 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 779 pcmc->pvh_enabled); 780 for (i = 0; i < nb_option_roms; i++) { 781 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 782 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 783 !strcmp(option_rom[i].name, "pvh.bin") || 784 !strcmp(option_rom[i].name, "multiboot.bin") || 785 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 786 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 787 } 788 x86ms->fw_cfg = fw_cfg; 789 } 790 791 #define PC_ROM_MIN_VGA 0xc0000 792 #define PC_ROM_MIN_OPTION 0xc8000 793 #define PC_ROM_MAX 0xe0000 794 #define PC_ROM_ALIGN 0x800 795 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 796 797 void pc_memory_init(PCMachineState *pcms, 798 MemoryRegion *system_memory, 799 MemoryRegion *rom_memory, 800 MemoryRegion **ram_memory) 801 { 802 int linux_boot, i; 803 MemoryRegion *option_rom_mr; 804 MemoryRegion *ram_below_4g, *ram_above_4g; 805 FWCfgState *fw_cfg; 806 MachineState *machine = MACHINE(pcms); 807 MachineClass *mc = MACHINE_GET_CLASS(machine); 808 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 809 X86MachineState *x86ms = X86_MACHINE(pcms); 810 811 assert(machine->ram_size == x86ms->below_4g_mem_size + 812 x86ms->above_4g_mem_size); 813 814 linux_boot = (machine->kernel_filename != NULL); 815 816 /* 817 * Split single memory region and use aliases to address portions of it, 818 * done for backwards compatibility with older qemus. 819 */ 820 *ram_memory = machine->ram; 821 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 822 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 823 0, x86ms->below_4g_mem_size); 824 memory_region_add_subregion(system_memory, 0, ram_below_4g); 825 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 826 if (x86ms->above_4g_mem_size > 0) { 827 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 828 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 829 machine->ram, 830 x86ms->below_4g_mem_size, 831 x86ms->above_4g_mem_size); 832 memory_region_add_subregion(system_memory, 0x100000000ULL, 833 ram_above_4g); 834 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 835 } 836 837 if (pcms->sgx_epc.size != 0) { 838 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 839 } 840 841 if (!pcmc->has_reserved_memory && 842 (machine->ram_slots || 843 (machine->maxram_size > machine->ram_size))) { 844 845 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 846 mc->name); 847 exit(EXIT_FAILURE); 848 } 849 850 /* always allocate the device memory information */ 851 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 852 853 /* initialize device memory address space */ 854 if (pcmc->has_reserved_memory && 855 (machine->ram_size < machine->maxram_size)) { 856 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 857 858 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 859 error_report("unsupported amount of memory slots: %"PRIu64, 860 machine->ram_slots); 861 exit(EXIT_FAILURE); 862 } 863 864 if (QEMU_ALIGN_UP(machine->maxram_size, 865 TARGET_PAGE_SIZE) != machine->maxram_size) { 866 error_report("maximum memory size must by aligned to multiple of " 867 "%d bytes", TARGET_PAGE_SIZE); 868 exit(EXIT_FAILURE); 869 } 870 871 if (pcms->sgx_epc.size != 0) { 872 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 873 } else { 874 machine->device_memory->base = 875 0x100000000ULL + x86ms->above_4g_mem_size; 876 } 877 878 machine->device_memory->base = 879 ROUND_UP(machine->device_memory->base, 1 * GiB); 880 881 if (pcmc->enforce_aligned_dimm) { 882 /* size device region assuming 1G page max alignment per slot */ 883 device_mem_size += (1 * GiB) * machine->ram_slots; 884 } 885 886 if ((machine->device_memory->base + device_mem_size) < 887 device_mem_size) { 888 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 889 machine->maxram_size); 890 exit(EXIT_FAILURE); 891 } 892 893 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 894 "device-memory", device_mem_size); 895 memory_region_add_subregion(system_memory, machine->device_memory->base, 896 &machine->device_memory->mr); 897 } 898 899 /* Initialize PC system firmware */ 900 pc_system_firmware_init(pcms, rom_memory); 901 902 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 903 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 904 &error_fatal); 905 if (pcmc->pci_enabled) { 906 memory_region_set_readonly(option_rom_mr, true); 907 } 908 memory_region_add_subregion_overlap(rom_memory, 909 PC_ROM_MIN_VGA, 910 option_rom_mr, 911 1); 912 913 fw_cfg = fw_cfg_arch_create(machine, 914 x86ms->boot_cpus, x86ms->apic_id_limit); 915 916 rom_set_fw(fw_cfg); 917 918 if (pcmc->has_reserved_memory && machine->device_memory->base) { 919 uint64_t *val = g_malloc(sizeof(*val)); 920 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 921 uint64_t res_mem_end = machine->device_memory->base; 922 923 if (!pcmc->broken_reserved_end) { 924 res_mem_end += memory_region_size(&machine->device_memory->mr); 925 } 926 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 927 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 928 } 929 930 if (linux_boot) { 931 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 932 pcmc->pvh_enabled); 933 } 934 935 for (i = 0; i < nb_option_roms; i++) { 936 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 937 } 938 x86ms->fw_cfg = fw_cfg; 939 940 /* Init default IOAPIC address space */ 941 x86ms->ioapic_as = &address_space_memory; 942 943 /* Init ACPI memory hotplug IO base address */ 944 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 945 } 946 947 /* 948 * The 64bit pci hole starts after "above 4G RAM" and 949 * potentially the space reserved for memory hotplug. 950 */ 951 uint64_t pc_pci_hole64_start(void) 952 { 953 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 954 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 955 MachineState *ms = MACHINE(pcms); 956 X86MachineState *x86ms = X86_MACHINE(pcms); 957 uint64_t hole64_start = 0; 958 959 if (pcmc->has_reserved_memory && ms->device_memory->base) { 960 hole64_start = ms->device_memory->base; 961 if (!pcmc->broken_reserved_end) { 962 hole64_start += memory_region_size(&ms->device_memory->mr); 963 } 964 } else if (pcms->sgx_epc.size != 0) { 965 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 966 } else { 967 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 968 } 969 970 return ROUND_UP(hole64_start, 1 * GiB); 971 } 972 973 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 974 { 975 DeviceState *dev = NULL; 976 977 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 978 if (pci_bus) { 979 PCIDevice *pcidev = pci_vga_init(pci_bus); 980 dev = pcidev ? &pcidev->qdev : NULL; 981 } else if (isa_bus) { 982 ISADevice *isadev = isa_vga_init(isa_bus); 983 dev = isadev ? DEVICE(isadev) : NULL; 984 } 985 rom_reset_order_override(); 986 return dev; 987 } 988 989 static const MemoryRegionOps ioport80_io_ops = { 990 .write = ioport80_write, 991 .read = ioport80_read, 992 .endianness = DEVICE_NATIVE_ENDIAN, 993 .impl = { 994 .min_access_size = 1, 995 .max_access_size = 1, 996 }, 997 }; 998 999 static const MemoryRegionOps ioportF0_io_ops = { 1000 .write = ioportF0_write, 1001 .read = ioportF0_read, 1002 .endianness = DEVICE_NATIVE_ENDIAN, 1003 .impl = { 1004 .min_access_size = 1, 1005 .max_access_size = 1, 1006 }, 1007 }; 1008 1009 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1010 { 1011 int i; 1012 DriveInfo *fd[MAX_FD]; 1013 qemu_irq *a20_line; 1014 ISADevice *fdc, *i8042, *port92, *vmmouse; 1015 1016 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1017 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1018 1019 for (i = 0; i < MAX_FD; i++) { 1020 fd[i] = drive_get(IF_FLOPPY, 0, i); 1021 create_fdctrl |= !!fd[i]; 1022 } 1023 if (create_fdctrl) { 1024 fdc = isa_new(TYPE_ISA_FDC); 1025 if (fdc) { 1026 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1027 isa_fdc_init_drives(fdc, fd); 1028 } 1029 } 1030 1031 i8042 = isa_create_simple(isa_bus, "i8042"); 1032 if (!no_vmport) { 1033 isa_create_simple(isa_bus, TYPE_VMPORT); 1034 vmmouse = isa_try_new("vmmouse"); 1035 } else { 1036 vmmouse = NULL; 1037 } 1038 if (vmmouse) { 1039 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1040 &error_abort); 1041 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1042 } 1043 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1044 1045 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1046 i8042_setup_a20_line(i8042, a20_line[0]); 1047 qdev_connect_gpio_out_named(DEVICE(port92), 1048 PORT92_A20_LINE, 0, a20_line[1]); 1049 g_free(a20_line); 1050 } 1051 1052 void pc_basic_device_init(struct PCMachineState *pcms, 1053 ISABus *isa_bus, qemu_irq *gsi, 1054 ISADevice **rtc_state, 1055 bool create_fdctrl, 1056 uint32_t hpet_irqs) 1057 { 1058 int i; 1059 DeviceState *hpet = NULL; 1060 int pit_isa_irq = 0; 1061 qemu_irq pit_alt_irq = NULL; 1062 qemu_irq rtc_irq = NULL; 1063 ISADevice *pit = NULL; 1064 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1065 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1066 1067 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1068 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1069 1070 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1071 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1072 1073 /* 1074 * Check if an HPET shall be created. 1075 * 1076 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1077 * when the HPET wants to take over. Thus we have to disable the latter. 1078 */ 1079 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1080 kvm_has_pit_state2())) { 1081 hpet = qdev_try_new(TYPE_HPET); 1082 if (!hpet) { 1083 error_report("couldn't create HPET device"); 1084 exit(1); 1085 } 1086 /* 1087 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1088 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1089 * IRQ2. 1090 */ 1091 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1092 HPET_INTCAP, NULL); 1093 if (!compat) { 1094 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1095 } 1096 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1097 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1098 1099 for (i = 0; i < GSI_NUM_PINS; i++) { 1100 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1101 } 1102 pit_isa_irq = -1; 1103 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1104 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1105 } 1106 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1107 1108 qemu_register_boot_set(pc_boot_set, *rtc_state); 1109 1110 if (!xen_enabled() && pcms->pit_enabled) { 1111 if (kvm_pit_in_kernel()) { 1112 pit = kvm_pit_init(isa_bus, 0x40); 1113 } else { 1114 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1115 } 1116 if (hpet) { 1117 /* connect PIT to output control line of the HPET */ 1118 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1119 } 1120 pcspk_init(pcms->pcspk, isa_bus, pit); 1121 } 1122 1123 i8257_dma_init(isa_bus, 0); 1124 1125 /* Super I/O */ 1126 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1127 } 1128 1129 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1130 { 1131 int i; 1132 1133 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1134 for (i = 0; i < nb_nics; i++) { 1135 NICInfo *nd = &nd_table[i]; 1136 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1137 1138 if (g_str_equal(model, "ne2k_isa")) { 1139 pc_init_ne2k_isa(isa_bus, nd); 1140 } else { 1141 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1142 } 1143 } 1144 rom_reset_order_override(); 1145 } 1146 1147 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1148 { 1149 qemu_irq *i8259; 1150 1151 if (kvm_pic_in_kernel()) { 1152 i8259 = kvm_i8259_init(isa_bus); 1153 } else if (xen_enabled()) { 1154 i8259 = xen_interrupt_controller_init(); 1155 } else { 1156 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1157 } 1158 1159 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1160 i8259_irqs[i] = i8259[i]; 1161 } 1162 1163 g_free(i8259); 1164 } 1165 1166 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1167 Error **errp) 1168 { 1169 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1170 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1171 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1172 const MachineState *ms = MACHINE(hotplug_dev); 1173 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1174 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1175 Error *local_err = NULL; 1176 1177 /* 1178 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1179 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1180 * addition to cover this case. 1181 */ 1182 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1183 error_setg(errp, 1184 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1185 return; 1186 } 1187 1188 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1189 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1190 return; 1191 } 1192 1193 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1194 if (local_err) { 1195 error_propagate(errp, local_err); 1196 return; 1197 } 1198 1199 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1200 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1201 } 1202 1203 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1204 DeviceState *dev, Error **errp) 1205 { 1206 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1207 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1208 MachineState *ms = MACHINE(hotplug_dev); 1209 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1210 1211 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1212 1213 if (is_nvdimm) { 1214 nvdimm_plug(ms->nvdimms_state); 1215 } 1216 1217 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1218 } 1219 1220 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1221 DeviceState *dev, Error **errp) 1222 { 1223 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1224 1225 /* 1226 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1227 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1228 * addition to cover this case. 1229 */ 1230 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1231 error_setg(errp, 1232 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1233 return; 1234 } 1235 1236 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1237 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1238 return; 1239 } 1240 1241 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1242 errp); 1243 } 1244 1245 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1246 DeviceState *dev, Error **errp) 1247 { 1248 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1249 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1250 Error *local_err = NULL; 1251 1252 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1253 if (local_err) { 1254 goto out; 1255 } 1256 1257 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1258 qdev_unrealize(dev); 1259 out: 1260 error_propagate(errp, local_err); 1261 } 1262 1263 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1264 DeviceState *dev, Error **errp) 1265 { 1266 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1267 Error *local_err = NULL; 1268 1269 if (!hotplug_dev2 && dev->hotplugged) { 1270 /* 1271 * Without a bus hotplug handler, we cannot control the plug/unplug 1272 * order. We should never reach this point when hotplugging on x86, 1273 * however, better add a safety net. 1274 */ 1275 error_setg(errp, "hotplug of virtio based memory devices not supported" 1276 " on this bus."); 1277 return; 1278 } 1279 /* 1280 * First, see if we can plug this memory device at all. If that 1281 * succeeds, branch of to the actual hotplug handler. 1282 */ 1283 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1284 &local_err); 1285 if (!local_err && hotplug_dev2) { 1286 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1287 } 1288 error_propagate(errp, local_err); 1289 } 1290 1291 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1292 DeviceState *dev, Error **errp) 1293 { 1294 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1295 Error *local_err = NULL; 1296 1297 /* 1298 * Plug the memory device first and then branch off to the actual 1299 * hotplug handler. If that one fails, we can easily undo the memory 1300 * device bits. 1301 */ 1302 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1303 if (hotplug_dev2) { 1304 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1305 if (local_err) { 1306 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1307 } 1308 } 1309 error_propagate(errp, local_err); 1310 } 1311 1312 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1313 DeviceState *dev, Error **errp) 1314 { 1315 /* We don't support hot unplug of virtio based memory devices */ 1316 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1317 } 1318 1319 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1320 DeviceState *dev, Error **errp) 1321 { 1322 /* We don't support hot unplug of virtio based memory devices */ 1323 } 1324 1325 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1326 DeviceState *dev, Error **errp) 1327 { 1328 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1329 pc_memory_pre_plug(hotplug_dev, dev, errp); 1330 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1331 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1332 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1333 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1334 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1335 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1336 /* Declare the APIC range as the reserved MSI region */ 1337 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1338 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1339 1340 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1341 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1342 resv_prop_str, errp); 1343 g_free(resv_prop_str); 1344 } 1345 1346 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1347 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1348 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1349 1350 if (pcms->iommu) { 1351 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1352 "for x86 yet."); 1353 return; 1354 } 1355 pcms->iommu = dev; 1356 } 1357 } 1358 1359 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1360 DeviceState *dev, Error **errp) 1361 { 1362 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1363 pc_memory_plug(hotplug_dev, dev, errp); 1364 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1365 x86_cpu_plug(hotplug_dev, dev, errp); 1366 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1367 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1368 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1369 } 1370 } 1371 1372 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1373 DeviceState *dev, Error **errp) 1374 { 1375 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1376 pc_memory_unplug_request(hotplug_dev, dev, errp); 1377 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1378 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1380 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1381 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1382 } else { 1383 error_setg(errp, "acpi: device unplug request for not supported device" 1384 " type: %s", object_get_typename(OBJECT(dev))); 1385 } 1386 } 1387 1388 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1389 DeviceState *dev, Error **errp) 1390 { 1391 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1392 pc_memory_unplug(hotplug_dev, dev, errp); 1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1394 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1396 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1397 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1398 } else { 1399 error_setg(errp, "acpi: device unplug for not supported device" 1400 " type: %s", object_get_typename(OBJECT(dev))); 1401 } 1402 } 1403 1404 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1405 DeviceState *dev) 1406 { 1407 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1408 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1409 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1410 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1411 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1412 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1413 return HOTPLUG_HANDLER(machine); 1414 } 1415 1416 return NULL; 1417 } 1418 1419 static void 1420 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1421 const char *name, void *opaque, 1422 Error **errp) 1423 { 1424 MachineState *ms = MACHINE(obj); 1425 int64_t value = 0; 1426 1427 if (ms->device_memory) { 1428 value = memory_region_size(&ms->device_memory->mr); 1429 } 1430 1431 visit_type_int(v, name, &value, errp); 1432 } 1433 1434 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1435 void *opaque, Error **errp) 1436 { 1437 PCMachineState *pcms = PC_MACHINE(obj); 1438 OnOffAuto vmport = pcms->vmport; 1439 1440 visit_type_OnOffAuto(v, name, &vmport, errp); 1441 } 1442 1443 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1444 void *opaque, Error **errp) 1445 { 1446 PCMachineState *pcms = PC_MACHINE(obj); 1447 1448 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1449 } 1450 1451 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1452 { 1453 PCMachineState *pcms = PC_MACHINE(obj); 1454 1455 return pcms->smbus_enabled; 1456 } 1457 1458 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1459 { 1460 PCMachineState *pcms = PC_MACHINE(obj); 1461 1462 pcms->smbus_enabled = value; 1463 } 1464 1465 static bool pc_machine_get_sata(Object *obj, Error **errp) 1466 { 1467 PCMachineState *pcms = PC_MACHINE(obj); 1468 1469 return pcms->sata_enabled; 1470 } 1471 1472 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1473 { 1474 PCMachineState *pcms = PC_MACHINE(obj); 1475 1476 pcms->sata_enabled = value; 1477 } 1478 1479 static bool pc_machine_get_pit(Object *obj, Error **errp) 1480 { 1481 PCMachineState *pcms = PC_MACHINE(obj); 1482 1483 return pcms->pit_enabled; 1484 } 1485 1486 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1487 { 1488 PCMachineState *pcms = PC_MACHINE(obj); 1489 1490 pcms->pit_enabled = value; 1491 } 1492 1493 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1494 { 1495 PCMachineState *pcms = PC_MACHINE(obj); 1496 1497 return pcms->hpet_enabled; 1498 } 1499 1500 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1501 { 1502 PCMachineState *pcms = PC_MACHINE(obj); 1503 1504 pcms->hpet_enabled = value; 1505 } 1506 1507 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1508 { 1509 PCMachineState *pcms = PC_MACHINE(obj); 1510 1511 return pcms->default_bus_bypass_iommu; 1512 } 1513 1514 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1515 Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 pcms->default_bus_bypass_iommu = value; 1520 } 1521 1522 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1523 const char *name, void *opaque, 1524 Error **errp) 1525 { 1526 PCMachineState *pcms = PC_MACHINE(obj); 1527 uint64_t value = pcms->max_ram_below_4g; 1528 1529 visit_type_size(v, name, &value, errp); 1530 } 1531 1532 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1533 const char *name, void *opaque, 1534 Error **errp) 1535 { 1536 PCMachineState *pcms = PC_MACHINE(obj); 1537 uint64_t value; 1538 1539 if (!visit_type_size(v, name, &value, errp)) { 1540 return; 1541 } 1542 if (value > 4 * GiB) { 1543 error_setg(errp, 1544 "Machine option 'max-ram-below-4g=%"PRIu64 1545 "' expects size less than or equal to 4G", value); 1546 return; 1547 } 1548 1549 if (value < 1 * MiB) { 1550 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1551 "BIOS may not work with less than 1MiB", value); 1552 } 1553 1554 pcms->max_ram_below_4g = value; 1555 } 1556 1557 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1558 const char *name, void *opaque, 1559 Error **errp) 1560 { 1561 PCMachineState *pcms = PC_MACHINE(obj); 1562 uint64_t value = pcms->max_fw_size; 1563 1564 visit_type_size(v, name, &value, errp); 1565 } 1566 1567 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1568 const char *name, void *opaque, 1569 Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 Error *error = NULL; 1573 uint64_t value; 1574 1575 visit_type_size(v, name, &value, &error); 1576 if (error) { 1577 error_propagate(errp, error); 1578 return; 1579 } 1580 1581 /* 1582 * We don't have a theoretically justifiable exact lower bound on the base 1583 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1584 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1585 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1586 * size. 1587 */ 1588 if (value > 16 * MiB) { 1589 error_setg(errp, 1590 "User specified max allowed firmware size %" PRIu64 " is " 1591 "greater than 16MiB. If combined firwmare size exceeds " 1592 "16MiB the system may not boot, or experience intermittent" 1593 "stability issues.", 1594 value); 1595 return; 1596 } 1597 1598 pcms->max_fw_size = value; 1599 } 1600 1601 1602 static void pc_machine_initfn(Object *obj) 1603 { 1604 PCMachineState *pcms = PC_MACHINE(obj); 1605 1606 #ifdef CONFIG_VMPORT 1607 pcms->vmport = ON_OFF_AUTO_AUTO; 1608 #else 1609 pcms->vmport = ON_OFF_AUTO_OFF; 1610 #endif /* CONFIG_VMPORT */ 1611 pcms->max_ram_below_4g = 0; /* use default */ 1612 /* acpi build is enabled by default if machine supports it */ 1613 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1614 pcms->smbus_enabled = true; 1615 pcms->sata_enabled = true; 1616 pcms->pit_enabled = true; 1617 pcms->max_fw_size = 8 * MiB; 1618 #ifdef CONFIG_HPET 1619 pcms->hpet_enabled = true; 1620 #endif 1621 pcms->default_bus_bypass_iommu = false; 1622 1623 pc_system_flash_create(pcms); 1624 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1625 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1626 OBJECT(pcms->pcspk), "audiodev"); 1627 } 1628 1629 static void pc_machine_reset(MachineState *machine) 1630 { 1631 CPUState *cs; 1632 X86CPU *cpu; 1633 1634 qemu_devices_reset(); 1635 1636 /* Reset APIC after devices have been reset to cancel 1637 * any changes that qemu_devices_reset() might have done. 1638 */ 1639 CPU_FOREACH(cs) { 1640 cpu = X86_CPU(cs); 1641 1642 if (cpu->apic_state) { 1643 device_legacy_reset(cpu->apic_state); 1644 } 1645 } 1646 } 1647 1648 static void pc_machine_wakeup(MachineState *machine) 1649 { 1650 cpu_synchronize_all_states(); 1651 pc_machine_reset(machine); 1652 cpu_synchronize_all_post_reset(); 1653 } 1654 1655 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1656 { 1657 X86IOMMUState *iommu = x86_iommu_get_default(); 1658 IntelIOMMUState *intel_iommu; 1659 1660 if (iommu && 1661 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1662 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1663 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1664 if (!intel_iommu->caching_mode) { 1665 error_setg(errp, "Device assignment is not allowed without " 1666 "enabling caching-mode=on for Intel IOMMU."); 1667 return false; 1668 } 1669 } 1670 1671 return true; 1672 } 1673 1674 static void pc_machine_class_init(ObjectClass *oc, void *data) 1675 { 1676 MachineClass *mc = MACHINE_CLASS(oc); 1677 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1678 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1679 1680 pcmc->pci_enabled = true; 1681 pcmc->has_acpi_build = true; 1682 pcmc->rsdp_in_ram = true; 1683 pcmc->smbios_defaults = true; 1684 pcmc->smbios_uuid_encoded = true; 1685 pcmc->gigabyte_align = true; 1686 pcmc->has_reserved_memory = true; 1687 pcmc->kvmclock_enabled = true; 1688 pcmc->enforce_aligned_dimm = true; 1689 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1690 * to be used at the moment, 32K should be enough for a while. */ 1691 pcmc->acpi_data_size = 0x20000 + 0x8000; 1692 pcmc->pvh_enabled = true; 1693 pcmc->kvmclock_create_always = true; 1694 assert(!mc->get_hotplug_handler); 1695 mc->get_hotplug_handler = pc_get_hotplug_handler; 1696 mc->hotplug_allowed = pc_hotplug_allowed; 1697 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1698 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1699 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1700 mc->auto_enable_numa_with_memhp = true; 1701 mc->auto_enable_numa_with_memdev = true; 1702 mc->has_hotpluggable_cpus = true; 1703 mc->default_boot_order = "cad"; 1704 mc->block_default_type = IF_IDE; 1705 mc->max_cpus = 255; 1706 mc->reset = pc_machine_reset; 1707 mc->wakeup = pc_machine_wakeup; 1708 hc->pre_plug = pc_machine_device_pre_plug_cb; 1709 hc->plug = pc_machine_device_plug_cb; 1710 hc->unplug_request = pc_machine_device_unplug_request_cb; 1711 hc->unplug = pc_machine_device_unplug_cb; 1712 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1713 mc->nvdimm_supported = true; 1714 mc->smp_props.dies_supported = true; 1715 mc->default_ram_id = "pc.ram"; 1716 1717 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1718 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1719 NULL, NULL); 1720 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1721 "Maximum ram below the 4G boundary (32bit boundary)"); 1722 1723 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1724 pc_machine_get_device_memory_region_size, NULL, 1725 NULL, NULL); 1726 1727 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1728 pc_machine_get_vmport, pc_machine_set_vmport, 1729 NULL, NULL); 1730 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1731 "Enable vmport (pc & q35)"); 1732 1733 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1734 pc_machine_get_smbus, pc_machine_set_smbus); 1735 1736 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1737 pc_machine_get_sata, pc_machine_set_sata); 1738 1739 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1740 pc_machine_get_pit, pc_machine_set_pit); 1741 1742 object_class_property_add_bool(oc, "hpet", 1743 pc_machine_get_hpet, pc_machine_set_hpet); 1744 1745 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1746 pc_machine_get_default_bus_bypass_iommu, 1747 pc_machine_set_default_bus_bypass_iommu); 1748 1749 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1750 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1751 NULL, NULL); 1752 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1753 "Maximum combined firmware size"); 1754 } 1755 1756 static const TypeInfo pc_machine_info = { 1757 .name = TYPE_PC_MACHINE, 1758 .parent = TYPE_X86_MACHINE, 1759 .abstract = true, 1760 .instance_size = sizeof(PCMachineState), 1761 .instance_init = pc_machine_initfn, 1762 .class_size = sizeof(PCMachineClass), 1763 .class_init = pc_machine_class_init, 1764 .interfaces = (InterfaceInfo[]) { 1765 { TYPE_HOTPLUG_HANDLER }, 1766 { } 1767 }, 1768 }; 1769 1770 static void pc_machine_register_types(void) 1771 { 1772 type_register_static(&pc_machine_info); 1773 } 1774 1775 type_init(pc_machine_register_types) 1776