1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "sysemu/arch_init.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_0[] = {}; 98 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 99 100 GlobalProperty pc_compat_5_2[] = { 101 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 102 }; 103 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 104 105 GlobalProperty pc_compat_5_1[] = { 106 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 107 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 108 }; 109 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 110 111 GlobalProperty pc_compat_5_0[] = { 112 }; 113 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 114 115 GlobalProperty pc_compat_4_2[] = { 116 { "mch", "smbase-smram", "off" }, 117 }; 118 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 119 120 GlobalProperty pc_compat_4_1[] = {}; 121 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 122 123 GlobalProperty pc_compat_4_0[] = {}; 124 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 125 126 GlobalProperty pc_compat_3_1[] = { 127 { "intel-iommu", "dma-drain", "off" }, 128 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 129 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 130 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 131 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 132 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 133 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 134 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 135 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 136 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 137 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 138 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 139 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 140 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 141 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 142 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 143 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 144 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 146 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 147 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 148 }; 149 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 150 151 GlobalProperty pc_compat_3_0[] = { 152 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 153 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 154 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 155 }; 156 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 157 158 GlobalProperty pc_compat_2_12[] = { 159 { TYPE_X86_CPU, "legacy-cache", "on" }, 160 { TYPE_X86_CPU, "topoext", "off" }, 161 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 162 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 163 }; 164 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 165 166 GlobalProperty pc_compat_2_11[] = { 167 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 168 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 169 }; 170 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 171 172 GlobalProperty pc_compat_2_10[] = { 173 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 174 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 175 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 176 }; 177 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 178 179 GlobalProperty pc_compat_2_9[] = { 180 { "mch", "extended-tseg-mbytes", "0" }, 181 }; 182 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 183 184 GlobalProperty pc_compat_2_8[] = { 185 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 186 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 187 { "ICH9-LPC", "x-smi-broadcast", "off" }, 188 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 189 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 190 }; 191 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 192 193 GlobalProperty pc_compat_2_7[] = { 194 { TYPE_X86_CPU, "l3-cache", "off" }, 195 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 196 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 197 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 198 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 199 { "isa-pcspk", "migrate", "off" }, 200 }; 201 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 202 203 GlobalProperty pc_compat_2_6[] = { 204 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 205 { "vmxnet3", "romfile", "" }, 206 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 207 { "apic-common", "legacy-instance-id", "on", } 208 }; 209 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 210 211 GlobalProperty pc_compat_2_5[] = {}; 212 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 213 214 GlobalProperty pc_compat_2_4[] = { 215 PC_CPU_MODEL_IDS("2.4.0") 216 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 217 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 218 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 219 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 220 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 221 { TYPE_X86_CPU, "check", "off" }, 222 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 223 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 224 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 225 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 226 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 227 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 228 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 229 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 230 }; 231 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 232 233 GlobalProperty pc_compat_2_3[] = { 234 PC_CPU_MODEL_IDS("2.3.0") 235 { TYPE_X86_CPU, "arat", "off" }, 236 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 237 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 238 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 239 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 240 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 241 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 242 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 243 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 255 }; 256 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 257 258 GlobalProperty pc_compat_2_2[] = { 259 PC_CPU_MODEL_IDS("2.2.0") 260 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 275 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 276 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 277 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 278 }; 279 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 280 281 GlobalProperty pc_compat_2_1[] = { 282 PC_CPU_MODEL_IDS("2.1.0") 283 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 284 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 285 }; 286 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 287 288 GlobalProperty pc_compat_2_0[] = { 289 PC_CPU_MODEL_IDS("2.0.0") 290 { "virtio-scsi-pci", "any_layout", "off" }, 291 { "PIIX4_PM", "memory-hotplug-support", "off" }, 292 { "apic", "version", "0x11" }, 293 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 294 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 295 { "pci-serial", "prog_if", "0" }, 296 { "pci-serial-2x", "prog_if", "0" }, 297 { "pci-serial-4x", "prog_if", "0" }, 298 { "virtio-net-pci", "guest_announce", "off" }, 299 { "ICH9-LPC", "memory-hotplug-support", "off" }, 300 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 301 { "ioh3420", COMPAT_PROP_PCP, "off" }, 302 }; 303 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 304 305 GlobalProperty pc_compat_1_7[] = { 306 PC_CPU_MODEL_IDS("1.7.0") 307 { TYPE_USB_DEVICE, "msos-desc", "no" }, 308 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 309 { "hpet", HPET_INTCAP, "4" }, 310 }; 311 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 312 313 GlobalProperty pc_compat_1_6[] = { 314 PC_CPU_MODEL_IDS("1.6.0") 315 { "e1000", "mitigation", "off" }, 316 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 317 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 318 { "i440FX-pcihost", "short_root_bus", "1" }, 319 { "q35-pcihost", "short_root_bus", "1" }, 320 }; 321 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 322 323 GlobalProperty pc_compat_1_5[] = { 324 PC_CPU_MODEL_IDS("1.5.0") 325 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 326 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 327 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 328 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 329 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 330 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 331 { "virtio-net-pci", "any_layout", "off" }, 332 { TYPE_X86_CPU, "pmu", "on" }, 333 { "i440FX-pcihost", "short_root_bus", "0" }, 334 { "q35-pcihost", "short_root_bus", "0" }, 335 }; 336 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 337 338 GlobalProperty pc_compat_1_4[] = { 339 PC_CPU_MODEL_IDS("1.4.0") 340 { "scsi-hd", "discard_granularity", "0" }, 341 { "scsi-cd", "discard_granularity", "0" }, 342 { "ide-hd", "discard_granularity", "0" }, 343 { "ide-cd", "discard_granularity", "0" }, 344 { "virtio-blk-pci", "discard_granularity", "0" }, 345 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 346 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 347 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 348 { "e1000", "romfile", "pxe-e1000.rom" }, 349 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 350 { "pcnet", "romfile", "pxe-pcnet.rom" }, 351 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 352 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 353 { "486-" TYPE_X86_CPU, "model", "0" }, 354 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 355 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 356 }; 357 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 358 359 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 360 { 361 GSIState *s; 362 363 s = g_new0(GSIState, 1); 364 if (kvm_ioapic_in_kernel()) { 365 kvm_pc_setup_irq_routing(pci_enabled); 366 } 367 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 368 369 return s; 370 } 371 372 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 373 unsigned size) 374 { 375 } 376 377 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 378 { 379 return 0xffffffffffffffffULL; 380 } 381 382 /* MSDOS compatibility mode FPU exception support */ 383 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 384 unsigned size) 385 { 386 if (tcg_enabled()) { 387 cpu_set_ignne(); 388 } 389 } 390 391 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 392 { 393 return 0xffffffffffffffffULL; 394 } 395 396 /* PC cmos mappings */ 397 398 #define REG_EQUIPMENT_BYTE 0x14 399 400 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 401 int16_t cylinders, int8_t heads, int8_t sectors) 402 { 403 rtc_set_memory(s, type_ofs, 47); 404 rtc_set_memory(s, info_ofs, cylinders); 405 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 406 rtc_set_memory(s, info_ofs + 2, heads); 407 rtc_set_memory(s, info_ofs + 3, 0xff); 408 rtc_set_memory(s, info_ofs + 4, 0xff); 409 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 410 rtc_set_memory(s, info_ofs + 6, cylinders); 411 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 412 rtc_set_memory(s, info_ofs + 8, sectors); 413 } 414 415 /* convert boot_device letter to something recognizable by the bios */ 416 static int boot_device2nibble(char boot_device) 417 { 418 switch(boot_device) { 419 case 'a': 420 case 'b': 421 return 0x01; /* floppy boot */ 422 case 'c': 423 return 0x02; /* hard drive boot */ 424 case 'd': 425 return 0x03; /* CD-ROM boot */ 426 case 'n': 427 return 0x04; /* Network boot */ 428 } 429 return 0; 430 } 431 432 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 433 { 434 #define PC_MAX_BOOT_DEVICES 3 435 int nbds, bds[3] = { 0, }; 436 int i; 437 438 nbds = strlen(boot_device); 439 if (nbds > PC_MAX_BOOT_DEVICES) { 440 error_setg(errp, "Too many boot devices for PC"); 441 return; 442 } 443 for (i = 0; i < nbds; i++) { 444 bds[i] = boot_device2nibble(boot_device[i]); 445 if (bds[i] == 0) { 446 error_setg(errp, "Invalid boot device for PC: '%c'", 447 boot_device[i]); 448 return; 449 } 450 } 451 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 452 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 453 } 454 455 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 456 { 457 set_boot_dev(opaque, boot_device, errp); 458 } 459 460 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 461 { 462 int val, nb, i; 463 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 464 FLOPPY_DRIVE_TYPE_NONE }; 465 466 /* floppy type */ 467 if (floppy) { 468 for (i = 0; i < 2; i++) { 469 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 470 } 471 } 472 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 473 cmos_get_fd_drive_type(fd_type[1]); 474 rtc_set_memory(rtc_state, 0x10, val); 475 476 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 477 nb = 0; 478 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 479 nb++; 480 } 481 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 482 nb++; 483 } 484 switch (nb) { 485 case 0: 486 break; 487 case 1: 488 val |= 0x01; /* 1 drive, ready for boot */ 489 break; 490 case 2: 491 val |= 0x41; /* 2 drives, ready for boot */ 492 break; 493 } 494 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 495 } 496 497 typedef struct pc_cmos_init_late_arg { 498 ISADevice *rtc_state; 499 BusState *idebus[2]; 500 } pc_cmos_init_late_arg; 501 502 typedef struct check_fdc_state { 503 ISADevice *floppy; 504 bool multiple; 505 } CheckFdcState; 506 507 static int check_fdc(Object *obj, void *opaque) 508 { 509 CheckFdcState *state = opaque; 510 Object *fdc; 511 uint32_t iobase; 512 Error *local_err = NULL; 513 514 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 515 if (!fdc) { 516 return 0; 517 } 518 519 iobase = object_property_get_uint(obj, "iobase", &local_err); 520 if (local_err || iobase != 0x3f0) { 521 error_free(local_err); 522 return 0; 523 } 524 525 if (state->floppy) { 526 state->multiple = true; 527 } else { 528 state->floppy = ISA_DEVICE(obj); 529 } 530 return 0; 531 } 532 533 static const char * const fdc_container_path[] = { 534 "/unattached", "/peripheral", "/peripheral-anon" 535 }; 536 537 /* 538 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 539 * and ACPI objects. 540 */ 541 ISADevice *pc_find_fdc0(void) 542 { 543 int i; 544 Object *container; 545 CheckFdcState state = { 0 }; 546 547 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 548 container = container_get(qdev_get_machine(), fdc_container_path[i]); 549 object_child_foreach(container, check_fdc, &state); 550 } 551 552 if (state.multiple) { 553 warn_report("multiple floppy disk controllers with " 554 "iobase=0x3f0 have been found"); 555 error_printf("the one being picked for CMOS setup might not reflect " 556 "your intent"); 557 } 558 559 return state.floppy; 560 } 561 562 static void pc_cmos_init_late(void *opaque) 563 { 564 pc_cmos_init_late_arg *arg = opaque; 565 ISADevice *s = arg->rtc_state; 566 int16_t cylinders; 567 int8_t heads, sectors; 568 int val; 569 int i, trans; 570 571 val = 0; 572 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 573 &cylinders, &heads, §ors) >= 0) { 574 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 575 val |= 0xf0; 576 } 577 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 578 &cylinders, &heads, §ors) >= 0) { 579 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 580 val |= 0x0f; 581 } 582 rtc_set_memory(s, 0x12, val); 583 584 val = 0; 585 for (i = 0; i < 4; i++) { 586 /* NOTE: ide_get_geometry() returns the physical 587 geometry. It is always such that: 1 <= sects <= 63, 1 588 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 589 geometry can be different if a translation is done. */ 590 if (arg->idebus[i / 2] && 591 ide_get_geometry(arg->idebus[i / 2], i % 2, 592 &cylinders, &heads, §ors) >= 0) { 593 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 594 assert((trans & ~3) == 0); 595 val |= trans << (i * 2); 596 } 597 } 598 rtc_set_memory(s, 0x39, val); 599 600 pc_cmos_init_floppy(s, pc_find_fdc0()); 601 602 qemu_unregister_reset(pc_cmos_init_late, opaque); 603 } 604 605 void pc_cmos_init(PCMachineState *pcms, 606 BusState *idebus0, BusState *idebus1, 607 ISADevice *s) 608 { 609 int val; 610 static pc_cmos_init_late_arg arg; 611 X86MachineState *x86ms = X86_MACHINE(pcms); 612 613 /* various important CMOS locations needed by PC/Bochs bios */ 614 615 /* memory size */ 616 /* base memory (first MiB) */ 617 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 618 rtc_set_memory(s, 0x15, val); 619 rtc_set_memory(s, 0x16, val >> 8); 620 /* extended memory (next 64MiB) */ 621 if (x86ms->below_4g_mem_size > 1 * MiB) { 622 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 623 } else { 624 val = 0; 625 } 626 if (val > 65535) 627 val = 65535; 628 rtc_set_memory(s, 0x17, val); 629 rtc_set_memory(s, 0x18, val >> 8); 630 rtc_set_memory(s, 0x30, val); 631 rtc_set_memory(s, 0x31, val >> 8); 632 /* memory between 16MiB and 4GiB */ 633 if (x86ms->below_4g_mem_size > 16 * MiB) { 634 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 635 } else { 636 val = 0; 637 } 638 if (val > 65535) 639 val = 65535; 640 rtc_set_memory(s, 0x34, val); 641 rtc_set_memory(s, 0x35, val >> 8); 642 /* memory above 4GiB */ 643 val = x86ms->above_4g_mem_size / 65536; 644 rtc_set_memory(s, 0x5b, val); 645 rtc_set_memory(s, 0x5c, val >> 8); 646 rtc_set_memory(s, 0x5d, val >> 16); 647 648 object_property_add_link(OBJECT(pcms), "rtc_state", 649 TYPE_ISA_DEVICE, 650 (Object **)&x86ms->rtc, 651 object_property_allow_set_link, 652 OBJ_PROP_LINK_STRONG); 653 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 654 &error_abort); 655 656 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 657 658 val = 0; 659 val |= 0x02; /* FPU is there */ 660 val |= 0x04; /* PS/2 mouse installed */ 661 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 662 663 /* hard drives and FDC */ 664 arg.rtc_state = s; 665 arg.idebus[0] = idebus0; 666 arg.idebus[1] = idebus1; 667 qemu_register_reset(pc_cmos_init_late, &arg); 668 } 669 670 static void handle_a20_line_change(void *opaque, int irq, int level) 671 { 672 X86CPU *cpu = opaque; 673 674 /* XXX: send to all CPUs ? */ 675 /* XXX: add logic to handle multiple A20 line sources */ 676 x86_cpu_set_a20(cpu, level); 677 } 678 679 #define NE2000_NB_MAX 6 680 681 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 682 0x280, 0x380 }; 683 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 684 685 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 686 { 687 static int nb_ne2k = 0; 688 689 if (nb_ne2k == NE2000_NB_MAX) 690 return; 691 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 692 ne2000_irq[nb_ne2k], nd); 693 nb_ne2k++; 694 } 695 696 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 697 { 698 X86CPU *cpu = opaque; 699 700 if (level) { 701 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 702 } 703 } 704 705 /* 706 * This function is very similar to smp_parse() 707 * in hw/core/machine.c but includes CPU die support. 708 */ 709 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 710 { 711 X86MachineState *x86ms = X86_MACHINE(ms); 712 713 if (opts) { 714 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 715 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 716 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 717 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 718 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 719 720 /* compute missing values, prefer sockets over cores over threads */ 721 if (cpus == 0 || sockets == 0) { 722 cores = cores > 0 ? cores : 1; 723 threads = threads > 0 ? threads : 1; 724 if (cpus == 0) { 725 sockets = sockets > 0 ? sockets : 1; 726 cpus = cores * threads * dies * sockets; 727 } else { 728 ms->smp.max_cpus = 729 qemu_opt_get_number(opts, "maxcpus", cpus); 730 sockets = ms->smp.max_cpus / (cores * threads * dies); 731 } 732 } else if (cores == 0) { 733 threads = threads > 0 ? threads : 1; 734 cores = cpus / (sockets * dies * threads); 735 cores = cores > 0 ? cores : 1; 736 } else if (threads == 0) { 737 threads = cpus / (cores * dies * sockets); 738 threads = threads > 0 ? threads : 1; 739 } else if (sockets * dies * cores * threads < cpus) { 740 error_report("cpu topology: " 741 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 742 "smp_cpus (%u)", 743 sockets, dies, cores, threads, cpus); 744 exit(1); 745 } 746 747 ms->smp.max_cpus = 748 qemu_opt_get_number(opts, "maxcpus", cpus); 749 750 if (ms->smp.max_cpus < cpus) { 751 error_report("maxcpus must be equal to or greater than smp"); 752 exit(1); 753 } 754 755 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 756 error_report("Invalid CPU topology deprecated: " 757 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 758 "!= maxcpus (%u)", 759 sockets, dies, cores, threads, 760 ms->smp.max_cpus); 761 exit(1); 762 } 763 764 ms->smp.cpus = cpus; 765 ms->smp.cores = cores; 766 ms->smp.threads = threads; 767 ms->smp.sockets = sockets; 768 x86ms->smp_dies = dies; 769 } 770 771 if (ms->smp.cpus > 1) { 772 Error *blocker = NULL; 773 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 774 replay_add_blocker(blocker); 775 } 776 } 777 778 static 779 void pc_machine_done(Notifier *notifier, void *data) 780 { 781 PCMachineState *pcms = container_of(notifier, 782 PCMachineState, machine_done); 783 X86MachineState *x86ms = X86_MACHINE(pcms); 784 785 /* set the number of CPUs */ 786 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 787 788 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 789 790 acpi_setup(); 791 if (x86ms->fw_cfg) { 792 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 793 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 794 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 795 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 796 } 797 798 799 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 800 !kvm_irqchip_in_kernel()) { 801 error_report("current -smp configuration requires kernel " 802 "irqchip support."); 803 exit(EXIT_FAILURE); 804 } 805 } 806 807 void pc_guest_info_init(PCMachineState *pcms) 808 { 809 int i; 810 MachineState *ms = MACHINE(pcms); 811 X86MachineState *x86ms = X86_MACHINE(pcms); 812 813 x86ms->apic_xrupt_override = true; 814 pcms->numa_nodes = ms->numa_state->num_nodes; 815 pcms->node_mem = g_malloc0(pcms->numa_nodes * 816 sizeof *pcms->node_mem); 817 for (i = 0; i < ms->numa_state->num_nodes; i++) { 818 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 819 } 820 821 pcms->machine_done.notify = pc_machine_done; 822 qemu_add_machine_init_done_notifier(&pcms->machine_done); 823 } 824 825 /* setup pci memory address space mapping into system address space */ 826 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 827 MemoryRegion *pci_address_space) 828 { 829 /* Set to lower priority than RAM */ 830 memory_region_add_subregion_overlap(system_memory, 0x0, 831 pci_address_space, -1); 832 } 833 834 void xen_load_linux(PCMachineState *pcms) 835 { 836 int i; 837 FWCfgState *fw_cfg; 838 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 839 X86MachineState *x86ms = X86_MACHINE(pcms); 840 841 assert(MACHINE(pcms)->kernel_filename != NULL); 842 843 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 844 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 845 rom_set_fw(fw_cfg); 846 847 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 848 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 849 for (i = 0; i < nb_option_roms; i++) { 850 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 851 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 852 !strcmp(option_rom[i].name, "pvh.bin") || 853 !strcmp(option_rom[i].name, "multiboot.bin")); 854 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 855 } 856 x86ms->fw_cfg = fw_cfg; 857 } 858 859 void pc_memory_init(PCMachineState *pcms, 860 MemoryRegion *system_memory, 861 MemoryRegion *rom_memory, 862 MemoryRegion **ram_memory) 863 { 864 int linux_boot, i; 865 MemoryRegion *option_rom_mr; 866 MemoryRegion *ram_below_4g, *ram_above_4g; 867 FWCfgState *fw_cfg; 868 MachineState *machine = MACHINE(pcms); 869 MachineClass *mc = MACHINE_GET_CLASS(machine); 870 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 871 X86MachineState *x86ms = X86_MACHINE(pcms); 872 873 assert(machine->ram_size == x86ms->below_4g_mem_size + 874 x86ms->above_4g_mem_size); 875 876 linux_boot = (machine->kernel_filename != NULL); 877 878 /* 879 * Split single memory region and use aliases to address portions of it, 880 * done for backwards compatibility with older qemus. 881 */ 882 *ram_memory = machine->ram; 883 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 884 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 885 0, x86ms->below_4g_mem_size); 886 memory_region_add_subregion(system_memory, 0, ram_below_4g); 887 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 888 if (x86ms->above_4g_mem_size > 0) { 889 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 890 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 891 machine->ram, 892 x86ms->below_4g_mem_size, 893 x86ms->above_4g_mem_size); 894 memory_region_add_subregion(system_memory, 0x100000000ULL, 895 ram_above_4g); 896 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 897 } 898 899 if (!pcmc->has_reserved_memory && 900 (machine->ram_slots || 901 (machine->maxram_size > machine->ram_size))) { 902 903 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 904 mc->name); 905 exit(EXIT_FAILURE); 906 } 907 908 /* always allocate the device memory information */ 909 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 910 911 /* initialize device memory address space */ 912 if (pcmc->has_reserved_memory && 913 (machine->ram_size < machine->maxram_size)) { 914 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 915 916 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 917 error_report("unsupported amount of memory slots: %"PRIu64, 918 machine->ram_slots); 919 exit(EXIT_FAILURE); 920 } 921 922 if (QEMU_ALIGN_UP(machine->maxram_size, 923 TARGET_PAGE_SIZE) != machine->maxram_size) { 924 error_report("maximum memory size must by aligned to multiple of " 925 "%d bytes", TARGET_PAGE_SIZE); 926 exit(EXIT_FAILURE); 927 } 928 929 machine->device_memory->base = 930 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 931 932 if (pcmc->enforce_aligned_dimm) { 933 /* size device region assuming 1G page max alignment per slot */ 934 device_mem_size += (1 * GiB) * machine->ram_slots; 935 } 936 937 if ((machine->device_memory->base + device_mem_size) < 938 device_mem_size) { 939 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 940 machine->maxram_size); 941 exit(EXIT_FAILURE); 942 } 943 944 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 945 "device-memory", device_mem_size); 946 memory_region_add_subregion(system_memory, machine->device_memory->base, 947 &machine->device_memory->mr); 948 } 949 950 /* Initialize PC system firmware */ 951 pc_system_firmware_init(pcms, rom_memory); 952 953 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 954 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 955 &error_fatal); 956 if (pcmc->pci_enabled) { 957 memory_region_set_readonly(option_rom_mr, true); 958 } 959 memory_region_add_subregion_overlap(rom_memory, 960 PC_ROM_MIN_VGA, 961 option_rom_mr, 962 1); 963 964 fw_cfg = fw_cfg_arch_create(machine, 965 x86ms->boot_cpus, x86ms->apic_id_limit); 966 967 rom_set_fw(fw_cfg); 968 969 if (pcmc->has_reserved_memory && machine->device_memory->base) { 970 uint64_t *val = g_malloc(sizeof(*val)); 971 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 972 uint64_t res_mem_end = machine->device_memory->base; 973 974 if (!pcmc->broken_reserved_end) { 975 res_mem_end += memory_region_size(&machine->device_memory->mr); 976 } 977 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 978 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 979 } 980 981 if (linux_boot) { 982 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 983 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 984 } 985 986 for (i = 0; i < nb_option_roms; i++) { 987 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 988 } 989 x86ms->fw_cfg = fw_cfg; 990 991 /* Init default IOAPIC address space */ 992 x86ms->ioapic_as = &address_space_memory; 993 994 /* Init ACPI memory hotplug IO base address */ 995 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 996 } 997 998 /* 999 * The 64bit pci hole starts after "above 4G RAM" and 1000 * potentially the space reserved for memory hotplug. 1001 */ 1002 uint64_t pc_pci_hole64_start(void) 1003 { 1004 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1005 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1006 MachineState *ms = MACHINE(pcms); 1007 X86MachineState *x86ms = X86_MACHINE(pcms); 1008 uint64_t hole64_start = 0; 1009 1010 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1011 hole64_start = ms->device_memory->base; 1012 if (!pcmc->broken_reserved_end) { 1013 hole64_start += memory_region_size(&ms->device_memory->mr); 1014 } 1015 } else { 1016 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1017 } 1018 1019 return ROUND_UP(hole64_start, 1 * GiB); 1020 } 1021 1022 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1023 { 1024 DeviceState *dev = NULL; 1025 1026 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1027 if (pci_bus) { 1028 PCIDevice *pcidev = pci_vga_init(pci_bus); 1029 dev = pcidev ? &pcidev->qdev : NULL; 1030 } else if (isa_bus) { 1031 ISADevice *isadev = isa_vga_init(isa_bus); 1032 dev = isadev ? DEVICE(isadev) : NULL; 1033 } 1034 rom_reset_order_override(); 1035 return dev; 1036 } 1037 1038 static const MemoryRegionOps ioport80_io_ops = { 1039 .write = ioport80_write, 1040 .read = ioport80_read, 1041 .endianness = DEVICE_NATIVE_ENDIAN, 1042 .impl = { 1043 .min_access_size = 1, 1044 .max_access_size = 1, 1045 }, 1046 }; 1047 1048 static const MemoryRegionOps ioportF0_io_ops = { 1049 .write = ioportF0_write, 1050 .read = ioportF0_read, 1051 .endianness = DEVICE_NATIVE_ENDIAN, 1052 .impl = { 1053 .min_access_size = 1, 1054 .max_access_size = 1, 1055 }, 1056 }; 1057 1058 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1059 { 1060 int i; 1061 DriveInfo *fd[MAX_FD]; 1062 qemu_irq *a20_line; 1063 ISADevice *fdc, *i8042, *port92, *vmmouse; 1064 1065 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1066 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1067 1068 for (i = 0; i < MAX_FD; i++) { 1069 fd[i] = drive_get(IF_FLOPPY, 0, i); 1070 create_fdctrl |= !!fd[i]; 1071 } 1072 if (create_fdctrl) { 1073 fdc = isa_new(TYPE_ISA_FDC); 1074 if (fdc) { 1075 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1076 isa_fdc_init_drives(fdc, fd); 1077 } 1078 } 1079 1080 i8042 = isa_create_simple(isa_bus, "i8042"); 1081 if (!no_vmport) { 1082 isa_create_simple(isa_bus, TYPE_VMPORT); 1083 vmmouse = isa_try_new("vmmouse"); 1084 } else { 1085 vmmouse = NULL; 1086 } 1087 if (vmmouse) { 1088 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1089 &error_abort); 1090 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1091 } 1092 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1093 1094 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1095 i8042_setup_a20_line(i8042, a20_line[0]); 1096 qdev_connect_gpio_out_named(DEVICE(port92), 1097 PORT92_A20_LINE, 0, a20_line[1]); 1098 g_free(a20_line); 1099 } 1100 1101 void pc_basic_device_init(struct PCMachineState *pcms, 1102 ISABus *isa_bus, qemu_irq *gsi, 1103 ISADevice **rtc_state, 1104 bool create_fdctrl, 1105 uint32_t hpet_irqs) 1106 { 1107 int i; 1108 DeviceState *hpet = NULL; 1109 int pit_isa_irq = 0; 1110 qemu_irq pit_alt_irq = NULL; 1111 qemu_irq rtc_irq = NULL; 1112 ISADevice *pit = NULL; 1113 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1114 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1115 1116 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1117 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1118 1119 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1120 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1121 1122 /* 1123 * Check if an HPET shall be created. 1124 * 1125 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1126 * when the HPET wants to take over. Thus we have to disable the latter. 1127 */ 1128 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1129 kvm_has_pit_state2())) { 1130 hpet = qdev_try_new(TYPE_HPET); 1131 if (!hpet) { 1132 error_report("couldn't create HPET device"); 1133 exit(1); 1134 } 1135 /* 1136 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1137 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1138 * IRQ2. 1139 */ 1140 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1141 HPET_INTCAP, NULL); 1142 if (!compat) { 1143 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1144 } 1145 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1146 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1147 1148 for (i = 0; i < GSI_NUM_PINS; i++) { 1149 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1150 } 1151 pit_isa_irq = -1; 1152 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1153 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1154 } 1155 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1156 1157 qemu_register_boot_set(pc_boot_set, *rtc_state); 1158 1159 if (!xen_enabled() && pcms->pit_enabled) { 1160 if (kvm_pit_in_kernel()) { 1161 pit = kvm_pit_init(isa_bus, 0x40); 1162 } else { 1163 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1164 } 1165 if (hpet) { 1166 /* connect PIT to output control line of the HPET */ 1167 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1168 } 1169 pcspk_init(pcms->pcspk, isa_bus, pit); 1170 } 1171 1172 i8257_dma_init(isa_bus, 0); 1173 1174 /* Super I/O */ 1175 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1176 } 1177 1178 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1179 { 1180 int i; 1181 1182 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1183 for (i = 0; i < nb_nics; i++) { 1184 NICInfo *nd = &nd_table[i]; 1185 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1186 1187 if (g_str_equal(model, "ne2k_isa")) { 1188 pc_init_ne2k_isa(isa_bus, nd); 1189 } else { 1190 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1191 } 1192 } 1193 rom_reset_order_override(); 1194 } 1195 1196 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1197 { 1198 qemu_irq *i8259; 1199 1200 if (kvm_pic_in_kernel()) { 1201 i8259 = kvm_i8259_init(isa_bus); 1202 } else if (xen_enabled()) { 1203 i8259 = xen_interrupt_controller_init(); 1204 } else { 1205 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1206 } 1207 1208 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1209 i8259_irqs[i] = i8259[i]; 1210 } 1211 1212 g_free(i8259); 1213 } 1214 1215 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1216 Error **errp) 1217 { 1218 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1219 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1220 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1221 const MachineState *ms = MACHINE(hotplug_dev); 1222 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1223 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1224 Error *local_err = NULL; 1225 1226 /* 1227 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1228 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1229 * addition to cover this case. 1230 */ 1231 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1232 error_setg(errp, 1233 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1234 return; 1235 } 1236 1237 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1238 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1239 return; 1240 } 1241 1242 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1243 if (local_err) { 1244 error_propagate(errp, local_err); 1245 return; 1246 } 1247 1248 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1249 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1250 } 1251 1252 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1253 DeviceState *dev, Error **errp) 1254 { 1255 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1256 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1257 MachineState *ms = MACHINE(hotplug_dev); 1258 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1259 1260 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1261 1262 if (is_nvdimm) { 1263 nvdimm_plug(ms->nvdimms_state); 1264 } 1265 1266 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1267 } 1268 1269 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1270 DeviceState *dev, Error **errp) 1271 { 1272 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1273 1274 /* 1275 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1276 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1277 * addition to cover this case. 1278 */ 1279 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1280 error_setg(errp, 1281 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1282 return; 1283 } 1284 1285 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1286 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1287 return; 1288 } 1289 1290 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1291 errp); 1292 } 1293 1294 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1295 DeviceState *dev, Error **errp) 1296 { 1297 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1298 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1299 Error *local_err = NULL; 1300 1301 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1302 if (local_err) { 1303 goto out; 1304 } 1305 1306 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1307 qdev_unrealize(dev); 1308 out: 1309 error_propagate(errp, local_err); 1310 } 1311 1312 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1313 DeviceState *dev, Error **errp) 1314 { 1315 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1316 Error *local_err = NULL; 1317 1318 if (!hotplug_dev2 && dev->hotplugged) { 1319 /* 1320 * Without a bus hotplug handler, we cannot control the plug/unplug 1321 * order. We should never reach this point when hotplugging on x86, 1322 * however, better add a safety net. 1323 */ 1324 error_setg(errp, "hotplug of virtio based memory devices not supported" 1325 " on this bus."); 1326 return; 1327 } 1328 /* 1329 * First, see if we can plug this memory device at all. If that 1330 * succeeds, branch of to the actual hotplug handler. 1331 */ 1332 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1333 &local_err); 1334 if (!local_err && hotplug_dev2) { 1335 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1336 } 1337 error_propagate(errp, local_err); 1338 } 1339 1340 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1341 DeviceState *dev, Error **errp) 1342 { 1343 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1344 Error *local_err = NULL; 1345 1346 /* 1347 * Plug the memory device first and then branch off to the actual 1348 * hotplug handler. If that one fails, we can easily undo the memory 1349 * device bits. 1350 */ 1351 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1352 if (hotplug_dev2) { 1353 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1354 if (local_err) { 1355 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1356 } 1357 } 1358 error_propagate(errp, local_err); 1359 } 1360 1361 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 /* We don't support hot unplug of virtio based memory devices */ 1365 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1366 } 1367 1368 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1369 DeviceState *dev, Error **errp) 1370 { 1371 /* We don't support hot unplug of virtio based memory devices */ 1372 } 1373 1374 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1378 pc_memory_pre_plug(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1380 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1382 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1383 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1384 } 1385 } 1386 1387 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1388 DeviceState *dev, Error **errp) 1389 { 1390 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1391 pc_memory_plug(hotplug_dev, dev, errp); 1392 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1393 x86_cpu_plug(hotplug_dev, dev, errp); 1394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1395 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1396 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1397 } 1398 } 1399 1400 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1401 DeviceState *dev, Error **errp) 1402 { 1403 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1404 pc_memory_unplug_request(hotplug_dev, dev, errp); 1405 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1406 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1408 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1409 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1410 } else { 1411 error_setg(errp, "acpi: device unplug request for not supported device" 1412 " type: %s", object_get_typename(OBJECT(dev))); 1413 } 1414 } 1415 1416 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1417 DeviceState *dev, Error **errp) 1418 { 1419 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1420 pc_memory_unplug(hotplug_dev, dev, errp); 1421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1422 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1424 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1425 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1426 } else { 1427 error_setg(errp, "acpi: device unplug for not supported device" 1428 " type: %s", object_get_typename(OBJECT(dev))); 1429 } 1430 } 1431 1432 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1433 DeviceState *dev) 1434 { 1435 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1436 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1437 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1438 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1439 return HOTPLUG_HANDLER(machine); 1440 } 1441 1442 return NULL; 1443 } 1444 1445 static void 1446 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1447 const char *name, void *opaque, 1448 Error **errp) 1449 { 1450 MachineState *ms = MACHINE(obj); 1451 int64_t value = 0; 1452 1453 if (ms->device_memory) { 1454 value = memory_region_size(&ms->device_memory->mr); 1455 } 1456 1457 visit_type_int(v, name, &value, errp); 1458 } 1459 1460 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1461 void *opaque, Error **errp) 1462 { 1463 PCMachineState *pcms = PC_MACHINE(obj); 1464 OnOffAuto vmport = pcms->vmport; 1465 1466 visit_type_OnOffAuto(v, name, &vmport, errp); 1467 } 1468 1469 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1470 void *opaque, Error **errp) 1471 { 1472 PCMachineState *pcms = PC_MACHINE(obj); 1473 1474 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1475 } 1476 1477 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1478 { 1479 PCMachineState *pcms = PC_MACHINE(obj); 1480 1481 return pcms->smbus_enabled; 1482 } 1483 1484 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1485 { 1486 PCMachineState *pcms = PC_MACHINE(obj); 1487 1488 pcms->smbus_enabled = value; 1489 } 1490 1491 static bool pc_machine_get_sata(Object *obj, Error **errp) 1492 { 1493 PCMachineState *pcms = PC_MACHINE(obj); 1494 1495 return pcms->sata_enabled; 1496 } 1497 1498 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1499 { 1500 PCMachineState *pcms = PC_MACHINE(obj); 1501 1502 pcms->sata_enabled = value; 1503 } 1504 1505 static bool pc_machine_get_pit(Object *obj, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 return pcms->pit_enabled; 1510 } 1511 1512 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 pcms->pit_enabled = value; 1517 } 1518 1519 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 return pcms->hpet_enabled; 1524 } 1525 1526 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 pcms->hpet_enabled = value; 1531 } 1532 1533 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1534 const char *name, void *opaque, 1535 Error **errp) 1536 { 1537 PCMachineState *pcms = PC_MACHINE(obj); 1538 uint64_t value = pcms->max_ram_below_4g; 1539 1540 visit_type_size(v, name, &value, errp); 1541 } 1542 1543 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1544 const char *name, void *opaque, 1545 Error **errp) 1546 { 1547 PCMachineState *pcms = PC_MACHINE(obj); 1548 uint64_t value; 1549 1550 if (!visit_type_size(v, name, &value, errp)) { 1551 return; 1552 } 1553 if (value > 4 * GiB) { 1554 error_setg(errp, 1555 "Machine option 'max-ram-below-4g=%"PRIu64 1556 "' expects size less than or equal to 4G", value); 1557 return; 1558 } 1559 1560 if (value < 1 * MiB) { 1561 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1562 "BIOS may not work with less than 1MiB", value); 1563 } 1564 1565 pcms->max_ram_below_4g = value; 1566 } 1567 1568 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1569 const char *name, void *opaque, 1570 Error **errp) 1571 { 1572 PCMachineState *pcms = PC_MACHINE(obj); 1573 uint64_t value = pcms->max_fw_size; 1574 1575 visit_type_size(v, name, &value, errp); 1576 } 1577 1578 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1579 const char *name, void *opaque, 1580 Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 Error *error = NULL; 1584 uint64_t value; 1585 1586 visit_type_size(v, name, &value, &error); 1587 if (error) { 1588 error_propagate(errp, error); 1589 return; 1590 } 1591 1592 /* 1593 * We don't have a theoretically justifiable exact lower bound on the base 1594 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1595 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1596 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1597 * size. 1598 */ 1599 if (value > 16 * MiB) { 1600 error_setg(errp, 1601 "User specified max allowed firmware size %" PRIu64 " is " 1602 "greater than 16MiB. If combined firwmare size exceeds " 1603 "16MiB the system may not boot, or experience intermittent" 1604 "stability issues.", 1605 value); 1606 return; 1607 } 1608 1609 pcms->max_fw_size = value; 1610 } 1611 1612 1613 static void pc_machine_initfn(Object *obj) 1614 { 1615 PCMachineState *pcms = PC_MACHINE(obj); 1616 1617 #ifdef CONFIG_VMPORT 1618 pcms->vmport = ON_OFF_AUTO_AUTO; 1619 #else 1620 pcms->vmport = ON_OFF_AUTO_OFF; 1621 #endif /* CONFIG_VMPORT */ 1622 pcms->max_ram_below_4g = 0; /* use default */ 1623 /* acpi build is enabled by default if machine supports it */ 1624 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1625 pcms->smbus_enabled = true; 1626 pcms->sata_enabled = true; 1627 pcms->pit_enabled = true; 1628 pcms->max_fw_size = 8 * MiB; 1629 #ifdef CONFIG_HPET 1630 pcms->hpet_enabled = true; 1631 #endif 1632 1633 pc_system_flash_create(pcms); 1634 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1635 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1636 OBJECT(pcms->pcspk), "audiodev"); 1637 } 1638 1639 static void pc_machine_reset(MachineState *machine) 1640 { 1641 CPUState *cs; 1642 X86CPU *cpu; 1643 1644 qemu_devices_reset(); 1645 1646 /* Reset APIC after devices have been reset to cancel 1647 * any changes that qemu_devices_reset() might have done. 1648 */ 1649 CPU_FOREACH(cs) { 1650 cpu = X86_CPU(cs); 1651 1652 if (cpu->apic_state) { 1653 device_legacy_reset(cpu->apic_state); 1654 } 1655 } 1656 } 1657 1658 static void pc_machine_wakeup(MachineState *machine) 1659 { 1660 cpu_synchronize_all_states(); 1661 pc_machine_reset(machine); 1662 cpu_synchronize_all_post_reset(); 1663 } 1664 1665 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1666 { 1667 X86IOMMUState *iommu = x86_iommu_get_default(); 1668 IntelIOMMUState *intel_iommu; 1669 1670 if (iommu && 1671 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1672 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1673 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1674 if (!intel_iommu->caching_mode) { 1675 error_setg(errp, "Device assignment is not allowed without " 1676 "enabling caching-mode=on for Intel IOMMU."); 1677 return false; 1678 } 1679 } 1680 1681 return true; 1682 } 1683 1684 static void pc_machine_class_init(ObjectClass *oc, void *data) 1685 { 1686 MachineClass *mc = MACHINE_CLASS(oc); 1687 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1688 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1689 1690 pcmc->pci_enabled = true; 1691 pcmc->has_acpi_build = true; 1692 pcmc->rsdp_in_ram = true; 1693 pcmc->smbios_defaults = true; 1694 pcmc->smbios_uuid_encoded = true; 1695 pcmc->gigabyte_align = true; 1696 pcmc->has_reserved_memory = true; 1697 pcmc->kvmclock_enabled = true; 1698 pcmc->enforce_aligned_dimm = true; 1699 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1700 * to be used at the moment, 32K should be enough for a while. */ 1701 pcmc->acpi_data_size = 0x20000 + 0x8000; 1702 pcmc->linuxboot_dma_enabled = true; 1703 pcmc->pvh_enabled = true; 1704 pcmc->kvmclock_create_always = true; 1705 assert(!mc->get_hotplug_handler); 1706 mc->get_hotplug_handler = pc_get_hotplug_handler; 1707 mc->hotplug_allowed = pc_hotplug_allowed; 1708 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1709 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1710 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1711 mc->auto_enable_numa_with_memhp = true; 1712 mc->auto_enable_numa_with_memdev = true; 1713 mc->has_hotpluggable_cpus = true; 1714 mc->default_boot_order = "cad"; 1715 mc->smp_parse = pc_smp_parse; 1716 mc->block_default_type = IF_IDE; 1717 mc->max_cpus = 255; 1718 mc->reset = pc_machine_reset; 1719 mc->wakeup = pc_machine_wakeup; 1720 hc->pre_plug = pc_machine_device_pre_plug_cb; 1721 hc->plug = pc_machine_device_plug_cb; 1722 hc->unplug_request = pc_machine_device_unplug_request_cb; 1723 hc->unplug = pc_machine_device_unplug_cb; 1724 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1725 mc->nvdimm_supported = true; 1726 mc->default_ram_id = "pc.ram"; 1727 1728 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1729 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1730 NULL, NULL); 1731 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1732 "Maximum ram below the 4G boundary (32bit boundary)"); 1733 1734 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1735 pc_machine_get_device_memory_region_size, NULL, 1736 NULL, NULL); 1737 1738 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1739 pc_machine_get_vmport, pc_machine_set_vmport, 1740 NULL, NULL); 1741 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1742 "Enable vmport (pc & q35)"); 1743 1744 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1745 pc_machine_get_smbus, pc_machine_set_smbus); 1746 1747 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1748 pc_machine_get_sata, pc_machine_set_sata); 1749 1750 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1751 pc_machine_get_pit, pc_machine_set_pit); 1752 1753 object_class_property_add_bool(oc, "hpet", 1754 pc_machine_get_hpet, pc_machine_set_hpet); 1755 1756 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1757 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1758 NULL, NULL); 1759 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1760 "Maximum combined firmware size"); 1761 } 1762 1763 static const TypeInfo pc_machine_info = { 1764 .name = TYPE_PC_MACHINE, 1765 .parent = TYPE_X86_MACHINE, 1766 .abstract = true, 1767 .instance_size = sizeof(PCMachineState), 1768 .instance_init = pc_machine_initfn, 1769 .class_size = sizeof(PCMachineClass), 1770 .class_init = pc_machine_class_init, 1771 .interfaces = (InterfaceInfo[]) { 1772 { TYPE_HOTPLUG_HANDLER }, 1773 { } 1774 }, 1775 }; 1776 1777 static void pc_machine_register_types(void) 1778 { 1779 type_register_static(&pc_machine_info); 1780 } 1781 1782 type_init(pc_machine_register_types) 1783