1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/smbios/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "qemu/error-report.h" 47 #include "migration/migration.h" 48 49 /* ICH9 AHCI has 6 ports */ 50 #define MAX_SATA_PORTS 6 51 52 static bool has_acpi_build = true; 53 static bool rsdp_in_ram = true; 54 static bool smbios_defaults = true; 55 static bool smbios_legacy_mode; 56 static bool smbios_uuid_encoded = true; 57 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 58 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 59 * pages in the host. 60 */ 61 static bool gigabyte_align = true; 62 static bool has_reserved_memory = true; 63 64 /* PC hardware initialisation */ 65 static void pc_q35_init(MachineState *machine) 66 { 67 PCMachineState *pcms = PC_MACHINE(machine); 68 Q35PCIHost *q35_host; 69 PCIHostState *phb; 70 PCIBus *host_bus; 71 PCIDevice *lpc; 72 BusState *idebus[MAX_SATA_PORTS]; 73 ISADevice *rtc_state; 74 MemoryRegion *pci_memory; 75 MemoryRegion *rom_memory; 76 MemoryRegion *ram_memory; 77 GSIState *gsi_state; 78 ISABus *isa_bus; 79 int pci_enabled = 1; 80 qemu_irq *gsi; 81 qemu_irq *i8259; 82 int i; 83 ICH9LPCState *ich9_lpc; 84 PCIDevice *ahci; 85 PcGuestInfo *guest_info; 86 ram_addr_t lowmem; 87 DriveInfo *hd[MAX_SATA_PORTS]; 88 MachineClass *mc = MACHINE_GET_CLASS(machine); 89 90 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 91 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 92 * also known as MMCFG). 93 * If it doesn't, we need to split it in chunks below and above 4G. 94 * In any case, try to make sure that guest addresses aligned at 95 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 96 * For old machine types, use whatever split we used historically to avoid 97 * breaking migration. 98 */ 99 if (machine->ram_size >= 0xb0000000) { 100 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 101 } else { 102 lowmem = 0xb0000000; 103 } 104 105 /* Handle the machine opt max-ram-below-4g. It is basically doing 106 * min(qemu limit, user limit). 107 */ 108 if (lowmem > pcms->max_ram_below_4g) { 109 lowmem = pcms->max_ram_below_4g; 110 if (machine->ram_size - lowmem > lowmem && 111 lowmem & ((1ULL << 30) - 1)) { 112 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 113 ") not a multiple of 1G; possible bad performance.", 114 pcms->max_ram_below_4g); 115 } 116 } 117 118 if (machine->ram_size >= lowmem) { 119 pcms->above_4g_mem_size = machine->ram_size - lowmem; 120 pcms->below_4g_mem_size = lowmem; 121 } else { 122 pcms->above_4g_mem_size = 0; 123 pcms->below_4g_mem_size = machine->ram_size; 124 } 125 126 if (xen_enabled() && xen_hvm_init(pcms, &ram_memory) != 0) { 127 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 128 exit(1); 129 } 130 131 pc_cpus_init(pcms); 132 pc_acpi_init("q35-acpi-dsdt.aml"); 133 134 kvmclock_create(); 135 136 /* pci enabled */ 137 if (pci_enabled) { 138 pci_memory = g_new(MemoryRegion, 1); 139 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 140 rom_memory = pci_memory; 141 } else { 142 pci_memory = NULL; 143 rom_memory = get_system_memory(); 144 } 145 146 guest_info = pc_guest_info_init(pcms); 147 guest_info->isapc_ram_fw = false; 148 guest_info->has_acpi_build = has_acpi_build; 149 guest_info->has_reserved_memory = has_reserved_memory; 150 guest_info->rsdp_in_ram = rsdp_in_ram; 151 152 /* Migration was not supported in 2.0 for Q35, so do not bother 153 * with this hack (see hw/i386/acpi-build.c). 154 */ 155 guest_info->legacy_acpi_table_size = 0; 156 157 if (smbios_defaults) { 158 /* These values are guest ABI, do not change */ 159 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 160 mc->name, smbios_legacy_mode, smbios_uuid_encoded, 161 SMBIOS_ENTRY_POINT_21); 162 } 163 164 /* allocate ram and load rom/bios */ 165 if (!xen_enabled()) { 166 pc_memory_init(pcms, get_system_memory(), 167 rom_memory, &ram_memory, guest_info); 168 } 169 170 /* irq lines */ 171 gsi_state = g_malloc0(sizeof(*gsi_state)); 172 if (kvm_irqchip_in_kernel()) { 173 kvm_pc_setup_irq_routing(pci_enabled); 174 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 175 GSI_NUM_PINS); 176 } else { 177 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 178 } 179 180 /* create pci host bus */ 181 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 182 183 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 184 q35_host->mch.ram_memory = ram_memory; 185 q35_host->mch.pci_address_space = pci_memory; 186 q35_host->mch.system_memory = get_system_memory(); 187 q35_host->mch.address_space_io = get_system_io(); 188 q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size; 189 q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size; 190 q35_host->mch.guest_info = guest_info; 191 /* pci */ 192 qdev_init_nofail(DEVICE(q35_host)); 193 phb = PCI_HOST_BRIDGE(q35_host); 194 host_bus = phb->bus; 195 /* create ISA bus */ 196 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 197 ICH9_LPC_FUNC), true, 198 TYPE_ICH9_LPC_DEVICE); 199 200 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 201 TYPE_HOTPLUG_HANDLER, 202 (Object **)&pcms->acpi_dev, 203 object_property_allow_set_link, 204 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 205 object_property_set_link(OBJECT(machine), OBJECT(lpc), 206 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 207 208 ich9_lpc = ICH9_LPC_DEVICE(lpc); 209 ich9_lpc->pic = gsi; 210 ich9_lpc->ioapic = gsi_state->ioapic_irq; 211 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 212 ICH9_LPC_NB_PIRQS); 213 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 214 isa_bus = ich9_lpc->isa_bus; 215 216 /*end early*/ 217 isa_bus_irqs(isa_bus, gsi); 218 219 if (kvm_irqchip_in_kernel()) { 220 i8259 = kvm_i8259_init(isa_bus); 221 } else if (xen_enabled()) { 222 i8259 = xen_interrupt_controller_init(); 223 } else { 224 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 225 } 226 227 for (i = 0; i < ISA_NUM_IRQS; i++) { 228 gsi_state->i8259_irq[i] = i8259[i]; 229 } 230 if (pci_enabled) { 231 ioapic_init_gsi(gsi_state, "q35"); 232 } 233 234 pc_register_ferr_irq(gsi[13]); 235 236 assert(pcms->vmport != ON_OFF_AUTO_MAX); 237 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 238 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 239 } 240 241 /* init basic PC hardware */ 242 pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy, 243 (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104); 244 245 /* connect pm stuff to lpc */ 246 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms), !mc->no_tco); 247 248 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 249 ahci = pci_create_simple_multifunction(host_bus, 250 PCI_DEVFN(ICH9_SATA1_DEV, 251 ICH9_SATA1_FUNC), 252 true, "ich9-ahci"); 253 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 254 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 255 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 256 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 257 ahci_ide_create_devs(ahci, hd); 258 259 if (usb_enabled()) { 260 /* Should we create 6 UHCI according to ich9 spec? */ 261 ehci_create_ich9_with_companions(host_bus, 0x1d); 262 } 263 264 /* TODO: Populate SPD eeprom data. */ 265 smbus_eeprom_init(ich9_smb_init(host_bus, 266 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 267 0xb100), 268 8, NULL, 0); 269 270 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 271 272 /* the rest devices to which pci devfn is automatically assigned */ 273 pc_vga_init(isa_bus, host_bus); 274 pc_nic_init(isa_bus, host_bus); 275 if (pci_enabled) { 276 pc_pci_device_init(host_bus); 277 } 278 } 279 280 /* Looking for a pc_compat_2_4() function? It doesn't exist. 281 * pc_compat_*() functions that run on machine-init time and 282 * change global QEMU state are deprecated. Please don't create 283 * one, and implement any pc-*-2.4 (and newer) compat code in 284 * HW_COMPAT_*, PC_COMPAT_*, or * pc_*_machine_options(). 285 */ 286 287 static void pc_compat_2_3(MachineState *machine) 288 { 289 PCMachineState *pcms = PC_MACHINE(machine); 290 savevm_skip_section_footers(); 291 if (kvm_enabled()) { 292 pcms->smm = ON_OFF_AUTO_OFF; 293 } 294 global_state_set_optional(); 295 savevm_skip_configuration(); 296 } 297 298 static void pc_compat_2_2(MachineState *machine) 299 { 300 pc_compat_2_3(machine); 301 rsdp_in_ram = false; 302 machine->suppress_vmdesc = true; 303 } 304 305 static void pc_compat_2_1(MachineState *machine) 306 { 307 PCMachineState *pcms = PC_MACHINE(machine); 308 309 pc_compat_2_2(machine); 310 pcms->enforce_aligned_dimm = false; 311 smbios_uuid_encoded = false; 312 x86_cpu_change_kvm_default("svm", NULL); 313 } 314 315 static void pc_compat_2_0(MachineState *machine) 316 { 317 pc_compat_2_1(machine); 318 smbios_legacy_mode = true; 319 has_reserved_memory = false; 320 pc_set_legacy_acpi_data_size(); 321 } 322 323 static void pc_compat_1_7(MachineState *machine) 324 { 325 pc_compat_2_0(machine); 326 smbios_defaults = false; 327 gigabyte_align = false; 328 option_rom_has_mr = true; 329 x86_cpu_change_kvm_default("x2apic", NULL); 330 } 331 332 static void pc_compat_1_6(MachineState *machine) 333 { 334 pc_compat_1_7(machine); 335 rom_file_has_mr = false; 336 has_acpi_build = false; 337 } 338 339 static void pc_compat_1_5(MachineState *machine) 340 { 341 pc_compat_1_6(machine); 342 } 343 344 static void pc_compat_1_4(MachineState *machine) 345 { 346 pc_compat_1_5(machine); 347 } 348 349 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 350 static void pc_init_##suffix(MachineState *machine) \ 351 { \ 352 void (*compat)(MachineState *m) = (compatfn); \ 353 if (compat) { \ 354 compat(machine); \ 355 } \ 356 pc_q35_init(machine); \ 357 } \ 358 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 359 360 361 static void pc_q35_machine_options(MachineClass *m) 362 { 363 m->family = "pc_q35"; 364 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 365 m->hot_add_cpu = pc_hot_add_cpu; 366 m->units_per_default_bus = 1; 367 m->default_machine_opts = "firmware=bios-256k.bin"; 368 m->default_display = "std"; 369 m->no_floppy = 1; 370 m->no_tco = 0; 371 } 372 373 static void pc_q35_2_5_machine_options(MachineClass *m) 374 { 375 pc_q35_machine_options(m); 376 m->alias = "q35"; 377 } 378 379 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 380 pc_q35_2_5_machine_options); 381 382 static void pc_q35_2_4_machine_options(MachineClass *m) 383 { 384 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 385 pc_q35_2_5_machine_options(m); 386 m->alias = NULL; 387 pcmc->broken_reserved_end = true; 388 SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); 389 } 390 391 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 392 pc_q35_2_4_machine_options); 393 394 395 static void pc_q35_2_3_machine_options(MachineClass *m) 396 { 397 pc_q35_2_4_machine_options(m); 398 m->no_floppy = 0; 399 m->no_tco = 1; 400 m->alias = NULL; 401 SET_MACHINE_COMPAT(m, PC_COMPAT_2_3); 402 } 403 404 DEFINE_Q35_MACHINE(v2_3, "pc-q35-2.3", pc_compat_2_3, 405 pc_q35_2_3_machine_options); 406 407 408 static void pc_q35_2_2_machine_options(MachineClass *m) 409 { 410 pc_q35_2_3_machine_options(m); 411 SET_MACHINE_COMPAT(m, PC_COMPAT_2_2); 412 } 413 414 DEFINE_Q35_MACHINE(v2_2, "pc-q35-2.2", pc_compat_2_2, 415 pc_q35_2_2_machine_options); 416 417 418 static void pc_q35_2_1_machine_options(MachineClass *m) 419 { 420 pc_q35_2_2_machine_options(m); 421 m->default_display = NULL; 422 SET_MACHINE_COMPAT(m, PC_COMPAT_2_1); 423 } 424 425 DEFINE_Q35_MACHINE(v2_1, "pc-q35-2.1", pc_compat_2_1, 426 pc_q35_2_1_machine_options); 427 428 429 static void pc_q35_2_0_machine_options(MachineClass *m) 430 { 431 pc_q35_2_1_machine_options(m); 432 SET_MACHINE_COMPAT(m, PC_COMPAT_2_0); 433 } 434 435 DEFINE_Q35_MACHINE(v2_0, "pc-q35-2.0", pc_compat_2_0, 436 pc_q35_2_0_machine_options); 437 438 439 static void pc_q35_1_7_machine_options(MachineClass *m) 440 { 441 pc_q35_2_0_machine_options(m); 442 m->default_machine_opts = NULL; 443 SET_MACHINE_COMPAT(m, PC_COMPAT_1_7); 444 } 445 446 DEFINE_Q35_MACHINE(v1_7, "pc-q35-1.7", pc_compat_1_7, 447 pc_q35_1_7_machine_options); 448 449 450 static void pc_q35_1_6_machine_options(MachineClass *m) 451 { 452 pc_q35_machine_options(m); 453 SET_MACHINE_COMPAT(m, PC_COMPAT_1_6); 454 } 455 456 DEFINE_Q35_MACHINE(v1_6, "pc-q35-1.6", pc_compat_1_6, 457 pc_q35_1_6_machine_options); 458 459 460 static void pc_q35_1_5_machine_options(MachineClass *m) 461 { 462 pc_q35_1_6_machine_options(m); 463 SET_MACHINE_COMPAT(m, PC_COMPAT_1_5); 464 } 465 466 DEFINE_Q35_MACHINE(v1_5, "pc-q35-1.5", pc_compat_1_5, 467 pc_q35_1_5_machine_options); 468 469 470 static void pc_q35_1_4_machine_options(MachineClass *m) 471 { 472 pc_q35_1_5_machine_options(m); 473 m->hot_add_cpu = NULL; 474 SET_MACHINE_COMPAT(m, PC_COMPAT_1_4); 475 } 476 477 DEFINE_Q35_MACHINE(v1_4, "pc-q35-1.4", pc_compat_1_4, 478 pc_q35_1_4_machine_options); 479