1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/loader.h" 33 #include "sysemu/arch_init.h" 34 #include "hw/i2c/smbus.h" 35 #include "hw/boards.h" 36 #include "hw/timer/mc146818rtc.h" 37 #include "hw/xen/xen.h" 38 #include "sysemu/kvm.h" 39 #include "hw/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "exec/address-spaces.h" 42 #include "hw/i386/ich9.h" 43 #include "hw/smbios/smbios.h" 44 #include "hw/ide/pci.h" 45 #include "hw/ide/ahci.h" 46 #include "hw/usb.h" 47 #include "qemu/error-report.h" 48 #include "migration/migration.h" 49 50 /* ICH9 AHCI has 6 ports */ 51 #define MAX_SATA_PORTS 6 52 53 /* PC hardware initialisation */ 54 static void pc_q35_init(MachineState *machine) 55 { 56 PCMachineState *pcms = PC_MACHINE(machine); 57 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 58 Q35PCIHost *q35_host; 59 PCIHostState *phb; 60 PCIBus *host_bus; 61 PCIDevice *lpc; 62 BusState *idebus[MAX_SATA_PORTS]; 63 ISADevice *rtc_state; 64 MemoryRegion *pci_memory; 65 MemoryRegion *rom_memory; 66 MemoryRegion *ram_memory; 67 GSIState *gsi_state; 68 ISABus *isa_bus; 69 qemu_irq *gsi; 70 qemu_irq *i8259; 71 int i; 72 ICH9LPCState *ich9_lpc; 73 PCIDevice *ahci; 74 ram_addr_t lowmem; 75 DriveInfo *hd[MAX_SATA_PORTS]; 76 MachineClass *mc = MACHINE_GET_CLASS(machine); 77 78 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 79 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 80 * also known as MMCFG). 81 * If it doesn't, we need to split it in chunks below and above 4G. 82 * In any case, try to make sure that guest addresses aligned at 83 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 84 */ 85 if (machine->ram_size >= 0xb0000000) { 86 lowmem = 0x80000000; 87 } else { 88 lowmem = 0xb0000000; 89 } 90 91 /* Handle the machine opt max-ram-below-4g. It is basically doing 92 * min(qemu limit, user limit). 93 */ 94 if (lowmem > pcms->max_ram_below_4g) { 95 lowmem = pcms->max_ram_below_4g; 96 if (machine->ram_size - lowmem > lowmem && 97 lowmem & ((1ULL << 30) - 1)) { 98 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 99 ") not a multiple of 1G; possible bad performance.", 100 pcms->max_ram_below_4g); 101 } 102 } 103 104 if (machine->ram_size >= lowmem) { 105 pcms->above_4g_mem_size = machine->ram_size - lowmem; 106 pcms->below_4g_mem_size = lowmem; 107 } else { 108 pcms->above_4g_mem_size = 0; 109 pcms->below_4g_mem_size = machine->ram_size; 110 } 111 112 if (xen_enabled()) { 113 xen_hvm_init(pcms, &ram_memory); 114 } 115 116 pc_cpus_init(pcms); 117 118 kvmclock_create(); 119 120 /* pci enabled */ 121 if (pcmc->pci_enabled) { 122 pci_memory = g_new(MemoryRegion, 1); 123 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 124 rom_memory = pci_memory; 125 } else { 126 pci_memory = NULL; 127 rom_memory = get_system_memory(); 128 } 129 130 pc_guest_info_init(pcms); 131 132 if (pcmc->smbios_defaults) { 133 /* These values are guest ABI, do not change */ 134 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 135 mc->name, pcmc->smbios_legacy_mode, 136 pcmc->smbios_uuid_encoded, 137 SMBIOS_ENTRY_POINT_21); 138 } 139 140 /* allocate ram and load rom/bios */ 141 if (!xen_enabled()) { 142 pc_memory_init(pcms, get_system_memory(), 143 rom_memory, &ram_memory); 144 } 145 146 /* irq lines */ 147 gsi_state = g_malloc0(sizeof(*gsi_state)); 148 if (kvm_irqchip_in_kernel()) { 149 kvm_pc_setup_irq_routing(pcmc->pci_enabled); 150 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 151 GSI_NUM_PINS); 152 } else { 153 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 154 } 155 156 /* create pci host bus */ 157 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 158 159 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 160 q35_host->mch.ram_memory = ram_memory; 161 q35_host->mch.pci_address_space = pci_memory; 162 q35_host->mch.system_memory = get_system_memory(); 163 q35_host->mch.address_space_io = get_system_io(); 164 q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size; 165 q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size; 166 /* pci */ 167 qdev_init_nofail(DEVICE(q35_host)); 168 phb = PCI_HOST_BRIDGE(q35_host); 169 host_bus = phb->bus; 170 pcms->bus = phb->bus; 171 /* create ISA bus */ 172 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 173 ICH9_LPC_FUNC), true, 174 TYPE_ICH9_LPC_DEVICE); 175 176 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 177 TYPE_HOTPLUG_HANDLER, 178 (Object **)&pcms->acpi_dev, 179 object_property_allow_set_link, 180 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 181 object_property_set_link(OBJECT(machine), OBJECT(lpc), 182 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 183 184 ich9_lpc = ICH9_LPC_DEVICE(lpc); 185 ich9_lpc->pic = gsi; 186 ich9_lpc->ioapic = gsi_state->ioapic_irq; 187 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 188 ICH9_LPC_NB_PIRQS); 189 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 190 isa_bus = ich9_lpc->isa_bus; 191 192 /*end early*/ 193 isa_bus_irqs(isa_bus, gsi); 194 195 if (kvm_irqchip_in_kernel()) { 196 i8259 = kvm_i8259_init(isa_bus); 197 } else if (xen_enabled()) { 198 i8259 = xen_interrupt_controller_init(); 199 } else { 200 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 201 } 202 203 for (i = 0; i < ISA_NUM_IRQS; i++) { 204 gsi_state->i8259_irq[i] = i8259[i]; 205 } 206 if (pcmc->pci_enabled) { 207 ioapic_init_gsi(gsi_state, "q35"); 208 } 209 210 pc_register_ferr_irq(gsi[13]); 211 212 assert(pcms->vmport != ON_OFF_AUTO__MAX); 213 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 214 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 215 } 216 217 /* init basic PC hardware */ 218 pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy, 219 (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104); 220 221 /* connect pm stuff to lpc */ 222 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); 223 224 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 225 ahci = pci_create_simple_multifunction(host_bus, 226 PCI_DEVFN(ICH9_SATA1_DEV, 227 ICH9_SATA1_FUNC), 228 true, "ich9-ahci"); 229 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 230 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 231 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 232 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 233 ahci_ide_create_devs(ahci, hd); 234 235 if (usb_enabled()) { 236 /* Should we create 6 UHCI according to ich9 spec? */ 237 ehci_create_ich9_with_companions(host_bus, 0x1d); 238 } 239 240 /* TODO: Populate SPD eeprom data. */ 241 smbus_eeprom_init(ich9_smb_init(host_bus, 242 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 243 0xb100), 244 8, NULL, 0); 245 246 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 247 248 /* the rest devices to which pci devfn is automatically assigned */ 249 pc_vga_init(isa_bus, host_bus); 250 pc_nic_init(isa_bus, host_bus); 251 if (pcmc->pci_enabled) { 252 pc_pci_device_init(host_bus); 253 } 254 } 255 256 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 257 static void pc_init_##suffix(MachineState *machine) \ 258 { \ 259 void (*compat)(MachineState *m) = (compatfn); \ 260 if (compat) { \ 261 compat(machine); \ 262 } \ 263 pc_q35_init(machine); \ 264 } \ 265 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 266 267 268 static void pc_q35_machine_options(MachineClass *m) 269 { 270 m->family = "pc_q35"; 271 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 272 m->hot_add_cpu = pc_hot_add_cpu; 273 m->units_per_default_bus = 1; 274 m->default_machine_opts = "firmware=bios-256k.bin"; 275 m->default_display = "std"; 276 m->no_floppy = 1; 277 } 278 279 static void pc_q35_2_6_machine_options(MachineClass *m) 280 { 281 pc_q35_machine_options(m); 282 m->alias = "q35"; 283 } 284 285 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 286 pc_q35_2_6_machine_options); 287 288 static void pc_q35_2_5_machine_options(MachineClass *m) 289 { 290 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 291 pc_q35_2_6_machine_options(m); 292 m->alias = NULL; 293 pcmc->save_tsc_khz = false; 294 SET_MACHINE_COMPAT(m, PC_COMPAT_2_5); 295 } 296 297 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 298 pc_q35_2_5_machine_options); 299 300 static void pc_q35_2_4_machine_options(MachineClass *m) 301 { 302 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 303 pc_q35_2_5_machine_options(m); 304 m->hw_version = "2.4.0"; 305 pcmc->broken_reserved_end = true; 306 SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); 307 } 308 309 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 310 pc_q35_2_4_machine_options); 311