1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/char/parallel-isa.h" 34 #include "hw/loader.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/kvm.h" 39 #include "hw/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "hw/pci/pcie_port.h" 42 #include "hw/qdev-properties.h" 43 #include "hw/i386/x86.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/firmware/smbios.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci.h" 51 #include "hw/intc/ioapic.h" 52 #include "hw/southbridge/ich9.h" 53 #include "hw/usb.h" 54 #include "hw/usb/hcd-uhci.h" 55 #include "qapi/error.h" 56 #include "qemu/error-report.h" 57 #include "sysemu/numa.h" 58 #include "hw/hyperv/vmbus-bridge.h" 59 #include "hw/mem/nvdimm.h" 60 #include "hw/i386/acpi-build.h" 61 #include "target/i386/cpu.h" 62 63 /* ICH9 AHCI has 6 ports */ 64 #define MAX_SATA_PORTS 6 65 66 struct ehci_companions { 67 const char *name; 68 int func; 69 int port; 70 }; 71 72 static const struct ehci_companions ich9_1d[] = { 73 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 74 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 75 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 76 }; 77 78 static const struct ehci_companions ich9_1a[] = { 79 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 80 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 81 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 82 }; 83 84 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 85 { 86 const struct ehci_companions *comp; 87 PCIDevice *ehci, *uhci; 88 BusState *usbbus; 89 const char *name; 90 int i; 91 92 switch (slot) { 93 case 0x1d: 94 name = "ich9-usb-ehci1"; 95 comp = ich9_1d; 96 break; 97 case 0x1a: 98 name = "ich9-usb-ehci2"; 99 comp = ich9_1a; 100 break; 101 default: 102 return -1; 103 } 104 105 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 106 pci_realize_and_unref(ehci, bus, &error_fatal); 107 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 108 109 for (i = 0; i < 3; i++) { 110 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 111 comp[i].name); 112 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 113 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 114 pci_realize_and_unref(uhci, bus, &error_fatal); 115 } 116 return 0; 117 } 118 119 /* PC hardware initialisation */ 120 static void pc_q35_init(MachineState *machine) 121 { 122 PCMachineState *pcms = PC_MACHINE(machine); 123 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 124 X86MachineState *x86ms = X86_MACHINE(machine); 125 Object *phb; 126 PCIBus *host_bus; 127 PCIDevice *lpc; 128 DeviceState *lpc_dev; 129 BusState *idebus[MAX_SATA_PORTS]; 130 ISADevice *rtc_state; 131 MemoryRegion *system_memory = get_system_memory(); 132 MemoryRegion *system_io = get_system_io(); 133 MemoryRegion *pci_memory; 134 MemoryRegion *rom_memory; 135 GSIState *gsi_state; 136 ISABus *isa_bus; 137 int i; 138 PCIDevice *ahci; 139 ram_addr_t lowmem; 140 DriveInfo *hd[MAX_SATA_PORTS]; 141 MachineClass *mc = MACHINE_GET_CLASS(machine); 142 bool acpi_pcihp; 143 bool keep_pci_slot_hpc; 144 uint64_t pci_hole64_size = 0; 145 146 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 147 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 148 * also known as MMCFG). 149 * If it doesn't, we need to split it in chunks below and above 4G. 150 * In any case, try to make sure that guest addresses aligned at 151 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 152 */ 153 if (machine->ram_size >= 0xb0000000) { 154 lowmem = 0x80000000; 155 } else { 156 lowmem = 0xb0000000; 157 } 158 159 /* Handle the machine opt max-ram-below-4g. It is basically doing 160 * min(qemu limit, user limit). 161 */ 162 if (!pcms->max_ram_below_4g) { 163 pcms->max_ram_below_4g = 4 * GiB; 164 } 165 if (lowmem > pcms->max_ram_below_4g) { 166 lowmem = pcms->max_ram_below_4g; 167 if (machine->ram_size - lowmem > lowmem && 168 lowmem & (1 * GiB - 1)) { 169 warn_report("There is possibly poor performance as the ram size " 170 " (0x%" PRIx64 ") is more then twice the size of" 171 " max-ram-below-4g (%"PRIu64") and" 172 " max-ram-below-4g is not a multiple of 1G.", 173 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 174 } 175 } 176 177 if (machine->ram_size >= lowmem) { 178 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 179 x86ms->below_4g_mem_size = lowmem; 180 } else { 181 x86ms->above_4g_mem_size = 0; 182 x86ms->below_4g_mem_size = machine->ram_size; 183 } 184 185 pc_machine_init_sgx_epc(pcms); 186 x86_cpus_init(x86ms, pcmc->default_cpu_version); 187 188 kvmclock_create(pcmc->kvmclock_create_always); 189 190 /* pci enabled */ 191 if (pcmc->pci_enabled) { 192 pci_memory = g_new(MemoryRegion, 1); 193 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 194 rom_memory = pci_memory; 195 } else { 196 pci_memory = NULL; 197 rom_memory = system_memory; 198 } 199 200 pc_guest_info_init(pcms); 201 202 if (pcmc->smbios_defaults) { 203 /* These values are guest ABI, do not change */ 204 smbios_set_defaults("QEMU", mc->desc, 205 mc->name, pcmc->smbios_legacy_mode, 206 pcmc->smbios_uuid_encoded, 207 pcms->smbios_entry_point_type); 208 } 209 210 /* create pci host bus */ 211 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 212 213 if (pcmc->pci_enabled) { 214 pci_hole64_size = object_property_get_uint(phb, 215 PCI_HOST_PROP_PCI_HOLE64_SIZE, 216 &error_abort); 217 } 218 219 /* allocate ram and load rom/bios */ 220 pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); 221 222 object_property_add_child(OBJECT(machine), "q35", phb); 223 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 224 OBJECT(machine->ram), NULL); 225 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 226 OBJECT(pci_memory), NULL); 227 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 228 OBJECT(system_memory), NULL); 229 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 230 OBJECT(system_io), NULL); 231 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 232 x86ms->below_4g_mem_size, NULL); 233 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 234 x86ms->above_4g_mem_size, NULL); 235 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 236 pcms->default_bus_bypass_iommu, NULL); 237 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 238 239 /* pci */ 240 host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 241 pcms->bus = host_bus; 242 243 /* create ISA bus */ 244 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 245 TYPE_ICH9_LPC_DEVICE); 246 qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", 247 x86_machine_is_smm_enabled(x86ms)); 248 pci_realize_and_unref(lpc, host_bus, &error_fatal); 249 250 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 251 252 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 253 TYPE_HOTPLUG_HANDLER, 254 (Object **)&x86ms->acpi_dev, 255 object_property_allow_set_link, 256 OBJ_PROP_LINK_STRONG); 257 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 258 OBJECT(lpc), &error_abort); 259 260 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 261 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 262 NULL); 263 264 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 265 "x-keep-pci-slot-hpc", 266 NULL); 267 268 if (!keep_pci_slot_hpc && acpi_pcihp) { 269 object_register_sugar_prop(TYPE_PCIE_SLOT, 270 "x-do-not-expose-native-hotplug-cap", 271 "true", true); 272 } 273 274 /* irq lines */ 275 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 276 277 lpc_dev = DEVICE(lpc); 278 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 279 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 280 } 281 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 282 283 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 284 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 285 } 286 287 if (pcmc->pci_enabled) { 288 ioapic_init_gsi(gsi_state, "q35"); 289 } 290 291 if (tcg_enabled()) { 292 x86_register_ferr_irq(x86ms->gsi[13]); 293 } 294 295 assert(pcms->vmport != ON_OFF_AUTO__MAX); 296 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 297 pcms->vmport = ON_OFF_AUTO_ON; 298 } 299 300 /* init basic PC hardware */ 301 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 302 0xff0104); 303 304 if (pcms->sata_enabled) { 305 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 306 ahci = pci_create_simple_multifunction(host_bus, 307 PCI_DEVFN(ICH9_SATA1_DEV, 308 ICH9_SATA1_FUNC), 309 "ich9-ahci"); 310 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 311 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 312 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 313 ide_drive_get(hd, ahci_get_num_ports(ahci)); 314 ahci_ide_create_devs(ahci, hd); 315 } else { 316 idebus[0] = idebus[1] = NULL; 317 } 318 319 if (machine_usb(machine)) { 320 /* Should we create 6 UHCI according to ich9 spec? */ 321 ehci_create_ich9_with_companions(host_bus, 0x1d); 322 } 323 324 if (pcms->smbus_enabled) { 325 PCIDevice *smb; 326 327 /* TODO: Populate SPD eeprom data. */ 328 smb = pci_create_simple_multifunction(host_bus, 329 PCI_DEVFN(ICH9_SMB_DEV, 330 ICH9_SMB_FUNC), 331 TYPE_ICH9_SMB_DEVICE); 332 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 333 334 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 335 } 336 337 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 338 339 /* the rest devices to which pci devfn is automatically assigned */ 340 pc_vga_init(isa_bus, host_bus); 341 pc_nic_init(pcmc, isa_bus, host_bus); 342 343 if (machine->nvdimms_state->is_enabled) { 344 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 345 x86_nvdimm_acpi_dsmio, 346 x86ms->fw_cfg, OBJECT(pcms)); 347 } 348 } 349 350 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 351 static void pc_init_##suffix(MachineState *machine) \ 352 { \ 353 void (*compat)(MachineState *m) = (compatfn); \ 354 if (compat) { \ 355 compat(machine); \ 356 } \ 357 pc_q35_init(machine); \ 358 } \ 359 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 360 361 362 static void pc_q35_machine_options(MachineClass *m) 363 { 364 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 365 pcmc->pci_root_uid = 0; 366 pcmc->default_cpu_version = 1; 367 368 m->family = "pc_q35"; 369 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 370 m->units_per_default_bus = 1; 371 m->default_machine_opts = "firmware=bios-256k.bin"; 372 m->default_display = "std"; 373 m->default_nic = "e1000e"; 374 m->default_kernel_irqchip_split = false; 375 m->no_floppy = 1; 376 m->max_cpus = 1024; 377 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 378 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 379 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 380 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 381 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 382 } 383 384 static void pc_q35_8_2_machine_options(MachineClass *m) 385 { 386 pc_q35_machine_options(m); 387 m->alias = "q35"; 388 } 389 390 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 391 pc_q35_8_2_machine_options); 392 393 static void pc_q35_8_1_machine_options(MachineClass *m) 394 { 395 pc_q35_8_2_machine_options(m); 396 m->alias = NULL; 397 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 398 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 399 } 400 401 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 402 pc_q35_8_1_machine_options); 403 404 static void pc_q35_8_0_machine_options(MachineClass *m) 405 { 406 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 407 408 pc_q35_8_1_machine_options(m); 409 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 410 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 411 412 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 413 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 414 m->max_cpus = 288; 415 } 416 417 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 418 pc_q35_8_0_machine_options); 419 420 static void pc_q35_7_2_machine_options(MachineClass *m) 421 { 422 pc_q35_8_0_machine_options(m); 423 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 424 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 425 } 426 427 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 428 pc_q35_7_2_machine_options); 429 430 static void pc_q35_7_1_machine_options(MachineClass *m) 431 { 432 pc_q35_7_2_machine_options(m); 433 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 434 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 435 } 436 437 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 438 pc_q35_7_1_machine_options); 439 440 static void pc_q35_7_0_machine_options(MachineClass *m) 441 { 442 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 443 pc_q35_7_1_machine_options(m); 444 pcmc->enforce_amd_1tb_hole = false; 445 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 446 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 447 } 448 449 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 450 pc_q35_7_0_machine_options); 451 452 static void pc_q35_6_2_machine_options(MachineClass *m) 453 { 454 pc_q35_7_0_machine_options(m); 455 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 456 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 457 } 458 459 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 460 pc_q35_6_2_machine_options); 461 462 static void pc_q35_6_1_machine_options(MachineClass *m) 463 { 464 pc_q35_6_2_machine_options(m); 465 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 466 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 467 m->smp_props.prefer_sockets = true; 468 } 469 470 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 471 pc_q35_6_1_machine_options); 472 473 static void pc_q35_6_0_machine_options(MachineClass *m) 474 { 475 pc_q35_6_1_machine_options(m); 476 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 477 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 478 } 479 480 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 481 pc_q35_6_0_machine_options); 482 483 static void pc_q35_5_2_machine_options(MachineClass *m) 484 { 485 pc_q35_6_0_machine_options(m); 486 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 487 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 488 } 489 490 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 491 pc_q35_5_2_machine_options); 492 493 static void pc_q35_5_1_machine_options(MachineClass *m) 494 { 495 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 496 497 pc_q35_5_2_machine_options(m); 498 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 499 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 500 pcmc->kvmclock_create_always = false; 501 pcmc->pci_root_uid = 1; 502 } 503 504 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 505 pc_q35_5_1_machine_options); 506 507 static void pc_q35_5_0_machine_options(MachineClass *m) 508 { 509 pc_q35_5_1_machine_options(m); 510 m->numa_mem_supported = true; 511 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 512 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 513 m->auto_enable_numa_with_memdev = false; 514 } 515 516 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 517 pc_q35_5_0_machine_options); 518 519 static void pc_q35_4_2_machine_options(MachineClass *m) 520 { 521 pc_q35_5_0_machine_options(m); 522 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 523 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 524 } 525 526 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 527 pc_q35_4_2_machine_options); 528 529 static void pc_q35_4_1_machine_options(MachineClass *m) 530 { 531 pc_q35_4_2_machine_options(m); 532 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 533 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 534 } 535 536 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 537 pc_q35_4_1_machine_options); 538 539 static void pc_q35_4_0_1_machine_options(MachineClass *m) 540 { 541 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 542 pc_q35_4_1_machine_options(m); 543 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 544 /* 545 * This is the default machine for the 4.0-stable branch. It is basically 546 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 547 * 4.0 compat props. 548 */ 549 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 550 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 551 } 552 553 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 554 pc_q35_4_0_1_machine_options); 555 556 static void pc_q35_4_0_machine_options(MachineClass *m) 557 { 558 pc_q35_4_0_1_machine_options(m); 559 m->default_kernel_irqchip_split = true; 560 /* Compat props are applied by the 4.0.1 machine */ 561 } 562 563 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 564 pc_q35_4_0_machine_options); 565 566 static void pc_q35_3_1_machine_options(MachineClass *m) 567 { 568 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 569 570 pc_q35_4_0_machine_options(m); 571 m->default_kernel_irqchip_split = false; 572 m->smbus_no_migration_support = true; 573 pcmc->pvh_enabled = false; 574 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 575 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 576 } 577 578 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 579 pc_q35_3_1_machine_options); 580 581 static void pc_q35_3_0_machine_options(MachineClass *m) 582 { 583 pc_q35_3_1_machine_options(m); 584 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 585 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 586 } 587 588 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 589 pc_q35_3_0_machine_options); 590 591 static void pc_q35_2_12_machine_options(MachineClass *m) 592 { 593 pc_q35_3_0_machine_options(m); 594 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 595 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 596 } 597 598 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 599 pc_q35_2_12_machine_options); 600 601 static void pc_q35_2_11_machine_options(MachineClass *m) 602 { 603 pc_q35_2_12_machine_options(m); 604 m->default_nic = "e1000"; 605 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 606 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 607 } 608 609 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 610 pc_q35_2_11_machine_options); 611 612 static void pc_q35_2_10_machine_options(MachineClass *m) 613 { 614 pc_q35_2_11_machine_options(m); 615 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 616 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 617 m->auto_enable_numa_with_memhp = false; 618 } 619 620 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 621 pc_q35_2_10_machine_options); 622 623 static void pc_q35_2_9_machine_options(MachineClass *m) 624 { 625 pc_q35_2_10_machine_options(m); 626 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 627 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 628 } 629 630 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 631 pc_q35_2_9_machine_options); 632 633 static void pc_q35_2_8_machine_options(MachineClass *m) 634 { 635 pc_q35_2_9_machine_options(m); 636 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 637 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 638 } 639 640 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 641 pc_q35_2_8_machine_options); 642 643 static void pc_q35_2_7_machine_options(MachineClass *m) 644 { 645 pc_q35_2_8_machine_options(m); 646 m->max_cpus = 255; 647 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 648 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 649 } 650 651 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 652 pc_q35_2_7_machine_options); 653 654 static void pc_q35_2_6_machine_options(MachineClass *m) 655 { 656 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 657 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 658 659 pc_q35_2_7_machine_options(m); 660 pcmc->legacy_cpu_hotplug = true; 661 x86mc->fwcfg_dma_enabled = false; 662 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 663 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 664 } 665 666 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 667 pc_q35_2_6_machine_options); 668 669 static void pc_q35_2_5_machine_options(MachineClass *m) 670 { 671 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 672 673 pc_q35_2_6_machine_options(m); 674 x86mc->save_tsc_khz = false; 675 m->legacy_fw_cfg_order = 1; 676 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 677 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 678 } 679 680 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 681 pc_q35_2_5_machine_options); 682 683 static void pc_q35_2_4_machine_options(MachineClass *m) 684 { 685 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 686 687 pc_q35_2_5_machine_options(m); 688 m->hw_version = "2.4.0"; 689 pcmc->broken_reserved_end = true; 690 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 691 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 692 } 693 694 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 695 pc_q35_2_4_machine_options); 696