xref: /qemu/hw/i386/pc_q35.c (revision 83ecdb18)
1 /*
2  * Q35 chipset based pc system emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2009, 2010
6  *               Isaku Yamahata <yamahata at valinux co jp>
7  *               VA Linux Systems Japan K.K.
8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9  *
10  * This is based on pc.c, but heavily modified.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a copy
13  * of this software and associated documentation files (the "Software"), to deal
14  * in the Software without restriction, including without limitation the rights
15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16  * copies of the Software, and to permit persons to whom the Software is
17  * furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice shall be included in
20  * all copies or substantial portions of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28  * THE SOFTWARE.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/loader.h"
34 #include "hw/i2c/smbus_eeprom.h"
35 #include "hw/rtc/mc146818rtc.h"
36 #include "sysemu/kvm.h"
37 #include "hw/kvm/clock.h"
38 #include "hw/pci-host/q35.h"
39 #include "hw/pci/pcie_port.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/i386/x86.h"
42 #include "hw/i386/pc.h"
43 #include "hw/i386/amd_iommu.h"
44 #include "hw/i386/intel_iommu.h"
45 #include "hw/display/ramfb.h"
46 #include "hw/firmware/smbios.h"
47 #include "hw/ide/pci.h"
48 #include "hw/ide/ahci.h"
49 #include "hw/intc/ioapic.h"
50 #include "hw/southbridge/ich9.h"
51 #include "hw/usb.h"
52 #include "hw/usb/hcd-uhci.h"
53 #include "qapi/error.h"
54 #include "qemu/error-report.h"
55 #include "sysemu/numa.h"
56 #include "hw/hyperv/vmbus-bridge.h"
57 #include "hw/mem/nvdimm.h"
58 #include "hw/i386/acpi-build.h"
59 
60 /* ICH9 AHCI has 6 ports */
61 #define MAX_SATA_PORTS     6
62 
63 struct ehci_companions {
64     const char *name;
65     int func;
66     int port;
67 };
68 
69 static const struct ehci_companions ich9_1d[] = {
70     { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
71     { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
72     { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
73 };
74 
75 static const struct ehci_companions ich9_1a[] = {
76     { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
77     { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
78     { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
79 };
80 
81 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
82 {
83     const struct ehci_companions *comp;
84     PCIDevice *ehci, *uhci;
85     BusState *usbbus;
86     const char *name;
87     int i;
88 
89     switch (slot) {
90     case 0x1d:
91         name = "ich9-usb-ehci1";
92         comp = ich9_1d;
93         break;
94     case 0x1a:
95         name = "ich9-usb-ehci2";
96         comp = ich9_1a;
97         break;
98     default:
99         return -1;
100     }
101 
102     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
103     pci_realize_and_unref(ehci, bus, &error_fatal);
104     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
105 
106     for (i = 0; i < 3; i++) {
107         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
108                                      comp[i].name);
109         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
110         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
111         pci_realize_and_unref(uhci, bus, &error_fatal);
112     }
113     return 0;
114 }
115 
116 /* PC hardware initialisation */
117 static void pc_q35_init(MachineState *machine)
118 {
119     PCMachineState *pcms = PC_MACHINE(machine);
120     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
121     X86MachineState *x86ms = X86_MACHINE(machine);
122     Q35PCIHost *q35_host;
123     PCIHostState *phb;
124     PCIBus *host_bus;
125     PCIDevice *lpc;
126     DeviceState *lpc_dev;
127     BusState *idebus[MAX_SATA_PORTS];
128     ISADevice *rtc_state;
129     MemoryRegion *system_io = get_system_io();
130     MemoryRegion *pci_memory;
131     MemoryRegion *rom_memory;
132     MemoryRegion *ram_memory;
133     GSIState *gsi_state;
134     ISABus *isa_bus;
135     int i;
136     PCIDevice *ahci;
137     ram_addr_t lowmem;
138     DriveInfo *hd[MAX_SATA_PORTS];
139     MachineClass *mc = MACHINE_GET_CLASS(machine);
140     bool acpi_pcihp;
141     bool keep_pci_slot_hpc;
142     uint64_t pci_hole64_size = 0;
143 
144     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
145      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
146      * also known as MMCFG).
147      * If it doesn't, we need to split it in chunks below and above 4G.
148      * In any case, try to make sure that guest addresses aligned at
149      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
150      */
151     if (machine->ram_size >= 0xb0000000) {
152         lowmem = 0x80000000;
153     } else {
154         lowmem = 0xb0000000;
155     }
156 
157     /* Handle the machine opt max-ram-below-4g.  It is basically doing
158      * min(qemu limit, user limit).
159      */
160     if (!pcms->max_ram_below_4g) {
161         pcms->max_ram_below_4g = 4 * GiB;
162     }
163     if (lowmem > pcms->max_ram_below_4g) {
164         lowmem = pcms->max_ram_below_4g;
165         if (machine->ram_size - lowmem > lowmem &&
166             lowmem & (1 * GiB - 1)) {
167             warn_report("There is possibly poor performance as the ram size "
168                         " (0x%" PRIx64 ") is more then twice the size of"
169                         " max-ram-below-4g (%"PRIu64") and"
170                         " max-ram-below-4g is not a multiple of 1G.",
171                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
172         }
173     }
174 
175     if (machine->ram_size >= lowmem) {
176         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
177         x86ms->below_4g_mem_size = lowmem;
178     } else {
179         x86ms->above_4g_mem_size = 0;
180         x86ms->below_4g_mem_size = machine->ram_size;
181     }
182 
183     pc_machine_init_sgx_epc(pcms);
184     x86_cpus_init(x86ms, pcmc->default_cpu_version);
185 
186     kvmclock_create(pcmc->kvmclock_create_always);
187 
188     /* pci enabled */
189     if (pcmc->pci_enabled) {
190         pci_memory = g_new(MemoryRegion, 1);
191         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
192         rom_memory = pci_memory;
193     } else {
194         pci_memory = NULL;
195         rom_memory = get_system_memory();
196     }
197 
198     pc_guest_info_init(pcms);
199 
200     if (pcmc->smbios_defaults) {
201         /* These values are guest ABI, do not change */
202         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
203                             mc->name, pcmc->smbios_legacy_mode,
204                             pcmc->smbios_uuid_encoded,
205                             pcms->smbios_entry_point_type);
206     }
207 
208     /* create pci host bus */
209     q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
210 
211     if (pcmc->pci_enabled) {
212         pci_hole64_size = object_property_get_uint(OBJECT(q35_host),
213                                                    PCI_HOST_PROP_PCI_HOLE64_SIZE,
214                                                    &error_abort);
215     }
216 
217     /* allocate ram and load rom/bios */
218     pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory,
219                    pci_hole64_size);
220 
221     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
222     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
223                              OBJECT(ram_memory), NULL);
224     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
225                              OBJECT(pci_memory), NULL);
226     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
227                              OBJECT(get_system_memory()), NULL);
228     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
229                              OBJECT(system_io), NULL);
230     object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
231                             x86ms->below_4g_mem_size, NULL);
232     object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
233                             x86ms->above_4g_mem_size, NULL);
234     /* pci */
235     sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
236     phb = PCI_HOST_BRIDGE(q35_host);
237     host_bus = phb->bus;
238     /* create ISA bus */
239     lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,
240                                 TYPE_ICH9_LPC_DEVICE);
241     qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
242                       x86_machine_is_smm_enabled(x86ms));
243     pci_realize_and_unref(lpc, host_bus, &error_fatal);
244 
245     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
246                              TYPE_HOTPLUG_HANDLER,
247                              (Object **)&x86ms->acpi_dev,
248                              object_property_allow_set_link,
249                              OBJ_PROP_LINK_STRONG);
250     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
251                              OBJECT(lpc), &error_abort);
252 
253     acpi_pcihp = object_property_get_bool(OBJECT(lpc),
254                                           ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
255                                           NULL);
256 
257     keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
258                                                  "x-keep-pci-slot-hpc",
259                                                  NULL);
260 
261     if (!keep_pci_slot_hpc && acpi_pcihp) {
262         object_register_sugar_prop(TYPE_PCIE_SLOT,
263                                    "x-do-not-expose-native-hotplug-cap",
264                                    "true", true);
265     }
266 
267     /* irq lines */
268     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
269 
270     lpc_dev = DEVICE(lpc);
271     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
272         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
273     }
274     isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
275 
276     if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
277         pc_i8259_create(isa_bus, gsi_state->i8259_irq);
278     }
279 
280     if (pcmc->pci_enabled) {
281         ioapic_init_gsi(gsi_state, "q35");
282     }
283 
284     if (tcg_enabled()) {
285         x86_register_ferr_irq(x86ms->gsi[13]);
286     }
287 
288     assert(pcms->vmport != ON_OFF_AUTO__MAX);
289     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
290         pcms->vmport = ON_OFF_AUTO_ON;
291     }
292 
293     /* init basic PC hardware */
294     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
295                          0xff0104);
296 
297     if (pcms->sata_enabled) {
298         /* ahci and SATA device, for q35 1 ahci controller is built-in */
299         ahci = pci_create_simple_multifunction(host_bus,
300                                                PCI_DEVFN(ICH9_SATA1_DEV,
301                                                          ICH9_SATA1_FUNC),
302                                                true, "ich9-ahci");
303         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
304         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
305         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
306         ide_drive_get(hd, ahci_get_num_ports(ahci));
307         ahci_ide_create_devs(ahci, hd);
308     } else {
309         idebus[0] = idebus[1] = NULL;
310     }
311 
312     if (machine_usb(machine)) {
313         /* Should we create 6 UHCI according to ich9 spec? */
314         ehci_create_ich9_with_companions(host_bus, 0x1d);
315     }
316 
317     if (pcms->smbus_enabled) {
318         PCIDevice *smb;
319 
320         /* TODO: Populate SPD eeprom data.  */
321         smb = pci_create_simple_multifunction(host_bus,
322                                               PCI_DEVFN(ICH9_SMB_DEV,
323                                                         ICH9_SMB_FUNC),
324                                               true, TYPE_ICH9_SMB_DEVICE);
325         pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
326 
327         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
328     }
329 
330     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
331 
332     /* the rest devices to which pci devfn is automatically assigned */
333     pc_vga_init(isa_bus, host_bus);
334     pc_nic_init(pcmc, isa_bus, host_bus);
335 
336     if (machine->nvdimms_state->is_enabled) {
337         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
338                                x86_nvdimm_acpi_dsmio,
339                                x86ms->fw_cfg, OBJECT(pcms));
340     }
341 }
342 
343 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
344     static void pc_init_##suffix(MachineState *machine) \
345     { \
346         void (*compat)(MachineState *m) = (compatfn); \
347         if (compat) { \
348             compat(machine); \
349         } \
350         pc_q35_init(machine); \
351     } \
352     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
353 
354 
355 static void pc_q35_machine_options(MachineClass *m)
356 {
357     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
358     pcmc->default_nic_model = "e1000e";
359     pcmc->pci_root_uid = 0;
360     pcmc->default_cpu_version = 1;
361 
362     m->family = "pc_q35";
363     m->desc = "Standard PC (Q35 + ICH9, 2009)";
364     m->units_per_default_bus = 1;
365     m->default_machine_opts = "firmware=bios-256k.bin";
366     m->default_display = "std";
367     m->default_kernel_irqchip_split = false;
368     m->no_floppy = 1;
369     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
370     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
371     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
372     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
373     m->max_cpus = 288;
374 }
375 
376 static void pc_q35_8_1_machine_options(MachineClass *m)
377 {
378     pc_q35_machine_options(m);
379     m->alias = "q35";
380 }
381 
382 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL,
383                    pc_q35_8_1_machine_options);
384 
385 static void pc_q35_8_0_machine_options(MachineClass *m)
386 {
387     pc_q35_8_1_machine_options(m);
388     m->alias = NULL;
389     compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
390     compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
391 }
392 
393 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
394                    pc_q35_8_0_machine_options);
395 
396 static void pc_q35_7_2_machine_options(MachineClass *m)
397 {
398     pc_q35_8_0_machine_options(m);
399     compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
400     compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
401 }
402 
403 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL,
404                    pc_q35_7_2_machine_options);
405 
406 static void pc_q35_7_1_machine_options(MachineClass *m)
407 {
408     pc_q35_7_2_machine_options(m);
409     compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
410     compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
411 }
412 
413 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
414                    pc_q35_7_1_machine_options);
415 
416 static void pc_q35_7_0_machine_options(MachineClass *m)
417 {
418     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
419     pc_q35_7_1_machine_options(m);
420     pcmc->enforce_amd_1tb_hole = false;
421     compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
422     compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
423 }
424 
425 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL,
426                    pc_q35_7_0_machine_options);
427 
428 static void pc_q35_6_2_machine_options(MachineClass *m)
429 {
430     pc_q35_7_0_machine_options(m);
431     compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
432     compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
433 }
434 
435 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
436                    pc_q35_6_2_machine_options);
437 
438 static void pc_q35_6_1_machine_options(MachineClass *m)
439 {
440     pc_q35_6_2_machine_options(m);
441     compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
442     compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
443     m->smp_props.prefer_sockets = true;
444 }
445 
446 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
447                    pc_q35_6_1_machine_options);
448 
449 static void pc_q35_6_0_machine_options(MachineClass *m)
450 {
451     pc_q35_6_1_machine_options(m);
452     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
453     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
454 }
455 
456 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
457                    pc_q35_6_0_machine_options);
458 
459 static void pc_q35_5_2_machine_options(MachineClass *m)
460 {
461     pc_q35_6_0_machine_options(m);
462     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
463     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
464 }
465 
466 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
467                    pc_q35_5_2_machine_options);
468 
469 static void pc_q35_5_1_machine_options(MachineClass *m)
470 {
471     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
472 
473     pc_q35_5_2_machine_options(m);
474     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
475     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
476     pcmc->kvmclock_create_always = false;
477     pcmc->pci_root_uid = 1;
478 }
479 
480 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
481                    pc_q35_5_1_machine_options);
482 
483 static void pc_q35_5_0_machine_options(MachineClass *m)
484 {
485     pc_q35_5_1_machine_options(m);
486     m->numa_mem_supported = true;
487     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
488     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
489     m->auto_enable_numa_with_memdev = false;
490 }
491 
492 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
493                    pc_q35_5_0_machine_options);
494 
495 static void pc_q35_4_2_machine_options(MachineClass *m)
496 {
497     pc_q35_5_0_machine_options(m);
498     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
499     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
500 }
501 
502 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
503                    pc_q35_4_2_machine_options);
504 
505 static void pc_q35_4_1_machine_options(MachineClass *m)
506 {
507     pc_q35_4_2_machine_options(m);
508     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
509     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
510 }
511 
512 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
513                    pc_q35_4_1_machine_options);
514 
515 static void pc_q35_4_0_1_machine_options(MachineClass *m)
516 {
517     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
518     pc_q35_4_1_machine_options(m);
519     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
520     /*
521      * This is the default machine for the 4.0-stable branch. It is basically
522      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
523      * 4.0 compat props.
524      */
525     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
526     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
527 }
528 
529 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
530                    pc_q35_4_0_1_machine_options);
531 
532 static void pc_q35_4_0_machine_options(MachineClass *m)
533 {
534     pc_q35_4_0_1_machine_options(m);
535     m->default_kernel_irqchip_split = true;
536     /* Compat props are applied by the 4.0.1 machine */
537 }
538 
539 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
540                    pc_q35_4_0_machine_options);
541 
542 static void pc_q35_3_1_machine_options(MachineClass *m)
543 {
544     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
545 
546     pc_q35_4_0_machine_options(m);
547     m->default_kernel_irqchip_split = false;
548     m->smbus_no_migration_support = true;
549     pcmc->pvh_enabled = false;
550     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
551     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
552 }
553 
554 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
555                    pc_q35_3_1_machine_options);
556 
557 static void pc_q35_3_0_machine_options(MachineClass *m)
558 {
559     pc_q35_3_1_machine_options(m);
560     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
561     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
562 }
563 
564 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
565                     pc_q35_3_0_machine_options);
566 
567 static void pc_q35_2_12_machine_options(MachineClass *m)
568 {
569     pc_q35_3_0_machine_options(m);
570     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
571     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
572 }
573 
574 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
575                    pc_q35_2_12_machine_options);
576 
577 static void pc_q35_2_11_machine_options(MachineClass *m)
578 {
579     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
580 
581     pc_q35_2_12_machine_options(m);
582     pcmc->default_nic_model = "e1000";
583     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
584     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
585 }
586 
587 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
588                    pc_q35_2_11_machine_options);
589 
590 static void pc_q35_2_10_machine_options(MachineClass *m)
591 {
592     pc_q35_2_11_machine_options(m);
593     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
594     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
595     m->auto_enable_numa_with_memhp = false;
596 }
597 
598 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
599                    pc_q35_2_10_machine_options);
600 
601 static void pc_q35_2_9_machine_options(MachineClass *m)
602 {
603     pc_q35_2_10_machine_options(m);
604     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
605     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
606 }
607 
608 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
609                    pc_q35_2_9_machine_options);
610 
611 static void pc_q35_2_8_machine_options(MachineClass *m)
612 {
613     pc_q35_2_9_machine_options(m);
614     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
615     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
616 }
617 
618 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
619                    pc_q35_2_8_machine_options);
620 
621 static void pc_q35_2_7_machine_options(MachineClass *m)
622 {
623     pc_q35_2_8_machine_options(m);
624     m->max_cpus = 255;
625     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
626     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
627 }
628 
629 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
630                    pc_q35_2_7_machine_options);
631 
632 static void pc_q35_2_6_machine_options(MachineClass *m)
633 {
634     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
635     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
636 
637     pc_q35_2_7_machine_options(m);
638     pcmc->legacy_cpu_hotplug = true;
639     x86mc->fwcfg_dma_enabled = false;
640     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
641     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
642 }
643 
644 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
645                    pc_q35_2_6_machine_options);
646 
647 static void pc_q35_2_5_machine_options(MachineClass *m)
648 {
649     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
650 
651     pc_q35_2_6_machine_options(m);
652     x86mc->save_tsc_khz = false;
653     m->legacy_fw_cfg_order = 1;
654     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
655     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
656 }
657 
658 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
659                    pc_q35_2_5_machine_options);
660 
661 static void pc_q35_2_4_machine_options(MachineClass *m)
662 {
663     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
664 
665     pc_q35_2_5_machine_options(m);
666     m->hw_version = "2.4.0";
667     pcmc->broken_reserved_end = true;
668     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
669     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
670 }
671 
672 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
673                    pc_q35_2_4_machine_options);
674