1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/char/parallel-isa.h" 34 #include "hw/loader.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/kvm.h" 39 #include "hw/i386/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "hw/pci/pcie_port.h" 42 #include "hw/qdev-properties.h" 43 #include "hw/i386/x86.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/firmware/smbios.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci-pci.h" 51 #include "hw/intc/ioapic.h" 52 #include "hw/southbridge/ich9.h" 53 #include "hw/usb.h" 54 #include "hw/usb/hcd-uhci.h" 55 #include "qapi/error.h" 56 #include "qemu/error-report.h" 57 #include "sysemu/numa.h" 58 #include "hw/hyperv/vmbus-bridge.h" 59 #include "hw/mem/nvdimm.h" 60 #include "hw/i386/acpi-build.h" 61 #include "target/i386/cpu.h" 62 63 /* ICH9 AHCI has 6 ports */ 64 #define MAX_SATA_PORTS 6 65 66 struct ehci_companions { 67 const char *name; 68 int func; 69 int port; 70 }; 71 72 static const struct ehci_companions ich9_1d[] = { 73 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 74 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 75 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 76 }; 77 78 static const struct ehci_companions ich9_1a[] = { 79 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 80 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 81 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 82 }; 83 84 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 85 { 86 const struct ehci_companions *comp; 87 PCIDevice *ehci, *uhci; 88 BusState *usbbus; 89 const char *name; 90 int i; 91 92 switch (slot) { 93 case 0x1d: 94 name = "ich9-usb-ehci1"; 95 comp = ich9_1d; 96 break; 97 case 0x1a: 98 name = "ich9-usb-ehci2"; 99 comp = ich9_1a; 100 break; 101 default: 102 return -1; 103 } 104 105 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 106 pci_realize_and_unref(ehci, bus, &error_fatal); 107 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 108 109 for (i = 0; i < 3; i++) { 110 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 111 comp[i].name); 112 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 113 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 114 pci_realize_and_unref(uhci, bus, &error_fatal); 115 } 116 return 0; 117 } 118 119 /* PC hardware initialisation */ 120 static void pc_q35_init(MachineState *machine) 121 { 122 PCMachineState *pcms = PC_MACHINE(machine); 123 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 124 X86MachineState *x86ms = X86_MACHINE(machine); 125 Object *phb; 126 PCIBus *host_bus; 127 PCIDevice *lpc; 128 DeviceState *lpc_dev; 129 BusState *idebus[MAX_SATA_PORTS]; 130 ISADevice *rtc_state; 131 MemoryRegion *system_memory = get_system_memory(); 132 MemoryRegion *system_io = get_system_io(); 133 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 134 GSIState *gsi_state; 135 ISABus *isa_bus; 136 int i; 137 ram_addr_t lowmem; 138 DriveInfo *hd[MAX_SATA_PORTS]; 139 MachineClass *mc = MACHINE_GET_CLASS(machine); 140 bool acpi_pcihp; 141 bool keep_pci_slot_hpc; 142 uint64_t pci_hole64_size = 0; 143 144 assert(pcmc->pci_enabled); 145 146 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 147 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 148 * also known as MMCFG). 149 * If it doesn't, we need to split it in chunks below and above 4G. 150 * In any case, try to make sure that guest addresses aligned at 151 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 152 */ 153 if (machine->ram_size >= 0xb0000000) { 154 lowmem = 0x80000000; 155 } else { 156 lowmem = 0xb0000000; 157 } 158 159 /* Handle the machine opt max-ram-below-4g. It is basically doing 160 * min(qemu limit, user limit). 161 */ 162 if (!pcms->max_ram_below_4g) { 163 pcms->max_ram_below_4g = 4 * GiB; 164 } 165 if (lowmem > pcms->max_ram_below_4g) { 166 lowmem = pcms->max_ram_below_4g; 167 if (machine->ram_size - lowmem > lowmem && 168 lowmem & (1 * GiB - 1)) { 169 warn_report("There is possibly poor performance as the ram size " 170 " (0x%" PRIx64 ") is more then twice the size of" 171 " max-ram-below-4g (%"PRIu64") and" 172 " max-ram-below-4g is not a multiple of 1G.", 173 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 174 } 175 } 176 177 if (machine->ram_size >= lowmem) { 178 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 179 x86ms->below_4g_mem_size = lowmem; 180 } else { 181 x86ms->above_4g_mem_size = 0; 182 x86ms->below_4g_mem_size = machine->ram_size; 183 } 184 185 pc_machine_init_sgx_epc(pcms); 186 x86_cpus_init(x86ms, pcmc->default_cpu_version); 187 188 if (kvm_enabled()) { 189 kvmclock_create(pcmc->kvmclock_create_always); 190 } 191 192 pc_guest_info_init(pcms); 193 194 if (pcmc->smbios_defaults) { 195 /* These values are guest ABI, do not change */ 196 smbios_set_defaults("QEMU", mc->desc, 197 mc->name, pcmc->smbios_legacy_mode, 198 pcmc->smbios_uuid_encoded, 199 pcms->smbios_entry_point_type); 200 } 201 202 /* create pci host bus */ 203 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 204 205 pci_hole64_size = object_property_get_uint(phb, 206 PCI_HOST_PROP_PCI_HOLE64_SIZE, 207 &error_abort); 208 209 /* allocate ram and load rom/bios */ 210 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 211 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 212 213 object_property_add_child(OBJECT(machine), "q35", phb); 214 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 215 OBJECT(machine->ram), NULL); 216 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 217 OBJECT(pci_memory), NULL); 218 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 219 OBJECT(system_memory), NULL); 220 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 221 OBJECT(system_io), NULL); 222 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 223 x86ms->below_4g_mem_size, NULL); 224 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 225 x86ms->above_4g_mem_size, NULL); 226 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 227 pcms->default_bus_bypass_iommu, NULL); 228 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 229 230 /* pci */ 231 host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 232 pcms->bus = host_bus; 233 234 /* irq lines */ 235 gsi_state = pc_gsi_create(&x86ms->gsi, true); 236 237 /* create ISA bus */ 238 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 239 TYPE_ICH9_LPC_DEVICE); 240 lpc_dev = DEVICE(lpc); 241 qdev_prop_set_bit(lpc_dev, "smm-enabled", 242 x86_machine_is_smm_enabled(x86ms)); 243 pci_realize_and_unref(lpc, host_bus, &error_fatal); 244 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 245 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 246 } 247 248 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 249 250 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 251 TYPE_HOTPLUG_HANDLER, 252 (Object **)&x86ms->acpi_dev, 253 object_property_allow_set_link, 254 OBJ_PROP_LINK_STRONG); 255 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 256 OBJECT(lpc), &error_abort); 257 258 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 259 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 260 NULL); 261 262 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 263 "x-keep-pci-slot-hpc", 264 NULL); 265 266 if (!keep_pci_slot_hpc && acpi_pcihp) { 267 object_register_sugar_prop(TYPE_PCIE_SLOT, 268 "x-do-not-expose-native-hotplug-cap", 269 "true", true); 270 } 271 272 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 273 274 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 275 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 276 } 277 278 ioapic_init_gsi(gsi_state, "q35"); 279 280 if (tcg_enabled()) { 281 x86_register_ferr_irq(x86ms->gsi[13]); 282 } 283 284 assert(pcms->vmport != ON_OFF_AUTO__MAX); 285 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 286 pcms->vmport = ON_OFF_AUTO_ON; 287 } 288 289 /* init basic PC hardware */ 290 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 291 0xff0104); 292 293 if (pcms->sata_enabled) { 294 PCIDevice *pdev; 295 AHCIPCIState *ich9; 296 297 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 298 pdev = pci_create_simple_multifunction(host_bus, 299 PCI_DEVFN(ICH9_SATA1_DEV, 300 ICH9_SATA1_FUNC), 301 "ich9-ahci"); 302 ich9 = ICH9_AHCI(pdev); 303 idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 304 idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 305 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 306 ide_drive_get(hd, ich9->ahci.ports); 307 ahci_ide_create_devs(&ich9->ahci, hd); 308 } else { 309 idebus[0] = idebus[1] = NULL; 310 } 311 312 if (machine_usb(machine)) { 313 /* Should we create 6 UHCI according to ich9 spec? */ 314 ehci_create_ich9_with_companions(host_bus, 0x1d); 315 } 316 317 if (pcms->smbus_enabled) { 318 PCIDevice *smb; 319 320 /* TODO: Populate SPD eeprom data. */ 321 smb = pci_create_simple_multifunction(host_bus, 322 PCI_DEVFN(ICH9_SMB_DEV, 323 ICH9_SMB_FUNC), 324 TYPE_ICH9_SMB_DEVICE); 325 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 326 327 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 328 } 329 330 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 331 332 /* the rest devices to which pci devfn is automatically assigned */ 333 pc_vga_init(isa_bus, host_bus); 334 pc_nic_init(pcmc, isa_bus, host_bus); 335 336 if (machine->nvdimms_state->is_enabled) { 337 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 338 x86_nvdimm_acpi_dsmio, 339 x86ms->fw_cfg, OBJECT(pcms)); 340 } 341 } 342 343 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 344 static void pc_init_##suffix(MachineState *machine) \ 345 { \ 346 void (*compat)(MachineState *m) = (compatfn); \ 347 if (compat) { \ 348 compat(machine); \ 349 } \ 350 pc_q35_init(machine); \ 351 } \ 352 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 353 354 355 static void pc_q35_machine_options(MachineClass *m) 356 { 357 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 358 pcmc->pci_root_uid = 0; 359 pcmc->default_cpu_version = 1; 360 361 m->family = "pc_q35"; 362 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 363 m->units_per_default_bus = 1; 364 m->default_machine_opts = "firmware=bios-256k.bin"; 365 m->default_display = "std"; 366 m->default_nic = "e1000e"; 367 m->default_kernel_irqchip_split = false; 368 m->no_floppy = 1; 369 m->max_cpus = 1024; 370 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 371 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 372 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 373 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 374 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 375 } 376 377 static void pc_q35_9_0_machine_options(MachineClass *m) 378 { 379 pc_q35_machine_options(m); 380 m->alias = "q35"; 381 } 382 383 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, 384 pc_q35_9_0_machine_options); 385 386 static void pc_q35_8_2_machine_options(MachineClass *m) 387 { 388 pc_q35_9_0_machine_options(m); 389 m->alias = NULL; 390 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 391 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 392 } 393 394 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 395 pc_q35_8_2_machine_options); 396 397 static void pc_q35_8_1_machine_options(MachineClass *m) 398 { 399 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 400 pc_q35_8_2_machine_options(m); 401 m->alias = NULL; 402 pcmc->broken_32bit_mem_addr_check = true; 403 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 404 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 405 } 406 407 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 408 pc_q35_8_1_machine_options); 409 410 static void pc_q35_8_0_machine_options(MachineClass *m) 411 { 412 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 413 414 pc_q35_8_1_machine_options(m); 415 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 416 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 417 418 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 419 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 420 m->max_cpus = 288; 421 } 422 423 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 424 pc_q35_8_0_machine_options); 425 426 static void pc_q35_7_2_machine_options(MachineClass *m) 427 { 428 pc_q35_8_0_machine_options(m); 429 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 430 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 431 } 432 433 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 434 pc_q35_7_2_machine_options); 435 436 static void pc_q35_7_1_machine_options(MachineClass *m) 437 { 438 pc_q35_7_2_machine_options(m); 439 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 440 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 441 } 442 443 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 444 pc_q35_7_1_machine_options); 445 446 static void pc_q35_7_0_machine_options(MachineClass *m) 447 { 448 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 449 pc_q35_7_1_machine_options(m); 450 pcmc->enforce_amd_1tb_hole = false; 451 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 452 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 453 } 454 455 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 456 pc_q35_7_0_machine_options); 457 458 static void pc_q35_6_2_machine_options(MachineClass *m) 459 { 460 pc_q35_7_0_machine_options(m); 461 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 462 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 463 } 464 465 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 466 pc_q35_6_2_machine_options); 467 468 static void pc_q35_6_1_machine_options(MachineClass *m) 469 { 470 pc_q35_6_2_machine_options(m); 471 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 472 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 473 m->smp_props.prefer_sockets = true; 474 } 475 476 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 477 pc_q35_6_1_machine_options); 478 479 static void pc_q35_6_0_machine_options(MachineClass *m) 480 { 481 pc_q35_6_1_machine_options(m); 482 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 483 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 484 } 485 486 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 487 pc_q35_6_0_machine_options); 488 489 static void pc_q35_5_2_machine_options(MachineClass *m) 490 { 491 pc_q35_6_0_machine_options(m); 492 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 493 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 494 } 495 496 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 497 pc_q35_5_2_machine_options); 498 499 static void pc_q35_5_1_machine_options(MachineClass *m) 500 { 501 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 502 503 pc_q35_5_2_machine_options(m); 504 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 505 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 506 pcmc->kvmclock_create_always = false; 507 pcmc->pci_root_uid = 1; 508 } 509 510 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 511 pc_q35_5_1_machine_options); 512 513 static void pc_q35_5_0_machine_options(MachineClass *m) 514 { 515 pc_q35_5_1_machine_options(m); 516 m->numa_mem_supported = true; 517 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 518 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 519 m->auto_enable_numa_with_memdev = false; 520 } 521 522 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 523 pc_q35_5_0_machine_options); 524 525 static void pc_q35_4_2_machine_options(MachineClass *m) 526 { 527 pc_q35_5_0_machine_options(m); 528 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 529 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 530 } 531 532 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 533 pc_q35_4_2_machine_options); 534 535 static void pc_q35_4_1_machine_options(MachineClass *m) 536 { 537 pc_q35_4_2_machine_options(m); 538 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 539 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 540 } 541 542 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 543 pc_q35_4_1_machine_options); 544 545 static void pc_q35_4_0_1_machine_options(MachineClass *m) 546 { 547 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 548 pc_q35_4_1_machine_options(m); 549 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 550 /* 551 * This is the default machine for the 4.0-stable branch. It is basically 552 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 553 * 4.0 compat props. 554 */ 555 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 556 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 557 } 558 559 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 560 pc_q35_4_0_1_machine_options); 561 562 static void pc_q35_4_0_machine_options(MachineClass *m) 563 { 564 pc_q35_4_0_1_machine_options(m); 565 m->default_kernel_irqchip_split = true; 566 /* Compat props are applied by the 4.0.1 machine */ 567 } 568 569 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 570 pc_q35_4_0_machine_options); 571 572 static void pc_q35_3_1_machine_options(MachineClass *m) 573 { 574 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 575 576 pc_q35_4_0_machine_options(m); 577 m->default_kernel_irqchip_split = false; 578 m->smbus_no_migration_support = true; 579 pcmc->pvh_enabled = false; 580 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 581 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 582 } 583 584 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 585 pc_q35_3_1_machine_options); 586 587 static void pc_q35_3_0_machine_options(MachineClass *m) 588 { 589 pc_q35_3_1_machine_options(m); 590 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 591 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 592 } 593 594 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 595 pc_q35_3_0_machine_options); 596 597 static void pc_q35_2_12_machine_options(MachineClass *m) 598 { 599 pc_q35_3_0_machine_options(m); 600 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 601 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 602 } 603 604 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 605 pc_q35_2_12_machine_options); 606 607 static void pc_q35_2_11_machine_options(MachineClass *m) 608 { 609 pc_q35_2_12_machine_options(m); 610 m->default_nic = "e1000"; 611 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 612 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 613 } 614 615 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 616 pc_q35_2_11_machine_options); 617 618 static void pc_q35_2_10_machine_options(MachineClass *m) 619 { 620 pc_q35_2_11_machine_options(m); 621 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 622 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 623 m->auto_enable_numa_with_memhp = false; 624 } 625 626 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 627 pc_q35_2_10_machine_options); 628 629 static void pc_q35_2_9_machine_options(MachineClass *m) 630 { 631 pc_q35_2_10_machine_options(m); 632 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 633 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 634 } 635 636 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 637 pc_q35_2_9_machine_options); 638 639 static void pc_q35_2_8_machine_options(MachineClass *m) 640 { 641 pc_q35_2_9_machine_options(m); 642 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 643 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 644 } 645 646 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 647 pc_q35_2_8_machine_options); 648 649 static void pc_q35_2_7_machine_options(MachineClass *m) 650 { 651 pc_q35_2_8_machine_options(m); 652 m->max_cpus = 255; 653 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 654 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 655 } 656 657 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 658 pc_q35_2_7_machine_options); 659 660 static void pc_q35_2_6_machine_options(MachineClass *m) 661 { 662 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 663 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 664 665 pc_q35_2_7_machine_options(m); 666 pcmc->legacy_cpu_hotplug = true; 667 x86mc->fwcfg_dma_enabled = false; 668 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 669 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 670 } 671 672 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 673 pc_q35_2_6_machine_options); 674 675 static void pc_q35_2_5_machine_options(MachineClass *m) 676 { 677 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 678 679 pc_q35_2_6_machine_options(m); 680 x86mc->save_tsc_khz = false; 681 m->legacy_fw_cfg_order = 1; 682 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 683 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 684 } 685 686 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 687 pc_q35_2_5_machine_options); 688 689 static void pc_q35_2_4_machine_options(MachineClass *m) 690 { 691 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 692 693 pc_q35_2_5_machine_options(m); 694 m->hw_version = "2.4.0"; 695 pcmc->broken_reserved_end = true; 696 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 697 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 698 } 699 700 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 701 pc_q35_2_4_machine_options); 702