1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/timer/mc146818rtc.h" 37 #include "hw/xen/xen.h" 38 #include "sysemu/kvm.h" 39 #include "kvm_i386.h" 40 #include "hw/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/qdev-properties.h" 43 #include "exec/address-spaces.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/ich9.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/display/ramfb.h" 49 #include "hw/firmware/smbios.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci.h" 52 #include "hw/usb.h" 53 #include "qapi/error.h" 54 #include "qemu/error-report.h" 55 #include "sysemu/numa.h" 56 57 /* ICH9 AHCI has 6 ports */ 58 #define MAX_SATA_PORTS 6 59 60 struct ehci_companions { 61 const char *name; 62 int func; 63 int port; 64 }; 65 66 static const struct ehci_companions ich9_1d[] = { 67 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 68 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 69 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 70 }; 71 72 static const struct ehci_companions ich9_1a[] = { 73 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 74 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 75 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 76 }; 77 78 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 79 { 80 const struct ehci_companions *comp; 81 PCIDevice *ehci, *uhci; 82 BusState *usbbus; 83 const char *name; 84 int i; 85 86 switch (slot) { 87 case 0x1d: 88 name = "ich9-usb-ehci1"; 89 comp = ich9_1d; 90 break; 91 case 0x1a: 92 name = "ich9-usb-ehci2"; 93 comp = ich9_1a; 94 break; 95 default: 96 return -1; 97 } 98 99 ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); 100 qdev_init_nofail(&ehci->qdev); 101 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 102 103 for (i = 0; i < 3; i++) { 104 uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), 105 true, comp[i].name); 106 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 107 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 108 qdev_init_nofail(&uhci->qdev); 109 } 110 return 0; 111 } 112 113 /* PC hardware initialisation */ 114 static void pc_q35_init(MachineState *machine) 115 { 116 PCMachineState *pcms = PC_MACHINE(machine); 117 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 118 Q35PCIHost *q35_host; 119 PCIHostState *phb; 120 PCIBus *host_bus; 121 PCIDevice *lpc; 122 DeviceState *lpc_dev; 123 BusState *idebus[MAX_SATA_PORTS]; 124 ISADevice *rtc_state; 125 MemoryRegion *system_io = get_system_io(); 126 MemoryRegion *pci_memory; 127 MemoryRegion *rom_memory; 128 MemoryRegion *ram_memory; 129 GSIState *gsi_state; 130 ISABus *isa_bus; 131 qemu_irq *i8259; 132 int i; 133 ICH9LPCState *ich9_lpc; 134 PCIDevice *ahci; 135 ram_addr_t lowmem; 136 DriveInfo *hd[MAX_SATA_PORTS]; 137 MachineClass *mc = MACHINE_GET_CLASS(machine); 138 139 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 140 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 141 * also known as MMCFG). 142 * If it doesn't, we need to split it in chunks below and above 4G. 143 * In any case, try to make sure that guest addresses aligned at 144 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 145 */ 146 if (machine->ram_size >= 0xb0000000) { 147 lowmem = 0x80000000; 148 } else { 149 lowmem = 0xb0000000; 150 } 151 152 /* Handle the machine opt max-ram-below-4g. It is basically doing 153 * min(qemu limit, user limit). 154 */ 155 if (!pcms->max_ram_below_4g) { 156 pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */; 157 } 158 if (lowmem > pcms->max_ram_below_4g) { 159 lowmem = pcms->max_ram_below_4g; 160 if (machine->ram_size - lowmem > lowmem && 161 lowmem & (1 * GiB - 1)) { 162 warn_report("There is possibly poor performance as the ram size " 163 " (0x%" PRIx64 ") is more then twice the size of" 164 " max-ram-below-4g (%"PRIu64") and" 165 " max-ram-below-4g is not a multiple of 1G.", 166 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 167 } 168 } 169 170 if (machine->ram_size >= lowmem) { 171 pcms->above_4g_mem_size = machine->ram_size - lowmem; 172 pcms->below_4g_mem_size = lowmem; 173 } else { 174 pcms->above_4g_mem_size = 0; 175 pcms->below_4g_mem_size = machine->ram_size; 176 } 177 178 if (xen_enabled()) { 179 xen_hvm_init(pcms, &ram_memory); 180 } 181 182 pc_cpus_init(pcms); 183 184 kvmclock_create(); 185 186 /* pci enabled */ 187 if (pcmc->pci_enabled) { 188 pci_memory = g_new(MemoryRegion, 1); 189 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 190 rom_memory = pci_memory; 191 } else { 192 pci_memory = NULL; 193 rom_memory = get_system_memory(); 194 } 195 196 pc_guest_info_init(pcms); 197 198 if (pcmc->smbios_defaults) { 199 /* These values are guest ABI, do not change */ 200 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 201 mc->name, pcmc->smbios_legacy_mode, 202 pcmc->smbios_uuid_encoded, 203 SMBIOS_ENTRY_POINT_21); 204 } 205 206 /* allocate ram and load rom/bios */ 207 if (!xen_enabled()) { 208 pc_memory_init(pcms, get_system_memory(), 209 rom_memory, &ram_memory); 210 } 211 212 /* irq lines */ 213 gsi_state = g_malloc0(sizeof(*gsi_state)); 214 if (kvm_ioapic_in_kernel()) { 215 kvm_pc_setup_irq_routing(pcmc->pci_enabled); 216 pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 217 GSI_NUM_PINS); 218 } else { 219 pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 220 } 221 222 /* create pci host bus */ 223 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 224 225 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 226 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 227 MCH_HOST_PROP_RAM_MEM, NULL); 228 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 229 MCH_HOST_PROP_PCI_MEM, NULL); 230 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 231 MCH_HOST_PROP_SYSTEM_MEM, NULL); 232 object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 233 MCH_HOST_PROP_IO_MEM, NULL); 234 object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size, 235 PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 236 object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size, 237 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 238 /* pci */ 239 qdev_init_nofail(DEVICE(q35_host)); 240 phb = PCI_HOST_BRIDGE(q35_host); 241 host_bus = phb->bus; 242 /* create ISA bus */ 243 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 244 ICH9_LPC_FUNC), true, 245 TYPE_ICH9_LPC_DEVICE); 246 247 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 248 TYPE_HOTPLUG_HANDLER, 249 (Object **)&pcms->acpi_dev, 250 object_property_allow_set_link, 251 OBJ_PROP_LINK_STRONG, &error_abort); 252 object_property_set_link(OBJECT(machine), OBJECT(lpc), 253 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 254 255 ich9_lpc = ICH9_LPC_DEVICE(lpc); 256 lpc_dev = DEVICE(lpc); 257 for (i = 0; i < GSI_NUM_PINS; i++) { 258 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]); 259 } 260 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 261 ICH9_LPC_NB_PIRQS); 262 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 263 isa_bus = ich9_lpc->isa_bus; 264 265 if (kvm_pic_in_kernel()) { 266 i8259 = kvm_i8259_init(isa_bus); 267 } else if (xen_enabled()) { 268 i8259 = xen_interrupt_controller_init(); 269 } else { 270 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 271 } 272 273 for (i = 0; i < ISA_NUM_IRQS; i++) { 274 gsi_state->i8259_irq[i] = i8259[i]; 275 } 276 g_free(i8259); 277 278 if (pcmc->pci_enabled) { 279 ioapic_init_gsi(gsi_state, "q35"); 280 } 281 282 pc_register_ferr_irq(pcms->gsi[13]); 283 284 assert(pcms->vmport != ON_OFF_AUTO__MAX); 285 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 286 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 287 } 288 289 /* init basic PC hardware */ 290 pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy, 291 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled, 292 0xff0104); 293 294 /* connect pm stuff to lpc */ 295 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); 296 297 if (pcms->sata_enabled) { 298 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 299 ahci = pci_create_simple_multifunction(host_bus, 300 PCI_DEVFN(ICH9_SATA1_DEV, 301 ICH9_SATA1_FUNC), 302 true, "ich9-ahci"); 303 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 304 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 305 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 306 ide_drive_get(hd, ahci_get_num_ports(ahci)); 307 ahci_ide_create_devs(ahci, hd); 308 } else { 309 idebus[0] = idebus[1] = NULL; 310 } 311 312 if (machine_usb(machine)) { 313 /* Should we create 6 UHCI according to ich9 spec? */ 314 ehci_create_ich9_with_companions(host_bus, 0x1d); 315 } 316 317 if (pcms->smbus_enabled) { 318 /* TODO: Populate SPD eeprom data. */ 319 smbus_eeprom_init(ich9_smb_init(host_bus, 320 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 321 0xb100), 322 8, NULL, 0); 323 } 324 325 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 326 327 /* the rest devices to which pci devfn is automatically assigned */ 328 pc_vga_init(isa_bus, host_bus); 329 pc_nic_init(pcmc, isa_bus, host_bus); 330 331 if (machine->nvdimms_state->is_enabled) { 332 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 333 pcms->fw_cfg, OBJECT(pcms)); 334 } 335 } 336 337 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 338 static void pc_init_##suffix(MachineState *machine) \ 339 { \ 340 void (*compat)(MachineState *m) = (compatfn); \ 341 if (compat) { \ 342 compat(machine); \ 343 } \ 344 pc_q35_init(machine); \ 345 } \ 346 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 347 348 349 static void pc_q35_machine_options(MachineClass *m) 350 { 351 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 352 pcmc->default_nic_model = "e1000e"; 353 354 m->family = "pc_q35"; 355 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 356 m->units_per_default_bus = 1; 357 m->default_machine_opts = "firmware=bios-256k.bin"; 358 m->default_display = "std"; 359 m->default_kernel_irqchip_split = false; 360 m->no_floppy = 1; 361 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 362 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 363 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 364 m->max_cpus = 288; 365 } 366 367 static void pc_q35_4_2_machine_options(MachineClass *m) 368 { 369 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 370 pc_q35_machine_options(m); 371 m->alias = "q35"; 372 pcmc->default_cpu_version = 1; 373 } 374 375 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 376 pc_q35_4_2_machine_options); 377 378 static void pc_q35_4_1_machine_options(MachineClass *m) 379 { 380 pc_q35_4_2_machine_options(m); 381 m->alias = NULL; 382 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 383 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 384 } 385 386 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 387 pc_q35_4_1_machine_options); 388 389 static void pc_q35_4_0_1_machine_options(MachineClass *m) 390 { 391 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 392 pc_q35_4_1_machine_options(m); 393 m->alias = NULL; 394 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 395 /* 396 * This is the default machine for the 4.0-stable branch. It is basically 397 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 398 * 4.0 compat props. 399 */ 400 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 401 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 402 } 403 404 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 405 pc_q35_4_0_1_machine_options); 406 407 static void pc_q35_4_0_machine_options(MachineClass *m) 408 { 409 pc_q35_4_0_1_machine_options(m); 410 m->default_kernel_irqchip_split = true; 411 m->alias = NULL; 412 /* Compat props are applied by the 4.0.1 machine */ 413 } 414 415 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 416 pc_q35_4_0_machine_options); 417 418 static void pc_q35_3_1_machine_options(MachineClass *m) 419 { 420 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 421 422 pc_q35_4_0_machine_options(m); 423 m->default_kernel_irqchip_split = false; 424 m->smbus_no_migration_support = true; 425 m->alias = NULL; 426 pcmc->pvh_enabled = false; 427 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 428 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 429 } 430 431 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 432 pc_q35_3_1_machine_options); 433 434 static void pc_q35_3_0_machine_options(MachineClass *m) 435 { 436 pc_q35_3_1_machine_options(m); 437 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 438 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 439 } 440 441 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 442 pc_q35_3_0_machine_options); 443 444 static void pc_q35_2_12_machine_options(MachineClass *m) 445 { 446 pc_q35_3_0_machine_options(m); 447 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 448 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 449 } 450 451 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 452 pc_q35_2_12_machine_options); 453 454 static void pc_q35_2_11_machine_options(MachineClass *m) 455 { 456 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 457 458 pc_q35_2_12_machine_options(m); 459 pcmc->default_nic_model = "e1000"; 460 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 461 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 462 } 463 464 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 465 pc_q35_2_11_machine_options); 466 467 static void pc_q35_2_10_machine_options(MachineClass *m) 468 { 469 pc_q35_2_11_machine_options(m); 470 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 471 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 472 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 473 m->auto_enable_numa_with_memhp = false; 474 } 475 476 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 477 pc_q35_2_10_machine_options); 478 479 static void pc_q35_2_9_machine_options(MachineClass *m) 480 { 481 pc_q35_2_10_machine_options(m); 482 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 483 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 484 } 485 486 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 487 pc_q35_2_9_machine_options); 488 489 static void pc_q35_2_8_machine_options(MachineClass *m) 490 { 491 pc_q35_2_9_machine_options(m); 492 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 493 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 494 } 495 496 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 497 pc_q35_2_8_machine_options); 498 499 static void pc_q35_2_7_machine_options(MachineClass *m) 500 { 501 pc_q35_2_8_machine_options(m); 502 m->max_cpus = 255; 503 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 504 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 505 } 506 507 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 508 pc_q35_2_7_machine_options); 509 510 static void pc_q35_2_6_machine_options(MachineClass *m) 511 { 512 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 513 514 pc_q35_2_7_machine_options(m); 515 pcmc->legacy_cpu_hotplug = true; 516 pcmc->linuxboot_dma_enabled = false; 517 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 518 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 519 } 520 521 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 522 pc_q35_2_6_machine_options); 523 524 static void pc_q35_2_5_machine_options(MachineClass *m) 525 { 526 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 527 528 pc_q35_2_6_machine_options(m); 529 pcmc->save_tsc_khz = false; 530 m->legacy_fw_cfg_order = 1; 531 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 532 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 533 } 534 535 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 536 pc_q35_2_5_machine_options); 537 538 static void pc_q35_2_4_machine_options(MachineClass *m) 539 { 540 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 541 542 pc_q35_2_5_machine_options(m); 543 m->hw_version = "2.4.0"; 544 pcmc->broken_reserved_end = true; 545 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 546 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 547 } 548 549 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 550 pc_q35_2_4_machine_options); 551