1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor/monitor.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 /* #define DEBUG_AHCI */ 37 38 #ifdef DEBUG_AHCI 39 #define DPRINTF(port, fmt, ...) \ 40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(port, fmt, ...) do {} while(0) 44 #endif 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s,int port,int slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 53 { 54 uint32_t val; 55 AHCIPortRegs *pr; 56 pr = &s->dev[port].port_regs; 57 58 switch (offset) { 59 case PORT_LST_ADDR: 60 val = pr->lst_addr; 61 break; 62 case PORT_LST_ADDR_HI: 63 val = pr->lst_addr_hi; 64 break; 65 case PORT_FIS_ADDR: 66 val = pr->fis_addr; 67 break; 68 case PORT_FIS_ADDR_HI: 69 val = pr->fis_addr_hi; 70 break; 71 case PORT_IRQ_STAT: 72 val = pr->irq_stat; 73 break; 74 case PORT_IRQ_MASK: 75 val = pr->irq_mask; 76 break; 77 case PORT_CMD: 78 val = pr->cmd; 79 break; 80 case PORT_TFDATA: 81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 82 s->dev[port].port.ifs[0].status; 83 break; 84 case PORT_SIG: 85 val = pr->sig; 86 break; 87 case PORT_SCR_STAT: 88 if (s->dev[port].port.ifs[0].bs) { 89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 91 } else { 92 val = SATA_SCR_SSTATUS_DET_NODEV; 93 } 94 break; 95 case PORT_SCR_CTL: 96 val = pr->scr_ctl; 97 break; 98 case PORT_SCR_ERR: 99 val = pr->scr_err; 100 break; 101 case PORT_SCR_ACT: 102 pr->scr_act &= ~s->dev[port].finished; 103 s->dev[port].finished = 0; 104 val = pr->scr_act; 105 break; 106 case PORT_CMD_ISSUE: 107 val = pr->cmd_issue; 108 break; 109 case PORT_RESERVED: 110 default: 111 val = 0; 112 } 113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 114 return val; 115 116 } 117 118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 119 { 120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 121 PCIDevice *pci_dev = 122 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 123 124 DPRINTF(0, "raise irq\n"); 125 126 if (pci_dev && msi_enabled(pci_dev)) { 127 msi_notify(pci_dev, 0); 128 } else { 129 qemu_irq_raise(s->irq); 130 } 131 } 132 133 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 134 { 135 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 136 PCIDevice *pci_dev = 137 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 138 139 DPRINTF(0, "lower irq\n"); 140 141 if (!pci_dev || !msi_enabled(pci_dev)) { 142 qemu_irq_lower(s->irq); 143 } 144 } 145 146 static void ahci_check_irq(AHCIState *s) 147 { 148 int i; 149 150 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 151 152 s->control_regs.irqstatus = 0; 153 for (i = 0; i < s->ports; i++) { 154 AHCIPortRegs *pr = &s->dev[i].port_regs; 155 if (pr->irq_stat & pr->irq_mask) { 156 s->control_regs.irqstatus |= (1 << i); 157 } 158 } 159 160 if (s->control_regs.irqstatus && 161 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 162 ahci_irq_raise(s, NULL); 163 } else { 164 ahci_irq_lower(s, NULL); 165 } 166 } 167 168 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 169 int irq_type) 170 { 171 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 172 irq_type, d->port_regs.irq_mask & irq_type); 173 174 d->port_regs.irq_stat |= irq_type; 175 ahci_check_irq(s); 176 } 177 178 static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted) 179 { 180 hwaddr len = wanted; 181 182 if (*ptr) { 183 cpu_physical_memory_unmap(*ptr, len, 1, len); 184 } 185 186 *ptr = cpu_physical_memory_map(addr, &len, 1); 187 if (len < wanted) { 188 cpu_physical_memory_unmap(*ptr, len, 1, len); 189 *ptr = NULL; 190 } 191 } 192 193 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 194 { 195 AHCIPortRegs *pr = &s->dev[port].port_regs; 196 197 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 198 switch (offset) { 199 case PORT_LST_ADDR: 200 pr->lst_addr = val; 201 map_page(&s->dev[port].lst, 202 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 203 s->dev[port].cur_cmd = NULL; 204 break; 205 case PORT_LST_ADDR_HI: 206 pr->lst_addr_hi = val; 207 map_page(&s->dev[port].lst, 208 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 209 s->dev[port].cur_cmd = NULL; 210 break; 211 case PORT_FIS_ADDR: 212 pr->fis_addr = val; 213 map_page(&s->dev[port].res_fis, 214 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 215 break; 216 case PORT_FIS_ADDR_HI: 217 pr->fis_addr_hi = val; 218 map_page(&s->dev[port].res_fis, 219 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 220 break; 221 case PORT_IRQ_STAT: 222 pr->irq_stat &= ~val; 223 ahci_check_irq(s); 224 break; 225 case PORT_IRQ_MASK: 226 pr->irq_mask = val & 0xfdc000ff; 227 ahci_check_irq(s); 228 break; 229 case PORT_CMD: 230 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 231 232 if (pr->cmd & PORT_CMD_START) { 233 pr->cmd |= PORT_CMD_LIST_ON; 234 } 235 236 if (pr->cmd & PORT_CMD_FIS_RX) { 237 pr->cmd |= PORT_CMD_FIS_ON; 238 } 239 240 /* XXX usually the FIS would be pending on the bus here and 241 issuing deferred until the OS enables FIS receival. 242 Instead, we only submit it once - which works in most 243 cases, but is a hack. */ 244 if ((pr->cmd & PORT_CMD_FIS_ON) && 245 !s->dev[port].init_d2h_sent) { 246 ahci_init_d2h(&s->dev[port]); 247 s->dev[port].init_d2h_sent = true; 248 } 249 250 check_cmd(s, port); 251 break; 252 case PORT_TFDATA: 253 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 254 s->dev[port].port.ifs[0].status = val & 0xff; 255 break; 256 case PORT_SIG: 257 pr->sig = val; 258 break; 259 case PORT_SCR_STAT: 260 pr->scr_stat = val; 261 break; 262 case PORT_SCR_CTL: 263 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 264 ((val & AHCI_SCR_SCTL_DET) == 0)) { 265 ahci_reset_port(s, port); 266 } 267 pr->scr_ctl = val; 268 break; 269 case PORT_SCR_ERR: 270 pr->scr_err &= ~val; 271 break; 272 case PORT_SCR_ACT: 273 /* RW1 */ 274 pr->scr_act |= val; 275 break; 276 case PORT_CMD_ISSUE: 277 pr->cmd_issue |= val; 278 check_cmd(s, port); 279 break; 280 default: 281 break; 282 } 283 } 284 285 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 286 unsigned size) 287 { 288 AHCIState *s = opaque; 289 uint32_t val = 0; 290 291 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 292 switch (addr) { 293 case HOST_CAP: 294 val = s->control_regs.cap; 295 break; 296 case HOST_CTL: 297 val = s->control_regs.ghc; 298 break; 299 case HOST_IRQ_STAT: 300 val = s->control_regs.irqstatus; 301 break; 302 case HOST_PORTS_IMPL: 303 val = s->control_regs.impl; 304 break; 305 case HOST_VERSION: 306 val = s->control_regs.version; 307 break; 308 } 309 310 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 311 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 312 (addr < (AHCI_PORT_REGS_START_ADDR + 313 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 314 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 315 addr & AHCI_PORT_ADDR_OFFSET_MASK); 316 } 317 318 return val; 319 } 320 321 322 323 static void ahci_mem_write(void *opaque, hwaddr addr, 324 uint64_t val, unsigned size) 325 { 326 AHCIState *s = opaque; 327 328 /* Only aligned reads are allowed on AHCI */ 329 if (addr & 3) { 330 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 331 TARGET_FMT_plx "\n", addr); 332 return; 333 } 334 335 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 336 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 337 338 switch (addr) { 339 case HOST_CAP: /* R/WO, RO */ 340 /* FIXME handle R/WO */ 341 break; 342 case HOST_CTL: /* R/W */ 343 if (val & HOST_CTL_RESET) { 344 DPRINTF(-1, "HBA Reset\n"); 345 ahci_reset(s); 346 } else { 347 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 348 ahci_check_irq(s); 349 } 350 break; 351 case HOST_IRQ_STAT: /* R/WC, RO */ 352 s->control_regs.irqstatus &= ~val; 353 ahci_check_irq(s); 354 break; 355 case HOST_PORTS_IMPL: /* R/WO, RO */ 356 /* FIXME handle R/WO */ 357 break; 358 case HOST_VERSION: /* RO */ 359 /* FIXME report write? */ 360 break; 361 default: 362 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 363 } 364 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 365 (addr < (AHCI_PORT_REGS_START_ADDR + 366 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 367 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 368 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 369 } 370 371 } 372 373 static const MemoryRegionOps ahci_mem_ops = { 374 .read = ahci_mem_read, 375 .write = ahci_mem_write, 376 .endianness = DEVICE_LITTLE_ENDIAN, 377 }; 378 379 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 380 unsigned size) 381 { 382 AHCIState *s = opaque; 383 384 if (addr == s->idp_offset) { 385 /* index register */ 386 return s->idp_index; 387 } else if (addr == s->idp_offset + 4) { 388 /* data register - do memory read at location selected by index */ 389 return ahci_mem_read(opaque, s->idp_index, size); 390 } else { 391 return 0; 392 } 393 } 394 395 static void ahci_idp_write(void *opaque, hwaddr addr, 396 uint64_t val, unsigned size) 397 { 398 AHCIState *s = opaque; 399 400 if (addr == s->idp_offset) { 401 /* index register - mask off reserved bits */ 402 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 403 } else if (addr == s->idp_offset + 4) { 404 /* data register - do memory write at location selected by index */ 405 ahci_mem_write(opaque, s->idp_index, val, size); 406 } 407 } 408 409 static const MemoryRegionOps ahci_idp_ops = { 410 .read = ahci_idp_read, 411 .write = ahci_idp_write, 412 .endianness = DEVICE_LITTLE_ENDIAN, 413 }; 414 415 416 static void ahci_reg_init(AHCIState *s) 417 { 418 int i; 419 420 s->control_regs.cap = (s->ports - 1) | 421 (AHCI_NUM_COMMAND_SLOTS << 8) | 422 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 423 HOST_CAP_NCQ | HOST_CAP_AHCI; 424 425 s->control_regs.impl = (1 << s->ports) - 1; 426 427 s->control_regs.version = AHCI_VERSION_1_0; 428 429 for (i = 0; i < s->ports; i++) { 430 s->dev[i].port_state = STATE_RUN; 431 } 432 } 433 434 static void check_cmd(AHCIState *s, int port) 435 { 436 AHCIPortRegs *pr = &s->dev[port].port_regs; 437 int slot; 438 439 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 440 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 441 if ((pr->cmd_issue & (1U << slot)) && 442 !handle_cmd(s, port, slot)) { 443 pr->cmd_issue &= ~(1U << slot); 444 } 445 } 446 } 447 } 448 449 static void ahci_check_cmd_bh(void *opaque) 450 { 451 AHCIDevice *ad = opaque; 452 453 qemu_bh_delete(ad->check_bh); 454 ad->check_bh = NULL; 455 456 if ((ad->busy_slot != -1) && 457 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 458 /* no longer busy */ 459 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 460 ad->busy_slot = -1; 461 } 462 463 check_cmd(ad->hba, ad->port_no); 464 } 465 466 static void ahci_init_d2h(AHCIDevice *ad) 467 { 468 uint8_t init_fis[20]; 469 IDEState *ide_state = &ad->port.ifs[0]; 470 471 memset(init_fis, 0, sizeof(init_fis)); 472 473 init_fis[4] = 1; 474 init_fis[12] = 1; 475 476 if (ide_state->drive_kind == IDE_CD) { 477 init_fis[5] = ide_state->lcyl; 478 init_fis[6] = ide_state->hcyl; 479 } 480 481 ahci_write_fis_d2h(ad, init_fis); 482 } 483 484 static void ahci_reset_port(AHCIState *s, int port) 485 { 486 AHCIDevice *d = &s->dev[port]; 487 AHCIPortRegs *pr = &d->port_regs; 488 IDEState *ide_state = &d->port.ifs[0]; 489 int i; 490 491 DPRINTF(port, "reset port\n"); 492 493 ide_bus_reset(&d->port); 494 ide_state->ncq_queues = AHCI_MAX_CMDS; 495 496 pr->scr_stat = 0; 497 pr->scr_err = 0; 498 pr->scr_act = 0; 499 d->busy_slot = -1; 500 d->init_d2h_sent = false; 501 502 ide_state = &s->dev[port].port.ifs[0]; 503 if (!ide_state->bs) { 504 return; 505 } 506 507 /* reset ncq queue */ 508 for (i = 0; i < AHCI_MAX_CMDS; i++) { 509 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 510 if (!ncq_tfs->used) { 511 continue; 512 } 513 514 if (ncq_tfs->aiocb) { 515 bdrv_aio_cancel(ncq_tfs->aiocb); 516 ncq_tfs->aiocb = NULL; 517 } 518 519 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 520 if (!ncq_tfs->used) { 521 continue; 522 } 523 524 qemu_sglist_destroy(&ncq_tfs->sglist); 525 ncq_tfs->used = 0; 526 } 527 528 s->dev[port].port_state = STATE_RUN; 529 if (!ide_state->bs) { 530 s->dev[port].port_regs.sig = 0; 531 ide_state->status = SEEK_STAT | WRERR_STAT; 532 } else if (ide_state->drive_kind == IDE_CD) { 533 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 534 ide_state->lcyl = 0x14; 535 ide_state->hcyl = 0xeb; 536 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 537 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 538 } else { 539 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 540 ide_state->status = SEEK_STAT | WRERR_STAT; 541 } 542 543 ide_state->error = 1; 544 ahci_init_d2h(d); 545 } 546 547 static void debug_print_fis(uint8_t *fis, int cmd_len) 548 { 549 #ifdef DEBUG_AHCI 550 int i; 551 552 fprintf(stderr, "fis:"); 553 for (i = 0; i < cmd_len; i++) { 554 if ((i & 0xf) == 0) { 555 fprintf(stderr, "\n%02x:",i); 556 } 557 fprintf(stderr, "%02x ",fis[i]); 558 } 559 fprintf(stderr, "\n"); 560 #endif 561 } 562 563 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 564 { 565 AHCIPortRegs *pr = &s->dev[port].port_regs; 566 IDEState *ide_state; 567 uint8_t *sdb_fis; 568 569 if (!s->dev[port].res_fis || 570 !(pr->cmd & PORT_CMD_FIS_RX)) { 571 return; 572 } 573 574 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 575 ide_state = &s->dev[port].port.ifs[0]; 576 577 /* clear memory */ 578 *(uint32_t*)sdb_fis = 0; 579 580 /* write values */ 581 sdb_fis[0] = ide_state->error; 582 sdb_fis[2] = ide_state->status & 0x77; 583 s->dev[port].finished |= finished; 584 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 585 586 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS); 587 } 588 589 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 590 { 591 AHCIPortRegs *pr = &ad->port_regs; 592 uint8_t *d2h_fis; 593 int i; 594 dma_addr_t cmd_len = 0x80; 595 int cmd_mapped = 0; 596 597 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 598 return; 599 } 600 601 if (!cmd_fis) { 602 /* map cmd_fis */ 603 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 604 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 605 DMA_DIRECTION_TO_DEVICE); 606 cmd_mapped = 1; 607 } 608 609 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 610 611 d2h_fis[0] = 0x34; 612 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 613 d2h_fis[2] = ad->port.ifs[0].status; 614 d2h_fis[3] = ad->port.ifs[0].error; 615 616 d2h_fis[4] = cmd_fis[4]; 617 d2h_fis[5] = cmd_fis[5]; 618 d2h_fis[6] = cmd_fis[6]; 619 d2h_fis[7] = cmd_fis[7]; 620 d2h_fis[8] = cmd_fis[8]; 621 d2h_fis[9] = cmd_fis[9]; 622 d2h_fis[10] = cmd_fis[10]; 623 d2h_fis[11] = cmd_fis[11]; 624 d2h_fis[12] = cmd_fis[12]; 625 d2h_fis[13] = cmd_fis[13]; 626 for (i = 14; i < 20; i++) { 627 d2h_fis[i] = 0; 628 } 629 630 if (d2h_fis[2] & ERR_STAT) { 631 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES); 632 } 633 634 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 635 636 if (cmd_mapped) { 637 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 638 DMA_DIRECTION_TO_DEVICE, cmd_len); 639 } 640 } 641 642 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset) 643 { 644 AHCICmdHdr *cmd = ad->cur_cmd; 645 uint32_t opts = le32_to_cpu(cmd->opts); 646 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 647 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 648 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 649 dma_addr_t real_prdt_len = prdt_len; 650 uint8_t *prdt; 651 int i; 652 int r = 0; 653 int sum = 0; 654 int off_idx = -1; 655 int off_pos = -1; 656 int tbl_entry_size; 657 IDEBus *bus = &ad->port; 658 BusState *qbus = BUS(bus); 659 660 if (!sglist_alloc_hint) { 661 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 662 return -1; 663 } 664 665 /* map PRDT */ 666 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 667 DMA_DIRECTION_TO_DEVICE))){ 668 DPRINTF(ad->port_no, "map failed\n"); 669 return -1; 670 } 671 672 if (prdt_len < real_prdt_len) { 673 DPRINTF(ad->port_no, "mapped less than expected\n"); 674 r = -1; 675 goto out; 676 } 677 678 /* Get entries in the PRDT, init a qemu sglist accordingly */ 679 if (sglist_alloc_hint > 0) { 680 AHCI_SG *tbl = (AHCI_SG *)prdt; 681 sum = 0; 682 for (i = 0; i < sglist_alloc_hint; i++) { 683 /* flags_size is zero-based */ 684 tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1); 685 if (offset <= (sum + tbl_entry_size)) { 686 off_idx = i; 687 off_pos = offset - sum; 688 break; 689 } 690 sum += tbl_entry_size; 691 } 692 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 693 DPRINTF(ad->port_no, "%s: Incorrect offset! " 694 "off_idx: %d, off_pos: %d\n", 695 __func__, off_idx, off_pos); 696 r = -1; 697 goto out; 698 } 699 700 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx), 701 ad->hba->as); 702 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos), 703 le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos); 704 705 for (i = off_idx + 1; i < sglist_alloc_hint; i++) { 706 /* flags_size is zero-based */ 707 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 708 le32_to_cpu(tbl[i].flags_size) + 1); 709 } 710 } 711 712 out: 713 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 714 DMA_DIRECTION_TO_DEVICE, prdt_len); 715 return r; 716 } 717 718 static void ncq_cb(void *opaque, int ret) 719 { 720 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 721 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 722 723 /* Clear bit for this tag in SActive */ 724 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 725 726 if (ret < 0) { 727 /* error */ 728 ide_state->error = ABRT_ERR; 729 ide_state->status = READY_STAT | ERR_STAT; 730 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 731 } else { 732 ide_state->status = READY_STAT | SEEK_STAT; 733 } 734 735 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 736 (1 << ncq_tfs->tag)); 737 738 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 739 ncq_tfs->tag); 740 741 bdrv_acct_done(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct); 742 qemu_sglist_destroy(&ncq_tfs->sglist); 743 ncq_tfs->used = 0; 744 } 745 746 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 747 int slot) 748 { 749 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 750 uint8_t tag = ncq_fis->tag >> 3; 751 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 752 753 if (ncq_tfs->used) { 754 /* error - already in use */ 755 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 756 return; 757 } 758 759 ncq_tfs->used = 1; 760 ncq_tfs->drive = &s->dev[port]; 761 ncq_tfs->slot = slot; 762 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 763 ((uint64_t)ncq_fis->lba4 << 32) | 764 ((uint64_t)ncq_fis->lba3 << 24) | 765 ((uint64_t)ncq_fis->lba2 << 16) | 766 ((uint64_t)ncq_fis->lba1 << 8) | 767 (uint64_t)ncq_fis->lba0; 768 769 /* Note: We calculate the sector count, but don't currently rely on it. 770 * The total size of the DMA buffer tells us the transfer size instead. */ 771 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 772 ncq_fis->sector_count_low; 773 774 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 775 "drive max %"PRId64"\n", 776 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 777 s->dev[port].port.ifs[0].nb_sectors - 1); 778 779 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0); 780 ncq_tfs->tag = tag; 781 782 switch(ncq_fis->command) { 783 case READ_FPDMA_QUEUED: 784 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 785 "tag %d\n", 786 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 787 788 DPRINTF(port, "tag %d aio read %"PRId64"\n", 789 ncq_tfs->tag, ncq_tfs->lba); 790 791 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 792 &ncq_tfs->sglist, BDRV_ACCT_READ); 793 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 794 &ncq_tfs->sglist, ncq_tfs->lba, 795 ncq_cb, ncq_tfs); 796 break; 797 case WRITE_FPDMA_QUEUED: 798 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 799 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 800 801 DPRINTF(port, "tag %d aio write %"PRId64"\n", 802 ncq_tfs->tag, ncq_tfs->lba); 803 804 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 805 &ncq_tfs->sglist, BDRV_ACCT_WRITE); 806 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 807 &ncq_tfs->sglist, ncq_tfs->lba, 808 ncq_cb, ncq_tfs); 809 break; 810 default: 811 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 812 qemu_sglist_destroy(&ncq_tfs->sglist); 813 break; 814 } 815 } 816 817 static int handle_cmd(AHCIState *s, int port, int slot) 818 { 819 IDEState *ide_state; 820 uint32_t opts; 821 uint64_t tbl_addr; 822 AHCICmdHdr *cmd; 823 uint8_t *cmd_fis; 824 dma_addr_t cmd_len; 825 826 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 827 /* Engine currently busy, try again later */ 828 DPRINTF(port, "engine busy\n"); 829 return -1; 830 } 831 832 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 833 834 if (!s->dev[port].lst) { 835 DPRINTF(port, "error: lst not given but cmd handled"); 836 return -1; 837 } 838 839 /* remember current slot handle for later */ 840 s->dev[port].cur_cmd = cmd; 841 842 opts = le32_to_cpu(cmd->opts); 843 tbl_addr = le64_to_cpu(cmd->tbl_addr); 844 845 cmd_len = 0x80; 846 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 847 DMA_DIRECTION_FROM_DEVICE); 848 849 if (!cmd_fis) { 850 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 851 return -1; 852 } 853 854 /* The device we are working for */ 855 ide_state = &s->dev[port].port.ifs[0]; 856 857 if (!ide_state->bs) { 858 DPRINTF(port, "error: guest accessed unused port"); 859 goto out; 860 } 861 862 debug_print_fis(cmd_fis, 0x90); 863 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 864 865 switch (cmd_fis[0]) { 866 case SATA_FIS_TYPE_REGISTER_H2D: 867 break; 868 default: 869 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 870 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 871 cmd_fis[2]); 872 goto out; 873 break; 874 } 875 876 switch (cmd_fis[1]) { 877 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 878 break; 879 case 0: 880 break; 881 default: 882 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 883 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 884 cmd_fis[2]); 885 goto out; 886 break; 887 } 888 889 switch (s->dev[port].port_state) { 890 case STATE_RUN: 891 if (cmd_fis[15] & ATA_SRST) { 892 s->dev[port].port_state = STATE_RESET; 893 } 894 break; 895 case STATE_RESET: 896 if (!(cmd_fis[15] & ATA_SRST)) { 897 ahci_reset_port(s, port); 898 } 899 break; 900 } 901 902 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 903 904 /* Check for NCQ command */ 905 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 906 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 907 process_ncq_command(s, port, cmd_fis, slot); 908 goto out; 909 } 910 911 /* Decompose the FIS */ 912 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 913 ide_state->feature = cmd_fis[3]; 914 if (!ide_state->nsector) { 915 ide_state->nsector = 256; 916 } 917 918 if (ide_state->drive_kind != IDE_CD) { 919 /* 920 * We set the sector depending on the sector defined in the FIS. 921 * Unfortunately, the spec isn't exactly obvious on this one. 922 * 923 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 924 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 925 * such a command. 926 * 927 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 928 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 929 * a command. 930 * 931 * Since the spec doesn't explicitly state what each field should 932 * do, I simply assume non-used fields as reserved and OR everything 933 * together, independent of the command. 934 */ 935 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 936 | ((uint64_t)cmd_fis[9] << 32) 937 /* This is used for LBA48 commands */ 938 | ((uint64_t)cmd_fis[8] << 24) 939 /* This is used for non-LBA48 commands */ 940 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 941 | ((uint64_t)cmd_fis[6] << 16) 942 | ((uint64_t)cmd_fis[5] << 8) 943 | cmd_fis[4]); 944 } 945 946 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 947 * table to ide_state->io_buffer 948 */ 949 if (opts & AHCI_CMD_ATAPI) { 950 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 951 ide_state->lcyl = 0x14; 952 ide_state->hcyl = 0xeb; 953 debug_print_fis(ide_state->io_buffer, 0x10); 954 ide_state->feature = IDE_FEATURE_DMA; 955 s->dev[port].done_atapi_packet = false; 956 /* XXX send PIO setup FIS */ 957 } 958 959 ide_state->error = 0; 960 961 /* Reset transferred byte counter */ 962 cmd->status = 0; 963 964 /* We're ready to process the command in FIS byte 2. */ 965 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 966 967 if ((s->dev[port].port.ifs[0].status & (READY_STAT|DRQ_STAT|BUSY_STAT)) == 968 READY_STAT) { 969 ahci_write_fis_d2h(&s->dev[port], cmd_fis); 970 } 971 } 972 973 out: 974 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 975 cmd_len); 976 977 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 978 /* async command, complete later */ 979 s->dev[port].busy_slot = slot; 980 return -1; 981 } 982 983 /* done handling the command */ 984 return 0; 985 } 986 987 /* DMA dev <-> ram */ 988 static int ahci_start_transfer(IDEDMA *dma) 989 { 990 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 991 IDEState *s = &ad->port.ifs[0]; 992 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 993 /* write == ram -> device */ 994 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 995 int is_write = opts & AHCI_CMD_WRITE; 996 int is_atapi = opts & AHCI_CMD_ATAPI; 997 int has_sglist = 0; 998 999 if (is_atapi && !ad->done_atapi_packet) { 1000 /* already prepopulated iobuffer */ 1001 ad->done_atapi_packet = true; 1002 goto out; 1003 } 1004 1005 if (!ahci_populate_sglist(ad, &s->sg, 0)) { 1006 has_sglist = 1; 1007 } 1008 1009 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1010 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1011 has_sglist ? "" : "o"); 1012 1013 if (has_sglist && size) { 1014 if (is_write) { 1015 dma_buf_write(s->data_ptr, size, &s->sg); 1016 } else { 1017 dma_buf_read(s->data_ptr, size, &s->sg); 1018 } 1019 } 1020 1021 /* update number of transferred bytes */ 1022 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1023 1024 out: 1025 /* declare that we processed everything */ 1026 s->data_ptr = s->data_end; 1027 1028 if (has_sglist) { 1029 qemu_sglist_destroy(&s->sg); 1030 } 1031 1032 s->end_transfer_func(s); 1033 1034 if (!(s->status & DRQ_STAT)) { 1035 /* done with DMA */ 1036 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1043 BlockDriverCompletionFunc *dma_cb) 1044 { 1045 #ifdef DEBUG_AHCI 1046 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1047 #endif 1048 DPRINTF(ad->port_no, "\n"); 1049 s->io_buffer_offset = 0; 1050 dma_cb(s, 0); 1051 } 1052 1053 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1054 { 1055 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1056 IDEState *s = &ad->port.ifs[0]; 1057 1058 ahci_populate_sglist(ad, &s->sg, 0); 1059 s->io_buffer_size = s->sg.size; 1060 1061 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1062 return s->io_buffer_size != 0; 1063 } 1064 1065 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1066 { 1067 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1068 IDEState *s = &ad->port.ifs[0]; 1069 uint8_t *p = s->io_buffer + s->io_buffer_index; 1070 int l = s->io_buffer_size - s->io_buffer_index; 1071 1072 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) { 1073 return 0; 1074 } 1075 1076 if (is_write) { 1077 dma_buf_read(p, l, &s->sg); 1078 } else { 1079 dma_buf_write(p, l, &s->sg); 1080 } 1081 1082 /* free sglist that was created in ahci_populate_sglist() */ 1083 qemu_sglist_destroy(&s->sg); 1084 1085 /* update number of transferred bytes */ 1086 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1087 s->io_buffer_index += l; 1088 s->io_buffer_offset += l; 1089 1090 DPRINTF(ad->port_no, "len=%#x\n", l); 1091 1092 return 1; 1093 } 1094 1095 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1096 { 1097 /* only a single unit per link */ 1098 return 0; 1099 } 1100 1101 static int ahci_dma_add_status(IDEDMA *dma, int status) 1102 { 1103 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1104 DPRINTF(ad->port_no, "set status: %x\n", status); 1105 1106 if (status & BM_STATUS_INT) { 1107 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int ahci_dma_set_inactive(IDEDMA *dma) 1114 { 1115 return 0; 1116 } 1117 1118 static int ahci_async_cmd_done(IDEDMA *dma) 1119 { 1120 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1121 1122 DPRINTF(ad->port_no, "async cmd done\n"); 1123 1124 /* update d2h status */ 1125 ahci_write_fis_d2h(ad, NULL); 1126 1127 if (!ad->check_bh) { 1128 /* maybe we still have something to process, check later */ 1129 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1130 qemu_bh_schedule(ad->check_bh); 1131 } 1132 1133 return 0; 1134 } 1135 1136 static void ahci_irq_set(void *opaque, int n, int level) 1137 { 1138 } 1139 1140 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1141 { 1142 } 1143 1144 static int ahci_dma_reset(IDEDMA *dma) 1145 { 1146 return 0; 1147 } 1148 1149 static const IDEDMAOps ahci_dma_ops = { 1150 .start_dma = ahci_start_dma, 1151 .start_transfer = ahci_start_transfer, 1152 .prepare_buf = ahci_dma_prepare_buf, 1153 .rw_buf = ahci_dma_rw_buf, 1154 .set_unit = ahci_dma_set_unit, 1155 .add_status = ahci_dma_add_status, 1156 .set_inactive = ahci_dma_set_inactive, 1157 .async_cmd_done = ahci_async_cmd_done, 1158 .restart_cb = ahci_dma_restart_cb, 1159 .reset = ahci_dma_reset, 1160 }; 1161 1162 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1163 { 1164 qemu_irq *irqs; 1165 int i; 1166 1167 s->as = as; 1168 s->ports = ports; 1169 s->dev = g_malloc0(sizeof(AHCIDevice) * ports); 1170 ahci_reg_init(s); 1171 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1172 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1173 "ahci", AHCI_MEM_BAR_SIZE); 1174 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1175 "ahci-idp", 32); 1176 1177 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1178 1179 for (i = 0; i < s->ports; i++) { 1180 AHCIDevice *ad = &s->dev[i]; 1181 1182 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1183 ide_init2(&ad->port, irqs[i]); 1184 1185 ad->hba = s; 1186 ad->port_no = i; 1187 ad->port.dma = &ad->dma; 1188 ad->port.dma->ops = &ahci_dma_ops; 1189 } 1190 } 1191 1192 void ahci_uninit(AHCIState *s) 1193 { 1194 memory_region_destroy(&s->mem); 1195 memory_region_destroy(&s->idp); 1196 g_free(s->dev); 1197 } 1198 1199 void ahci_reset(AHCIState *s) 1200 { 1201 AHCIPortRegs *pr; 1202 int i; 1203 1204 s->control_regs.irqstatus = 0; 1205 /* AHCI Enable (AE) 1206 * The implementation of this bit is dependent upon the value of the 1207 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1208 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1209 * read-only and shall have a reset value of '1'. 1210 * 1211 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1212 */ 1213 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1214 1215 for (i = 0; i < s->ports; i++) { 1216 pr = &s->dev[i].port_regs; 1217 pr->irq_stat = 0; 1218 pr->irq_mask = 0; 1219 pr->scr_ctl = 0; 1220 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1221 ahci_reset_port(s, i); 1222 } 1223 } 1224 1225 static const VMStateDescription vmstate_ahci_device = { 1226 .name = "ahci port", 1227 .version_id = 1, 1228 .fields = (VMStateField[]) { 1229 VMSTATE_IDE_BUS(port, AHCIDevice), 1230 VMSTATE_UINT32(port_state, AHCIDevice), 1231 VMSTATE_UINT32(finished, AHCIDevice), 1232 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1233 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1234 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1235 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1236 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1237 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1238 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1239 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1240 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1241 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1242 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1243 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1244 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1245 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1246 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1247 VMSTATE_INT32(busy_slot, AHCIDevice), 1248 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1249 VMSTATE_END_OF_LIST() 1250 }, 1251 }; 1252 1253 static int ahci_state_post_load(void *opaque, int version_id) 1254 { 1255 int i; 1256 struct AHCIDevice *ad; 1257 AHCIState *s = opaque; 1258 1259 for (i = 0; i < s->ports; i++) { 1260 ad = &s->dev[i]; 1261 AHCIPortRegs *pr = &ad->port_regs; 1262 1263 map_page(&ad->lst, 1264 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 1265 map_page(&ad->res_fis, 1266 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 1267 /* 1268 * All pending i/o should be flushed out on a migrate. However, 1269 * we might not have cleared the busy_slot since this is done 1270 * in a bh. Also, issue i/o against any slots that are pending. 1271 */ 1272 if ((ad->busy_slot != -1) && 1273 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 1274 pr->cmd_issue &= ~(1 << ad->busy_slot); 1275 ad->busy_slot = -1; 1276 } 1277 check_cmd(s, i); 1278 } 1279 1280 return 0; 1281 } 1282 1283 const VMStateDescription vmstate_ahci = { 1284 .name = "ahci", 1285 .version_id = 1, 1286 .post_load = ahci_state_post_load, 1287 .fields = (VMStateField[]) { 1288 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1289 vmstate_ahci_device, AHCIDevice), 1290 VMSTATE_UINT32(control_regs.cap, AHCIState), 1291 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1292 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1293 VMSTATE_UINT32(control_regs.impl, AHCIState), 1294 VMSTATE_UINT32(control_regs.version, AHCIState), 1295 VMSTATE_UINT32(idp_index, AHCIState), 1296 VMSTATE_INT32_EQUAL(ports, AHCIState), 1297 VMSTATE_END_OF_LIST() 1298 }, 1299 }; 1300 1301 #define TYPE_SYSBUS_AHCI "sysbus-ahci" 1302 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 1303 1304 typedef struct SysbusAHCIState { 1305 /*< private >*/ 1306 SysBusDevice parent_obj; 1307 /*< public >*/ 1308 1309 AHCIState ahci; 1310 uint32_t num_ports; 1311 } SysbusAHCIState; 1312 1313 static const VMStateDescription vmstate_sysbus_ahci = { 1314 .name = "sysbus-ahci", 1315 .unmigratable = 1, /* Still buggy under I/O load */ 1316 .fields = (VMStateField[]) { 1317 VMSTATE_AHCI(ahci, SysbusAHCIState), 1318 VMSTATE_END_OF_LIST() 1319 }, 1320 }; 1321 1322 static void sysbus_ahci_reset(DeviceState *dev) 1323 { 1324 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1325 1326 ahci_reset(&s->ahci); 1327 } 1328 1329 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1330 { 1331 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1332 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1333 1334 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports); 1335 1336 sysbus_init_mmio(sbd, &s->ahci.mem); 1337 sysbus_init_irq(sbd, &s->ahci.irq); 1338 } 1339 1340 static Property sysbus_ahci_properties[] = { 1341 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1342 DEFINE_PROP_END_OF_LIST(), 1343 }; 1344 1345 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1346 { 1347 DeviceClass *dc = DEVICE_CLASS(klass); 1348 1349 dc->realize = sysbus_ahci_realize; 1350 dc->vmsd = &vmstate_sysbus_ahci; 1351 dc->props = sysbus_ahci_properties; 1352 dc->reset = sysbus_ahci_reset; 1353 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1354 } 1355 1356 static const TypeInfo sysbus_ahci_info = { 1357 .name = TYPE_SYSBUS_AHCI, 1358 .parent = TYPE_SYS_BUS_DEVICE, 1359 .instance_size = sizeof(SysbusAHCIState), 1360 .class_init = sysbus_ahci_class_init, 1361 }; 1362 1363 static void sysbus_ahci_register_types(void) 1364 { 1365 type_register_static(&sysbus_ahci_info); 1366 } 1367 1368 type_init(sysbus_ahci_register_types) 1369