1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/msi.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor.h" 31 #include "dma.h" 32 #include "cpu-common.h" 33 #include "internal.h" 34 #include <hw/ide/pci.h> 35 #include <hw/ide/ahci.h> 36 37 /* #define DEBUG_AHCI */ 38 39 #ifdef DEBUG_AHCI 40 #define DPRINTF(port, fmt, ...) \ 41 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 42 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 43 #else 44 #define DPRINTF(port, fmt, ...) do {} while(0) 45 #endif 46 47 static void check_cmd(AHCIState *s, int port); 48 static int handle_cmd(AHCIState *s,int port,int slot); 49 static void ahci_reset_port(AHCIState *s, int port); 50 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 51 static void ahci_init_d2h(AHCIDevice *ad); 52 53 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 54 { 55 uint32_t val; 56 AHCIPortRegs *pr; 57 pr = &s->dev[port].port_regs; 58 59 switch (offset) { 60 case PORT_LST_ADDR: 61 val = pr->lst_addr; 62 break; 63 case PORT_LST_ADDR_HI: 64 val = pr->lst_addr_hi; 65 break; 66 case PORT_FIS_ADDR: 67 val = pr->fis_addr; 68 break; 69 case PORT_FIS_ADDR_HI: 70 val = pr->fis_addr_hi; 71 break; 72 case PORT_IRQ_STAT: 73 val = pr->irq_stat; 74 break; 75 case PORT_IRQ_MASK: 76 val = pr->irq_mask; 77 break; 78 case PORT_CMD: 79 val = pr->cmd; 80 break; 81 case PORT_TFDATA: 82 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 83 s->dev[port].port.ifs[0].status; 84 break; 85 case PORT_SIG: 86 val = pr->sig; 87 break; 88 case PORT_SCR_STAT: 89 if (s->dev[port].port.ifs[0].bs) { 90 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 91 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 92 } else { 93 val = SATA_SCR_SSTATUS_DET_NODEV; 94 } 95 break; 96 case PORT_SCR_CTL: 97 val = pr->scr_ctl; 98 break; 99 case PORT_SCR_ERR: 100 val = pr->scr_err; 101 break; 102 case PORT_SCR_ACT: 103 pr->scr_act &= ~s->dev[port].finished; 104 s->dev[port].finished = 0; 105 val = pr->scr_act; 106 break; 107 case PORT_CMD_ISSUE: 108 val = pr->cmd_issue; 109 break; 110 case PORT_RESERVED: 111 default: 112 val = 0; 113 } 114 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 115 return val; 116 117 } 118 119 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 120 { 121 struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 122 123 DPRINTF(0, "raise irq\n"); 124 125 if (msi_enabled(&d->card)) { 126 msi_notify(&d->card, 0); 127 } else { 128 qemu_irq_raise(s->irq); 129 } 130 } 131 132 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 133 { 134 struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 135 136 DPRINTF(0, "lower irq\n"); 137 138 if (!msi_enabled(&d->card)) { 139 qemu_irq_lower(s->irq); 140 } 141 } 142 143 static void ahci_check_irq(AHCIState *s) 144 { 145 int i; 146 147 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 148 149 s->control_regs.irqstatus = 0; 150 for (i = 0; i < s->ports; i++) { 151 AHCIPortRegs *pr = &s->dev[i].port_regs; 152 if (pr->irq_stat & pr->irq_mask) { 153 s->control_regs.irqstatus |= (1 << i); 154 } 155 } 156 157 if (s->control_regs.irqstatus && 158 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 159 ahci_irq_raise(s, NULL); 160 } else { 161 ahci_irq_lower(s, NULL); 162 } 163 } 164 165 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 166 int irq_type) 167 { 168 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 169 irq_type, d->port_regs.irq_mask & irq_type); 170 171 d->port_regs.irq_stat |= irq_type; 172 ahci_check_irq(s); 173 } 174 175 static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted) 176 { 177 target_phys_addr_t len = wanted; 178 179 if (*ptr) { 180 cpu_physical_memory_unmap(*ptr, len, 1, len); 181 } 182 183 *ptr = cpu_physical_memory_map(addr, &len, 1); 184 if (len < wanted) { 185 cpu_physical_memory_unmap(*ptr, len, 1, len); 186 *ptr = NULL; 187 } 188 } 189 190 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 191 { 192 AHCIPortRegs *pr = &s->dev[port].port_regs; 193 194 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 195 switch (offset) { 196 case PORT_LST_ADDR: 197 pr->lst_addr = val; 198 map_page(&s->dev[port].lst, 199 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 200 s->dev[port].cur_cmd = NULL; 201 break; 202 case PORT_LST_ADDR_HI: 203 pr->lst_addr_hi = val; 204 map_page(&s->dev[port].lst, 205 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 206 s->dev[port].cur_cmd = NULL; 207 break; 208 case PORT_FIS_ADDR: 209 pr->fis_addr = val; 210 map_page(&s->dev[port].res_fis, 211 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 212 break; 213 case PORT_FIS_ADDR_HI: 214 pr->fis_addr_hi = val; 215 map_page(&s->dev[port].res_fis, 216 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 217 break; 218 case PORT_IRQ_STAT: 219 pr->irq_stat &= ~val; 220 ahci_check_irq(s); 221 break; 222 case PORT_IRQ_MASK: 223 pr->irq_mask = val & 0xfdc000ff; 224 ahci_check_irq(s); 225 break; 226 case PORT_CMD: 227 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 228 229 if (pr->cmd & PORT_CMD_START) { 230 pr->cmd |= PORT_CMD_LIST_ON; 231 } 232 233 if (pr->cmd & PORT_CMD_FIS_RX) { 234 pr->cmd |= PORT_CMD_FIS_ON; 235 } 236 237 /* XXX usually the FIS would be pending on the bus here and 238 issuing deferred until the OS enables FIS receival. 239 Instead, we only submit it once - which works in most 240 cases, but is a hack. */ 241 if ((pr->cmd & PORT_CMD_FIS_ON) && 242 !s->dev[port].init_d2h_sent) { 243 ahci_init_d2h(&s->dev[port]); 244 s->dev[port].init_d2h_sent = 1; 245 } 246 247 check_cmd(s, port); 248 break; 249 case PORT_TFDATA: 250 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 251 s->dev[port].port.ifs[0].status = val & 0xff; 252 break; 253 case PORT_SIG: 254 pr->sig = val; 255 break; 256 case PORT_SCR_STAT: 257 pr->scr_stat = val; 258 break; 259 case PORT_SCR_CTL: 260 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 261 ((val & AHCI_SCR_SCTL_DET) == 0)) { 262 ahci_reset_port(s, port); 263 } 264 pr->scr_ctl = val; 265 break; 266 case PORT_SCR_ERR: 267 pr->scr_err &= ~val; 268 break; 269 case PORT_SCR_ACT: 270 /* RW1 */ 271 pr->scr_act |= val; 272 break; 273 case PORT_CMD_ISSUE: 274 pr->cmd_issue |= val; 275 check_cmd(s, port); 276 break; 277 default: 278 break; 279 } 280 } 281 282 static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr, 283 unsigned size) 284 { 285 AHCIState *s = opaque; 286 uint32_t val = 0; 287 288 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 289 switch (addr) { 290 case HOST_CAP: 291 val = s->control_regs.cap; 292 break; 293 case HOST_CTL: 294 val = s->control_regs.ghc; 295 break; 296 case HOST_IRQ_STAT: 297 val = s->control_regs.irqstatus; 298 break; 299 case HOST_PORTS_IMPL: 300 val = s->control_regs.impl; 301 break; 302 case HOST_VERSION: 303 val = s->control_regs.version; 304 break; 305 } 306 307 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 308 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 309 (addr < (AHCI_PORT_REGS_START_ADDR + 310 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 311 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 312 addr & AHCI_PORT_ADDR_OFFSET_MASK); 313 } 314 315 return val; 316 } 317 318 319 320 static void ahci_mem_write(void *opaque, target_phys_addr_t addr, 321 uint64_t val, unsigned size) 322 { 323 AHCIState *s = opaque; 324 325 /* Only aligned reads are allowed on AHCI */ 326 if (addr & 3) { 327 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 328 TARGET_FMT_plx "\n", addr); 329 return; 330 } 331 332 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 333 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 334 335 switch (addr) { 336 case HOST_CAP: /* R/WO, RO */ 337 /* FIXME handle R/WO */ 338 break; 339 case HOST_CTL: /* R/W */ 340 if (val & HOST_CTL_RESET) { 341 DPRINTF(-1, "HBA Reset\n"); 342 ahci_reset(container_of(s, AHCIPCIState, ahci)); 343 } else { 344 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 345 ahci_check_irq(s); 346 } 347 break; 348 case HOST_IRQ_STAT: /* R/WC, RO */ 349 s->control_regs.irqstatus &= ~val; 350 ahci_check_irq(s); 351 break; 352 case HOST_PORTS_IMPL: /* R/WO, RO */ 353 /* FIXME handle R/WO */ 354 break; 355 case HOST_VERSION: /* RO */ 356 /* FIXME report write? */ 357 break; 358 default: 359 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 360 } 361 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 362 (addr < (AHCI_PORT_REGS_START_ADDR + 363 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 364 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 365 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 366 } 367 368 } 369 370 static MemoryRegionOps ahci_mem_ops = { 371 .read = ahci_mem_read, 372 .write = ahci_mem_write, 373 .endianness = DEVICE_LITTLE_ENDIAN, 374 }; 375 376 static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr, 377 unsigned size) 378 { 379 AHCIState *s = opaque; 380 381 if (addr == s->idp_offset) { 382 /* index register */ 383 return s->idp_index; 384 } else if (addr == s->idp_offset + 4) { 385 /* data register - do memory read at location selected by index */ 386 return ahci_mem_read(opaque, s->idp_index, size); 387 } else { 388 return 0; 389 } 390 } 391 392 static void ahci_idp_write(void *opaque, target_phys_addr_t addr, 393 uint64_t val, unsigned size) 394 { 395 AHCIState *s = opaque; 396 397 if (addr == s->idp_offset) { 398 /* index register - mask off reserved bits */ 399 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 400 } else if (addr == s->idp_offset + 4) { 401 /* data register - do memory write at location selected by index */ 402 ahci_mem_write(opaque, s->idp_index, val, size); 403 } 404 } 405 406 static MemoryRegionOps ahci_idp_ops = { 407 .read = ahci_idp_read, 408 .write = ahci_idp_write, 409 .endianness = DEVICE_LITTLE_ENDIAN, 410 }; 411 412 413 static void ahci_reg_init(AHCIState *s) 414 { 415 int i; 416 417 s->control_regs.cap = (s->ports - 1) | 418 (AHCI_NUM_COMMAND_SLOTS << 8) | 419 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 420 HOST_CAP_NCQ | HOST_CAP_AHCI; 421 422 s->control_regs.impl = (1 << s->ports) - 1; 423 424 s->control_regs.version = AHCI_VERSION_1_0; 425 426 for (i = 0; i < s->ports; i++) { 427 s->dev[i].port_state = STATE_RUN; 428 } 429 } 430 431 static uint32_t read_from_sglist(uint8_t *buffer, uint32_t len, 432 QEMUSGList *sglist) 433 { 434 uint32_t i = 0; 435 uint32_t total = 0, once; 436 ScatterGatherEntry *cur_prd; 437 uint32_t sgcount; 438 439 cur_prd = sglist->sg; 440 sgcount = sglist->nsg; 441 for (i = 0; len && sgcount; i++) { 442 once = MIN(cur_prd->len, len); 443 cpu_physical_memory_read(cur_prd->base, buffer, once); 444 cur_prd++; 445 sgcount--; 446 len -= once; 447 buffer += once; 448 total += once; 449 } 450 451 return total; 452 } 453 454 static uint32_t write_to_sglist(uint8_t *buffer, uint32_t len, 455 QEMUSGList *sglist) 456 { 457 uint32_t i = 0; 458 uint32_t total = 0, once; 459 ScatterGatherEntry *cur_prd; 460 uint32_t sgcount; 461 462 DPRINTF(-1, "total: 0x%x bytes\n", len); 463 464 cur_prd = sglist->sg; 465 sgcount = sglist->nsg; 466 for (i = 0; len && sgcount; i++) { 467 once = MIN(cur_prd->len, len); 468 DPRINTF(-1, "write 0x%x bytes to 0x%lx\n", once, (long)cur_prd->base); 469 cpu_physical_memory_write(cur_prd->base, buffer, once); 470 cur_prd++; 471 sgcount--; 472 len -= once; 473 buffer += once; 474 total += once; 475 } 476 477 return total; 478 } 479 480 static void check_cmd(AHCIState *s, int port) 481 { 482 AHCIPortRegs *pr = &s->dev[port].port_regs; 483 int slot; 484 485 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 486 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 487 if ((pr->cmd_issue & (1 << slot)) && 488 !handle_cmd(s, port, slot)) { 489 pr->cmd_issue &= ~(1 << slot); 490 } 491 } 492 } 493 } 494 495 static void ahci_check_cmd_bh(void *opaque) 496 { 497 AHCIDevice *ad = opaque; 498 499 qemu_bh_delete(ad->check_bh); 500 ad->check_bh = NULL; 501 502 if ((ad->busy_slot != -1) && 503 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 504 /* no longer busy */ 505 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 506 ad->busy_slot = -1; 507 } 508 509 check_cmd(ad->hba, ad->port_no); 510 } 511 512 static void ahci_init_d2h(AHCIDevice *ad) 513 { 514 uint8_t init_fis[0x20]; 515 IDEState *ide_state = &ad->port.ifs[0]; 516 517 memset(init_fis, 0, sizeof(init_fis)); 518 519 init_fis[4] = 1; 520 init_fis[12] = 1; 521 522 if (ide_state->drive_kind == IDE_CD) { 523 init_fis[5] = ide_state->lcyl; 524 init_fis[6] = ide_state->hcyl; 525 } 526 527 ahci_write_fis_d2h(ad, init_fis); 528 } 529 530 static void ahci_reset_port(AHCIState *s, int port) 531 { 532 AHCIDevice *d = &s->dev[port]; 533 AHCIPortRegs *pr = &d->port_regs; 534 IDEState *ide_state = &d->port.ifs[0]; 535 int i; 536 537 DPRINTF(port, "reset port\n"); 538 539 ide_bus_reset(&d->port); 540 ide_state->ncq_queues = AHCI_MAX_CMDS; 541 542 pr->scr_stat = 0; 543 pr->scr_err = 0; 544 pr->scr_act = 0; 545 d->busy_slot = -1; 546 d->init_d2h_sent = 0; 547 548 ide_state = &s->dev[port].port.ifs[0]; 549 if (!ide_state->bs) { 550 return; 551 } 552 553 /* reset ncq queue */ 554 for (i = 0; i < AHCI_MAX_CMDS; i++) { 555 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 556 if (!ncq_tfs->used) { 557 continue; 558 } 559 560 if (ncq_tfs->aiocb) { 561 bdrv_aio_cancel(ncq_tfs->aiocb); 562 ncq_tfs->aiocb = NULL; 563 } 564 565 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 566 if (!ncq_tfs->used) { 567 continue; 568 } 569 570 qemu_sglist_destroy(&ncq_tfs->sglist); 571 ncq_tfs->used = 0; 572 } 573 574 s->dev[port].port_state = STATE_RUN; 575 if (!ide_state->bs) { 576 s->dev[port].port_regs.sig = 0; 577 ide_state->status = SEEK_STAT | WRERR_STAT; 578 } else if (ide_state->drive_kind == IDE_CD) { 579 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 580 ide_state->lcyl = 0x14; 581 ide_state->hcyl = 0xeb; 582 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 583 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 584 } else { 585 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 586 ide_state->status = SEEK_STAT | WRERR_STAT; 587 } 588 589 ide_state->error = 1; 590 ahci_init_d2h(d); 591 } 592 593 static void debug_print_fis(uint8_t *fis, int cmd_len) 594 { 595 #ifdef DEBUG_AHCI 596 int i; 597 598 fprintf(stderr, "fis:"); 599 for (i = 0; i < cmd_len; i++) { 600 if ((i & 0xf) == 0) { 601 fprintf(stderr, "\n%02x:",i); 602 } 603 fprintf(stderr, "%02x ",fis[i]); 604 } 605 fprintf(stderr, "\n"); 606 #endif 607 } 608 609 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 610 { 611 AHCIPortRegs *pr = &s->dev[port].port_regs; 612 IDEState *ide_state; 613 uint8_t *sdb_fis; 614 615 if (!s->dev[port].res_fis || 616 !(pr->cmd & PORT_CMD_FIS_RX)) { 617 return; 618 } 619 620 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 621 ide_state = &s->dev[port].port.ifs[0]; 622 623 /* clear memory */ 624 *(uint32_t*)sdb_fis = 0; 625 626 /* write values */ 627 sdb_fis[0] = ide_state->error; 628 sdb_fis[2] = ide_state->status & 0x77; 629 s->dev[port].finished |= finished; 630 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 631 632 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS); 633 } 634 635 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 636 { 637 AHCIPortRegs *pr = &ad->port_regs; 638 uint8_t *d2h_fis; 639 int i; 640 target_phys_addr_t cmd_len = 0x80; 641 int cmd_mapped = 0; 642 643 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 644 return; 645 } 646 647 if (!cmd_fis) { 648 /* map cmd_fis */ 649 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 650 cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 0); 651 cmd_mapped = 1; 652 } 653 654 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 655 656 d2h_fis[0] = 0x34; 657 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 658 d2h_fis[2] = ad->port.ifs[0].status; 659 d2h_fis[3] = ad->port.ifs[0].error; 660 661 d2h_fis[4] = cmd_fis[4]; 662 d2h_fis[5] = cmd_fis[5]; 663 d2h_fis[6] = cmd_fis[6]; 664 d2h_fis[7] = cmd_fis[7]; 665 d2h_fis[8] = cmd_fis[8]; 666 d2h_fis[9] = cmd_fis[9]; 667 d2h_fis[10] = cmd_fis[10]; 668 d2h_fis[11] = cmd_fis[11]; 669 d2h_fis[12] = cmd_fis[12]; 670 d2h_fis[13] = cmd_fis[13]; 671 for (i = 14; i < 0x20; i++) { 672 d2h_fis[i] = 0; 673 } 674 675 if (d2h_fis[2] & ERR_STAT) { 676 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES); 677 } 678 679 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 680 681 if (cmd_mapped) { 682 cpu_physical_memory_unmap(cmd_fis, cmd_len, 0, cmd_len); 683 } 684 } 685 686 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist) 687 { 688 AHCICmdHdr *cmd = ad->cur_cmd; 689 uint32_t opts = le32_to_cpu(cmd->opts); 690 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 691 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 692 target_phys_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 693 target_phys_addr_t real_prdt_len = prdt_len; 694 uint8_t *prdt; 695 int i; 696 int r = 0; 697 698 if (!sglist_alloc_hint) { 699 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 700 return -1; 701 } 702 703 /* map PRDT */ 704 if (!(prdt = cpu_physical_memory_map(prdt_addr, &prdt_len, 0))){ 705 DPRINTF(ad->port_no, "map failed\n"); 706 return -1; 707 } 708 709 if (prdt_len < real_prdt_len) { 710 DPRINTF(ad->port_no, "mapped less than expected\n"); 711 r = -1; 712 goto out; 713 } 714 715 /* Get entries in the PRDT, init a qemu sglist accordingly */ 716 if (sglist_alloc_hint > 0) { 717 AHCI_SG *tbl = (AHCI_SG *)prdt; 718 719 qemu_sglist_init(sglist, sglist_alloc_hint); 720 for (i = 0; i < sglist_alloc_hint; i++) { 721 /* flags_size is zero-based */ 722 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 723 le32_to_cpu(tbl[i].flags_size) + 1); 724 } 725 } 726 727 out: 728 cpu_physical_memory_unmap(prdt, prdt_len, 0, prdt_len); 729 return r; 730 } 731 732 static void ncq_cb(void *opaque, int ret) 733 { 734 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 735 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 736 737 /* Clear bit for this tag in SActive */ 738 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 739 740 if (ret < 0) { 741 /* error */ 742 ide_state->error = ABRT_ERR; 743 ide_state->status = READY_STAT | ERR_STAT; 744 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 745 } else { 746 ide_state->status = READY_STAT | SEEK_STAT; 747 } 748 749 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 750 (1 << ncq_tfs->tag)); 751 752 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 753 ncq_tfs->tag); 754 755 bdrv_acct_done(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct); 756 qemu_sglist_destroy(&ncq_tfs->sglist); 757 ncq_tfs->used = 0; 758 } 759 760 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 761 int slot) 762 { 763 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 764 uint8_t tag = ncq_fis->tag >> 3; 765 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 766 767 if (ncq_tfs->used) { 768 /* error - already in use */ 769 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 770 return; 771 } 772 773 ncq_tfs->used = 1; 774 ncq_tfs->drive = &s->dev[port]; 775 ncq_tfs->slot = slot; 776 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 777 ((uint64_t)ncq_fis->lba4 << 32) | 778 ((uint64_t)ncq_fis->lba3 << 24) | 779 ((uint64_t)ncq_fis->lba2 << 16) | 780 ((uint64_t)ncq_fis->lba1 << 8) | 781 (uint64_t)ncq_fis->lba0; 782 783 /* Note: We calculate the sector count, but don't currently rely on it. 784 * The total size of the DMA buffer tells us the transfer size instead. */ 785 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 786 ncq_fis->sector_count_low; 787 788 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 789 "drive max %"PRId64"\n", 790 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 791 s->dev[port].port.ifs[0].nb_sectors - 1); 792 793 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist); 794 ncq_tfs->tag = tag; 795 796 switch(ncq_fis->command) { 797 case READ_FPDMA_QUEUED: 798 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 799 "tag %d\n", 800 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 801 802 DPRINTF(port, "tag %d aio read %"PRId64"\n", 803 ncq_tfs->tag, ncq_tfs->lba); 804 805 bdrv_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 806 (ncq_tfs->sector_count-1) * BDRV_SECTOR_SIZE, 807 BDRV_ACCT_READ); 808 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 809 &ncq_tfs->sglist, ncq_tfs->lba, 810 ncq_cb, ncq_tfs); 811 break; 812 case WRITE_FPDMA_QUEUED: 813 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 814 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 815 816 DPRINTF(port, "tag %d aio write %"PRId64"\n", 817 ncq_tfs->tag, ncq_tfs->lba); 818 819 bdrv_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 820 (ncq_tfs->sector_count-1) * BDRV_SECTOR_SIZE, 821 BDRV_ACCT_WRITE); 822 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 823 &ncq_tfs->sglist, ncq_tfs->lba, 824 ncq_cb, ncq_tfs); 825 break; 826 default: 827 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 828 qemu_sglist_destroy(&ncq_tfs->sglist); 829 break; 830 } 831 } 832 833 static int handle_cmd(AHCIState *s, int port, int slot) 834 { 835 IDEState *ide_state; 836 uint32_t opts; 837 uint64_t tbl_addr; 838 AHCICmdHdr *cmd; 839 uint8_t *cmd_fis; 840 target_phys_addr_t cmd_len; 841 842 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 843 /* Engine currently busy, try again later */ 844 DPRINTF(port, "engine busy\n"); 845 return -1; 846 } 847 848 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 849 850 if (!s->dev[port].lst) { 851 DPRINTF(port, "error: lst not given but cmd handled"); 852 return -1; 853 } 854 855 /* remember current slot handle for later */ 856 s->dev[port].cur_cmd = cmd; 857 858 opts = le32_to_cpu(cmd->opts); 859 tbl_addr = le64_to_cpu(cmd->tbl_addr); 860 861 cmd_len = 0x80; 862 cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 1); 863 864 if (!cmd_fis) { 865 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 866 return -1; 867 } 868 869 /* The device we are working for */ 870 ide_state = &s->dev[port].port.ifs[0]; 871 872 if (!ide_state->bs) { 873 DPRINTF(port, "error: guest accessed unused port"); 874 goto out; 875 } 876 877 debug_print_fis(cmd_fis, 0x90); 878 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 879 880 switch (cmd_fis[0]) { 881 case SATA_FIS_TYPE_REGISTER_H2D: 882 break; 883 default: 884 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 885 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 886 cmd_fis[2]); 887 goto out; 888 break; 889 } 890 891 switch (cmd_fis[1]) { 892 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 893 break; 894 case 0: 895 break; 896 default: 897 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 898 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 899 cmd_fis[2]); 900 goto out; 901 break; 902 } 903 904 switch (s->dev[port].port_state) { 905 case STATE_RUN: 906 if (cmd_fis[15] & ATA_SRST) { 907 s->dev[port].port_state = STATE_RESET; 908 } 909 break; 910 case STATE_RESET: 911 if (!(cmd_fis[15] & ATA_SRST)) { 912 ahci_reset_port(s, port); 913 } 914 break; 915 } 916 917 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 918 919 /* Check for NCQ command */ 920 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 921 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 922 process_ncq_command(s, port, cmd_fis, slot); 923 goto out; 924 } 925 926 /* Decompose the FIS */ 927 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 928 ide_state->feature = cmd_fis[3]; 929 if (!ide_state->nsector) { 930 ide_state->nsector = 256; 931 } 932 933 if (ide_state->drive_kind != IDE_CD) { 934 /* 935 * We set the sector depending on the sector defined in the FIS. 936 * Unfortunately, the spec isn't exactly obvious on this one. 937 * 938 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 939 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 940 * such a command. 941 * 942 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 943 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 944 * a command. 945 * 946 * Since the spec doesn't explicitly state what each field should 947 * do, I simply assume non-used fields as reserved and OR everything 948 * together, independent of the command. 949 */ 950 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 951 | ((uint64_t)cmd_fis[9] << 32) 952 /* This is used for LBA48 commands */ 953 | ((uint64_t)cmd_fis[8] << 24) 954 /* This is used for non-LBA48 commands */ 955 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 956 | ((uint64_t)cmd_fis[6] << 16) 957 | ((uint64_t)cmd_fis[5] << 8) 958 | cmd_fis[4]); 959 } 960 961 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 962 * table to ide_state->io_buffer 963 */ 964 if (opts & AHCI_CMD_ATAPI) { 965 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 966 ide_state->lcyl = 0x14; 967 ide_state->hcyl = 0xeb; 968 debug_print_fis(ide_state->io_buffer, 0x10); 969 ide_state->feature = IDE_FEATURE_DMA; 970 s->dev[port].done_atapi_packet = 0; 971 /* XXX send PIO setup FIS */ 972 } 973 974 ide_state->error = 0; 975 976 /* Reset transferred byte counter */ 977 cmd->status = 0; 978 979 /* We're ready to process the command in FIS byte 2. */ 980 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 981 982 if (s->dev[port].port.ifs[0].status & READY_STAT) { 983 ahci_write_fis_d2h(&s->dev[port], cmd_fis); 984 } 985 } 986 987 out: 988 cpu_physical_memory_unmap(cmd_fis, cmd_len, 1, cmd_len); 989 990 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 991 /* async command, complete later */ 992 s->dev[port].busy_slot = slot; 993 return -1; 994 } 995 996 /* done handling the command */ 997 return 0; 998 } 999 1000 /* DMA dev <-> ram */ 1001 static int ahci_start_transfer(IDEDMA *dma) 1002 { 1003 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1004 IDEState *s = &ad->port.ifs[0]; 1005 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1006 /* write == ram -> device */ 1007 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 1008 int is_write = opts & AHCI_CMD_WRITE; 1009 int is_atapi = opts & AHCI_CMD_ATAPI; 1010 int has_sglist = 0; 1011 1012 if (is_atapi && !ad->done_atapi_packet) { 1013 /* already prepopulated iobuffer */ 1014 ad->done_atapi_packet = 1; 1015 goto out; 1016 } 1017 1018 if (!ahci_populate_sglist(ad, &s->sg)) { 1019 has_sglist = 1; 1020 } 1021 1022 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1023 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1024 has_sglist ? "" : "o"); 1025 1026 if (is_write && has_sglist && (s->data_ptr < s->data_end)) { 1027 read_from_sglist(s->data_ptr, size, &s->sg); 1028 } 1029 1030 if (!is_write && has_sglist && (s->data_ptr < s->data_end)) { 1031 write_to_sglist(s->data_ptr, size, &s->sg); 1032 } 1033 1034 /* update number of transferred bytes */ 1035 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1036 1037 out: 1038 /* declare that we processed everything */ 1039 s->data_ptr = s->data_end; 1040 1041 if (has_sglist) { 1042 qemu_sglist_destroy(&s->sg); 1043 } 1044 1045 s->end_transfer_func(s); 1046 1047 if (!(s->status & DRQ_STAT)) { 1048 /* done with DMA */ 1049 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1050 } 1051 1052 return 0; 1053 } 1054 1055 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1056 BlockDriverCompletionFunc *dma_cb) 1057 { 1058 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1059 1060 DPRINTF(ad->port_no, "\n"); 1061 ad->dma_cb = dma_cb; 1062 ad->dma_status |= BM_STATUS_DMAING; 1063 dma_cb(s, 0); 1064 } 1065 1066 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1067 { 1068 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1069 IDEState *s = &ad->port.ifs[0]; 1070 int i; 1071 1072 ahci_populate_sglist(ad, &s->sg); 1073 1074 s->io_buffer_size = 0; 1075 for (i = 0; i < s->sg.nsg; i++) { 1076 s->io_buffer_size += s->sg.sg[i].len; 1077 } 1078 1079 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1080 return s->io_buffer_size != 0; 1081 } 1082 1083 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1084 { 1085 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1086 IDEState *s = &ad->port.ifs[0]; 1087 uint8_t *p = s->io_buffer + s->io_buffer_index; 1088 int l = s->io_buffer_size - s->io_buffer_index; 1089 1090 if (ahci_populate_sglist(ad, &s->sg)) { 1091 return 0; 1092 } 1093 1094 if (is_write) { 1095 write_to_sglist(p, l, &s->sg); 1096 } else { 1097 read_from_sglist(p, l, &s->sg); 1098 } 1099 1100 /* update number of transferred bytes */ 1101 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1102 s->io_buffer_index += l; 1103 1104 DPRINTF(ad->port_no, "len=%#x\n", l); 1105 1106 return 1; 1107 } 1108 1109 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1110 { 1111 /* only a single unit per link */ 1112 return 0; 1113 } 1114 1115 static int ahci_dma_add_status(IDEDMA *dma, int status) 1116 { 1117 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1118 ad->dma_status |= status; 1119 DPRINTF(ad->port_no, "set status: %x\n", status); 1120 1121 if (status & BM_STATUS_INT) { 1122 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int ahci_dma_set_inactive(IDEDMA *dma) 1129 { 1130 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1131 1132 DPRINTF(ad->port_no, "dma done\n"); 1133 1134 /* update d2h status */ 1135 ahci_write_fis_d2h(ad, NULL); 1136 1137 ad->dma_cb = NULL; 1138 1139 if (!ad->check_bh) { 1140 /* maybe we still have something to process, check later */ 1141 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1142 qemu_bh_schedule(ad->check_bh); 1143 } 1144 1145 return 0; 1146 } 1147 1148 static void ahci_irq_set(void *opaque, int n, int level) 1149 { 1150 } 1151 1152 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1153 { 1154 } 1155 1156 static int ahci_dma_reset(IDEDMA *dma) 1157 { 1158 return 0; 1159 } 1160 1161 static const IDEDMAOps ahci_dma_ops = { 1162 .start_dma = ahci_start_dma, 1163 .start_transfer = ahci_start_transfer, 1164 .prepare_buf = ahci_dma_prepare_buf, 1165 .rw_buf = ahci_dma_rw_buf, 1166 .set_unit = ahci_dma_set_unit, 1167 .add_status = ahci_dma_add_status, 1168 .set_inactive = ahci_dma_set_inactive, 1169 .restart_cb = ahci_dma_restart_cb, 1170 .reset = ahci_dma_reset, 1171 }; 1172 1173 void ahci_init(AHCIState *s, DeviceState *qdev, int ports) 1174 { 1175 qemu_irq *irqs; 1176 int i; 1177 1178 s->ports = ports; 1179 s->dev = g_malloc0(sizeof(AHCIDevice) * ports); 1180 ahci_reg_init(s); 1181 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1182 memory_region_init_io(&s->mem, &ahci_mem_ops, s, "ahci", AHCI_MEM_BAR_SIZE); 1183 memory_region_init_io(&s->idp, &ahci_idp_ops, s, "ahci-idp", 32); 1184 1185 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1186 1187 for (i = 0; i < s->ports; i++) { 1188 AHCIDevice *ad = &s->dev[i]; 1189 1190 ide_bus_new(&ad->port, qdev, i); 1191 ide_init2(&ad->port, irqs[i]); 1192 1193 ad->hba = s; 1194 ad->port_no = i; 1195 ad->port.dma = &ad->dma; 1196 ad->port.dma->ops = &ahci_dma_ops; 1197 ad->port_regs.cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1198 } 1199 } 1200 1201 void ahci_uninit(AHCIState *s) 1202 { 1203 memory_region_destroy(&s->mem); 1204 memory_region_destroy(&s->idp); 1205 g_free(s->dev); 1206 } 1207 1208 void ahci_reset(void *opaque) 1209 { 1210 struct AHCIPCIState *d = opaque; 1211 AHCIPortRegs *pr; 1212 int i; 1213 1214 d->ahci.control_regs.irqstatus = 0; 1215 d->ahci.control_regs.ghc = 0; 1216 1217 for (i = 0; i < d->ahci.ports; i++) { 1218 pr = &d->ahci.dev[i].port_regs; 1219 pr->irq_stat = 0; 1220 pr->irq_mask = 0; 1221 pr->scr_ctl = 0; 1222 ahci_reset_port(&d->ahci, i); 1223 } 1224 } 1225 1226 typedef struct SysbusAHCIState { 1227 SysBusDevice busdev; 1228 AHCIState ahci; 1229 uint32_t num_ports; 1230 } SysbusAHCIState; 1231 1232 static const VMStateDescription vmstate_sysbus_ahci = { 1233 .name = "sysbus-ahci", 1234 .unmigratable = 1, 1235 }; 1236 1237 static int sysbus_ahci_init(SysBusDevice *dev) 1238 { 1239 SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev); 1240 ahci_init(&s->ahci, &dev->qdev, s->num_ports); 1241 1242 sysbus_init_mmio(dev, &s->ahci.mem); 1243 sysbus_init_irq(dev, &s->ahci.irq); 1244 1245 qemu_register_reset(ahci_reset, &s->ahci); 1246 return 0; 1247 } 1248 1249 static Property sysbus_ahci_properties[] = { 1250 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1251 DEFINE_PROP_END_OF_LIST(), 1252 }; 1253 1254 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1255 { 1256 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 1257 DeviceClass *dc = DEVICE_CLASS(klass); 1258 1259 sbc->init = sysbus_ahci_init; 1260 dc->vmsd = &vmstate_sysbus_ahci; 1261 dc->props = sysbus_ahci_properties; 1262 } 1263 1264 static TypeInfo sysbus_ahci_info = { 1265 .name = "sysbus-ahci", 1266 .parent = TYPE_SYS_BUS_DEVICE, 1267 .instance_size = sizeof(SysbusAHCIState), 1268 .class_init = sysbus_ahci_class_init, 1269 }; 1270 1271 static void sysbus_ahci_register_types(void) 1272 { 1273 type_register_static(&sysbus_ahci_info); 1274 } 1275 1276 type_init(sysbus_ahci_register_types) 1277