1 /* 2 * QEMU SiI3112A PCI to Serial ATA Controller Emulation 3 * 4 * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * 9 */ 10 11 /* For documentation on this and similar cards see: 12 * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/ide/pci.h" 17 #include "qemu/module.h" 18 #include "trace.h" 19 #include "qom/object.h" 20 21 #define TYPE_SII3112_PCI "sii3112" 22 typedef struct SiI3112PCIState SiI3112PCIState; 23 DECLARE_INSTANCE_CHECKER(SiI3112PCIState, SII3112_PCI, 24 TYPE_SII3112_PCI) 25 26 typedef struct SiI3112Regs { 27 uint32_t confstat; 28 uint32_t scontrol; 29 uint16_t sien; 30 uint8_t swdata; 31 } SiI3112Regs; 32 33 struct SiI3112PCIState { 34 PCIIDEState i; 35 MemoryRegion mmio; 36 SiI3112Regs regs[2]; 37 }; 38 39 /* The sii3112_reg_read and sii3112_reg_write functions implement the 40 * Internal Register Space - BAR5 (section 6.7 of the data sheet). 41 */ 42 43 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, 44 unsigned int size) 45 { 46 SiI3112PCIState *d = opaque; 47 uint64_t val; 48 49 switch (addr) { 50 case 0x00: 51 val = d->i.bmdma[0].cmd; 52 break; 53 case 0x01: 54 val = d->regs[0].swdata; 55 break; 56 case 0x02: 57 val = d->i.bmdma[0].status; 58 break; 59 case 0x03: 60 val = 0; 61 break; 62 case 0x04 ... 0x07: 63 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); 64 break; 65 case 0x08: 66 val = d->i.bmdma[1].cmd; 67 break; 68 case 0x09: 69 val = d->regs[1].swdata; 70 break; 71 case 0x0a: 72 val = d->i.bmdma[1].status; 73 break; 74 case 0x0b: 75 val = 0; 76 break; 77 case 0x0c ... 0x0f: 78 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); 79 break; 80 case 0x10: 81 val = d->i.bmdma[0].cmd; 82 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ 83 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ 84 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); 85 val |= (uint32_t)d->i.bmdma[0].status << 16; 86 val |= (uint32_t)d->i.bmdma[1].status << 24; 87 break; 88 case 0x18: 89 val = d->i.bmdma[1].cmd; 90 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); 91 val |= (uint32_t)d->i.bmdma[1].status << 16; 92 break; 93 case 0x80 ... 0x87: 94 val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size); 95 break; 96 case 0x8a: 97 val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size); 98 break; 99 case 0xa0: 100 val = d->regs[0].confstat; 101 break; 102 case 0xc0 ... 0xc7: 103 val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size); 104 break; 105 case 0xca: 106 val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size); 107 break; 108 case 0xe0: 109 val = d->regs[1].confstat; 110 break; 111 case 0x100: 112 val = d->regs[0].scontrol; 113 break; 114 case 0x104: 115 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0; 116 break; 117 case 0x148: 118 val = (uint32_t)d->regs[0].sien << 16; 119 break; 120 case 0x180: 121 val = d->regs[1].scontrol; 122 break; 123 case 0x184: 124 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0; 125 break; 126 case 0x1c8: 127 val = (uint32_t)d->regs[1].sien << 16; 128 break; 129 default: 130 val = 0; 131 break; 132 } 133 trace_sii3112_read(size, addr, val); 134 return val; 135 } 136 137 static void sii3112_reg_write(void *opaque, hwaddr addr, 138 uint64_t val, unsigned int size) 139 { 140 SiI3112PCIState *d = opaque; 141 142 trace_sii3112_write(size, addr, val); 143 switch (addr) { 144 case 0x00: 145 case 0x10: 146 bmdma_cmd_writeb(&d->i.bmdma[0], val); 147 break; 148 case 0x01: 149 case 0x11: 150 d->regs[0].swdata = val & 0x3f; 151 break; 152 case 0x02: 153 case 0x12: 154 d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) | 155 (d->i.bmdma[0].status & ~val & 6); 156 break; 157 case 0x04 ... 0x07: 158 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); 159 break; 160 case 0x08: 161 case 0x18: 162 bmdma_cmd_writeb(&d->i.bmdma[1], val); 163 break; 164 case 0x09: 165 case 0x19: 166 d->regs[1].swdata = val & 0x3f; 167 break; 168 case 0x0a: 169 case 0x1a: 170 d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) | 171 (d->i.bmdma[1].status & ~val & 6); 172 break; 173 case 0x0c ... 0x0f: 174 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); 175 break; 176 case 0x80 ... 0x87: 177 pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size); 178 break; 179 case 0x8a: 180 pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size); 181 break; 182 case 0xc0 ... 0xc7: 183 pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size); 184 break; 185 case 0xca: 186 pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size); 187 break; 188 case 0x100: 189 d->regs[0].scontrol = val & 0xfff; 190 if (val & 1) { 191 ide_bus_reset(&d->i.bus[0]); 192 } 193 break; 194 case 0x148: 195 d->regs[0].sien = (val >> 16) & 0x3eed; 196 break; 197 case 0x180: 198 d->regs[1].scontrol = val & 0xfff; 199 if (val & 1) { 200 ide_bus_reset(&d->i.bus[1]); 201 } 202 break; 203 case 0x1c8: 204 d->regs[1].sien = (val >> 16) & 0x3eed; 205 break; 206 default: 207 break; 208 } 209 } 210 211 static const MemoryRegionOps sii3112_reg_ops = { 212 .read = sii3112_reg_read, 213 .write = sii3112_reg_write, 214 .endianness = DEVICE_LITTLE_ENDIAN, 215 }; 216 217 /* the PCI irq level is the logical OR of the two channels */ 218 static void sii3112_update_irq(SiI3112PCIState *s) 219 { 220 int i, set = 0; 221 222 for (i = 0; i < 2; i++) { 223 set |= s->regs[i].confstat & (1UL << 11); 224 } 225 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0)); 226 } 227 228 static void sii3112_set_irq(void *opaque, int channel, int level) 229 { 230 SiI3112PCIState *s = opaque; 231 232 trace_sii3112_set_irq(channel, level); 233 if (level) { 234 s->regs[channel].confstat |= (1UL << 11); 235 } else { 236 s->regs[channel].confstat &= ~(1UL << 11); 237 } 238 239 sii3112_update_irq(s); 240 } 241 242 static void sii3112_reset(DeviceState *dev) 243 { 244 SiI3112PCIState *s = SII3112_PCI(dev); 245 int i; 246 247 for (i = 0; i < 2; i++) { 248 s->regs[i].confstat = 0x6515 << 16; 249 ide_bus_reset(&s->i.bus[i]); 250 } 251 } 252 253 static void sii3112_pci_realize(PCIDevice *dev, Error **errp) 254 { 255 SiI3112PCIState *d = SII3112_PCI(dev); 256 PCIIDEState *s = PCI_IDE(dev); 257 DeviceState *ds = DEVICE(dev); 258 MemoryRegion *mr; 259 int i; 260 261 pci_config_set_interrupt_pin(dev->config, 1); 262 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); 263 264 /* BAR5 is in PCI memory space */ 265 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, 266 "sii3112.bar5", 0x200); 267 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 268 269 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ 270 mr = g_new(MemoryRegion, 1); 271 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); 272 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); 273 mr = g_new(MemoryRegion, 1); 274 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); 275 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); 276 mr = g_new(MemoryRegion, 1); 277 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); 278 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); 279 mr = g_new(MemoryRegion, 1); 280 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); 281 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); 282 mr = g_new(MemoryRegion, 1); 283 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); 284 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); 285 286 qdev_init_gpio_in(ds, sii3112_set_irq, 2); 287 for (i = 0; i < 2; i++) { 288 ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); 289 ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i)); 290 291 bmdma_init(&s->bus[i], &s->bmdma[i], s); 292 s->bmdma[i].bus = &s->bus[i]; 293 ide_register_restart_cb(&s->bus[i]); 294 } 295 } 296 297 static void sii3112_pci_class_init(ObjectClass *klass, void *data) 298 { 299 DeviceClass *dc = DEVICE_CLASS(klass); 300 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass); 301 302 pd->vendor_id = 0x1095; 303 pd->device_id = 0x3112; 304 pd->class_id = PCI_CLASS_STORAGE_RAID; 305 pd->revision = 1; 306 pd->realize = sii3112_pci_realize; 307 dc->reset = sii3112_reset; 308 dc->desc = "SiI3112A SATA controller"; 309 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 310 } 311 312 static const TypeInfo sii3112_pci_info = { 313 .name = TYPE_SII3112_PCI, 314 .parent = TYPE_PCI_IDE, 315 .instance_size = sizeof(SiI3112PCIState), 316 .class_init = sii3112_pci_class_init, 317 }; 318 319 static void sii3112_register_types(void) 320 { 321 type_register_static(&sii3112_pci_info); 322 } 323 324 type_init(sii3112_register_types) 325