1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/thread.h" 21 #include "hw/i386/apic_internal.h" 22 #include "hw/i386/apic.h" 23 #include "hw/i386/ioapic.h" 24 #include "hw/intc/i8259.h" 25 #include "hw/intc/kvm_irqcount.h" 26 #include "hw/pci/msi.h" 27 #include "qemu/host-utils.h" 28 #include "sysemu/kvm.h" 29 #include "trace.h" 30 #include "hw/i386/apic-msidef.h" 31 #include "qapi/error.h" 32 #include "qom/object.h" 33 34 #define MAX_APICS 255 35 #define MAX_APIC_WORDS 8 36 37 #define SYNC_FROM_VAPIC 0x1 38 #define SYNC_TO_VAPIC 0x2 39 #define SYNC_ISR_IRR_TO_VAPIC 0x4 40 41 static APICCommonState *local_apics[MAX_APICS + 1]; 42 43 #define TYPE_APIC "apic" 44 /*This is reusing the APICCommonState typedef from APIC_COMMON */ 45 DECLARE_INSTANCE_CHECKER(APICCommonState, APIC, 46 TYPE_APIC) 47 48 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); 49 static void apic_update_irq(APICCommonState *s); 50 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 51 uint8_t dest, uint8_t dest_mode); 52 53 /* Find first bit starting from msb */ 54 static int apic_fls_bit(uint32_t value) 55 { 56 return 31 - clz32(value); 57 } 58 59 /* Find first bit starting from lsb */ 60 static int apic_ffs_bit(uint32_t value) 61 { 62 return ctz32(value); 63 } 64 65 static inline void apic_reset_bit(uint32_t *tab, int index) 66 { 67 int i, mask; 68 i = index >> 5; 69 mask = 1 << (index & 0x1f); 70 tab[i] &= ~mask; 71 } 72 73 /* return -1 if no bit is set */ 74 static int get_highest_priority_int(uint32_t *tab) 75 { 76 int i; 77 for (i = 7; i >= 0; i--) { 78 if (tab[i] != 0) { 79 return i * 32 + apic_fls_bit(tab[i]); 80 } 81 } 82 return -1; 83 } 84 85 static void apic_sync_vapic(APICCommonState *s, int sync_type) 86 { 87 VAPICState vapic_state; 88 size_t length; 89 off_t start; 90 int vector; 91 92 if (!s->vapic_paddr) { 93 return; 94 } 95 if (sync_type & SYNC_FROM_VAPIC) { 96 cpu_physical_memory_read(s->vapic_paddr, &vapic_state, 97 sizeof(vapic_state)); 98 s->tpr = vapic_state.tpr; 99 } 100 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { 101 start = offsetof(VAPICState, isr); 102 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); 103 104 if (sync_type & SYNC_TO_VAPIC) { 105 assert(qemu_cpu_is_self(CPU(s->cpu))); 106 107 vapic_state.tpr = s->tpr; 108 vapic_state.enabled = 1; 109 start = 0; 110 length = sizeof(VAPICState); 111 } 112 113 vector = get_highest_priority_int(s->isr); 114 if (vector < 0) { 115 vector = 0; 116 } 117 vapic_state.isr = vector & 0xf0; 118 119 vapic_state.zero = 0; 120 121 vector = get_highest_priority_int(s->irr); 122 if (vector < 0) { 123 vector = 0; 124 } 125 vapic_state.irr = vector & 0xff; 126 127 address_space_write_rom(&address_space_memory, 128 s->vapic_paddr + start, 129 MEMTXATTRS_UNSPECIFIED, 130 ((void *)&vapic_state) + start, length); 131 } 132 } 133 134 static void apic_vapic_base_update(APICCommonState *s) 135 { 136 apic_sync_vapic(s, SYNC_TO_VAPIC); 137 } 138 139 static void apic_local_deliver(APICCommonState *s, int vector) 140 { 141 uint32_t lvt = s->lvt[vector]; 142 int trigger_mode; 143 144 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 145 146 if (lvt & APIC_LVT_MASKED) 147 return; 148 149 switch ((lvt >> 8) & 7) { 150 case APIC_DM_SMI: 151 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); 152 break; 153 154 case APIC_DM_NMI: 155 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); 156 break; 157 158 case APIC_DM_EXTINT: 159 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); 160 break; 161 162 case APIC_DM_FIXED: 163 trigger_mode = APIC_TRIGGER_EDGE; 164 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 165 (lvt & APIC_LVT_LEVEL_TRIGGER)) 166 trigger_mode = APIC_TRIGGER_LEVEL; 167 apic_set_irq(s, lvt & 0xff, trigger_mode); 168 } 169 } 170 171 void apic_deliver_pic_intr(DeviceState *dev, int level) 172 { 173 APICCommonState *s = APIC(dev); 174 175 if (level) { 176 apic_local_deliver(s, APIC_LVT_LINT0); 177 } else { 178 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 179 180 switch ((lvt >> 8) & 7) { 181 case APIC_DM_FIXED: 182 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 183 break; 184 apic_reset_bit(s->irr, lvt & 0xff); 185 /* fall through */ 186 case APIC_DM_EXTINT: 187 apic_update_irq(s); 188 break; 189 } 190 } 191 } 192 193 static void apic_external_nmi(APICCommonState *s) 194 { 195 apic_local_deliver(s, APIC_LVT_LINT1); 196 } 197 198 #define foreach_apic(apic, deliver_bitmask, code) \ 199 {\ 200 int __i, __j;\ 201 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 202 uint32_t __mask = deliver_bitmask[__i];\ 203 if (__mask) {\ 204 for(__j = 0; __j < 32; __j++) {\ 205 if (__mask & (1U << __j)) {\ 206 apic = local_apics[__i * 32 + __j];\ 207 if (apic) {\ 208 code;\ 209 }\ 210 }\ 211 }\ 212 }\ 213 }\ 214 } 215 216 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 217 uint8_t delivery_mode, uint8_t vector_num, 218 uint8_t trigger_mode) 219 { 220 APICCommonState *apic_iter; 221 222 switch (delivery_mode) { 223 case APIC_DM_LOWPRI: 224 /* XXX: search for focus processor, arbitration */ 225 { 226 int i, d; 227 d = -1; 228 for(i = 0; i < MAX_APIC_WORDS; i++) { 229 if (deliver_bitmask[i]) { 230 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); 231 break; 232 } 233 } 234 if (d >= 0) { 235 apic_iter = local_apics[d]; 236 if (apic_iter) { 237 apic_set_irq(apic_iter, vector_num, trigger_mode); 238 } 239 } 240 } 241 return; 242 243 case APIC_DM_FIXED: 244 break; 245 246 case APIC_DM_SMI: 247 foreach_apic(apic_iter, deliver_bitmask, 248 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) 249 ); 250 return; 251 252 case APIC_DM_NMI: 253 foreach_apic(apic_iter, deliver_bitmask, 254 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) 255 ); 256 return; 257 258 case APIC_DM_INIT: 259 /* normal INIT IPI sent to processors */ 260 foreach_apic(apic_iter, deliver_bitmask, 261 cpu_interrupt(CPU(apic_iter->cpu), 262 CPU_INTERRUPT_INIT) 263 ); 264 return; 265 266 case APIC_DM_EXTINT: 267 /* handled in I/O APIC code */ 268 break; 269 270 default: 271 return; 272 } 273 274 foreach_apic(apic_iter, deliver_bitmask, 275 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 276 } 277 278 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, 279 uint8_t vector_num, uint8_t trigger_mode) 280 { 281 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 282 283 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 284 trigger_mode); 285 286 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 287 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 288 } 289 290 static void apic_set_base(APICCommonState *s, uint64_t val) 291 { 292 s->apicbase = (val & 0xfffff000) | 293 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 294 /* if disabled, cannot be enabled again */ 295 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 296 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 297 cpu_clear_apic_feature(&s->cpu->env); 298 s->spurious_vec &= ~APIC_SV_ENABLE; 299 } 300 } 301 302 static void apic_set_tpr(APICCommonState *s, uint8_t val) 303 { 304 /* Updates from cr8 are ignored while the VAPIC is active */ 305 if (!s->vapic_paddr) { 306 s->tpr = val << 4; 307 apic_update_irq(s); 308 } 309 } 310 311 int apic_get_highest_priority_irr(DeviceState *dev) 312 { 313 APICCommonState *s; 314 315 if (!dev) { 316 /* no interrupts */ 317 return -1; 318 } 319 s = APIC_COMMON(dev); 320 return get_highest_priority_int(s->irr); 321 } 322 323 static uint8_t apic_get_tpr(APICCommonState *s) 324 { 325 apic_sync_vapic(s, SYNC_FROM_VAPIC); 326 return s->tpr >> 4; 327 } 328 329 int apic_get_ppr(APICCommonState *s) 330 { 331 int tpr, isrv, ppr; 332 333 tpr = (s->tpr >> 4); 334 isrv = get_highest_priority_int(s->isr); 335 if (isrv < 0) 336 isrv = 0; 337 isrv >>= 4; 338 if (tpr >= isrv) 339 ppr = s->tpr; 340 else 341 ppr = isrv << 4; 342 return ppr; 343 } 344 345 static int apic_get_arb_pri(APICCommonState *s) 346 { 347 /* XXX: arbitration */ 348 return 0; 349 } 350 351 352 /* 353 * <0 - low prio interrupt, 354 * 0 - no interrupt, 355 * >0 - interrupt number 356 */ 357 static int apic_irq_pending(APICCommonState *s) 358 { 359 int irrv, ppr; 360 361 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 362 return 0; 363 } 364 365 irrv = get_highest_priority_int(s->irr); 366 if (irrv < 0) { 367 return 0; 368 } 369 ppr = apic_get_ppr(s); 370 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 371 return -1; 372 } 373 374 return irrv; 375 } 376 377 /* signal the CPU if an irq is pending */ 378 static void apic_update_irq(APICCommonState *s) 379 { 380 CPUState *cpu; 381 DeviceState *dev = (DeviceState *)s; 382 383 cpu = CPU(s->cpu); 384 if (!qemu_cpu_is_self(cpu)) { 385 cpu_interrupt(cpu, CPU_INTERRUPT_POLL); 386 } else if (apic_irq_pending(s) > 0) { 387 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 388 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 389 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 390 } 391 } 392 393 void apic_poll_irq(DeviceState *dev) 394 { 395 APICCommonState *s = APIC(dev); 396 397 apic_sync_vapic(s, SYNC_FROM_VAPIC); 398 apic_update_irq(s); 399 } 400 401 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) 402 { 403 kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); 404 405 apic_set_bit(s->irr, vector_num); 406 if (trigger_mode) 407 apic_set_bit(s->tmr, vector_num); 408 else 409 apic_reset_bit(s->tmr, vector_num); 410 if (s->vapic_paddr) { 411 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); 412 /* 413 * The vcpu thread needs to see the new IRR before we pull its current 414 * TPR value. That way, if we miss a lowering of the TRP, the guest 415 * has the chance to notice the new IRR and poll for IRQs on its own. 416 */ 417 smp_wmb(); 418 apic_sync_vapic(s, SYNC_FROM_VAPIC); 419 } 420 apic_update_irq(s); 421 } 422 423 static void apic_eoi(APICCommonState *s) 424 { 425 int isrv; 426 isrv = get_highest_priority_int(s->isr); 427 if (isrv < 0) 428 return; 429 apic_reset_bit(s->isr, isrv); 430 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { 431 ioapic_eoi_broadcast(isrv); 432 } 433 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); 434 apic_update_irq(s); 435 } 436 437 static int apic_find_dest(uint8_t dest) 438 { 439 APICCommonState *apic = local_apics[dest]; 440 int i; 441 442 if (apic && apic->id == dest) 443 return dest; /* shortcut in case apic->id == local_apics[dest]->id */ 444 445 for (i = 0; i < MAX_APICS; i++) { 446 apic = local_apics[i]; 447 if (apic && apic->id == dest) 448 return i; 449 if (!apic) 450 break; 451 } 452 453 return -1; 454 } 455 456 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 457 uint8_t dest, uint8_t dest_mode) 458 { 459 APICCommonState *apic_iter; 460 int i; 461 462 if (dest_mode == 0) { 463 if (dest == 0xff) { 464 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 465 } else { 466 int idx = apic_find_dest(dest); 467 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 468 if (idx >= 0) 469 apic_set_bit(deliver_bitmask, idx); 470 } 471 } else { 472 /* XXX: cluster mode */ 473 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 474 for(i = 0; i < MAX_APICS; i++) { 475 apic_iter = local_apics[i]; 476 if (apic_iter) { 477 if (apic_iter->dest_mode == 0xf) { 478 if (dest & apic_iter->log_dest) 479 apic_set_bit(deliver_bitmask, i); 480 } else if (apic_iter->dest_mode == 0x0) { 481 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 482 (dest & apic_iter->log_dest & 0x0f)) { 483 apic_set_bit(deliver_bitmask, i); 484 } 485 } 486 } else { 487 break; 488 } 489 } 490 } 491 } 492 493 static void apic_startup(APICCommonState *s, int vector_num) 494 { 495 s->sipi_vector = vector_num; 496 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 497 } 498 499 void apic_sipi(DeviceState *dev) 500 { 501 APICCommonState *s = APIC(dev); 502 503 cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 504 505 if (!s->wait_for_sipi) 506 return; 507 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); 508 s->wait_for_sipi = 0; 509 } 510 511 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, 512 uint8_t delivery_mode, uint8_t vector_num, 513 uint8_t trigger_mode) 514 { 515 APICCommonState *s = APIC(dev); 516 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 517 int dest_shorthand = (s->icr[0] >> 18) & 3; 518 APICCommonState *apic_iter; 519 520 switch (dest_shorthand) { 521 case 0: 522 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 523 break; 524 case 1: 525 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 526 apic_set_bit(deliver_bitmask, s->id); 527 break; 528 case 2: 529 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 530 break; 531 case 3: 532 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 533 apic_reset_bit(deliver_bitmask, s->id); 534 break; 535 } 536 537 switch (delivery_mode) { 538 case APIC_DM_INIT: 539 { 540 int trig_mode = (s->icr[0] >> 15) & 1; 541 int level = (s->icr[0] >> 14) & 1; 542 if (level == 0 && trig_mode == 1) { 543 foreach_apic(apic_iter, deliver_bitmask, 544 apic_iter->arb_id = apic_iter->id ); 545 return; 546 } 547 } 548 break; 549 550 case APIC_DM_SIPI: 551 foreach_apic(apic_iter, deliver_bitmask, 552 apic_startup(apic_iter, vector_num) ); 553 return; 554 } 555 556 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 557 } 558 559 static bool apic_check_pic(APICCommonState *s) 560 { 561 DeviceState *dev = (DeviceState *)s; 562 563 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 564 return false; 565 } 566 apic_deliver_pic_intr(dev, 1); 567 return true; 568 } 569 570 int apic_get_interrupt(DeviceState *dev) 571 { 572 APICCommonState *s = APIC(dev); 573 int intno; 574 575 /* if the APIC is installed or enabled, we let the 8259 handle the 576 IRQs */ 577 if (!s) 578 return -1; 579 if (!(s->spurious_vec & APIC_SV_ENABLE)) 580 return -1; 581 582 apic_sync_vapic(s, SYNC_FROM_VAPIC); 583 intno = apic_irq_pending(s); 584 585 /* if there is an interrupt from the 8259, let the caller handle 586 * that first since ExtINT interrupts ignore the priority. 587 */ 588 if (intno == 0 || apic_check_pic(s)) { 589 apic_sync_vapic(s, SYNC_TO_VAPIC); 590 return -1; 591 } else if (intno < 0) { 592 apic_sync_vapic(s, SYNC_TO_VAPIC); 593 return s->spurious_vec & 0xff; 594 } 595 apic_reset_bit(s->irr, intno); 596 apic_set_bit(s->isr, intno); 597 apic_sync_vapic(s, SYNC_TO_VAPIC); 598 599 apic_update_irq(s); 600 601 return intno; 602 } 603 604 int apic_accept_pic_intr(DeviceState *dev) 605 { 606 APICCommonState *s = APIC(dev); 607 uint32_t lvt0; 608 609 if (!s) 610 return -1; 611 612 lvt0 = s->lvt[APIC_LVT_LINT0]; 613 614 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 615 (lvt0 & APIC_LVT_MASKED) == 0) 616 return isa_pic != NULL; 617 618 return 0; 619 } 620 621 static void apic_timer_update(APICCommonState *s, int64_t current_time) 622 { 623 if (apic_next_timer(s, current_time)) { 624 timer_mod(s->timer, s->next_time); 625 } else { 626 timer_del(s->timer); 627 } 628 } 629 630 static void apic_timer(void *opaque) 631 { 632 APICCommonState *s = opaque; 633 634 apic_local_deliver(s, APIC_LVT_TIMER); 635 apic_timer_update(s, s->next_time); 636 } 637 638 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) 639 { 640 DeviceState *dev; 641 APICCommonState *s; 642 uint32_t val; 643 int index; 644 645 if (size < 4) { 646 return 0; 647 } 648 649 dev = cpu_get_current_apic(); 650 if (!dev) { 651 return 0; 652 } 653 s = APIC(dev); 654 655 index = (addr >> 4) & 0xff; 656 switch(index) { 657 case 0x02: /* id */ 658 val = s->id << 24; 659 break; 660 case 0x03: /* version */ 661 val = s->version | ((APIC_LVT_NB - 1) << 16); 662 break; 663 case 0x08: 664 apic_sync_vapic(s, SYNC_FROM_VAPIC); 665 if (apic_report_tpr_access) { 666 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); 667 } 668 val = s->tpr; 669 break; 670 case 0x09: 671 val = apic_get_arb_pri(s); 672 break; 673 case 0x0a: 674 /* ppr */ 675 val = apic_get_ppr(s); 676 break; 677 case 0x0b: 678 val = 0; 679 break; 680 case 0x0d: 681 val = s->log_dest << 24; 682 break; 683 case 0x0e: 684 val = (s->dest_mode << 28) | 0xfffffff; 685 break; 686 case 0x0f: 687 val = s->spurious_vec; 688 break; 689 case 0x10 ... 0x17: 690 val = s->isr[index & 7]; 691 break; 692 case 0x18 ... 0x1f: 693 val = s->tmr[index & 7]; 694 break; 695 case 0x20 ... 0x27: 696 val = s->irr[index & 7]; 697 break; 698 case 0x28: 699 val = s->esr; 700 break; 701 case 0x30: 702 case 0x31: 703 val = s->icr[index & 1]; 704 break; 705 case 0x32 ... 0x37: 706 val = s->lvt[index - 0x32]; 707 break; 708 case 0x38: 709 val = s->initial_count; 710 break; 711 case 0x39: 712 val = apic_get_current_count(s); 713 break; 714 case 0x3e: 715 val = s->divide_conf; 716 break; 717 default: 718 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 719 val = 0; 720 break; 721 } 722 trace_apic_mem_readl(addr, val); 723 return val; 724 } 725 726 static void apic_send_msi(MSIMessage *msi) 727 { 728 uint64_t addr = msi->address; 729 uint32_t data = msi->data; 730 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 731 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 732 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 733 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 734 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 735 /* XXX: Ignore redirection hint. */ 736 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 737 } 738 739 static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, 740 unsigned size) 741 { 742 DeviceState *dev; 743 APICCommonState *s; 744 int index = (addr >> 4) & 0xff; 745 746 if (size < 4) { 747 return; 748 } 749 750 if (addr > 0xfff || !index) { 751 /* MSI and MMIO APIC are at the same memory location, 752 * but actually not on the global bus: MSI is on PCI bus 753 * APIC is connected directly to the CPU. 754 * Mapping them on the global bus happens to work because 755 * MSI registers are reserved in APIC MMIO and vice versa. */ 756 MSIMessage msi = { .address = addr, .data = val }; 757 apic_send_msi(&msi); 758 return; 759 } 760 761 dev = cpu_get_current_apic(); 762 if (!dev) { 763 return; 764 } 765 s = APIC(dev); 766 767 trace_apic_mem_writel(addr, val); 768 769 switch(index) { 770 case 0x02: 771 s->id = (val >> 24); 772 break; 773 case 0x03: 774 break; 775 case 0x08: 776 if (apic_report_tpr_access) { 777 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); 778 } 779 s->tpr = val; 780 apic_sync_vapic(s, SYNC_TO_VAPIC); 781 apic_update_irq(s); 782 break; 783 case 0x09: 784 case 0x0a: 785 break; 786 case 0x0b: /* EOI */ 787 apic_eoi(s); 788 break; 789 case 0x0d: 790 s->log_dest = val >> 24; 791 break; 792 case 0x0e: 793 s->dest_mode = val >> 28; 794 break; 795 case 0x0f: 796 s->spurious_vec = val & 0x1ff; 797 apic_update_irq(s); 798 break; 799 case 0x10 ... 0x17: 800 case 0x18 ... 0x1f: 801 case 0x20 ... 0x27: 802 case 0x28: 803 break; 804 case 0x30: 805 s->icr[0] = val; 806 apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 807 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 808 (s->icr[0] >> 15) & 1); 809 break; 810 case 0x31: 811 s->icr[1] = val; 812 break; 813 case 0x32 ... 0x37: 814 { 815 int n = index - 0x32; 816 s->lvt[n] = val; 817 if (n == APIC_LVT_TIMER) { 818 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 819 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { 820 apic_update_irq(s); 821 } 822 } 823 break; 824 case 0x38: 825 s->initial_count = val; 826 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 827 apic_timer_update(s, s->initial_count_load_time); 828 break; 829 case 0x39: 830 break; 831 case 0x3e: 832 { 833 int v; 834 s->divide_conf = val & 0xb; 835 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 836 s->count_shift = (v + 1) & 7; 837 } 838 break; 839 default: 840 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 841 break; 842 } 843 } 844 845 static void apic_pre_save(APICCommonState *s) 846 { 847 apic_sync_vapic(s, SYNC_FROM_VAPIC); 848 } 849 850 static void apic_post_load(APICCommonState *s) 851 { 852 if (s->timer_expiry != -1) { 853 timer_mod(s->timer, s->timer_expiry); 854 } else { 855 timer_del(s->timer); 856 } 857 } 858 859 static const MemoryRegionOps apic_io_ops = { 860 .read = apic_mem_read, 861 .write = apic_mem_write, 862 .impl.min_access_size = 1, 863 .impl.max_access_size = 4, 864 .valid.min_access_size = 1, 865 .valid.max_access_size = 4, 866 .endianness = DEVICE_NATIVE_ENDIAN, 867 }; 868 869 static void apic_realize(DeviceState *dev, Error **errp) 870 { 871 APICCommonState *s = APIC(dev); 872 873 if (s->id >= MAX_APICS) { 874 error_setg(errp, "%s initialization failed. APIC ID %d is invalid", 875 object_get_typename(OBJECT(dev)), s->id); 876 return; 877 } 878 879 if (kvm_enabled()) { 880 warn_report("Userspace local APIC is deprecated for KVM."); 881 warn_report("Do not use kernel-irqchip except for the -M isapc machine type."); 882 } 883 884 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", 885 APIC_SPACE_SIZE); 886 887 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); 888 local_apics[s->id] = s; 889 890 msi_nonbroken = true; 891 } 892 893 static void apic_unrealize(DeviceState *dev) 894 { 895 APICCommonState *s = APIC(dev); 896 897 timer_free(s->timer); 898 local_apics[s->id] = NULL; 899 } 900 901 static void apic_class_init(ObjectClass *klass, void *data) 902 { 903 APICCommonClass *k = APIC_COMMON_CLASS(klass); 904 905 k->realize = apic_realize; 906 k->unrealize = apic_unrealize; 907 k->set_base = apic_set_base; 908 k->set_tpr = apic_set_tpr; 909 k->get_tpr = apic_get_tpr; 910 k->vapic_base_update = apic_vapic_base_update; 911 k->external_nmi = apic_external_nmi; 912 k->pre_save = apic_pre_save; 913 k->post_load = apic_post_load; 914 k->send_msi = apic_send_msi; 915 } 916 917 static const TypeInfo apic_info = { 918 .name = TYPE_APIC, 919 .instance_size = sizeof(APICCommonState), 920 .parent = TYPE_APIC_COMMON, 921 .class_init = apic_class_init, 922 }; 923 924 static void apic_register_types(void) 925 { 926 type_register_static(&apic_info); 927 } 928 929 type_init(apic_register_types) 930