1 /* 2 * APIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qemu/module.h" 24 #include "qapi/error.h" 25 #include "qapi/visitor.h" 26 #include "hw/i386/apic.h" 27 #include "hw/i386/apic_internal.h" 28 #include "hw/intc/kvm_irqcount.h" 29 #include "trace.h" 30 #include "hw/boards.h" 31 #include "sysemu/kvm.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "migration/vmstate.h" 35 36 bool apic_report_tpr_access; 37 38 void cpu_set_apic_base(DeviceState *dev, uint64_t val) 39 { 40 trace_cpu_set_apic_base(val); 41 42 if (dev) { 43 APICCommonState *s = APIC_COMMON(dev); 44 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 45 /* switching to x2APIC, reset possibly modified xAPIC ID */ 46 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) && 47 (val & MSR_IA32_APICBASE_EXTD)) { 48 s->id = s->initial_apic_id; 49 } 50 info->set_base(s, val); 51 } 52 } 53 54 uint64_t cpu_get_apic_base(DeviceState *dev) 55 { 56 if (dev) { 57 APICCommonState *s = APIC_COMMON(dev); 58 trace_cpu_get_apic_base((uint64_t)s->apicbase); 59 return s->apicbase; 60 } else { 61 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); 62 return MSR_IA32_APICBASE_BSP; 63 } 64 } 65 66 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) 67 { 68 APICCommonState *s; 69 APICCommonClass *info; 70 71 if (!dev) { 72 return; 73 } 74 75 s = APIC_COMMON(dev); 76 info = APIC_COMMON_GET_CLASS(s); 77 78 info->set_tpr(s, val); 79 } 80 81 uint8_t cpu_get_apic_tpr(DeviceState *dev) 82 { 83 APICCommonState *s; 84 APICCommonClass *info; 85 86 if (!dev) { 87 return 0; 88 } 89 90 s = APIC_COMMON(dev); 91 info = APIC_COMMON_GET_CLASS(s); 92 93 return info->get_tpr(s); 94 } 95 96 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) 97 { 98 APICCommonState *s = APIC_COMMON(dev); 99 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 100 101 apic_report_tpr_access = enable; 102 if (info->enable_tpr_reporting) { 103 info->enable_tpr_reporting(s, enable); 104 } 105 } 106 107 void apic_enable_vapic(DeviceState *dev, hwaddr paddr) 108 { 109 APICCommonState *s = APIC_COMMON(dev); 110 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 111 112 s->vapic_paddr = paddr; 113 info->vapic_base_update(s); 114 } 115 116 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, 117 TPRAccess access) 118 { 119 APICCommonState *s = APIC_COMMON(dev); 120 121 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); 122 } 123 124 void apic_deliver_nmi(DeviceState *dev) 125 { 126 APICCommonState *s = APIC_COMMON(dev); 127 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 128 129 info->external_nmi(s); 130 } 131 132 bool apic_next_timer(APICCommonState *s, int64_t current_time) 133 { 134 int64_t d; 135 136 /* We need to store the timer state separately to support APIC 137 * implementations that maintain a non-QEMU timer, e.g. inside the 138 * host kernel. This open-coded state allows us to migrate between 139 * both models. */ 140 s->timer_expiry = -1; 141 142 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { 143 return false; 144 } 145 146 d = (current_time - s->initial_count_load_time) >> s->count_shift; 147 148 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 149 if (!s->initial_count) { 150 return false; 151 } 152 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * 153 ((uint64_t)s->initial_count + 1); 154 } else { 155 if (d >= s->initial_count) { 156 return false; 157 } 158 d = (uint64_t)s->initial_count + 1; 159 } 160 s->next_time = s->initial_count_load_time + (d << s->count_shift); 161 s->timer_expiry = s->next_time; 162 return true; 163 } 164 165 uint32_t apic_get_current_count(APICCommonState *s) 166 { 167 int64_t d; 168 uint32_t val; 169 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >> 170 s->count_shift; 171 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 172 /* periodic */ 173 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 174 } else { 175 if (d >= s->initial_count) { 176 val = 0; 177 } else { 178 val = s->initial_count - d; 179 } 180 } 181 return val; 182 } 183 184 void apic_init_reset(DeviceState *dev) 185 { 186 APICCommonState *s; 187 APICCommonClass *info; 188 int i; 189 190 if (!dev) { 191 return; 192 } 193 s = APIC_COMMON(dev); 194 s->tpr = 0; 195 s->spurious_vec = 0xff; 196 s->log_dest = 0; 197 s->dest_mode = 0xf; 198 memset(s->isr, 0, sizeof(s->isr)); 199 memset(s->tmr, 0, sizeof(s->tmr)); 200 memset(s->irr, 0, sizeof(s->irr)); 201 for (i = 0; i < APIC_LVT_NB; i++) { 202 s->lvt[i] = APIC_LVT_MASKED; 203 } 204 s->esr = 0; 205 memset(s->icr, 0, sizeof(s->icr)); 206 s->divide_conf = 0; 207 s->count_shift = 0; 208 s->initial_count = 0; 209 s->initial_count_load_time = 0; 210 s->next_time = 0; 211 s->wait_for_sipi = !cpu_is_bsp(s->cpu); 212 213 if (s->timer) { 214 timer_del(s->timer); 215 } 216 s->timer_expiry = -1; 217 218 info = APIC_COMMON_GET_CLASS(s); 219 if (info->reset) { 220 info->reset(s); 221 } 222 } 223 224 void apic_designate_bsp(DeviceState *dev, bool bsp) 225 { 226 if (dev == NULL) { 227 return; 228 } 229 230 APICCommonState *s = APIC_COMMON(dev); 231 if (bsp) { 232 s->apicbase |= MSR_IA32_APICBASE_BSP; 233 } else { 234 s->apicbase &= ~MSR_IA32_APICBASE_BSP; 235 } 236 } 237 238 static void apic_reset_common(DeviceState *dev) 239 { 240 APICCommonState *s = APIC_COMMON(dev); 241 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 242 uint32_t bsp; 243 244 bsp = s->apicbase & MSR_IA32_APICBASE_BSP; 245 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; 246 s->id = s->initial_apic_id; 247 248 kvm_reset_irq_delivered(); 249 250 s->vapic_paddr = 0; 251 info->vapic_base_update(s); 252 253 apic_init_reset(dev); 254 } 255 256 static const VMStateDescription vmstate_apic_common; 257 258 static void apic_common_realize(DeviceState *dev, Error **errp) 259 { 260 ERRP_GUARD(); 261 APICCommonState *s = APIC_COMMON(dev); 262 APICCommonClass *info; 263 static DeviceState *vapic; 264 uint32_t instance_id = s->initial_apic_id; 265 266 /* Normally initial APIC ID should be no more than hundreds */ 267 assert(instance_id != VMSTATE_INSTANCE_ID_ANY); 268 269 info = APIC_COMMON_GET_CLASS(s); 270 info->realize(dev, errp); 271 if (*errp) { 272 return; 273 } 274 275 /* Note: We need at least 1M to map the VAPIC option ROM */ 276 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && 277 current_machine->ram_size >= 1024 * 1024) { 278 vapic = sysbus_create_simple("kvmvapic", -1, NULL); 279 } 280 s->vapic = vapic; 281 if (apic_report_tpr_access && info->enable_tpr_reporting) { 282 info->enable_tpr_reporting(s, true); 283 } 284 285 if (s->legacy_instance_id) { 286 instance_id = VMSTATE_INSTANCE_ID_ANY; 287 } 288 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, 289 s, -1, 0, NULL); 290 291 /* APIC LDR in x2APIC mode */ 292 s->extended_log_dest = ((s->initial_apic_id >> 4) << 16) | 293 (1 << (s->initial_apic_id & 0xf)); 294 } 295 296 static void apic_common_unrealize(DeviceState *dev) 297 { 298 APICCommonState *s = APIC_COMMON(dev); 299 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 300 301 vmstate_unregister(NULL, &vmstate_apic_common, s); 302 info->unrealize(dev); 303 304 if (apic_report_tpr_access && info->enable_tpr_reporting) { 305 info->enable_tpr_reporting(s, false); 306 } 307 } 308 309 static int apic_pre_load(void *opaque) 310 { 311 APICCommonState *s = APIC_COMMON(opaque); 312 313 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 314 * so that's what apic_common_sipi_needed checks for. Reset to 315 * the value that is assumed when the apic_sipi subsection is 316 * absent. 317 */ 318 s->wait_for_sipi = 0; 319 return 0; 320 } 321 322 static int apic_dispatch_pre_save(void *opaque) 323 { 324 APICCommonState *s = APIC_COMMON(opaque); 325 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 326 327 if (info->pre_save) { 328 info->pre_save(s); 329 } 330 331 return 0; 332 } 333 334 static int apic_dispatch_post_load(void *opaque, int version_id) 335 { 336 APICCommonState *s = APIC_COMMON(opaque); 337 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 338 339 if (info->post_load) { 340 info->post_load(s); 341 } 342 return 0; 343 } 344 345 static bool apic_common_sipi_needed(void *opaque) 346 { 347 APICCommonState *s = APIC_COMMON(opaque); 348 return s->wait_for_sipi != 0; 349 } 350 351 static const VMStateDescription vmstate_apic_common_sipi = { 352 .name = "apic_sipi", 353 .version_id = 1, 354 .minimum_version_id = 1, 355 .needed = apic_common_sipi_needed, 356 .fields = (const VMStateField[]) { 357 VMSTATE_INT32(sipi_vector, APICCommonState), 358 VMSTATE_INT32(wait_for_sipi, APICCommonState), 359 VMSTATE_END_OF_LIST() 360 } 361 }; 362 363 static const VMStateDescription vmstate_apic_common = { 364 .name = "apic", 365 .version_id = 3, 366 .minimum_version_id = 3, 367 .pre_load = apic_pre_load, 368 .pre_save = apic_dispatch_pre_save, 369 .post_load = apic_dispatch_post_load, 370 .fields = (const VMStateField[]) { 371 VMSTATE_UINT32(apicbase, APICCommonState), 372 VMSTATE_UINT8(id, APICCommonState), 373 VMSTATE_UINT8(arb_id, APICCommonState), 374 VMSTATE_UINT8(tpr, APICCommonState), 375 VMSTATE_UINT32(spurious_vec, APICCommonState), 376 VMSTATE_UINT8(log_dest, APICCommonState), 377 VMSTATE_UINT8(dest_mode, APICCommonState), 378 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), 379 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), 380 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), 381 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), 382 VMSTATE_UINT32(esr, APICCommonState), 383 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), 384 VMSTATE_UINT32(divide_conf, APICCommonState), 385 VMSTATE_INT32(count_shift, APICCommonState), 386 VMSTATE_UINT32(initial_count, APICCommonState), 387 VMSTATE_INT64(initial_count_load_time, APICCommonState), 388 VMSTATE_INT64(next_time, APICCommonState), 389 VMSTATE_INT64(timer_expiry, 390 APICCommonState), /* open-coded timer state */ 391 VMSTATE_END_OF_LIST() 392 }, 393 .subsections = (const VMStateDescription * const []) { 394 &vmstate_apic_common_sipi, 395 NULL 396 } 397 }; 398 399 static Property apic_properties_common[] = { 400 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), 401 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, 402 true), 403 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, 404 false), 405 DEFINE_PROP_END_OF_LIST(), 406 }; 407 408 static void apic_common_get_id(Object *obj, Visitor *v, const char *name, 409 void *opaque, Error **errp) 410 { 411 APICCommonState *s = APIC_COMMON(obj); 412 uint32_t value; 413 414 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; 415 visit_type_uint32(v, name, &value, errp); 416 } 417 418 static void apic_common_set_id(Object *obj, Visitor *v, const char *name, 419 void *opaque, Error **errp) 420 { 421 APICCommonState *s = APIC_COMMON(obj); 422 DeviceState *dev = DEVICE(obj); 423 uint32_t value; 424 425 if (dev->realized) { 426 qdev_prop_set_after_realize(dev, name, errp); 427 return; 428 } 429 430 if (!visit_type_uint32(v, name, &value, errp)) { 431 return; 432 } 433 434 if (value >= 255 && !cpu_has_x2apic_feature(&s->cpu->env)) { 435 error_setg(errp, "APIC ID %d requires x2APIC feature in CPU", value); 436 return; 437 } 438 439 s->initial_apic_id = value; 440 s->id = (uint8_t)value; 441 } 442 443 static void apic_common_initfn(Object *obj) 444 { 445 APICCommonState *s = APIC_COMMON(obj); 446 447 s->id = s->initial_apic_id = -1; 448 object_property_add(obj, "id", "uint32", 449 apic_common_get_id, 450 apic_common_set_id, NULL, NULL); 451 } 452 453 static void apic_common_class_init(ObjectClass *klass, void *data) 454 { 455 DeviceClass *dc = DEVICE_CLASS(klass); 456 457 dc->reset = apic_reset_common; 458 device_class_set_props(dc, apic_properties_common); 459 dc->realize = apic_common_realize; 460 dc->unrealize = apic_common_unrealize; 461 /* 462 * Reason: APIC and CPU need to be wired up by 463 * x86_cpu_apic_create() 464 */ 465 dc->user_creatable = false; 466 } 467 468 static const TypeInfo apic_common_type = { 469 .name = TYPE_APIC_COMMON, 470 .parent = TYPE_DEVICE, 471 .instance_size = sizeof(APICCommonState), 472 .instance_init = apic_common_initfn, 473 .class_size = sizeof(APICCommonClass), 474 .class_init = apic_common_class_init, 475 .abstract = true, 476 }; 477 478 static void apic_common_register_types(void) 479 { 480 type_register_static(&apic_common_type); 481 } 482 483 type_init(apic_common_register_types) 484