1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qom/cpu.h" 25 26 //#define DEBUG_GIC 27 28 #ifdef DEBUG_GIC 29 #define DPRINTF(fmt, ...) \ 30 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 31 #else 32 #define DPRINTF(fmt, ...) do {} while(0) 33 #endif 34 35 static const uint8_t gic_id_11mpcore[] = { 36 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 37 }; 38 39 static const uint8_t gic_id_gicv1[] = { 40 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 41 }; 42 43 static const uint8_t gic_id_gicv2[] = { 44 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 45 }; 46 47 static inline int gic_get_current_cpu(GICState *s) 48 { 49 if (s->num_cpu > 1) { 50 return current_cpu->cpu_index; 51 } 52 return 0; 53 } 54 55 /* Return true if this GIC config has interrupt groups, which is 56 * true if we're a GICv2, or a GICv1 with the security extensions. 57 */ 58 static inline bool gic_has_groups(GICState *s) 59 { 60 return s->revision == 2 || s->security_extn; 61 } 62 63 /* TODO: Many places that call this routine could be optimized. */ 64 /* Update interrupt status after enabled or pending bits have been changed. */ 65 void gic_update(GICState *s) 66 { 67 int best_irq; 68 int best_prio; 69 int irq; 70 int irq_level, fiq_level; 71 int cpu; 72 int cm; 73 74 for (cpu = 0; cpu < s->num_cpu; cpu++) { 75 cm = 1 << cpu; 76 s->current_pending[cpu] = 1023; 77 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 78 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 79 qemu_irq_lower(s->parent_irq[cpu]); 80 qemu_irq_lower(s->parent_fiq[cpu]); 81 continue; 82 } 83 best_prio = 0x100; 84 best_irq = 1023; 85 for (irq = 0; irq < s->num_irq; irq++) { 86 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 87 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 88 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 89 best_prio = GIC_GET_PRIORITY(irq, cpu); 90 best_irq = irq; 91 } 92 } 93 } 94 95 irq_level = fiq_level = 0; 96 97 if (best_prio < s->priority_mask[cpu]) { 98 s->current_pending[cpu] = best_irq; 99 if (best_prio < s->running_priority[cpu]) { 100 int group = GIC_TEST_GROUP(best_irq, cm); 101 102 if (extract32(s->ctlr, group, 1) && 103 extract32(s->cpu_ctlr[cpu], group, 1)) { 104 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 105 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 106 best_irq, cpu); 107 fiq_level = 1; 108 } else { 109 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 110 best_irq, cpu); 111 irq_level = 1; 112 } 113 } 114 } 115 } 116 117 qemu_set_irq(s->parent_irq[cpu], irq_level); 118 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 119 } 120 } 121 122 void gic_set_pending_private(GICState *s, int cpu, int irq) 123 { 124 int cm = 1 << cpu; 125 126 if (gic_test_pending(s, irq, cm)) { 127 return; 128 } 129 130 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 131 GIC_SET_PENDING(irq, cm); 132 gic_update(s); 133 } 134 135 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 136 int cm, int target) 137 { 138 if (level) { 139 GIC_SET_LEVEL(irq, cm); 140 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 141 DPRINTF("Set %d pending mask %x\n", irq, target); 142 GIC_SET_PENDING(irq, target); 143 } 144 } else { 145 GIC_CLEAR_LEVEL(irq, cm); 146 } 147 } 148 149 static void gic_set_irq_generic(GICState *s, int irq, int level, 150 int cm, int target) 151 { 152 if (level) { 153 GIC_SET_LEVEL(irq, cm); 154 DPRINTF("Set %d pending mask %x\n", irq, target); 155 if (GIC_TEST_EDGE_TRIGGER(irq)) { 156 GIC_SET_PENDING(irq, target); 157 } 158 } else { 159 GIC_CLEAR_LEVEL(irq, cm); 160 } 161 } 162 163 /* Process a change in an external IRQ input. */ 164 static void gic_set_irq(void *opaque, int irq, int level) 165 { 166 /* Meaning of the 'irq' parameter: 167 * [0..N-1] : external interrupts 168 * [N..N+31] : PPI (internal) interrupts for CPU 0 169 * [N+32..N+63] : PPI (internal interrupts for CPU 1 170 * ... 171 */ 172 GICState *s = (GICState *)opaque; 173 int cm, target; 174 if (irq < (s->num_irq - GIC_INTERNAL)) { 175 /* The first external input line is internal interrupt 32. */ 176 cm = ALL_CPU_MASK; 177 irq += GIC_INTERNAL; 178 target = GIC_TARGET(irq); 179 } else { 180 int cpu; 181 irq -= (s->num_irq - GIC_INTERNAL); 182 cpu = irq / GIC_INTERNAL; 183 irq %= GIC_INTERNAL; 184 cm = 1 << cpu; 185 target = cm; 186 } 187 188 assert(irq >= GIC_NR_SGIS); 189 190 if (level == GIC_TEST_LEVEL(irq, cm)) { 191 return; 192 } 193 194 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 195 gic_set_irq_11mpcore(s, irq, level, cm, target); 196 } else { 197 gic_set_irq_generic(s, irq, level, cm, target); 198 } 199 200 gic_update(s); 201 } 202 203 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 204 MemTxAttrs attrs) 205 { 206 uint16_t pending_irq = s->current_pending[cpu]; 207 208 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 209 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 210 /* On a GIC without the security extensions, reading this register 211 * behaves in the same way as a secure access to a GIC with them. 212 */ 213 bool secure = !s->security_extn || attrs.secure; 214 215 if (group == 0 && !secure) { 216 /* Group0 interrupts hidden from Non-secure access */ 217 return 1023; 218 } 219 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 220 /* Group1 interrupts only seen by Secure access if 221 * AckCtl bit set. 222 */ 223 return 1022; 224 } 225 } 226 return pending_irq; 227 } 228 229 static int gic_get_group_priority(GICState *s, int cpu, int irq) 230 { 231 /* Return the group priority of the specified interrupt 232 * (which is the top bits of its priority, with the number 233 * of bits masked determined by the applicable binary point register). 234 */ 235 int bpr; 236 uint32_t mask; 237 238 if (gic_has_groups(s) && 239 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 240 GIC_TEST_GROUP(irq, (1 << cpu))) { 241 bpr = s->abpr[cpu]; 242 } else { 243 bpr = s->bpr[cpu]; 244 } 245 246 /* a BPR of 0 means the group priority bits are [7:1]; 247 * a BPR of 1 means they are [7:2], and so on down to 248 * a BPR of 7 meaning no group priority bits at all. 249 */ 250 mask = ~0U << ((bpr & 7) + 1); 251 252 return GIC_GET_PRIORITY(irq, cpu) & mask; 253 } 254 255 static void gic_activate_irq(GICState *s, int cpu, int irq) 256 { 257 /* Set the appropriate Active Priority Register bit for this IRQ, 258 * and update the running priority. 259 */ 260 int prio = gic_get_group_priority(s, cpu, irq); 261 int preemption_level = prio >> (GIC_MIN_BPR + 1); 262 int regno = preemption_level / 32; 263 int bitno = preemption_level % 32; 264 265 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 266 s->nsapr[regno][cpu] |= (1 << bitno); 267 } else { 268 s->apr[regno][cpu] |= (1 << bitno); 269 } 270 271 s->running_priority[cpu] = prio; 272 GIC_SET_ACTIVE(irq, 1 << cpu); 273 } 274 275 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 276 { 277 /* Recalculate the current running priority for this CPU based 278 * on the set bits in the Active Priority Registers. 279 */ 280 int i; 281 for (i = 0; i < GIC_NR_APRS; i++) { 282 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 283 if (!apr) { 284 continue; 285 } 286 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 287 } 288 return 0x100; 289 } 290 291 static void gic_drop_prio(GICState *s, int cpu, int group) 292 { 293 /* Drop the priority of the currently active interrupt in the 294 * specified group. 295 * 296 * Note that we can guarantee (because of the requirement to nest 297 * GICC_IAR reads [which activate an interrupt and raise priority] 298 * with GICC_EOIR writes [which drop the priority for the interrupt]) 299 * that the interrupt we're being called for is the highest priority 300 * active interrupt, meaning that it has the lowest set bit in the 301 * APR registers. 302 * 303 * If the guest does not honour the ordering constraints then the 304 * behaviour of the GIC is UNPREDICTABLE, which for us means that 305 * the values of the APR registers might become incorrect and the 306 * running priority will be wrong, so interrupts that should preempt 307 * might not do so, and interrupts that should not preempt might do so. 308 */ 309 int i; 310 311 for (i = 0; i < GIC_NR_APRS; i++) { 312 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 313 if (!*papr) { 314 continue; 315 } 316 /* Clear lowest set bit */ 317 *papr &= *papr - 1; 318 break; 319 } 320 321 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 322 } 323 324 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 325 { 326 int ret, irq, src; 327 int cm = 1 << cpu; 328 329 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 330 * for the case where this GIC supports grouping and the pending interrupt 331 * is in the wrong group. 332 */ 333 irq = gic_get_current_pending_irq(s, cpu, attrs); 334 335 if (irq >= GIC_MAXIRQ) { 336 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 337 return irq; 338 } 339 340 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 341 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 342 return 1023; 343 } 344 345 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 346 /* Clear pending flags for both level and edge triggered interrupts. 347 * Level triggered IRQs will be reasserted once they become inactive. 348 */ 349 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 350 ret = irq; 351 } else { 352 if (irq < GIC_NR_SGIS) { 353 /* Lookup the source CPU for the SGI and clear this in the 354 * sgi_pending map. Return the src and clear the overall pending 355 * state on this CPU if the SGI is not pending from any CPUs. 356 */ 357 assert(s->sgi_pending[irq][cpu] != 0); 358 src = ctz32(s->sgi_pending[irq][cpu]); 359 s->sgi_pending[irq][cpu] &= ~(1 << src); 360 if (s->sgi_pending[irq][cpu] == 0) { 361 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 362 } 363 ret = irq | ((src & 0x7) << 10); 364 } else { 365 /* Clear pending state for both level and edge triggered 366 * interrupts. (level triggered interrupts with an active line 367 * remain pending, see gic_test_pending) 368 */ 369 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 370 ret = irq; 371 } 372 } 373 374 gic_activate_irq(s, cpu, irq); 375 gic_update(s); 376 DPRINTF("ACK %d\n", irq); 377 return ret; 378 } 379 380 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 381 MemTxAttrs attrs) 382 { 383 if (s->security_extn && !attrs.secure) { 384 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 385 return; /* Ignore Non-secure access of Group0 IRQ */ 386 } 387 val = 0x80 | (val >> 1); /* Non-secure view */ 388 } 389 390 if (irq < GIC_INTERNAL) { 391 s->priority1[irq][cpu] = val; 392 } else { 393 s->priority2[(irq) - GIC_INTERNAL] = val; 394 } 395 } 396 397 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 398 MemTxAttrs attrs) 399 { 400 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 401 402 if (s->security_extn && !attrs.secure) { 403 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 404 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 405 } 406 prio = (prio << 1) & 0xff; /* Non-secure view */ 407 } 408 return prio; 409 } 410 411 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 412 MemTxAttrs attrs) 413 { 414 if (s->security_extn && !attrs.secure) { 415 if (s->priority_mask[cpu] & 0x80) { 416 /* Priority Mask in upper half */ 417 pmask = 0x80 | (pmask >> 1); 418 } else { 419 /* Non-secure write ignored if priority mask is in lower half */ 420 return; 421 } 422 } 423 s->priority_mask[cpu] = pmask; 424 } 425 426 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 427 { 428 uint32_t pmask = s->priority_mask[cpu]; 429 430 if (s->security_extn && !attrs.secure) { 431 if (pmask & 0x80) { 432 /* Priority Mask in upper half, return Non-secure view */ 433 pmask = (pmask << 1) & 0xff; 434 } else { 435 /* Priority Mask in lower half, RAZ */ 436 pmask = 0; 437 } 438 } 439 return pmask; 440 } 441 442 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 443 { 444 uint32_t ret = s->cpu_ctlr[cpu]; 445 446 if (s->security_extn && !attrs.secure) { 447 /* Construct the NS banked view of GICC_CTLR from the correct 448 * bits of the S banked view. We don't need to move the bypass 449 * control bits because we don't implement that (IMPDEF) part 450 * of the GIC architecture. 451 */ 452 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 453 } 454 return ret; 455 } 456 457 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 458 MemTxAttrs attrs) 459 { 460 uint32_t mask; 461 462 if (s->security_extn && !attrs.secure) { 463 /* The NS view can only write certain bits in the register; 464 * the rest are unchanged 465 */ 466 mask = GICC_CTLR_EN_GRP1; 467 if (s->revision == 2) { 468 mask |= GICC_CTLR_EOIMODE_NS; 469 } 470 s->cpu_ctlr[cpu] &= ~mask; 471 s->cpu_ctlr[cpu] |= (value << 1) & mask; 472 } else { 473 if (s->revision == 2) { 474 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 475 } else { 476 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 477 } 478 s->cpu_ctlr[cpu] = value & mask; 479 } 480 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 481 "Group1 Interrupts %sabled\n", cpu, 482 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 483 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 484 } 485 486 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 487 { 488 if (s->security_extn && !attrs.secure) { 489 if (s->running_priority[cpu] & 0x80) { 490 /* Running priority in upper half of range: return the Non-secure 491 * view of the priority. 492 */ 493 return s->running_priority[cpu] << 1; 494 } else { 495 /* Running priority in lower half of range: RAZ */ 496 return 0; 497 } 498 } else { 499 return s->running_priority[cpu]; 500 } 501 } 502 503 /* Return true if we should split priority drop and interrupt deactivation, 504 * ie whether the relevant EOIMode bit is set. 505 */ 506 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 507 { 508 if (s->revision != 2) { 509 /* Before GICv2 prio-drop and deactivate are not separable */ 510 return false; 511 } 512 if (s->security_extn && !attrs.secure) { 513 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 514 } 515 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 516 } 517 518 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 519 { 520 int cm = 1 << cpu; 521 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 522 523 if (!gic_eoi_split(s, cpu, attrs)) { 524 /* This is UNPREDICTABLE; we choose to ignore it */ 525 qemu_log_mask(LOG_GUEST_ERROR, 526 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 527 return; 528 } 529 530 if (s->security_extn && !attrs.secure && !group) { 531 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 532 return; 533 } 534 535 GIC_CLEAR_ACTIVE(irq, cm); 536 } 537 538 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 539 { 540 int cm = 1 << cpu; 541 int group; 542 543 DPRINTF("EOI %d\n", irq); 544 if (irq >= s->num_irq) { 545 /* This handles two cases: 546 * 1. If software writes the ID of a spurious interrupt [ie 1023] 547 * to the GICC_EOIR, the GIC ignores that write. 548 * 2. If software writes the number of a non-existent interrupt 549 * this must be a subcase of "value written does not match the last 550 * valid interrupt value read from the Interrupt Acknowledge 551 * register" and so this is UNPREDICTABLE. We choose to ignore it. 552 */ 553 return; 554 } 555 if (s->running_priority[cpu] == 0x100) { 556 return; /* No active IRQ. */ 557 } 558 559 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 560 /* Mark level triggered interrupts as pending if they are still 561 raised. */ 562 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 563 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 564 DPRINTF("Set %d pending mask %x\n", irq, cm); 565 GIC_SET_PENDING(irq, cm); 566 } 567 } 568 569 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 570 571 if (s->security_extn && !attrs.secure && !group) { 572 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 573 return; 574 } 575 576 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 577 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 578 * i.e. go ahead and complete the irq anyway. 579 */ 580 581 gic_drop_prio(s, cpu, group); 582 583 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 584 if (!gic_eoi_split(s, cpu, attrs)) { 585 GIC_CLEAR_ACTIVE(irq, cm); 586 } 587 gic_update(s); 588 } 589 590 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 591 { 592 GICState *s = (GICState *)opaque; 593 uint32_t res; 594 int irq; 595 int i; 596 int cpu; 597 int cm; 598 int mask; 599 600 cpu = gic_get_current_cpu(s); 601 cm = 1 << cpu; 602 if (offset < 0x100) { 603 if (offset == 0) { /* GICD_CTLR */ 604 if (s->security_extn && !attrs.secure) { 605 /* The NS bank of this register is just an alias of the 606 * EnableGrp1 bit in the S bank version. 607 */ 608 return extract32(s->ctlr, 1, 1); 609 } else { 610 return s->ctlr; 611 } 612 } 613 if (offset == 4) 614 /* Interrupt Controller Type Register */ 615 return ((s->num_irq / 32) - 1) 616 | ((s->num_cpu - 1) << 5) 617 | (s->security_extn << 10); 618 if (offset < 0x08) 619 return 0; 620 if (offset >= 0x80) { 621 /* Interrupt Group Registers: these RAZ/WI if this is an NS 622 * access to a GIC with the security extensions, or if the GIC 623 * doesn't have groups at all. 624 */ 625 res = 0; 626 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 627 /* Every byte offset holds 8 group status bits */ 628 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 629 if (irq >= s->num_irq) { 630 goto bad_reg; 631 } 632 for (i = 0; i < 8; i++) { 633 if (GIC_TEST_GROUP(irq + i, cm)) { 634 res |= (1 << i); 635 } 636 } 637 } 638 return res; 639 } 640 goto bad_reg; 641 } else if (offset < 0x200) { 642 /* Interrupt Set/Clear Enable. */ 643 if (offset < 0x180) 644 irq = (offset - 0x100) * 8; 645 else 646 irq = (offset - 0x180) * 8; 647 irq += GIC_BASE_IRQ; 648 if (irq >= s->num_irq) 649 goto bad_reg; 650 res = 0; 651 for (i = 0; i < 8; i++) { 652 if (GIC_TEST_ENABLED(irq + i, cm)) { 653 res |= (1 << i); 654 } 655 } 656 } else if (offset < 0x300) { 657 /* Interrupt Set/Clear Pending. */ 658 if (offset < 0x280) 659 irq = (offset - 0x200) * 8; 660 else 661 irq = (offset - 0x280) * 8; 662 irq += GIC_BASE_IRQ; 663 if (irq >= s->num_irq) 664 goto bad_reg; 665 res = 0; 666 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 667 for (i = 0; i < 8; i++) { 668 if (gic_test_pending(s, irq + i, mask)) { 669 res |= (1 << i); 670 } 671 } 672 } else if (offset < 0x400) { 673 /* Interrupt Active. */ 674 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 675 if (irq >= s->num_irq) 676 goto bad_reg; 677 res = 0; 678 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 679 for (i = 0; i < 8; i++) { 680 if (GIC_TEST_ACTIVE(irq + i, mask)) { 681 res |= (1 << i); 682 } 683 } 684 } else if (offset < 0x800) { 685 /* Interrupt Priority. */ 686 irq = (offset - 0x400) + GIC_BASE_IRQ; 687 if (irq >= s->num_irq) 688 goto bad_reg; 689 res = gic_get_priority(s, cpu, irq, attrs); 690 } else if (offset < 0xc00) { 691 /* Interrupt CPU Target. */ 692 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 693 /* For uniprocessor GICs these RAZ/WI */ 694 res = 0; 695 } else { 696 irq = (offset - 0x800) + GIC_BASE_IRQ; 697 if (irq >= s->num_irq) { 698 goto bad_reg; 699 } 700 if (irq >= 29 && irq <= 31) { 701 res = cm; 702 } else { 703 res = GIC_TARGET(irq); 704 } 705 } 706 } else if (offset < 0xf00) { 707 /* Interrupt Configuration. */ 708 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 709 if (irq >= s->num_irq) 710 goto bad_reg; 711 res = 0; 712 for (i = 0; i < 4; i++) { 713 if (GIC_TEST_MODEL(irq + i)) 714 res |= (1 << (i * 2)); 715 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 716 res |= (2 << (i * 2)); 717 } 718 } else if (offset < 0xf10) { 719 goto bad_reg; 720 } else if (offset < 0xf30) { 721 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 722 goto bad_reg; 723 } 724 725 if (offset < 0xf20) { 726 /* GICD_CPENDSGIRn */ 727 irq = (offset - 0xf10); 728 } else { 729 irq = (offset - 0xf20); 730 /* GICD_SPENDSGIRn */ 731 } 732 733 res = s->sgi_pending[irq][cpu]; 734 } else if (offset < 0xfd0) { 735 goto bad_reg; 736 } else if (offset < 0x1000) { 737 if (offset & 3) { 738 res = 0; 739 } else { 740 switch (s->revision) { 741 case REV_11MPCORE: 742 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 743 break; 744 case 1: 745 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 746 break; 747 case 2: 748 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 749 break; 750 case REV_NVIC: 751 /* Shouldn't be able to get here */ 752 abort(); 753 default: 754 res = 0; 755 } 756 } 757 } else { 758 g_assert_not_reached(); 759 } 760 return res; 761 bad_reg: 762 qemu_log_mask(LOG_GUEST_ERROR, 763 "gic_dist_readb: Bad offset %x\n", (int)offset); 764 return 0; 765 } 766 767 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 768 unsigned size, MemTxAttrs attrs) 769 { 770 switch (size) { 771 case 1: 772 *data = gic_dist_readb(opaque, offset, attrs); 773 return MEMTX_OK; 774 case 2: 775 *data = gic_dist_readb(opaque, offset, attrs); 776 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 777 return MEMTX_OK; 778 case 4: 779 *data = gic_dist_readb(opaque, offset, attrs); 780 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 781 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 782 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 783 return MEMTX_OK; 784 default: 785 return MEMTX_ERROR; 786 } 787 } 788 789 static void gic_dist_writeb(void *opaque, hwaddr offset, 790 uint32_t value, MemTxAttrs attrs) 791 { 792 GICState *s = (GICState *)opaque; 793 int irq; 794 int i; 795 int cpu; 796 797 cpu = gic_get_current_cpu(s); 798 if (offset < 0x100) { 799 if (offset == 0) { 800 if (s->security_extn && !attrs.secure) { 801 /* NS version is just an alias of the S version's bit 1 */ 802 s->ctlr = deposit32(s->ctlr, 1, 1, value); 803 } else if (gic_has_groups(s)) { 804 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 805 } else { 806 s->ctlr = value & GICD_CTLR_EN_GRP0; 807 } 808 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 809 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 810 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 811 } else if (offset < 4) { 812 /* ignored. */ 813 } else if (offset >= 0x80) { 814 /* Interrupt Group Registers: RAZ/WI for NS access to secure 815 * GIC, or for GICs without groups. 816 */ 817 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 818 /* Every byte offset holds 8 group status bits */ 819 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 820 if (irq >= s->num_irq) { 821 goto bad_reg; 822 } 823 for (i = 0; i < 8; i++) { 824 /* Group bits are banked for private interrupts */ 825 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 826 if (value & (1 << i)) { 827 /* Group1 (Non-secure) */ 828 GIC_SET_GROUP(irq + i, cm); 829 } else { 830 /* Group0 (Secure) */ 831 GIC_CLEAR_GROUP(irq + i, cm); 832 } 833 } 834 } 835 } else { 836 goto bad_reg; 837 } 838 } else if (offset < 0x180) { 839 /* Interrupt Set Enable. */ 840 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 841 if (irq >= s->num_irq) 842 goto bad_reg; 843 if (irq < GIC_NR_SGIS) { 844 value = 0xff; 845 } 846 847 for (i = 0; i < 8; i++) { 848 if (value & (1 << i)) { 849 int mask = 850 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 851 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 852 853 if (!GIC_TEST_ENABLED(irq + i, cm)) { 854 DPRINTF("Enabled IRQ %d\n", irq + i); 855 } 856 GIC_SET_ENABLED(irq + i, cm); 857 /* If a raised level triggered IRQ enabled then mark 858 is as pending. */ 859 if (GIC_TEST_LEVEL(irq + i, mask) 860 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 861 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 862 GIC_SET_PENDING(irq + i, mask); 863 } 864 } 865 } 866 } else if (offset < 0x200) { 867 /* Interrupt Clear Enable. */ 868 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 869 if (irq >= s->num_irq) 870 goto bad_reg; 871 if (irq < GIC_NR_SGIS) { 872 value = 0; 873 } 874 875 for (i = 0; i < 8; i++) { 876 if (value & (1 << i)) { 877 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 878 879 if (GIC_TEST_ENABLED(irq + i, cm)) { 880 DPRINTF("Disabled IRQ %d\n", irq + i); 881 } 882 GIC_CLEAR_ENABLED(irq + i, cm); 883 } 884 } 885 } else if (offset < 0x280) { 886 /* Interrupt Set Pending. */ 887 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 888 if (irq >= s->num_irq) 889 goto bad_reg; 890 if (irq < GIC_NR_SGIS) { 891 value = 0; 892 } 893 894 for (i = 0; i < 8; i++) { 895 if (value & (1 << i)) { 896 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 897 } 898 } 899 } else if (offset < 0x300) { 900 /* Interrupt Clear Pending. */ 901 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 902 if (irq >= s->num_irq) 903 goto bad_reg; 904 if (irq < GIC_NR_SGIS) { 905 value = 0; 906 } 907 908 for (i = 0; i < 8; i++) { 909 /* ??? This currently clears the pending bit for all CPUs, even 910 for per-CPU interrupts. It's unclear whether this is the 911 corect behavior. */ 912 if (value & (1 << i)) { 913 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 914 } 915 } 916 } else if (offset < 0x400) { 917 /* Interrupt Active. */ 918 goto bad_reg; 919 } else if (offset < 0x800) { 920 /* Interrupt Priority. */ 921 irq = (offset - 0x400) + GIC_BASE_IRQ; 922 if (irq >= s->num_irq) 923 goto bad_reg; 924 gic_set_priority(s, cpu, irq, value, attrs); 925 } else if (offset < 0xc00) { 926 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 927 * annoying exception of the 11MPCore's GIC. 928 */ 929 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 930 irq = (offset - 0x800) + GIC_BASE_IRQ; 931 if (irq >= s->num_irq) { 932 goto bad_reg; 933 } 934 if (irq < 29) { 935 value = 0; 936 } else if (irq < GIC_INTERNAL) { 937 value = ALL_CPU_MASK; 938 } 939 s->irq_target[irq] = value & ALL_CPU_MASK; 940 } 941 } else if (offset < 0xf00) { 942 /* Interrupt Configuration. */ 943 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 944 if (irq >= s->num_irq) 945 goto bad_reg; 946 if (irq < GIC_NR_SGIS) 947 value |= 0xaa; 948 for (i = 0; i < 4; i++) { 949 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 950 if (value & (1 << (i * 2))) { 951 GIC_SET_MODEL(irq + i); 952 } else { 953 GIC_CLEAR_MODEL(irq + i); 954 } 955 } 956 if (value & (2 << (i * 2))) { 957 GIC_SET_EDGE_TRIGGER(irq + i); 958 } else { 959 GIC_CLEAR_EDGE_TRIGGER(irq + i); 960 } 961 } 962 } else if (offset < 0xf10) { 963 /* 0xf00 is only handled for 32-bit writes. */ 964 goto bad_reg; 965 } else if (offset < 0xf20) { 966 /* GICD_CPENDSGIRn */ 967 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 968 goto bad_reg; 969 } 970 irq = (offset - 0xf10); 971 972 s->sgi_pending[irq][cpu] &= ~value; 973 if (s->sgi_pending[irq][cpu] == 0) { 974 GIC_CLEAR_PENDING(irq, 1 << cpu); 975 } 976 } else if (offset < 0xf30) { 977 /* GICD_SPENDSGIRn */ 978 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 979 goto bad_reg; 980 } 981 irq = (offset - 0xf20); 982 983 GIC_SET_PENDING(irq, 1 << cpu); 984 s->sgi_pending[irq][cpu] |= value; 985 } else { 986 goto bad_reg; 987 } 988 gic_update(s); 989 return; 990 bad_reg: 991 qemu_log_mask(LOG_GUEST_ERROR, 992 "gic_dist_writeb: Bad offset %x\n", (int)offset); 993 } 994 995 static void gic_dist_writew(void *opaque, hwaddr offset, 996 uint32_t value, MemTxAttrs attrs) 997 { 998 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 999 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1000 } 1001 1002 static void gic_dist_writel(void *opaque, hwaddr offset, 1003 uint32_t value, MemTxAttrs attrs) 1004 { 1005 GICState *s = (GICState *)opaque; 1006 if (offset == 0xf00) { 1007 int cpu; 1008 int irq; 1009 int mask; 1010 int target_cpu; 1011 1012 cpu = gic_get_current_cpu(s); 1013 irq = value & 0x3ff; 1014 switch ((value >> 24) & 3) { 1015 case 0: 1016 mask = (value >> 16) & ALL_CPU_MASK; 1017 break; 1018 case 1: 1019 mask = ALL_CPU_MASK ^ (1 << cpu); 1020 break; 1021 case 2: 1022 mask = 1 << cpu; 1023 break; 1024 default: 1025 DPRINTF("Bad Soft Int target filter\n"); 1026 mask = ALL_CPU_MASK; 1027 break; 1028 } 1029 GIC_SET_PENDING(irq, mask); 1030 target_cpu = ctz32(mask); 1031 while (target_cpu < GIC_NCPU) { 1032 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1033 mask &= ~(1 << target_cpu); 1034 target_cpu = ctz32(mask); 1035 } 1036 gic_update(s); 1037 return; 1038 } 1039 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1040 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1041 } 1042 1043 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1044 unsigned size, MemTxAttrs attrs) 1045 { 1046 switch (size) { 1047 case 1: 1048 gic_dist_writeb(opaque, offset, data, attrs); 1049 return MEMTX_OK; 1050 case 2: 1051 gic_dist_writew(opaque, offset, data, attrs); 1052 return MEMTX_OK; 1053 case 4: 1054 gic_dist_writel(opaque, offset, data, attrs); 1055 return MEMTX_OK; 1056 default: 1057 return MEMTX_ERROR; 1058 } 1059 } 1060 1061 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1062 { 1063 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1064 * second half of GICC_NSAPR. 1065 */ 1066 switch (GIC_MIN_BPR) { 1067 case 0: 1068 if (regno < 2) { 1069 return s->nsapr[regno + 2][cpu]; 1070 } 1071 break; 1072 case 1: 1073 if (regno == 0) { 1074 return s->nsapr[regno + 1][cpu]; 1075 } 1076 break; 1077 case 2: 1078 if (regno == 0) { 1079 return extract32(s->nsapr[0][cpu], 16, 16); 1080 } 1081 break; 1082 case 3: 1083 if (regno == 0) { 1084 return extract32(s->nsapr[0][cpu], 8, 8); 1085 } 1086 break; 1087 default: 1088 g_assert_not_reached(); 1089 } 1090 return 0; 1091 } 1092 1093 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1094 uint32_t value) 1095 { 1096 /* Write the Nonsecure view of GICC_APR<regno>. */ 1097 switch (GIC_MIN_BPR) { 1098 case 0: 1099 if (regno < 2) { 1100 s->nsapr[regno + 2][cpu] = value; 1101 } 1102 break; 1103 case 1: 1104 if (regno == 0) { 1105 s->nsapr[regno + 1][cpu] = value; 1106 } 1107 break; 1108 case 2: 1109 if (regno == 0) { 1110 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1111 } 1112 break; 1113 case 3: 1114 if (regno == 0) { 1115 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1116 } 1117 break; 1118 default: 1119 g_assert_not_reached(); 1120 } 1121 } 1122 1123 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1124 uint64_t *data, MemTxAttrs attrs) 1125 { 1126 switch (offset) { 1127 case 0x00: /* Control */ 1128 *data = gic_get_cpu_control(s, cpu, attrs); 1129 break; 1130 case 0x04: /* Priority mask */ 1131 *data = gic_get_priority_mask(s, cpu, attrs); 1132 break; 1133 case 0x08: /* Binary Point */ 1134 if (s->security_extn && !attrs.secure) { 1135 /* BPR is banked. Non-secure copy stored in ABPR. */ 1136 *data = s->abpr[cpu]; 1137 } else { 1138 *data = s->bpr[cpu]; 1139 } 1140 break; 1141 case 0x0c: /* Acknowledge */ 1142 *data = gic_acknowledge_irq(s, cpu, attrs); 1143 break; 1144 case 0x14: /* Running Priority */ 1145 *data = gic_get_running_priority(s, cpu, attrs); 1146 break; 1147 case 0x18: /* Highest Pending Interrupt */ 1148 *data = gic_get_current_pending_irq(s, cpu, attrs); 1149 break; 1150 case 0x1c: /* Aliased Binary Point */ 1151 /* GIC v2, no security: ABPR 1152 * GIC v1, no security: not implemented (RAZ/WI) 1153 * With security extensions, secure access: ABPR (alias of NS BPR) 1154 * With security extensions, nonsecure access: RAZ/WI 1155 */ 1156 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1157 *data = 0; 1158 } else { 1159 *data = s->abpr[cpu]; 1160 } 1161 break; 1162 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1163 { 1164 int regno = (offset - 0xd0) / 4; 1165 1166 if (regno >= GIC_NR_APRS || s->revision != 2) { 1167 *data = 0; 1168 } else if (s->security_extn && !attrs.secure) { 1169 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1170 *data = gic_apr_ns_view(s, regno, cpu); 1171 } else { 1172 *data = s->apr[regno][cpu]; 1173 } 1174 break; 1175 } 1176 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1177 { 1178 int regno = (offset - 0xe0) / 4; 1179 1180 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1181 (s->security_extn && !attrs.secure)) { 1182 *data = 0; 1183 } else { 1184 *data = s->nsapr[regno][cpu]; 1185 } 1186 break; 1187 } 1188 default: 1189 qemu_log_mask(LOG_GUEST_ERROR, 1190 "gic_cpu_read: Bad offset %x\n", (int)offset); 1191 return MEMTX_ERROR; 1192 } 1193 return MEMTX_OK; 1194 } 1195 1196 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1197 uint32_t value, MemTxAttrs attrs) 1198 { 1199 switch (offset) { 1200 case 0x00: /* Control */ 1201 gic_set_cpu_control(s, cpu, value, attrs); 1202 break; 1203 case 0x04: /* Priority mask */ 1204 gic_set_priority_mask(s, cpu, value, attrs); 1205 break; 1206 case 0x08: /* Binary Point */ 1207 if (s->security_extn && !attrs.secure) { 1208 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1209 } else { 1210 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1211 } 1212 break; 1213 case 0x10: /* End Of Interrupt */ 1214 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1215 return MEMTX_OK; 1216 case 0x1c: /* Aliased Binary Point */ 1217 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1218 /* unimplemented, or NS access: RAZ/WI */ 1219 return MEMTX_OK; 1220 } else { 1221 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1222 } 1223 break; 1224 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1225 { 1226 int regno = (offset - 0xd0) / 4; 1227 1228 if (regno >= GIC_NR_APRS || s->revision != 2) { 1229 return MEMTX_OK; 1230 } 1231 if (s->security_extn && !attrs.secure) { 1232 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1233 gic_apr_write_ns_view(s, regno, cpu, value); 1234 } else { 1235 s->apr[regno][cpu] = value; 1236 } 1237 break; 1238 } 1239 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1240 { 1241 int regno = (offset - 0xe0) / 4; 1242 1243 if (regno >= GIC_NR_APRS || s->revision != 2) { 1244 return MEMTX_OK; 1245 } 1246 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1247 return MEMTX_OK; 1248 } 1249 s->nsapr[regno][cpu] = value; 1250 break; 1251 } 1252 case 0x1000: 1253 /* GICC_DIR */ 1254 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1255 break; 1256 default: 1257 qemu_log_mask(LOG_GUEST_ERROR, 1258 "gic_cpu_write: Bad offset %x\n", (int)offset); 1259 return MEMTX_ERROR; 1260 } 1261 gic_update(s); 1262 return MEMTX_OK; 1263 } 1264 1265 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1266 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1267 unsigned size, MemTxAttrs attrs) 1268 { 1269 GICState *s = (GICState *)opaque; 1270 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1271 } 1272 1273 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1274 uint64_t value, unsigned size, 1275 MemTxAttrs attrs) 1276 { 1277 GICState *s = (GICState *)opaque; 1278 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1279 } 1280 1281 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1282 * These just decode the opaque pointer into GICState* + cpu id. 1283 */ 1284 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1285 unsigned size, MemTxAttrs attrs) 1286 { 1287 GICState **backref = (GICState **)opaque; 1288 GICState *s = *backref; 1289 int id = (backref - s->backref); 1290 return gic_cpu_read(s, id, addr, data, attrs); 1291 } 1292 1293 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1294 uint64_t value, unsigned size, 1295 MemTxAttrs attrs) 1296 { 1297 GICState **backref = (GICState **)opaque; 1298 GICState *s = *backref; 1299 int id = (backref - s->backref); 1300 return gic_cpu_write(s, id, addr, value, attrs); 1301 } 1302 1303 static const MemoryRegionOps gic_ops[2] = { 1304 { 1305 .read_with_attrs = gic_dist_read, 1306 .write_with_attrs = gic_dist_write, 1307 .endianness = DEVICE_NATIVE_ENDIAN, 1308 }, 1309 { 1310 .read_with_attrs = gic_thiscpu_read, 1311 .write_with_attrs = gic_thiscpu_write, 1312 .endianness = DEVICE_NATIVE_ENDIAN, 1313 } 1314 }; 1315 1316 static const MemoryRegionOps gic_cpu_ops = { 1317 .read_with_attrs = gic_do_cpu_read, 1318 .write_with_attrs = gic_do_cpu_write, 1319 .endianness = DEVICE_NATIVE_ENDIAN, 1320 }; 1321 1322 /* This function is used by nvic model */ 1323 void gic_init_irqs_and_distributor(GICState *s) 1324 { 1325 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1326 } 1327 1328 static void arm_gic_realize(DeviceState *dev, Error **errp) 1329 { 1330 /* Device instance realize function for the GIC sysbus device */ 1331 int i; 1332 GICState *s = ARM_GIC(dev); 1333 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1334 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1335 Error *local_err = NULL; 1336 1337 agc->parent_realize(dev, &local_err); 1338 if (local_err) { 1339 error_propagate(errp, local_err); 1340 return; 1341 } 1342 1343 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1344 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1345 1346 /* Extra core-specific regions for the CPU interfaces. This is 1347 * necessary for "franken-GIC" implementations, for example on 1348 * Exynos 4. 1349 * NB that the memory region size of 0x100 applies for the 11MPCore 1350 * and also cores following the GIC v1 spec (ie A9). 1351 * GIC v2 defines a larger memory region (0x1000) so this will need 1352 * to be extended when we implement A15. 1353 */ 1354 for (i = 0; i < s->num_cpu; i++) { 1355 s->backref[i] = s; 1356 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1357 &s->backref[i], "gic_cpu", 0x100); 1358 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1359 } 1360 } 1361 1362 static void arm_gic_class_init(ObjectClass *klass, void *data) 1363 { 1364 DeviceClass *dc = DEVICE_CLASS(klass); 1365 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1366 1367 agc->parent_realize = dc->realize; 1368 dc->realize = arm_gic_realize; 1369 } 1370 1371 static const TypeInfo arm_gic_info = { 1372 .name = TYPE_ARM_GIC, 1373 .parent = TYPE_ARM_GIC_COMMON, 1374 .instance_size = sizeof(GICState), 1375 .class_init = arm_gic_class_init, 1376 .class_size = sizeof(ARMGICClass), 1377 }; 1378 1379 static void arm_gic_register_types(void) 1380 { 1381 type_register_static(&arm_gic_info); 1382 } 1383 1384 type_init(arm_gic_register_types) 1385