1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 29 //#define DEBUG_GIC 30 31 #ifdef DEBUG_GIC 32 #define DPRINTF(fmt, ...) \ 33 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 34 #else 35 #define DPRINTF(fmt, ...) do {} while(0) 36 #endif 37 38 static const uint8_t gic_id_11mpcore[] = { 39 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 40 }; 41 42 static const uint8_t gic_id_gicv1[] = { 43 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 44 }; 45 46 static const uint8_t gic_id_gicv2[] = { 47 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 48 }; 49 50 static inline int gic_get_current_cpu(GICState *s) 51 { 52 if (s->num_cpu > 1) { 53 return current_cpu->cpu_index; 54 } 55 return 0; 56 } 57 58 /* Return true if this GIC config has interrupt groups, which is 59 * true if we're a GICv2, or a GICv1 with the security extensions. 60 */ 61 static inline bool gic_has_groups(GICState *s) 62 { 63 return s->revision == 2 || s->security_extn; 64 } 65 66 /* TODO: Many places that call this routine could be optimized. */ 67 /* Update interrupt status after enabled or pending bits have been changed. */ 68 void gic_update(GICState *s) 69 { 70 int best_irq; 71 int best_prio; 72 int irq; 73 int irq_level, fiq_level; 74 int cpu; 75 int cm; 76 77 for (cpu = 0; cpu < s->num_cpu; cpu++) { 78 cm = 1 << cpu; 79 s->current_pending[cpu] = 1023; 80 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 81 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 82 qemu_irq_lower(s->parent_irq[cpu]); 83 qemu_irq_lower(s->parent_fiq[cpu]); 84 continue; 85 } 86 best_prio = 0x100; 87 best_irq = 1023; 88 for (irq = 0; irq < s->num_irq; irq++) { 89 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 90 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 91 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 92 best_prio = GIC_GET_PRIORITY(irq, cpu); 93 best_irq = irq; 94 } 95 } 96 } 97 98 if (best_irq != 1023) { 99 trace_gic_update_bestirq(cpu, best_irq, best_prio, 100 s->priority_mask[cpu], s->running_priority[cpu]); 101 } 102 103 irq_level = fiq_level = 0; 104 105 if (best_prio < s->priority_mask[cpu]) { 106 s->current_pending[cpu] = best_irq; 107 if (best_prio < s->running_priority[cpu]) { 108 int group = GIC_TEST_GROUP(best_irq, cm); 109 110 if (extract32(s->ctlr, group, 1) && 111 extract32(s->cpu_ctlr[cpu], group, 1)) { 112 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 113 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 114 best_irq, cpu); 115 fiq_level = 1; 116 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 117 } else { 118 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 119 best_irq, cpu); 120 irq_level = 1; 121 trace_gic_update_set_irq(cpu, "irq", irq_level); 122 } 123 } 124 } 125 } 126 127 qemu_set_irq(s->parent_irq[cpu], irq_level); 128 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 129 } 130 } 131 132 void gic_set_pending_private(GICState *s, int cpu, int irq) 133 { 134 int cm = 1 << cpu; 135 136 if (gic_test_pending(s, irq, cm)) { 137 return; 138 } 139 140 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 141 GIC_SET_PENDING(irq, cm); 142 gic_update(s); 143 } 144 145 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 146 int cm, int target) 147 { 148 if (level) { 149 GIC_SET_LEVEL(irq, cm); 150 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 151 DPRINTF("Set %d pending mask %x\n", irq, target); 152 GIC_SET_PENDING(irq, target); 153 } 154 } else { 155 GIC_CLEAR_LEVEL(irq, cm); 156 } 157 } 158 159 static void gic_set_irq_generic(GICState *s, int irq, int level, 160 int cm, int target) 161 { 162 if (level) { 163 GIC_SET_LEVEL(irq, cm); 164 DPRINTF("Set %d pending mask %x\n", irq, target); 165 if (GIC_TEST_EDGE_TRIGGER(irq)) { 166 GIC_SET_PENDING(irq, target); 167 } 168 } else { 169 GIC_CLEAR_LEVEL(irq, cm); 170 } 171 } 172 173 /* Process a change in an external IRQ input. */ 174 static void gic_set_irq(void *opaque, int irq, int level) 175 { 176 /* Meaning of the 'irq' parameter: 177 * [0..N-1] : external interrupts 178 * [N..N+31] : PPI (internal) interrupts for CPU 0 179 * [N+32..N+63] : PPI (internal interrupts for CPU 1 180 * ... 181 */ 182 GICState *s = (GICState *)opaque; 183 int cm, target; 184 if (irq < (s->num_irq - GIC_INTERNAL)) { 185 /* The first external input line is internal interrupt 32. */ 186 cm = ALL_CPU_MASK; 187 irq += GIC_INTERNAL; 188 target = GIC_TARGET(irq); 189 } else { 190 int cpu; 191 irq -= (s->num_irq - GIC_INTERNAL); 192 cpu = irq / GIC_INTERNAL; 193 irq %= GIC_INTERNAL; 194 cm = 1 << cpu; 195 target = cm; 196 } 197 198 assert(irq >= GIC_NR_SGIS); 199 200 if (level == GIC_TEST_LEVEL(irq, cm)) { 201 return; 202 } 203 204 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 205 gic_set_irq_11mpcore(s, irq, level, cm, target); 206 } else { 207 gic_set_irq_generic(s, irq, level, cm, target); 208 } 209 trace_gic_set_irq(irq, level, cm, target); 210 211 gic_update(s); 212 } 213 214 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 215 MemTxAttrs attrs) 216 { 217 uint16_t pending_irq = s->current_pending[cpu]; 218 219 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 220 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 221 /* On a GIC without the security extensions, reading this register 222 * behaves in the same way as a secure access to a GIC with them. 223 */ 224 bool secure = !s->security_extn || attrs.secure; 225 226 if (group == 0 && !secure) { 227 /* Group0 interrupts hidden from Non-secure access */ 228 return 1023; 229 } 230 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 231 /* Group1 interrupts only seen by Secure access if 232 * AckCtl bit set. 233 */ 234 return 1022; 235 } 236 } 237 return pending_irq; 238 } 239 240 static int gic_get_group_priority(GICState *s, int cpu, int irq) 241 { 242 /* Return the group priority of the specified interrupt 243 * (which is the top bits of its priority, with the number 244 * of bits masked determined by the applicable binary point register). 245 */ 246 int bpr; 247 uint32_t mask; 248 249 if (gic_has_groups(s) && 250 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 251 GIC_TEST_GROUP(irq, (1 << cpu))) { 252 bpr = s->abpr[cpu]; 253 } else { 254 bpr = s->bpr[cpu]; 255 } 256 257 /* a BPR of 0 means the group priority bits are [7:1]; 258 * a BPR of 1 means they are [7:2], and so on down to 259 * a BPR of 7 meaning no group priority bits at all. 260 */ 261 mask = ~0U << ((bpr & 7) + 1); 262 263 return GIC_GET_PRIORITY(irq, cpu) & mask; 264 } 265 266 static void gic_activate_irq(GICState *s, int cpu, int irq) 267 { 268 /* Set the appropriate Active Priority Register bit for this IRQ, 269 * and update the running priority. 270 */ 271 int prio = gic_get_group_priority(s, cpu, irq); 272 int preemption_level = prio >> (GIC_MIN_BPR + 1); 273 int regno = preemption_level / 32; 274 int bitno = preemption_level % 32; 275 276 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 277 s->nsapr[regno][cpu] |= (1 << bitno); 278 } else { 279 s->apr[regno][cpu] |= (1 << bitno); 280 } 281 282 s->running_priority[cpu] = prio; 283 GIC_SET_ACTIVE(irq, 1 << cpu); 284 } 285 286 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 287 { 288 /* Recalculate the current running priority for this CPU based 289 * on the set bits in the Active Priority Registers. 290 */ 291 int i; 292 for (i = 0; i < GIC_NR_APRS; i++) { 293 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 294 if (!apr) { 295 continue; 296 } 297 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 298 } 299 return 0x100; 300 } 301 302 static void gic_drop_prio(GICState *s, int cpu, int group) 303 { 304 /* Drop the priority of the currently active interrupt in the 305 * specified group. 306 * 307 * Note that we can guarantee (because of the requirement to nest 308 * GICC_IAR reads [which activate an interrupt and raise priority] 309 * with GICC_EOIR writes [which drop the priority for the interrupt]) 310 * that the interrupt we're being called for is the highest priority 311 * active interrupt, meaning that it has the lowest set bit in the 312 * APR registers. 313 * 314 * If the guest does not honour the ordering constraints then the 315 * behaviour of the GIC is UNPREDICTABLE, which for us means that 316 * the values of the APR registers might become incorrect and the 317 * running priority will be wrong, so interrupts that should preempt 318 * might not do so, and interrupts that should not preempt might do so. 319 */ 320 int i; 321 322 for (i = 0; i < GIC_NR_APRS; i++) { 323 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 324 if (!*papr) { 325 continue; 326 } 327 /* Clear lowest set bit */ 328 *papr &= *papr - 1; 329 break; 330 } 331 332 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 333 } 334 335 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 336 { 337 int ret, irq, src; 338 int cm = 1 << cpu; 339 340 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 341 * for the case where this GIC supports grouping and the pending interrupt 342 * is in the wrong group. 343 */ 344 irq = gic_get_current_pending_irq(s, cpu, attrs); 345 trace_gic_acknowledge_irq(cpu, irq); 346 347 if (irq >= GIC_MAXIRQ) { 348 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 349 return irq; 350 } 351 352 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 353 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 354 return 1023; 355 } 356 357 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 358 /* Clear pending flags for both level and edge triggered interrupts. 359 * Level triggered IRQs will be reasserted once they become inactive. 360 */ 361 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 362 ret = irq; 363 } else { 364 if (irq < GIC_NR_SGIS) { 365 /* Lookup the source CPU for the SGI and clear this in the 366 * sgi_pending map. Return the src and clear the overall pending 367 * state on this CPU if the SGI is not pending from any CPUs. 368 */ 369 assert(s->sgi_pending[irq][cpu] != 0); 370 src = ctz32(s->sgi_pending[irq][cpu]); 371 s->sgi_pending[irq][cpu] &= ~(1 << src); 372 if (s->sgi_pending[irq][cpu] == 0) { 373 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 374 } 375 ret = irq | ((src & 0x7) << 10); 376 } else { 377 /* Clear pending state for both level and edge triggered 378 * interrupts. (level triggered interrupts with an active line 379 * remain pending, see gic_test_pending) 380 */ 381 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 382 ret = irq; 383 } 384 } 385 386 gic_activate_irq(s, cpu, irq); 387 gic_update(s); 388 DPRINTF("ACK %d\n", irq); 389 return ret; 390 } 391 392 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 393 MemTxAttrs attrs) 394 { 395 if (s->security_extn && !attrs.secure) { 396 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 397 return; /* Ignore Non-secure access of Group0 IRQ */ 398 } 399 val = 0x80 | (val >> 1); /* Non-secure view */ 400 } 401 402 if (irq < GIC_INTERNAL) { 403 s->priority1[irq][cpu] = val; 404 } else { 405 s->priority2[(irq) - GIC_INTERNAL] = val; 406 } 407 } 408 409 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 410 MemTxAttrs attrs) 411 { 412 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 413 414 if (s->security_extn && !attrs.secure) { 415 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 416 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 417 } 418 prio = (prio << 1) & 0xff; /* Non-secure view */ 419 } 420 return prio; 421 } 422 423 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 424 MemTxAttrs attrs) 425 { 426 if (s->security_extn && !attrs.secure) { 427 if (s->priority_mask[cpu] & 0x80) { 428 /* Priority Mask in upper half */ 429 pmask = 0x80 | (pmask >> 1); 430 } else { 431 /* Non-secure write ignored if priority mask is in lower half */ 432 return; 433 } 434 } 435 s->priority_mask[cpu] = pmask; 436 } 437 438 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 439 { 440 uint32_t pmask = s->priority_mask[cpu]; 441 442 if (s->security_extn && !attrs.secure) { 443 if (pmask & 0x80) { 444 /* Priority Mask in upper half, return Non-secure view */ 445 pmask = (pmask << 1) & 0xff; 446 } else { 447 /* Priority Mask in lower half, RAZ */ 448 pmask = 0; 449 } 450 } 451 return pmask; 452 } 453 454 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 455 { 456 uint32_t ret = s->cpu_ctlr[cpu]; 457 458 if (s->security_extn && !attrs.secure) { 459 /* Construct the NS banked view of GICC_CTLR from the correct 460 * bits of the S banked view. We don't need to move the bypass 461 * control bits because we don't implement that (IMPDEF) part 462 * of the GIC architecture. 463 */ 464 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 465 } 466 return ret; 467 } 468 469 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 470 MemTxAttrs attrs) 471 { 472 uint32_t mask; 473 474 if (s->security_extn && !attrs.secure) { 475 /* The NS view can only write certain bits in the register; 476 * the rest are unchanged 477 */ 478 mask = GICC_CTLR_EN_GRP1; 479 if (s->revision == 2) { 480 mask |= GICC_CTLR_EOIMODE_NS; 481 } 482 s->cpu_ctlr[cpu] &= ~mask; 483 s->cpu_ctlr[cpu] |= (value << 1) & mask; 484 } else { 485 if (s->revision == 2) { 486 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 487 } else { 488 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 489 } 490 s->cpu_ctlr[cpu] = value & mask; 491 } 492 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 493 "Group1 Interrupts %sabled\n", cpu, 494 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 495 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 496 } 497 498 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 499 { 500 if (s->security_extn && !attrs.secure) { 501 if (s->running_priority[cpu] & 0x80) { 502 /* Running priority in upper half of range: return the Non-secure 503 * view of the priority. 504 */ 505 return s->running_priority[cpu] << 1; 506 } else { 507 /* Running priority in lower half of range: RAZ */ 508 return 0; 509 } 510 } else { 511 return s->running_priority[cpu]; 512 } 513 } 514 515 /* Return true if we should split priority drop and interrupt deactivation, 516 * ie whether the relevant EOIMode bit is set. 517 */ 518 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 519 { 520 if (s->revision != 2) { 521 /* Before GICv2 prio-drop and deactivate are not separable */ 522 return false; 523 } 524 if (s->security_extn && !attrs.secure) { 525 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 526 } 527 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 528 } 529 530 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 531 { 532 int cm = 1 << cpu; 533 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 534 535 if (!gic_eoi_split(s, cpu, attrs)) { 536 /* This is UNPREDICTABLE; we choose to ignore it */ 537 qemu_log_mask(LOG_GUEST_ERROR, 538 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 539 return; 540 } 541 542 if (s->security_extn && !attrs.secure && !group) { 543 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 544 return; 545 } 546 547 GIC_CLEAR_ACTIVE(irq, cm); 548 } 549 550 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 551 { 552 int cm = 1 << cpu; 553 int group; 554 555 DPRINTF("EOI %d\n", irq); 556 if (irq >= s->num_irq) { 557 /* This handles two cases: 558 * 1. If software writes the ID of a spurious interrupt [ie 1023] 559 * to the GICC_EOIR, the GIC ignores that write. 560 * 2. If software writes the number of a non-existent interrupt 561 * this must be a subcase of "value written does not match the last 562 * valid interrupt value read from the Interrupt Acknowledge 563 * register" and so this is UNPREDICTABLE. We choose to ignore it. 564 */ 565 return; 566 } 567 if (s->running_priority[cpu] == 0x100) { 568 return; /* No active IRQ. */ 569 } 570 571 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 572 /* Mark level triggered interrupts as pending if they are still 573 raised. */ 574 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 575 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 576 DPRINTF("Set %d pending mask %x\n", irq, cm); 577 GIC_SET_PENDING(irq, cm); 578 } 579 } 580 581 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 582 583 if (s->security_extn && !attrs.secure && !group) { 584 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 585 return; 586 } 587 588 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 589 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 590 * i.e. go ahead and complete the irq anyway. 591 */ 592 593 gic_drop_prio(s, cpu, group); 594 595 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 596 if (!gic_eoi_split(s, cpu, attrs)) { 597 GIC_CLEAR_ACTIVE(irq, cm); 598 } 599 gic_update(s); 600 } 601 602 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 603 { 604 GICState *s = (GICState *)opaque; 605 uint32_t res; 606 int irq; 607 int i; 608 int cpu; 609 int cm; 610 int mask; 611 612 cpu = gic_get_current_cpu(s); 613 cm = 1 << cpu; 614 if (offset < 0x100) { 615 if (offset == 0) { /* GICD_CTLR */ 616 if (s->security_extn && !attrs.secure) { 617 /* The NS bank of this register is just an alias of the 618 * EnableGrp1 bit in the S bank version. 619 */ 620 return extract32(s->ctlr, 1, 1); 621 } else { 622 return s->ctlr; 623 } 624 } 625 if (offset == 4) 626 /* Interrupt Controller Type Register */ 627 return ((s->num_irq / 32) - 1) 628 | ((s->num_cpu - 1) << 5) 629 | (s->security_extn << 10); 630 if (offset < 0x08) 631 return 0; 632 if (offset >= 0x80) { 633 /* Interrupt Group Registers: these RAZ/WI if this is an NS 634 * access to a GIC with the security extensions, or if the GIC 635 * doesn't have groups at all. 636 */ 637 res = 0; 638 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 639 /* Every byte offset holds 8 group status bits */ 640 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 641 if (irq >= s->num_irq) { 642 goto bad_reg; 643 } 644 for (i = 0; i < 8; i++) { 645 if (GIC_TEST_GROUP(irq + i, cm)) { 646 res |= (1 << i); 647 } 648 } 649 } 650 return res; 651 } 652 goto bad_reg; 653 } else if (offset < 0x200) { 654 /* Interrupt Set/Clear Enable. */ 655 if (offset < 0x180) 656 irq = (offset - 0x100) * 8; 657 else 658 irq = (offset - 0x180) * 8; 659 irq += GIC_BASE_IRQ; 660 if (irq >= s->num_irq) 661 goto bad_reg; 662 res = 0; 663 for (i = 0; i < 8; i++) { 664 if (s->security_extn && !attrs.secure && 665 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 666 continue; /* Ignore Non-secure access of Group0 IRQ */ 667 } 668 669 if (GIC_TEST_ENABLED(irq + i, cm)) { 670 res |= (1 << i); 671 } 672 } 673 } else if (offset < 0x300) { 674 /* Interrupt Set/Clear Pending. */ 675 if (offset < 0x280) 676 irq = (offset - 0x200) * 8; 677 else 678 irq = (offset - 0x280) * 8; 679 irq += GIC_BASE_IRQ; 680 if (irq >= s->num_irq) 681 goto bad_reg; 682 res = 0; 683 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 684 for (i = 0; i < 8; i++) { 685 if (s->security_extn && !attrs.secure && 686 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 687 continue; /* Ignore Non-secure access of Group0 IRQ */ 688 } 689 690 if (gic_test_pending(s, irq + i, mask)) { 691 res |= (1 << i); 692 } 693 } 694 } else if (offset < 0x400) { 695 /* Interrupt Active. */ 696 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 697 if (irq >= s->num_irq) 698 goto bad_reg; 699 res = 0; 700 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 701 for (i = 0; i < 8; i++) { 702 if (s->security_extn && !attrs.secure && 703 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 704 continue; /* Ignore Non-secure access of Group0 IRQ */ 705 } 706 707 if (GIC_TEST_ACTIVE(irq + i, mask)) { 708 res |= (1 << i); 709 } 710 } 711 } else if (offset < 0x800) { 712 /* Interrupt Priority. */ 713 irq = (offset - 0x400) + GIC_BASE_IRQ; 714 if (irq >= s->num_irq) 715 goto bad_reg; 716 res = gic_get_priority(s, cpu, irq, attrs); 717 } else if (offset < 0xc00) { 718 /* Interrupt CPU Target. */ 719 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 720 /* For uniprocessor GICs these RAZ/WI */ 721 res = 0; 722 } else { 723 irq = (offset - 0x800) + GIC_BASE_IRQ; 724 if (irq >= s->num_irq) { 725 goto bad_reg; 726 } 727 if (irq >= 29 && irq <= 31) { 728 res = cm; 729 } else { 730 res = GIC_TARGET(irq); 731 } 732 } 733 } else if (offset < 0xf00) { 734 /* Interrupt Configuration. */ 735 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 736 if (irq >= s->num_irq) 737 goto bad_reg; 738 res = 0; 739 for (i = 0; i < 4; i++) { 740 if (s->security_extn && !attrs.secure && 741 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 742 continue; /* Ignore Non-secure access of Group0 IRQ */ 743 } 744 745 if (GIC_TEST_MODEL(irq + i)) 746 res |= (1 << (i * 2)); 747 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 748 res |= (2 << (i * 2)); 749 } 750 } else if (offset < 0xf10) { 751 goto bad_reg; 752 } else if (offset < 0xf30) { 753 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 754 goto bad_reg; 755 } 756 757 if (offset < 0xf20) { 758 /* GICD_CPENDSGIRn */ 759 irq = (offset - 0xf10); 760 } else { 761 irq = (offset - 0xf20); 762 /* GICD_SPENDSGIRn */ 763 } 764 765 if (s->security_extn && !attrs.secure && 766 !GIC_TEST_GROUP(irq, 1 << cpu)) { 767 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 768 } else { 769 res = s->sgi_pending[irq][cpu]; 770 } 771 } else if (offset < 0xfd0) { 772 goto bad_reg; 773 } else if (offset < 0x1000) { 774 if (offset & 3) { 775 res = 0; 776 } else { 777 switch (s->revision) { 778 case REV_11MPCORE: 779 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 780 break; 781 case 1: 782 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 783 break; 784 case 2: 785 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 786 break; 787 case REV_NVIC: 788 /* Shouldn't be able to get here */ 789 abort(); 790 default: 791 res = 0; 792 } 793 } 794 } else { 795 g_assert_not_reached(); 796 } 797 return res; 798 bad_reg: 799 qemu_log_mask(LOG_GUEST_ERROR, 800 "gic_dist_readb: Bad offset %x\n", (int)offset); 801 return 0; 802 } 803 804 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 805 unsigned size, MemTxAttrs attrs) 806 { 807 switch (size) { 808 case 1: 809 *data = gic_dist_readb(opaque, offset, attrs); 810 return MEMTX_OK; 811 case 2: 812 *data = gic_dist_readb(opaque, offset, attrs); 813 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 814 return MEMTX_OK; 815 case 4: 816 *data = gic_dist_readb(opaque, offset, attrs); 817 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 818 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 819 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 820 return MEMTX_OK; 821 default: 822 return MEMTX_ERROR; 823 } 824 } 825 826 static void gic_dist_writeb(void *opaque, hwaddr offset, 827 uint32_t value, MemTxAttrs attrs) 828 { 829 GICState *s = (GICState *)opaque; 830 int irq; 831 int i; 832 int cpu; 833 834 cpu = gic_get_current_cpu(s); 835 if (offset < 0x100) { 836 if (offset == 0) { 837 if (s->security_extn && !attrs.secure) { 838 /* NS version is just an alias of the S version's bit 1 */ 839 s->ctlr = deposit32(s->ctlr, 1, 1, value); 840 } else if (gic_has_groups(s)) { 841 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 842 } else { 843 s->ctlr = value & GICD_CTLR_EN_GRP0; 844 } 845 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 846 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 847 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 848 } else if (offset < 4) { 849 /* ignored. */ 850 } else if (offset >= 0x80) { 851 /* Interrupt Group Registers: RAZ/WI for NS access to secure 852 * GIC, or for GICs without groups. 853 */ 854 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 855 /* Every byte offset holds 8 group status bits */ 856 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 857 if (irq >= s->num_irq) { 858 goto bad_reg; 859 } 860 for (i = 0; i < 8; i++) { 861 /* Group bits are banked for private interrupts */ 862 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 863 if (value & (1 << i)) { 864 /* Group1 (Non-secure) */ 865 GIC_SET_GROUP(irq + i, cm); 866 } else { 867 /* Group0 (Secure) */ 868 GIC_CLEAR_GROUP(irq + i, cm); 869 } 870 } 871 } 872 } else { 873 goto bad_reg; 874 } 875 } else if (offset < 0x180) { 876 /* Interrupt Set Enable. */ 877 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 878 if (irq >= s->num_irq) 879 goto bad_reg; 880 if (irq < GIC_NR_SGIS) { 881 value = 0xff; 882 } 883 884 for (i = 0; i < 8; i++) { 885 if (value & (1 << i)) { 886 int mask = 887 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 888 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 889 890 if (s->security_extn && !attrs.secure && 891 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 892 continue; /* Ignore Non-secure access of Group0 IRQ */ 893 } 894 895 if (!GIC_TEST_ENABLED(irq + i, cm)) { 896 DPRINTF("Enabled IRQ %d\n", irq + i); 897 trace_gic_enable_irq(irq + i); 898 } 899 GIC_SET_ENABLED(irq + i, cm); 900 /* If a raised level triggered IRQ enabled then mark 901 is as pending. */ 902 if (GIC_TEST_LEVEL(irq + i, mask) 903 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 904 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 905 GIC_SET_PENDING(irq + i, mask); 906 } 907 } 908 } 909 } else if (offset < 0x200) { 910 /* Interrupt Clear Enable. */ 911 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 912 if (irq >= s->num_irq) 913 goto bad_reg; 914 if (irq < GIC_NR_SGIS) { 915 value = 0; 916 } 917 918 for (i = 0; i < 8; i++) { 919 if (value & (1 << i)) { 920 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 921 922 if (s->security_extn && !attrs.secure && 923 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 924 continue; /* Ignore Non-secure access of Group0 IRQ */ 925 } 926 927 if (GIC_TEST_ENABLED(irq + i, cm)) { 928 DPRINTF("Disabled IRQ %d\n", irq + i); 929 trace_gic_disable_irq(irq + i); 930 } 931 GIC_CLEAR_ENABLED(irq + i, cm); 932 } 933 } 934 } else if (offset < 0x280) { 935 /* Interrupt Set Pending. */ 936 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 937 if (irq >= s->num_irq) 938 goto bad_reg; 939 if (irq < GIC_NR_SGIS) { 940 value = 0; 941 } 942 943 for (i = 0; i < 8; i++) { 944 if (value & (1 << i)) { 945 if (s->security_extn && !attrs.secure && 946 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 947 continue; /* Ignore Non-secure access of Group0 IRQ */ 948 } 949 950 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 951 } 952 } 953 } else if (offset < 0x300) { 954 /* Interrupt Clear Pending. */ 955 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 956 if (irq >= s->num_irq) 957 goto bad_reg; 958 if (irq < GIC_NR_SGIS) { 959 value = 0; 960 } 961 962 for (i = 0; i < 8; i++) { 963 if (s->security_extn && !attrs.secure && 964 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 965 continue; /* Ignore Non-secure access of Group0 IRQ */ 966 } 967 968 /* ??? This currently clears the pending bit for all CPUs, even 969 for per-CPU interrupts. It's unclear whether this is the 970 corect behavior. */ 971 if (value & (1 << i)) { 972 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 973 } 974 } 975 } else if (offset < 0x400) { 976 /* Interrupt Active. */ 977 goto bad_reg; 978 } else if (offset < 0x800) { 979 /* Interrupt Priority. */ 980 irq = (offset - 0x400) + GIC_BASE_IRQ; 981 if (irq >= s->num_irq) 982 goto bad_reg; 983 gic_set_priority(s, cpu, irq, value, attrs); 984 } else if (offset < 0xc00) { 985 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 986 * annoying exception of the 11MPCore's GIC. 987 */ 988 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 989 irq = (offset - 0x800) + GIC_BASE_IRQ; 990 if (irq >= s->num_irq) { 991 goto bad_reg; 992 } 993 if (irq < 29) { 994 value = 0; 995 } else if (irq < GIC_INTERNAL) { 996 value = ALL_CPU_MASK; 997 } 998 s->irq_target[irq] = value & ALL_CPU_MASK; 999 } 1000 } else if (offset < 0xf00) { 1001 /* Interrupt Configuration. */ 1002 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1003 if (irq >= s->num_irq) 1004 goto bad_reg; 1005 if (irq < GIC_NR_SGIS) 1006 value |= 0xaa; 1007 for (i = 0; i < 4; i++) { 1008 if (s->security_extn && !attrs.secure && 1009 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1010 continue; /* Ignore Non-secure access of Group0 IRQ */ 1011 } 1012 1013 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 1014 if (value & (1 << (i * 2))) { 1015 GIC_SET_MODEL(irq + i); 1016 } else { 1017 GIC_CLEAR_MODEL(irq + i); 1018 } 1019 } 1020 if (value & (2 << (i * 2))) { 1021 GIC_SET_EDGE_TRIGGER(irq + i); 1022 } else { 1023 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1024 } 1025 } 1026 } else if (offset < 0xf10) { 1027 /* 0xf00 is only handled for 32-bit writes. */ 1028 goto bad_reg; 1029 } else if (offset < 0xf20) { 1030 /* GICD_CPENDSGIRn */ 1031 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 1032 goto bad_reg; 1033 } 1034 irq = (offset - 0xf10); 1035 1036 if (!s->security_extn || attrs.secure || 1037 GIC_TEST_GROUP(irq, 1 << cpu)) { 1038 s->sgi_pending[irq][cpu] &= ~value; 1039 if (s->sgi_pending[irq][cpu] == 0) { 1040 GIC_CLEAR_PENDING(irq, 1 << cpu); 1041 } 1042 } 1043 } else if (offset < 0xf30) { 1044 /* GICD_SPENDSGIRn */ 1045 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 1046 goto bad_reg; 1047 } 1048 irq = (offset - 0xf20); 1049 1050 if (!s->security_extn || attrs.secure || 1051 GIC_TEST_GROUP(irq, 1 << cpu)) { 1052 GIC_SET_PENDING(irq, 1 << cpu); 1053 s->sgi_pending[irq][cpu] |= value; 1054 } 1055 } else { 1056 goto bad_reg; 1057 } 1058 gic_update(s); 1059 return; 1060 bad_reg: 1061 qemu_log_mask(LOG_GUEST_ERROR, 1062 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1063 } 1064 1065 static void gic_dist_writew(void *opaque, hwaddr offset, 1066 uint32_t value, MemTxAttrs attrs) 1067 { 1068 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1069 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1070 } 1071 1072 static void gic_dist_writel(void *opaque, hwaddr offset, 1073 uint32_t value, MemTxAttrs attrs) 1074 { 1075 GICState *s = (GICState *)opaque; 1076 if (offset == 0xf00) { 1077 int cpu; 1078 int irq; 1079 int mask; 1080 int target_cpu; 1081 1082 cpu = gic_get_current_cpu(s); 1083 irq = value & 0x3ff; 1084 switch ((value >> 24) & 3) { 1085 case 0: 1086 mask = (value >> 16) & ALL_CPU_MASK; 1087 break; 1088 case 1: 1089 mask = ALL_CPU_MASK ^ (1 << cpu); 1090 break; 1091 case 2: 1092 mask = 1 << cpu; 1093 break; 1094 default: 1095 DPRINTF("Bad Soft Int target filter\n"); 1096 mask = ALL_CPU_MASK; 1097 break; 1098 } 1099 GIC_SET_PENDING(irq, mask); 1100 target_cpu = ctz32(mask); 1101 while (target_cpu < GIC_NCPU) { 1102 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1103 mask &= ~(1 << target_cpu); 1104 target_cpu = ctz32(mask); 1105 } 1106 gic_update(s); 1107 return; 1108 } 1109 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1110 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1111 } 1112 1113 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1114 unsigned size, MemTxAttrs attrs) 1115 { 1116 switch (size) { 1117 case 1: 1118 gic_dist_writeb(opaque, offset, data, attrs); 1119 return MEMTX_OK; 1120 case 2: 1121 gic_dist_writew(opaque, offset, data, attrs); 1122 return MEMTX_OK; 1123 case 4: 1124 gic_dist_writel(opaque, offset, data, attrs); 1125 return MEMTX_OK; 1126 default: 1127 return MEMTX_ERROR; 1128 } 1129 } 1130 1131 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1132 { 1133 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1134 * second half of GICC_NSAPR. 1135 */ 1136 switch (GIC_MIN_BPR) { 1137 case 0: 1138 if (regno < 2) { 1139 return s->nsapr[regno + 2][cpu]; 1140 } 1141 break; 1142 case 1: 1143 if (regno == 0) { 1144 return s->nsapr[regno + 1][cpu]; 1145 } 1146 break; 1147 case 2: 1148 if (regno == 0) { 1149 return extract32(s->nsapr[0][cpu], 16, 16); 1150 } 1151 break; 1152 case 3: 1153 if (regno == 0) { 1154 return extract32(s->nsapr[0][cpu], 8, 8); 1155 } 1156 break; 1157 default: 1158 g_assert_not_reached(); 1159 } 1160 return 0; 1161 } 1162 1163 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1164 uint32_t value) 1165 { 1166 /* Write the Nonsecure view of GICC_APR<regno>. */ 1167 switch (GIC_MIN_BPR) { 1168 case 0: 1169 if (regno < 2) { 1170 s->nsapr[regno + 2][cpu] = value; 1171 } 1172 break; 1173 case 1: 1174 if (regno == 0) { 1175 s->nsapr[regno + 1][cpu] = value; 1176 } 1177 break; 1178 case 2: 1179 if (regno == 0) { 1180 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1181 } 1182 break; 1183 case 3: 1184 if (regno == 0) { 1185 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1186 } 1187 break; 1188 default: 1189 g_assert_not_reached(); 1190 } 1191 } 1192 1193 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1194 uint64_t *data, MemTxAttrs attrs) 1195 { 1196 switch (offset) { 1197 case 0x00: /* Control */ 1198 *data = gic_get_cpu_control(s, cpu, attrs); 1199 break; 1200 case 0x04: /* Priority mask */ 1201 *data = gic_get_priority_mask(s, cpu, attrs); 1202 break; 1203 case 0x08: /* Binary Point */ 1204 if (s->security_extn && !attrs.secure) { 1205 /* BPR is banked. Non-secure copy stored in ABPR. */ 1206 *data = s->abpr[cpu]; 1207 } else { 1208 *data = s->bpr[cpu]; 1209 } 1210 break; 1211 case 0x0c: /* Acknowledge */ 1212 *data = gic_acknowledge_irq(s, cpu, attrs); 1213 break; 1214 case 0x14: /* Running Priority */ 1215 *data = gic_get_running_priority(s, cpu, attrs); 1216 break; 1217 case 0x18: /* Highest Pending Interrupt */ 1218 *data = gic_get_current_pending_irq(s, cpu, attrs); 1219 break; 1220 case 0x1c: /* Aliased Binary Point */ 1221 /* GIC v2, no security: ABPR 1222 * GIC v1, no security: not implemented (RAZ/WI) 1223 * With security extensions, secure access: ABPR (alias of NS BPR) 1224 * With security extensions, nonsecure access: RAZ/WI 1225 */ 1226 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1227 *data = 0; 1228 } else { 1229 *data = s->abpr[cpu]; 1230 } 1231 break; 1232 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1233 { 1234 int regno = (offset - 0xd0) / 4; 1235 1236 if (regno >= GIC_NR_APRS || s->revision != 2) { 1237 *data = 0; 1238 } else if (s->security_extn && !attrs.secure) { 1239 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1240 *data = gic_apr_ns_view(s, regno, cpu); 1241 } else { 1242 *data = s->apr[regno][cpu]; 1243 } 1244 break; 1245 } 1246 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1247 { 1248 int regno = (offset - 0xe0) / 4; 1249 1250 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1251 (s->security_extn && !attrs.secure)) { 1252 *data = 0; 1253 } else { 1254 *data = s->nsapr[regno][cpu]; 1255 } 1256 break; 1257 } 1258 default: 1259 qemu_log_mask(LOG_GUEST_ERROR, 1260 "gic_cpu_read: Bad offset %x\n", (int)offset); 1261 return MEMTX_ERROR; 1262 } 1263 return MEMTX_OK; 1264 } 1265 1266 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1267 uint32_t value, MemTxAttrs attrs) 1268 { 1269 switch (offset) { 1270 case 0x00: /* Control */ 1271 gic_set_cpu_control(s, cpu, value, attrs); 1272 break; 1273 case 0x04: /* Priority mask */ 1274 gic_set_priority_mask(s, cpu, value, attrs); 1275 break; 1276 case 0x08: /* Binary Point */ 1277 if (s->security_extn && !attrs.secure) { 1278 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1279 } else { 1280 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1281 } 1282 break; 1283 case 0x10: /* End Of Interrupt */ 1284 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1285 return MEMTX_OK; 1286 case 0x1c: /* Aliased Binary Point */ 1287 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1288 /* unimplemented, or NS access: RAZ/WI */ 1289 return MEMTX_OK; 1290 } else { 1291 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1292 } 1293 break; 1294 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1295 { 1296 int regno = (offset - 0xd0) / 4; 1297 1298 if (regno >= GIC_NR_APRS || s->revision != 2) { 1299 return MEMTX_OK; 1300 } 1301 if (s->security_extn && !attrs.secure) { 1302 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1303 gic_apr_write_ns_view(s, regno, cpu, value); 1304 } else { 1305 s->apr[regno][cpu] = value; 1306 } 1307 break; 1308 } 1309 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1310 { 1311 int regno = (offset - 0xe0) / 4; 1312 1313 if (regno >= GIC_NR_APRS || s->revision != 2) { 1314 return MEMTX_OK; 1315 } 1316 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1317 return MEMTX_OK; 1318 } 1319 s->nsapr[regno][cpu] = value; 1320 break; 1321 } 1322 case 0x1000: 1323 /* GICC_DIR */ 1324 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1325 break; 1326 default: 1327 qemu_log_mask(LOG_GUEST_ERROR, 1328 "gic_cpu_write: Bad offset %x\n", (int)offset); 1329 return MEMTX_ERROR; 1330 } 1331 gic_update(s); 1332 return MEMTX_OK; 1333 } 1334 1335 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1336 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1337 unsigned size, MemTxAttrs attrs) 1338 { 1339 GICState *s = (GICState *)opaque; 1340 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1341 } 1342 1343 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1344 uint64_t value, unsigned size, 1345 MemTxAttrs attrs) 1346 { 1347 GICState *s = (GICState *)opaque; 1348 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1349 } 1350 1351 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1352 * These just decode the opaque pointer into GICState* + cpu id. 1353 */ 1354 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1355 unsigned size, MemTxAttrs attrs) 1356 { 1357 GICState **backref = (GICState **)opaque; 1358 GICState *s = *backref; 1359 int id = (backref - s->backref); 1360 return gic_cpu_read(s, id, addr, data, attrs); 1361 } 1362 1363 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1364 uint64_t value, unsigned size, 1365 MemTxAttrs attrs) 1366 { 1367 GICState **backref = (GICState **)opaque; 1368 GICState *s = *backref; 1369 int id = (backref - s->backref); 1370 return gic_cpu_write(s, id, addr, value, attrs); 1371 } 1372 1373 static const MemoryRegionOps gic_ops[2] = { 1374 { 1375 .read_with_attrs = gic_dist_read, 1376 .write_with_attrs = gic_dist_write, 1377 .endianness = DEVICE_NATIVE_ENDIAN, 1378 }, 1379 { 1380 .read_with_attrs = gic_thiscpu_read, 1381 .write_with_attrs = gic_thiscpu_write, 1382 .endianness = DEVICE_NATIVE_ENDIAN, 1383 } 1384 }; 1385 1386 static const MemoryRegionOps gic_cpu_ops = { 1387 .read_with_attrs = gic_do_cpu_read, 1388 .write_with_attrs = gic_do_cpu_write, 1389 .endianness = DEVICE_NATIVE_ENDIAN, 1390 }; 1391 1392 /* This function is used by nvic model */ 1393 void gic_init_irqs_and_distributor(GICState *s) 1394 { 1395 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1396 } 1397 1398 static void arm_gic_realize(DeviceState *dev, Error **errp) 1399 { 1400 /* Device instance realize function for the GIC sysbus device */ 1401 int i; 1402 GICState *s = ARM_GIC(dev); 1403 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1404 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1405 Error *local_err = NULL; 1406 1407 agc->parent_realize(dev, &local_err); 1408 if (local_err) { 1409 error_propagate(errp, local_err); 1410 return; 1411 } 1412 1413 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1414 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1415 1416 /* Extra core-specific regions for the CPU interfaces. This is 1417 * necessary for "franken-GIC" implementations, for example on 1418 * Exynos 4. 1419 * NB that the memory region size of 0x100 applies for the 11MPCore 1420 * and also cores following the GIC v1 spec (ie A9). 1421 * GIC v2 defines a larger memory region (0x1000) so this will need 1422 * to be extended when we implement A15. 1423 */ 1424 for (i = 0; i < s->num_cpu; i++) { 1425 s->backref[i] = s; 1426 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1427 &s->backref[i], "gic_cpu", 0x100); 1428 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1429 } 1430 } 1431 1432 static void arm_gic_class_init(ObjectClass *klass, void *data) 1433 { 1434 DeviceClass *dc = DEVICE_CLASS(klass); 1435 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1436 1437 agc->parent_realize = dc->realize; 1438 dc->realize = arm_gic_realize; 1439 } 1440 1441 static const TypeInfo arm_gic_info = { 1442 .name = TYPE_ARM_GIC, 1443 .parent = TYPE_ARM_GIC_COMMON, 1444 .instance_size = sizeof(GICState), 1445 .class_init = arm_gic_class_init, 1446 .class_size = sizeof(ARMGICClass), 1447 }; 1448 1449 static void arm_gic_register_types(void) 1450 { 1451 type_register_static(&arm_gic_info); 1452 } 1453 1454 type_init(arm_gic_register_types) 1455