1 /* 2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system 3 * 4 * Copyright (C) 2015 Linaro, All rights reserved. 5 * 6 * Author: Christoffer Dall <christoffer.dall@linaro.org> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 /* This file implements an emulated GICv2m widget as described in the ARM 23 * Server Base System Architecture (SBSA) specification Version 2.2 24 * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined 25 * identification registers and with a single non-secure MSI register frame. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "hw/sysbus.h" 31 #include "hw/irq.h" 32 #include "hw/pci/msi.h" 33 #include "sysemu/kvm.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 37 #define TYPE_ARM_GICV2M "arm-gicv2m" 38 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M) 39 40 #define GICV2M_NUM_SPI_MAX 128 41 42 #define V2M_MSI_TYPER 0x008 43 #define V2M_MSI_SETSPI_NS 0x040 44 #define V2M_MSI_IIDR 0xFCC 45 #define V2M_IIDR0 0xFD0 46 #define V2M_IIDR11 0xFFC 47 48 #define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */ 49 50 typedef struct ARMGICv2mState { 51 SysBusDevice parent_obj; 52 53 MemoryRegion iomem; 54 qemu_irq spi[GICV2M_NUM_SPI_MAX]; 55 56 uint32_t base_spi; 57 uint32_t num_spi; 58 } ARMGICv2mState; 59 60 static void gicv2m_set_irq(void *opaque, int irq) 61 { 62 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 63 64 qemu_irq_pulse(s->spi[irq]); 65 } 66 67 static uint64_t gicv2m_read(void *opaque, hwaddr offset, 68 unsigned size) 69 { 70 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 71 uint32_t val; 72 73 if (size != 4) { 74 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size); 75 return 0; 76 } 77 78 switch (offset) { 79 case V2M_MSI_TYPER: 80 val = (s->base_spi + 32) << 16; 81 val |= s->num_spi; 82 return val; 83 case V2M_MSI_IIDR: 84 /* We don't have any valid implementor so we leave that field as zero 85 * and we return 0 in the arch revision as per the spec. 86 */ 87 return (PRODUCT_ID_QEMU << 20); 88 case V2M_IIDR0 ... V2M_IIDR11: 89 /* We do not implement any optional identification registers and the 90 * mandatory MSI_PIDR2 register reads as 0x0, so we capture all 91 * implementation defined registers here. 92 */ 93 return 0; 94 default: 95 qemu_log_mask(LOG_GUEST_ERROR, 96 "gicv2m_read: Bad offset %x\n", (int)offset); 97 return 0; 98 } 99 } 100 101 static void gicv2m_write(void *opaque, hwaddr offset, 102 uint64_t value, unsigned size) 103 { 104 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 105 106 if (size != 2 && size != 4) { 107 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size); 108 return; 109 } 110 111 switch (offset) { 112 case V2M_MSI_SETSPI_NS: { 113 int spi; 114 115 spi = (value & 0x3ff) - (s->base_spi + 32); 116 if (spi >= 0 && spi < s->num_spi) { 117 gicv2m_set_irq(s, spi); 118 } 119 return; 120 } 121 default: 122 qemu_log_mask(LOG_GUEST_ERROR, 123 "gicv2m_write: Bad offset %x\n", (int)offset); 124 } 125 } 126 127 static const MemoryRegionOps gicv2m_ops = { 128 .read = gicv2m_read, 129 .write = gicv2m_write, 130 .endianness = DEVICE_LITTLE_ENDIAN, 131 }; 132 133 static void gicv2m_realize(DeviceState *dev, Error **errp) 134 { 135 ARMGICv2mState *s = ARM_GICV2M(dev); 136 int i; 137 138 if (s->num_spi > GICV2M_NUM_SPI_MAX) { 139 error_setg(errp, 140 "requested %u SPIs exceeds GICv2m frame maximum %d", 141 s->num_spi, GICV2M_NUM_SPI_MAX); 142 return; 143 } 144 145 if (s->base_spi + 32 > 1020 - s->num_spi) { 146 error_setg(errp, 147 "requested base SPI %u+%u exceeds max. number 1020", 148 s->base_spi + 32, s->num_spi); 149 return; 150 } 151 152 for (i = 0; i < s->num_spi; i++) { 153 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); 154 } 155 156 msi_nonbroken = true; 157 kvm_gsi_direct_mapping = true; 158 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 159 } 160 161 static void gicv2m_init(Object *obj) 162 { 163 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 164 ARMGICv2mState *s = ARM_GICV2M(obj); 165 166 memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s, 167 "gicv2m", 0x1000); 168 sysbus_init_mmio(sbd, &s->iomem); 169 } 170 171 static Property gicv2m_properties[] = { 172 DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0), 173 DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64), 174 DEFINE_PROP_END_OF_LIST(), 175 }; 176 177 static void gicv2m_class_init(ObjectClass *klass, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->props = gicv2m_properties; 182 dc->realize = gicv2m_realize; 183 } 184 185 static const TypeInfo gicv2m_info = { 186 .name = TYPE_ARM_GICV2M, 187 .parent = TYPE_SYS_BUS_DEVICE, 188 .instance_size = sizeof(ARMGICv2mState), 189 .instance_init = gicv2m_init, 190 .class_init = gicv2m_class_init, 191 }; 192 193 static void gicv2m_register_types(void) 194 { 195 type_register_static(&gicv2m_info); 196 } 197 198 type_init(gicv2m_register_types) 199