1 /* 2 * ARM GICv3 emulation: Distributor 3 * 4 * Copyright (c) 2015 Huawei. 5 * Copyright (c) 2016 Linaro Limited. 6 * Written by Shlomo Pongratz, Peter Maydell 7 * 8 * This code is licensed under the GPL, version 2 or (at your option) 9 * any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "trace.h" 15 #include "gicv3_internal.h" 16 17 /* The GICD_NSACR registers contain a two bit field for each interrupt which 18 * allows the guest to give NonSecure code access to registers controlling 19 * Secure interrupts: 20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI) 21 * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR 22 * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER, 23 * and w/o to CLRSPI_NSR 24 * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR 25 * 26 * Given a (multiple-of-32) interrupt number, these mask functions return 27 * a mask word where each bit is 1 if the NSACR settings permit access 28 * to the interrupt. The mask returned can then be ORed with the GICD_GROUP 29 * word for this set of interrupts to give an overall mask. 30 */ 31 32 typedef uint32_t maskfn(GICv3State *s, int irq); 33 34 static uint32_t mask_nsacr_ge1(GICv3State *s, int irq) 35 { 36 /* Return a mask where each bit is set if the NSACR field is >= 1 */ 37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 38 39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr; 41 return half_unshuffle64(raw_nsacr); 42 } 43 44 static uint32_t mask_nsacr_ge2(GICv3State *s, int irq) 45 { 46 /* Return a mask where each bit is set if the NSACR field is >= 2 */ 47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 48 49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 50 raw_nsacr = raw_nsacr >> 1; 51 return half_unshuffle64(raw_nsacr); 52 } 53 54 /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register, 55 * but it would be implemented using: 56 * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr; 57 */ 58 59 static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs, 60 maskfn *maskfn, int irq) 61 { 62 /* Return a 32-bit mask which should be applied for this set of 32 63 * interrupts; each bit is 1 if access is permitted by the 64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. 65 */ 66 uint32_t mask; 67 68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI 70 * unless the NSACR bits permit access. 71 */ 72 mask = *gic_bmp_ptr32(s->group, irq); 73 if (maskfn) { 74 mask |= maskfn(s, irq); 75 } 76 return mask; 77 } 78 return 0xFFFFFFFFU; 79 } 80 81 static int gicd_ns_access(GICv3State *s, int irq) 82 { 83 /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the 84 * specified interrupt. 85 */ 86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 87 return 0; 88 } 89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); 90 } 91 92 static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 93 uint32_t *bmp, 94 maskfn *maskfn, 95 int offset, uint32_t val) 96 { 97 /* Helper routine to implement writing to a "set-bitmap" register 98 * (GICD_ISENABLER, GICD_ISPENDR, etc). 99 * Semantics implemented here: 100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 102 * Writing 1 means "set bit in bitmap"; writing 0 is ignored. 103 * offset should be the offset in bytes of the register from the start 104 * of its group. 105 */ 106 int irq = offset * 8; 107 108 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 109 return; 110 } 111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 112 *gic_bmp_ptr32(bmp, irq) |= val; 113 gicv3_update(s, irq, 32); 114 } 115 116 static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 117 uint32_t *bmp, 118 maskfn *maskfn, 119 int offset, uint32_t val) 120 { 121 /* Helper routine to implement writing to a "clear-bitmap" register 122 * (GICD_ICENABLER, GICD_ICPENDR, etc). 123 * Semantics implemented here: 124 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 125 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 126 * Writing 1 means "clear bit in bitmap"; writing 0 is ignored. 127 * offset should be the offset in bytes of the register from the start 128 * of its group. 129 */ 130 int irq = offset * 8; 131 132 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 133 return; 134 } 135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 136 *gic_bmp_ptr32(bmp, irq) &= ~val; 137 gicv3_update(s, irq, 32); 138 } 139 140 static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 141 uint32_t *bmp, 142 maskfn *maskfn, 143 int offset) 144 { 145 /* Helper routine to implement reading a "set/clear-bitmap" register 146 * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc). 147 * Semantics implemented here: 148 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 149 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 150 * offset should be the offset in bytes of the register from the start 151 * of its group. 152 */ 153 int irq = offset * 8; 154 uint32_t val; 155 156 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 157 return 0; 158 } 159 val = *gic_bmp_ptr32(bmp, irq); 160 if (bmp == s->pending) { 161 /* The PENDING register is a special case -- for level triggered 162 * interrupts, the PENDING state is the logical OR of the state of 163 * the PENDING latch with the input line level. 164 */ 165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); 166 uint32_t level = *gic_bmp_ptr32(s->level, irq); 167 val |= (~edge & level); 168 } 169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 170 return val; 171 } 172 173 static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq) 174 { 175 /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt, 176 * honouring security state (these are RAZ/WI for Group 0 or Secure 177 * Group 1 interrupts). 178 */ 179 uint32_t prio; 180 181 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 182 return 0; 183 } 184 185 prio = s->gicd_ipriority[irq]; 186 187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 188 if (!gicv3_gicd_group_test(s, irq)) { 189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 190 return 0; 191 } 192 /* NS view of the interrupt priority */ 193 prio = (prio << 1) & 0xff; 194 } 195 return prio; 196 } 197 198 static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq, 199 uint8_t value) 200 { 201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt, 202 * honouring security state (these are RAZ/WI for Group 0 or Secure 203 * Group 1 interrupts). 204 */ 205 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 206 return; 207 } 208 209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 210 if (!gicv3_gicd_group_test(s, irq)) { 211 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 212 return; 213 } 214 /* NS view of the interrupt priority */ 215 value = 0x80 | (value >> 1); 216 } 217 s->gicd_ipriority[irq] = value; 218 } 219 220 static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq) 221 { 222 /* Read the value of GICD_IROUTER<n> for the specified interrupt, 223 * honouring security state. 224 */ 225 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 226 return 0; 227 } 228 229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 230 /* RAZ/WI for NS accesses to secure interrupts */ 231 if (!gicv3_gicd_group_test(s, irq)) { 232 if (gicd_ns_access(s, irq) != 3) { 233 return 0; 234 } 235 } 236 } 237 238 return s->gicd_irouter[irq]; 239 } 240 241 static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq, 242 uint64_t val) 243 { 244 /* Write the value of GICD_IROUTER<n> for the specified interrupt, 245 * honouring security state. 246 */ 247 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 248 return; 249 } 250 251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 252 /* RAZ/WI for NS accesses to secure interrupts */ 253 if (!gicv3_gicd_group_test(s, irq)) { 254 if (gicd_ns_access(s, irq) != 3) { 255 return; 256 } 257 } 258 } 259 260 s->gicd_irouter[irq] = val; 261 gicv3_cache_target_cpustate(s, irq); 262 gicv3_update(s, irq, 1); 263 } 264 265 /** 266 * gicd_readb 267 * gicd_readw 268 * gicd_readl 269 * gicd_readq 270 * gicd_writeb 271 * gicd_writew 272 * gicd_writel 273 * gicd_writeq 274 * 275 * Return %true if the operation succeeded, %false otherwise. 276 */ 277 278 static bool gicd_readb(GICv3State *s, hwaddr offset, 279 uint64_t *data, MemTxAttrs attrs) 280 { 281 /* Most GICv3 distributor registers do not support byte accesses. */ 282 switch (offset) { 283 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 284 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 285 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 286 /* This GIC implementation always has affinity routing enabled, 287 * so these registers are all RAZ/WI. 288 */ 289 return true; 290 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 291 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static bool gicd_writeb(GICv3State *s, hwaddr offset, 299 uint64_t value, MemTxAttrs attrs) 300 { 301 /* Most GICv3 distributor registers do not support byte accesses. */ 302 switch (offset) { 303 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 304 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 305 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 306 /* This GIC implementation always has affinity routing enabled, 307 * so these registers are all RAZ/WI. 308 */ 309 return true; 310 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 311 { 312 int irq = offset - GICD_IPRIORITYR; 313 314 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 315 return true; 316 } 317 gicd_write_ipriorityr(s, attrs, irq, value); 318 gicv3_update(s, irq, 1); 319 return true; 320 } 321 default: 322 return false; 323 } 324 } 325 326 static bool gicd_readw(GICv3State *s, hwaddr offset, 327 uint64_t *data, MemTxAttrs attrs) 328 { 329 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 330 * support 16 bit accesses, and those registers are all part of the 331 * optional message-based SPI feature which this GIC does not currently 332 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 333 * reserved. 334 */ 335 return false; 336 } 337 338 static bool gicd_writew(GICv3State *s, hwaddr offset, 339 uint64_t value, MemTxAttrs attrs) 340 { 341 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 342 * support 16 bit accesses, and those registers are all part of the 343 * optional message-based SPI feature which this GIC does not currently 344 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 345 * reserved. 346 */ 347 return false; 348 } 349 350 static bool gicd_readl(GICv3State *s, hwaddr offset, 351 uint64_t *data, MemTxAttrs attrs) 352 { 353 /* Almost all GICv3 distributor registers are 32-bit. 354 * Note that WO registers must return an UNKNOWN value on reads, 355 * not an abort. 356 */ 357 358 switch (offset) { 359 case GICD_CTLR: 360 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 361 /* The NS view of the GICD_CTLR sees only certain bits: 362 * + bit [31] (RWP) is an alias of the Secure bit [31] 363 * + bit [4] (ARE_NS) is an alias of Secure bit [5] 364 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if 365 * NS affinity routing is enabled, otherwise RES0 366 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if 367 * NS affinity routing is not enabled, otherwise RES0 368 * Since for QEMU affinity routing is always enabled 369 * for both S and NS this means that bits [4] and [5] are 370 * both always 1, and we can simply make the NS view 371 * be bits 31, 4 and 1 of the S view. 372 */ 373 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | 374 GICD_CTLR_EN_GRP1NS | 375 GICD_CTLR_RWP); 376 } else { 377 *data = s->gicd_ctlr; 378 } 379 return true; 380 case GICD_TYPER: 381 { 382 /* For this implementation: 383 * No1N == 1 (1-of-N SPI interrupts not supported) 384 * A3V == 1 (non-zero values of Affinity level 3 supported) 385 * IDbits == 0xf (we support 16-bit interrupt identifiers) 386 * DVIS == 0 (Direct virtual LPI injection not supported) 387 * LPIS == 0 (LPIs not supported) 388 * MBIS == 0 (message-based SPIs not supported) 389 * SecurityExtn == 1 if security extns supported 390 * CPUNumber == 0 since for us ARE is always 1 391 * ITLinesNumber == (num external irqs / 32) - 1 392 */ 393 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; 394 /* 395 * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and 396 * "security extensions not supported" always implies DS == 1, 397 * so we only need to check the DS bit. 398 */ 399 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); 400 401 *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | 402 (0xf << 19) | itlinesnumber; 403 return true; 404 } 405 case GICD_IIDR: 406 /* We claim to be an ARM r0p0 with a zero ProductID. 407 * This is the same as an r0p0 GIC-500. 408 */ 409 *data = gicv3_iidr(); 410 return true; 411 case GICD_STATUSR: 412 /* RAZ/WI for us (this is an optional register and our implementation 413 * does not track RO/WO/reserved violations to report them to the guest) 414 */ 415 *data = 0; 416 return true; 417 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 418 { 419 int irq; 420 421 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 422 *data = 0; 423 return true; 424 } 425 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 426 irq = (offset - GICD_IGROUPR) * 8; 427 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 428 *data = 0; 429 return true; 430 } 431 *data = *gic_bmp_ptr32(s->group, irq); 432 return true; 433 } 434 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 435 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 436 offset - GICD_ISENABLER); 437 return true; 438 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 439 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 440 offset - GICD_ICENABLER); 441 return true; 442 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 443 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 444 offset - GICD_ISPENDR); 445 return true; 446 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 447 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 448 offset - GICD_ICPENDR); 449 return true; 450 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 451 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 452 offset - GICD_ISACTIVER); 453 return true; 454 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 455 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 456 offset - GICD_ICACTIVER); 457 return true; 458 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 459 { 460 int i, irq = offset - GICD_IPRIORITYR; 461 uint32_t value = 0; 462 463 for (i = irq + 3; i >= irq; i--) { 464 value <<= 8; 465 value |= gicd_read_ipriorityr(s, attrs, i); 466 } 467 *data = value; 468 return true; 469 } 470 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 471 /* RAZ/WI since affinity routing is always enabled */ 472 *data = 0; 473 return true; 474 case GICD_ICFGR ... GICD_ICFGR + 0xff: 475 { 476 /* Here only the even bits are used; odd bits are RES0 */ 477 int irq = (offset - GICD_ICFGR) * 4; 478 uint32_t value = 0; 479 480 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 481 *data = 0; 482 return true; 483 } 484 485 /* Since our edge_trigger bitmap is one bit per irq, we only need 486 * half of the 32-bit word, which we can then spread out 487 * into the odd bits. 488 */ 489 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); 490 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 491 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16); 492 value = half_shuffle32(value) << 1; 493 *data = value; 494 return true; 495 } 496 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 497 { 498 int irq; 499 500 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 501 /* RAZ/WI if security disabled, or if 502 * security enabled and this is an NS access 503 */ 504 *data = 0; 505 return true; 506 } 507 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 508 irq = (offset - GICD_IGRPMODR) * 8; 509 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 510 *data = 0; 511 return true; 512 } 513 *data = *gic_bmp_ptr32(s->grpmod, irq); 514 return true; 515 } 516 case GICD_NSACR ... GICD_NSACR + 0xff: 517 { 518 /* Two bits per interrupt */ 519 int irq = (offset - GICD_NSACR) * 4; 520 521 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 522 *data = 0; 523 return true; 524 } 525 526 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 527 /* RAZ/WI if security disabled, or if 528 * security enabled and this is an NS access 529 */ 530 *data = 0; 531 return true; 532 } 533 534 *data = s->gicd_nsacr[irq / 16]; 535 return true; 536 } 537 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 538 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 539 /* RAZ/WI since affinity routing is always enabled */ 540 *data = 0; 541 return true; 542 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 543 { 544 uint64_t r; 545 int irq = (offset - GICD_IROUTER) / 8; 546 547 r = gicd_read_irouter(s, attrs, irq); 548 if (offset & 7) { 549 *data = r >> 32; 550 } else { 551 *data = (uint32_t)r; 552 } 553 return true; 554 } 555 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 556 /* ID registers */ 557 *data = gicv3_idreg(offset - GICD_IDREGS); 558 return true; 559 case GICD_SGIR: 560 /* WO registers, return unknown value */ 561 qemu_log_mask(LOG_GUEST_ERROR, 562 "%s: invalid guest read from WO register at offset " 563 TARGET_FMT_plx "\n", __func__, offset); 564 *data = 0; 565 return true; 566 default: 567 return false; 568 } 569 } 570 571 static bool gicd_writel(GICv3State *s, hwaddr offset, 572 uint64_t value, MemTxAttrs attrs) 573 { 574 /* Almost all GICv3 distributor registers are 32-bit. Note that 575 * RO registers must ignore writes, not abort. 576 */ 577 578 switch (offset) { 579 case GICD_CTLR: 580 { 581 uint32_t mask; 582 /* GICv3 5.3.20 */ 583 if (s->gicd_ctlr & GICD_CTLR_DS) { 584 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, 585 * ARE is RAO/WI (affinity routing always on), and only 586 * bits 0 and 1 (group enables) are writable. 587 */ 588 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS; 589 } else { 590 if (attrs.secure) { 591 /* for secure access: 592 * ARE_NS and ARE_S are RAO/WI (affinity routing always on) 593 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) 594 * 595 * We can only modify bits[2:0] (the group enables). 596 */ 597 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL; 598 } else { 599 /* For non secure access ARE_NS is RAO/WI and EnableGrp1 600 * is RES0. The only writable bit is [1] (EnableGrp1A), which 601 * is an alias of the Secure bit [1]. 602 */ 603 mask = GICD_CTLR_EN_GRP1NS; 604 } 605 } 606 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); 607 if (value & mask & GICD_CTLR_DS) { 608 /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. 609 * Note that this is a one-way transition because if DS is set 610 * then it's not writeable, so it can only go back to 0 with a 611 * hardware reset. 612 */ 613 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); 614 } 615 gicv3_full_update(s); 616 return true; 617 } 618 case GICD_STATUSR: 619 /* RAZ/WI for our implementation */ 620 return true; 621 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 622 { 623 int irq; 624 625 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 626 return true; 627 } 628 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 629 irq = (offset - GICD_IGROUPR) * 8; 630 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 631 return true; 632 } 633 *gic_bmp_ptr32(s->group, irq) = value; 634 gicv3_update(s, irq, 32); 635 return true; 636 } 637 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 638 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, 639 offset - GICD_ISENABLER, value); 640 return true; 641 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 642 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, 643 offset - GICD_ICENABLER, value); 644 return true; 645 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 646 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 647 offset - GICD_ISPENDR, value); 648 return true; 649 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 650 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 651 offset - GICD_ICPENDR, value); 652 return true; 653 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 654 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, 655 offset - GICD_ISACTIVER, value); 656 return true; 657 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 658 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, 659 offset - GICD_ICACTIVER, value); 660 return true; 661 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 662 { 663 int i, irq = offset - GICD_IPRIORITYR; 664 665 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { 666 return true; 667 } 668 669 for (i = irq; i < irq + 4; i++, value >>= 8) { 670 gicd_write_ipriorityr(s, attrs, i, value); 671 } 672 gicv3_update(s, irq, 4); 673 return true; 674 } 675 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 676 /* RAZ/WI since affinity routing is always enabled */ 677 return true; 678 case GICD_ICFGR ... GICD_ICFGR + 0xff: 679 { 680 /* Here only the odd bits are used; even bits are RES0 */ 681 int irq = (offset - GICD_ICFGR) * 4; 682 uint32_t mask, oldval; 683 684 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 685 return true; 686 } 687 688 /* Since our edge_trigger bitmap is one bit per irq, our input 689 * 32-bits will compress down into 16 bits which we need 690 * to write into the bitmap. 691 */ 692 value = half_unshuffle32(value >> 1); 693 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 694 if (irq & 0x1f) { 695 value <<= 16; 696 mask &= 0xffff0000U; 697 } else { 698 mask &= 0xffff; 699 } 700 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); 701 value = (oldval & ~mask) | (value & mask); 702 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; 703 return true; 704 } 705 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 706 { 707 int irq; 708 709 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 710 /* RAZ/WI if security disabled, or if 711 * security enabled and this is an NS access 712 */ 713 return true; 714 } 715 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 716 irq = (offset - GICD_IGRPMODR) * 8; 717 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 718 return true; 719 } 720 *gic_bmp_ptr32(s->grpmod, irq) = value; 721 gicv3_update(s, irq, 32); 722 return true; 723 } 724 case GICD_NSACR ... GICD_NSACR + 0xff: 725 { 726 /* Two bits per interrupt */ 727 int irq = (offset - GICD_NSACR) * 4; 728 729 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 730 return true; 731 } 732 733 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 734 /* RAZ/WI if security disabled, or if 735 * security enabled and this is an NS access 736 */ 737 return true; 738 } 739 740 s->gicd_nsacr[irq / 16] = value; 741 /* No update required as this only affects access permission checks */ 742 return true; 743 } 744 case GICD_SGIR: 745 /* RES0 if affinity routing is enabled */ 746 return true; 747 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 748 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 749 /* RAZ/WI since affinity routing is always enabled */ 750 return true; 751 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 752 { 753 uint64_t r; 754 int irq = (offset - GICD_IROUTER) / 8; 755 756 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 757 return true; 758 } 759 760 /* Write half of the 64-bit register */ 761 r = gicd_read_irouter(s, attrs, irq); 762 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value); 763 gicd_write_irouter(s, attrs, irq, r); 764 return true; 765 } 766 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 767 case GICD_TYPER: 768 case GICD_IIDR: 769 /* RO registers, ignore the write */ 770 qemu_log_mask(LOG_GUEST_ERROR, 771 "%s: invalid guest write to RO register at offset " 772 TARGET_FMT_plx "\n", __func__, offset); 773 return true; 774 default: 775 return false; 776 } 777 } 778 779 static bool gicd_writeq(GICv3State *s, hwaddr offset, 780 uint64_t value, MemTxAttrs attrs) 781 { 782 /* Our only 64-bit registers are GICD_IROUTER<n> */ 783 int irq; 784 785 switch (offset) { 786 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 787 irq = (offset - GICD_IROUTER) / 8; 788 gicd_write_irouter(s, attrs, irq, value); 789 return true; 790 default: 791 return false; 792 } 793 } 794 795 static bool gicd_readq(GICv3State *s, hwaddr offset, 796 uint64_t *data, MemTxAttrs attrs) 797 { 798 /* Our only 64-bit registers are GICD_IROUTER<n> */ 799 int irq; 800 801 switch (offset) { 802 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 803 irq = (offset - GICD_IROUTER) / 8; 804 *data = gicd_read_irouter(s, attrs, irq); 805 return true; 806 default: 807 return false; 808 } 809 } 810 811 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 812 unsigned size, MemTxAttrs attrs) 813 { 814 GICv3State *s = (GICv3State *)opaque; 815 bool r; 816 817 switch (size) { 818 case 1: 819 r = gicd_readb(s, offset, data, attrs); 820 break; 821 case 2: 822 r = gicd_readw(s, offset, data, attrs); 823 break; 824 case 4: 825 r = gicd_readl(s, offset, data, attrs); 826 break; 827 case 8: 828 r = gicd_readq(s, offset, data, attrs); 829 break; 830 default: 831 r = false; 832 break; 833 } 834 835 if (!r) { 836 qemu_log_mask(LOG_GUEST_ERROR, 837 "%s: invalid guest read at offset " TARGET_FMT_plx 838 "size %u\n", __func__, offset, size); 839 trace_gicv3_dist_badread(offset, size, attrs.secure); 840 /* The spec requires that reserved registers are RAZ/WI; 841 * so use MEMTX_ERROR returns from leaf functions as a way to 842 * trigger the guest-error logging but don't return it to 843 * the caller, or we'll cause a spurious guest data abort. 844 */ 845 *data = 0; 846 } else { 847 trace_gicv3_dist_read(offset, *data, size, attrs.secure); 848 } 849 return MEMTX_OK; 850 } 851 852 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, 853 unsigned size, MemTxAttrs attrs) 854 { 855 GICv3State *s = (GICv3State *)opaque; 856 bool r; 857 858 switch (size) { 859 case 1: 860 r = gicd_writeb(s, offset, data, attrs); 861 break; 862 case 2: 863 r = gicd_writew(s, offset, data, attrs); 864 break; 865 case 4: 866 r = gicd_writel(s, offset, data, attrs); 867 break; 868 case 8: 869 r = gicd_writeq(s, offset, data, attrs); 870 break; 871 default: 872 r = false; 873 break; 874 } 875 876 if (!r) { 877 qemu_log_mask(LOG_GUEST_ERROR, 878 "%s: invalid guest write at offset " TARGET_FMT_plx 879 "size %u\n", __func__, offset, size); 880 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); 881 /* The spec requires that reserved registers are RAZ/WI; 882 * so use MEMTX_ERROR returns from leaf functions as a way to 883 * trigger the guest-error logging but don't return it to 884 * the caller, or we'll cause a spurious guest data abort. 885 */ 886 } else { 887 trace_gicv3_dist_write(offset, data, size, attrs.secure); 888 } 889 return MEMTX_OK; 890 } 891 892 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) 893 { 894 /* Update distributor state for a change in an external SPI input line */ 895 if (level == gicv3_gicd_level_test(s, irq)) { 896 return; 897 } 898 899 trace_gicv3_dist_set_irq(irq, level); 900 901 gicv3_gicd_level_replace(s, irq, level); 902 903 if (level) { 904 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ 905 if (gicv3_gicd_edge_trigger_test(s, irq)) { 906 gicv3_gicd_pending_set(s, irq); 907 } 908 } 909 910 gicv3_update(s, irq, 1); 911 } 912