xref: /qemu/hw/intc/bcm2836_control.c (revision 64552b6b) 
1 /*
2  * Rasperry Pi 2 emulation ARM control logic module.
3  * Copyright (c) 2015, Microsoft
4  * Written by Andrew Baumann
5  *
6  * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
7  * This code is licensed under the GNU GPLv2 and later.
8  *
9  * At present, only implements interrupt routing, and mailboxes (i.e.,
10  * not PMU interrupt, or AXI counters).
11  *
12  * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
13  *
14  * Ref:
15  * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
16  */
17 
18 #include "qemu/osdep.h"
19 #include "hw/intc/bcm2836_control.h"
20 #include "hw/irq.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 
24 #define REG_GPU_ROUTE           0x0c
25 #define REG_LOCALTIMERROUTING   0x24
26 #define REG_LOCALTIMERCONTROL   0x34
27 #define REG_LOCALTIMERACK       0x38
28 #define REG_TIMERCONTROL        0x40
29 #define REG_MBOXCONTROL         0x50
30 #define REG_IRQSRC              0x60
31 #define REG_FIQSRC              0x70
32 #define REG_MBOX0_WR            0x80
33 #define REG_MBOX0_RDCLR         0xc0
34 #define REG_LIMIT              0x100
35 
36 #define IRQ_BIT(cntrl, num) (((cntrl) & (1 << (num))) != 0)
37 #define FIQ_BIT(cntrl, num) (((cntrl) & (1 << ((num) + 4))) != 0)
38 
39 #define IRQ_CNTPSIRQ    0
40 #define IRQ_CNTPNSIRQ   1
41 #define IRQ_CNTHPIRQ    2
42 #define IRQ_CNTVIRQ     3
43 #define IRQ_MAILBOX0    4
44 #define IRQ_MAILBOX1    5
45 #define IRQ_MAILBOX2    6
46 #define IRQ_MAILBOX3    7
47 #define IRQ_GPU         8
48 #define IRQ_PMU         9
49 #define IRQ_AXI         10
50 #define IRQ_TIMER       11
51 #define IRQ_MAX         IRQ_TIMER
52 
53 #define LOCALTIMER_FREQ      38400000
54 #define LOCALTIMER_INTFLAG   (1 << 31)
55 #define LOCALTIMER_RELOAD    (1 << 30)
56 #define LOCALTIMER_INTENABLE (1 << 29)
57 #define LOCALTIMER_ENABLE    (1 << 28)
58 #define LOCALTIMER_VALUE(x)  ((x) & 0xfffffff)
59 
60 static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
61                           uint32_t controlreg, uint8_t controlidx)
62 {
63     if (FIQ_BIT(controlreg, controlidx)) {
64         /* deliver a FIQ */
65         s->fiqsrc[core] |= (uint32_t)1 << irq;
66     } else if (IRQ_BIT(controlreg, controlidx)) {
67         /* deliver an IRQ */
68         s->irqsrc[core] |= (uint32_t)1 << irq;
69     } else {
70         /* the interrupt is masked */
71     }
72 }
73 
74 /* Update interrupts.  */
75 static void bcm2836_control_update(BCM2836ControlState *s)
76 {
77     int i, j;
78 
79     /* reset pending IRQs/FIQs */
80     for (i = 0; i < BCM2836_NCORES; i++) {
81         s->irqsrc[i] = s->fiqsrc[i] = 0;
82     }
83 
84     /* apply routing logic, update status regs */
85     if (s->gpu_irq) {
86         assert(s->route_gpu_irq < BCM2836_NCORES);
87         s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU;
88     }
89 
90     if (s->gpu_fiq) {
91         assert(s->route_gpu_fiq < BCM2836_NCORES);
92         s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
93     }
94 
95     /*
96      * handle the control module 'local timer' interrupt for one of the
97      * cores' IRQ/FIQ;  this is distinct from the per-CPU timer
98      * interrupts handled below.
99      */
100     if ((s->local_timer_control & LOCALTIMER_INTENABLE) &&
101         (s->local_timer_control & LOCALTIMER_INTFLAG)) {
102         if (s->route_localtimer & 4) {
103             s->fiqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
104         } else {
105             s->irqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
106         }
107     }
108 
109     for (i = 0; i < BCM2836_NCORES; i++) {
110         /* handle local timer interrupts for this core */
111         if (s->timerirqs[i]) {
112             assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */
113             for (j = 0; j <= IRQ_CNTVIRQ; j++) {
114                 if ((s->timerirqs[i] & (1 << j)) != 0) {
115                     /* local interrupt j is set */
116                     deliver_local(s, i, j, s->timercontrol[i], j);
117                 }
118             }
119         }
120 
121         /* handle mailboxes for this core */
122         for (j = 0; j < BCM2836_MBPERCORE; j++) {
123             if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) {
124                 /* mailbox j is set */
125                 deliver_local(s, i, j + IRQ_MAILBOX0, s->mailboxcontrol[i], j);
126             }
127         }
128     }
129 
130     /* call set_irq appropriately for each output */
131     for (i = 0; i < BCM2836_NCORES; i++) {
132         qemu_set_irq(s->irq[i], s->irqsrc[i] != 0);
133         qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0);
134     }
135 }
136 
137 static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq,
138                                           int level)
139 {
140     BCM2836ControlState *s = opaque;
141 
142     assert(core >= 0 && core < BCM2836_NCORES);
143     assert(local_irq >= 0 && local_irq <= IRQ_CNTVIRQ);
144 
145     s->timerirqs[core] = deposit32(s->timerirqs[core], local_irq, 1, !!level);
146 
147     bcm2836_control_update(s);
148 }
149 
150 /* XXX: the following wrapper functions are a kludgy workaround,
151  * needed because I can't seem to pass useful information in the "irq"
152  * parameter when using named interrupts. Feel free to clean this up!
153  */
154 
155 static void bcm2836_control_set_local_irq0(void *opaque, int core, int level)
156 {
157     bcm2836_control_set_local_irq(opaque, core, 0, level);
158 }
159 
160 static void bcm2836_control_set_local_irq1(void *opaque, int core, int level)
161 {
162     bcm2836_control_set_local_irq(opaque, core, 1, level);
163 }
164 
165 static void bcm2836_control_set_local_irq2(void *opaque, int core, int level)
166 {
167     bcm2836_control_set_local_irq(opaque, core, 2, level);
168 }
169 
170 static void bcm2836_control_set_local_irq3(void *opaque, int core, int level)
171 {
172     bcm2836_control_set_local_irq(opaque, core, 3, level);
173 }
174 
175 static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level)
176 {
177     BCM2836ControlState *s = opaque;
178 
179     s->gpu_irq = level;
180 
181     bcm2836_control_update(s);
182 }
183 
184 static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level)
185 {
186     BCM2836ControlState *s = opaque;
187 
188     s->gpu_fiq = level;
189 
190     bcm2836_control_update(s);
191 }
192 
193 static void bcm2836_control_local_timer_set_next(void *opaque)
194 {
195     BCM2836ControlState *s = opaque;
196     uint64_t next_event;
197 
198     assert(LOCALTIMER_VALUE(s->local_timer_control) > 0);
199 
200     next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
201         muldiv64(LOCALTIMER_VALUE(s->local_timer_control),
202             NANOSECONDS_PER_SECOND, LOCALTIMER_FREQ);
203     timer_mod(&s->timer, next_event);
204 }
205 
206 static void bcm2836_control_local_timer_tick(void *opaque)
207 {
208     BCM2836ControlState *s = opaque;
209 
210     bcm2836_control_local_timer_set_next(s);
211 
212     s->local_timer_control |= LOCALTIMER_INTFLAG;
213     bcm2836_control_update(s);
214 }
215 
216 static void bcm2836_control_local_timer_control(void *opaque, uint32_t val)
217 {
218     BCM2836ControlState *s = opaque;
219 
220     s->local_timer_control = val;
221     if (val & LOCALTIMER_ENABLE) {
222         bcm2836_control_local_timer_set_next(s);
223     } else {
224         timer_del(&s->timer);
225     }
226 }
227 
228 static void bcm2836_control_local_timer_ack(void *opaque, uint32_t val)
229 {
230     BCM2836ControlState *s = opaque;
231 
232     if (val & LOCALTIMER_INTFLAG) {
233         s->local_timer_control &= ~LOCALTIMER_INTFLAG;
234     }
235     if ((val & LOCALTIMER_RELOAD) &&
236         (s->local_timer_control & LOCALTIMER_ENABLE)) {
237             bcm2836_control_local_timer_set_next(s);
238     }
239 }
240 
241 static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
242 {
243     BCM2836ControlState *s = opaque;
244 
245     if (offset == REG_GPU_ROUTE) {
246         assert(s->route_gpu_fiq < BCM2836_NCORES
247                && s->route_gpu_irq < BCM2836_NCORES);
248         return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
249     } else if (offset == REG_LOCALTIMERROUTING) {
250         return s->route_localtimer;
251     } else if (offset == REG_LOCALTIMERCONTROL) {
252         return s->local_timer_control;
253     } else if (offset == REG_LOCALTIMERACK) {
254         return 0;
255     } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
256         return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
257     } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
258         return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
259     } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
260         return s->irqsrc[(offset - REG_IRQSRC) >> 2];
261     } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
262         return s->fiqsrc[(offset - REG_FIQSRC) >> 2];
263     } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
264         return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2];
265     } else {
266         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
267                       __func__, offset);
268         return 0;
269     }
270 }
271 
272 static void bcm2836_control_write(void *opaque, hwaddr offset,
273                                   uint64_t val, unsigned size)
274 {
275     BCM2836ControlState *s = opaque;
276 
277     if (offset == REG_GPU_ROUTE) {
278         s->route_gpu_irq = val & 0x3;
279         s->route_gpu_fiq = (val >> 2) & 0x3;
280     } else if (offset == REG_LOCALTIMERROUTING) {
281         s->route_localtimer = val & 7;
282     } else if (offset == REG_LOCALTIMERCONTROL) {
283         bcm2836_control_local_timer_control(s, val);
284     } else if (offset == REG_LOCALTIMERACK) {
285         bcm2836_control_local_timer_ack(s, val);
286     } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
287         s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
288     } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
289         s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
290     } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
291         s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
292     } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
293         s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;
294     } else {
295         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
296                       __func__, offset);
297         return;
298     }
299 
300     bcm2836_control_update(s);
301 }
302 
303 static const MemoryRegionOps bcm2836_control_ops = {
304     .read = bcm2836_control_read,
305     .write = bcm2836_control_write,
306     .endianness = DEVICE_NATIVE_ENDIAN,
307     .valid.min_access_size = 4,
308     .valid.max_access_size = 4,
309 };
310 
311 static void bcm2836_control_reset(DeviceState *d)
312 {
313     BCM2836ControlState *s = BCM2836_CONTROL(d);
314     int i;
315 
316     s->route_gpu_irq = s->route_gpu_fiq = 0;
317 
318     timer_del(&s->timer);
319     s->route_localtimer = 0;
320     s->local_timer_control = 0;
321 
322     for (i = 0; i < BCM2836_NCORES; i++) {
323         s->timercontrol[i] = 0;
324         s->mailboxcontrol[i] = 0;
325     }
326 
327     for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) {
328         s->mailboxes[i] = 0;
329     }
330 }
331 
332 static void bcm2836_control_init(Object *obj)
333 {
334     BCM2836ControlState *s = BCM2836_CONTROL(obj);
335     DeviceState *dev = DEVICE(obj);
336 
337     memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s,
338                           TYPE_BCM2836_CONTROL, REG_LIMIT);
339     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
340 
341     /* inputs from each CPU core */
342     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq0, "cntpsirq",
343                             BCM2836_NCORES);
344     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq1, "cntpnsirq",
345                             BCM2836_NCORES);
346     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq2, "cnthpirq",
347                             BCM2836_NCORES);
348     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq3, "cntvirq",
349                             BCM2836_NCORES);
350 
351     /* IRQ and FIQ inputs from upstream bcm2835 controller */
352     qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1);
353     qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1);
354 
355     /* outputs to CPU cores */
356     qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
357     qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
358 
359     /* create a qemu virtual timer */
360     timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL,
361                   bcm2836_control_local_timer_tick, s);
362 }
363 
364 static const VMStateDescription vmstate_bcm2836_control = {
365     .name = TYPE_BCM2836_CONTROL,
366     .version_id = 2,
367     .minimum_version_id = 1,
368     .fields = (VMStateField[]) {
369         VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
370                              BCM2836_NCORES * BCM2836_MBPERCORE),
371         VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState),
372         VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState),
373         VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
374         VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
375                              BCM2836_NCORES),
376         VMSTATE_TIMER_V(timer, BCM2836ControlState, 2),
377         VMSTATE_UINT32_V(local_timer_control, BCM2836ControlState, 2),
378         VMSTATE_UINT8_V(route_localtimer, BCM2836ControlState, 2),
379         VMSTATE_END_OF_LIST()
380     }
381 };
382 
383 static void bcm2836_control_class_init(ObjectClass *klass, void *data)
384 {
385     DeviceClass *dc = DEVICE_CLASS(klass);
386 
387     dc->reset = bcm2836_control_reset;
388     dc->vmsd = &vmstate_bcm2836_control;
389 }
390 
391 static TypeInfo bcm2836_control_info = {
392     .name          = TYPE_BCM2836_CONTROL,
393     .parent        = TYPE_SYS_BUS_DEVICE,
394     .instance_size = sizeof(BCM2836ControlState),
395     .class_init    = bcm2836_control_class_init,
396     .instance_init = bcm2836_control_init,
397 };
398 
399 static void bcm2836_control_register_types(void)
400 {
401     type_register_static(&bcm2836_control_info);
402 }
403 
404 type_init(bcm2836_control_register_types)
405