1 /* 2 * Rasperry Pi 2 emulation ARM control logic module. 3 * Copyright (c) 2015, Microsoft 4 * Written by Andrew Baumann 5 * 6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade 7 * This code is licensed under the GNU GPLv2 and later. 8 * 9 * At present, only implements interrupt routing, and mailboxes (i.e., 10 * not local timer, PMU interrupt, or AXI counters). 11 * 12 * Ref: 13 * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf 14 */ 15 16 #include "hw/intc/bcm2836_control.h" 17 18 #define REG_GPU_ROUTE 0x0c 19 #define REG_TIMERCONTROL 0x40 20 #define REG_MBOXCONTROL 0x50 21 #define REG_IRQSRC 0x60 22 #define REG_FIQSRC 0x70 23 #define REG_MBOX0_WR 0x80 24 #define REG_MBOX0_RDCLR 0xc0 25 #define REG_LIMIT 0x100 26 27 #define IRQ_BIT(cntrl, num) (((cntrl) & (1 << (num))) != 0) 28 #define FIQ_BIT(cntrl, num) (((cntrl) & (1 << ((num) + 4))) != 0) 29 30 #define IRQ_CNTPSIRQ 0 31 #define IRQ_CNTPNSIRQ 1 32 #define IRQ_CNTHPIRQ 2 33 #define IRQ_CNTVIRQ 3 34 #define IRQ_MAILBOX0 4 35 #define IRQ_MAILBOX1 5 36 #define IRQ_MAILBOX2 6 37 #define IRQ_MAILBOX3 7 38 #define IRQ_GPU 8 39 #define IRQ_PMU 9 40 #define IRQ_AXI 10 41 #define IRQ_TIMER 11 42 #define IRQ_MAX IRQ_TIMER 43 44 static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq, 45 uint32_t controlreg, uint8_t controlidx) 46 { 47 if (FIQ_BIT(controlreg, controlidx)) { 48 /* deliver a FIQ */ 49 s->fiqsrc[core] |= (uint32_t)1 << irq; 50 } else if (IRQ_BIT(controlreg, controlidx)) { 51 /* deliver an IRQ */ 52 s->irqsrc[core] |= (uint32_t)1 << irq; 53 } else { 54 /* the interrupt is masked */ 55 } 56 } 57 58 /* Update interrupts. */ 59 static void bcm2836_control_update(BCM2836ControlState *s) 60 { 61 int i, j; 62 63 /* reset pending IRQs/FIQs */ 64 for (i = 0; i < BCM2836_NCORES; i++) { 65 s->irqsrc[i] = s->fiqsrc[i] = 0; 66 } 67 68 /* apply routing logic, update status regs */ 69 if (s->gpu_irq) { 70 assert(s->route_gpu_irq < BCM2836_NCORES); 71 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU; 72 } 73 74 if (s->gpu_fiq) { 75 assert(s->route_gpu_fiq < BCM2836_NCORES); 76 s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU; 77 } 78 79 for (i = 0; i < BCM2836_NCORES; i++) { 80 /* handle local timer interrupts for this core */ 81 if (s->timerirqs[i]) { 82 assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */ 83 for (j = 0; j <= IRQ_CNTVIRQ; j++) { 84 if ((s->timerirqs[i] & (1 << j)) != 0) { 85 /* local interrupt j is set */ 86 deliver_local(s, i, j, s->timercontrol[i], j); 87 } 88 } 89 } 90 91 /* handle mailboxes for this core */ 92 for (j = 0; j < BCM2836_MBPERCORE; j++) { 93 if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) { 94 /* mailbox j is set */ 95 deliver_local(s, i, j + IRQ_MAILBOX0, s->mailboxcontrol[i], j); 96 } 97 } 98 } 99 100 /* call set_irq appropriately for each output */ 101 for (i = 0; i < BCM2836_NCORES; i++) { 102 qemu_set_irq(s->irq[i], s->irqsrc[i] != 0); 103 qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0); 104 } 105 } 106 107 static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq, 108 int level) 109 { 110 BCM2836ControlState *s = opaque; 111 112 assert(core >= 0 && core < BCM2836_NCORES); 113 assert(local_irq >= 0 && local_irq <= IRQ_CNTVIRQ); 114 115 s->timerirqs[core] = deposit32(s->timerirqs[core], local_irq, 1, !!level); 116 117 bcm2836_control_update(s); 118 } 119 120 /* XXX: the following wrapper functions are a kludgy workaround, 121 * needed because I can't seem to pass useful information in the "irq" 122 * parameter when using named interrupts. Feel free to clean this up! 123 */ 124 125 static void bcm2836_control_set_local_irq0(void *opaque, int core, int level) 126 { 127 bcm2836_control_set_local_irq(opaque, core, 0, level); 128 } 129 130 static void bcm2836_control_set_local_irq1(void *opaque, int core, int level) 131 { 132 bcm2836_control_set_local_irq(opaque, core, 1, level); 133 } 134 135 static void bcm2836_control_set_local_irq2(void *opaque, int core, int level) 136 { 137 bcm2836_control_set_local_irq(opaque, core, 2, level); 138 } 139 140 static void bcm2836_control_set_local_irq3(void *opaque, int core, int level) 141 { 142 bcm2836_control_set_local_irq(opaque, core, 3, level); 143 } 144 145 static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level) 146 { 147 BCM2836ControlState *s = opaque; 148 149 s->gpu_irq = level; 150 151 bcm2836_control_update(s); 152 } 153 154 static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level) 155 { 156 BCM2836ControlState *s = opaque; 157 158 s->gpu_fiq = level; 159 160 bcm2836_control_update(s); 161 } 162 163 static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size) 164 { 165 BCM2836ControlState *s = opaque; 166 167 if (offset == REG_GPU_ROUTE) { 168 assert(s->route_gpu_fiq < BCM2836_NCORES 169 && s->route_gpu_irq < BCM2836_NCORES); 170 return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq; 171 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) { 172 return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2]; 173 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) { 174 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2]; 175 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) { 176 return s->irqsrc[(offset - REG_IRQSRC) >> 2]; 177 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) { 178 return s->fiqsrc[(offset - REG_FIQSRC) >> 2]; 179 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { 180 return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2]; 181 } else { 182 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 183 __func__, offset); 184 return 0; 185 } 186 } 187 188 static void bcm2836_control_write(void *opaque, hwaddr offset, 189 uint64_t val, unsigned size) 190 { 191 BCM2836ControlState *s = opaque; 192 193 if (offset == REG_GPU_ROUTE) { 194 s->route_gpu_irq = val & 0x3; 195 s->route_gpu_fiq = (val >> 2) & 0x3; 196 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) { 197 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff; 198 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) { 199 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff; 200 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) { 201 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val; 202 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { 203 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val; 204 } else { 205 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 206 __func__, offset); 207 return; 208 } 209 210 bcm2836_control_update(s); 211 } 212 213 static const MemoryRegionOps bcm2836_control_ops = { 214 .read = bcm2836_control_read, 215 .write = bcm2836_control_write, 216 .endianness = DEVICE_NATIVE_ENDIAN, 217 .valid.min_access_size = 4, 218 .valid.max_access_size = 4, 219 }; 220 221 static void bcm2836_control_reset(DeviceState *d) 222 { 223 BCM2836ControlState *s = BCM2836_CONTROL(d); 224 int i; 225 226 s->route_gpu_irq = s->route_gpu_fiq = 0; 227 228 for (i = 0; i < BCM2836_NCORES; i++) { 229 s->timercontrol[i] = 0; 230 s->mailboxcontrol[i] = 0; 231 } 232 233 for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) { 234 s->mailboxes[i] = 0; 235 } 236 } 237 238 static void bcm2836_control_init(Object *obj) 239 { 240 BCM2836ControlState *s = BCM2836_CONTROL(obj); 241 DeviceState *dev = DEVICE(obj); 242 243 memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s, 244 TYPE_BCM2836_CONTROL, REG_LIMIT); 245 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 246 247 /* inputs from each CPU core */ 248 qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq0, "cntpsirq", 249 BCM2836_NCORES); 250 qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq1, "cntpnsirq", 251 BCM2836_NCORES); 252 qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq2, "cnthpirq", 253 BCM2836_NCORES); 254 qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq3, "cntvirq", 255 BCM2836_NCORES); 256 257 /* IRQ and FIQ inputs from upstream bcm2835 controller */ 258 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1); 259 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1); 260 261 /* outputs to CPU cores */ 262 qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES); 263 qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES); 264 } 265 266 static const VMStateDescription vmstate_bcm2836_control = { 267 .name = TYPE_BCM2836_CONTROL, 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState, 272 BCM2836_NCORES * BCM2836_MBPERCORE), 273 VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState), 274 VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState), 275 VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES), 276 VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState, 277 BCM2836_NCORES), 278 VMSTATE_END_OF_LIST() 279 } 280 }; 281 282 static void bcm2836_control_class_init(ObjectClass *klass, void *data) 283 { 284 DeviceClass *dc = DEVICE_CLASS(klass); 285 286 dc->reset = bcm2836_control_reset; 287 dc->vmsd = &vmstate_bcm2836_control; 288 } 289 290 static TypeInfo bcm2836_control_info = { 291 .name = TYPE_BCM2836_CONTROL, 292 .parent = TYPE_SYS_BUS_DEVICE, 293 .instance_size = sizeof(BCM2836ControlState), 294 .class_init = bcm2836_control_class_init, 295 .instance_init = bcm2836_control_init, 296 }; 297 298 static void bcm2836_control_register_types(void) 299 { 300 type_register_static(&bcm2836_control_info); 301 } 302 303 type_init(bcm2836_control_register_types) 304