1 /* 2 * QEMU GRLIB IRQMP Emulator 3 * 4 * (Multiprocessor and extended interrupt not supported) 5 * 6 * Copyright (c) 2010-2011 AdaCore 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "hw/sysbus.h" 28 #include "cpu.h" 29 30 #include "hw/sparc/grlib.h" 31 32 #include "trace.h" 33 34 #define IRQMP_MAX_CPU 16 35 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */ 36 37 /* Memory mapped register offsets */ 38 #define LEVEL_OFFSET 0x00 39 #define PENDING_OFFSET 0x04 40 #define FORCE0_OFFSET 0x08 41 #define CLEAR_OFFSET 0x0C 42 #define MP_STATUS_OFFSET 0x10 43 #define BROADCAST_OFFSET 0x14 44 #define MASK_OFFSET 0x40 45 #define FORCE_OFFSET 0x80 46 #define EXTENDED_OFFSET 0xC0 47 48 #define TYPE_GRLIB_IRQMP "grlib,irqmp" 49 #define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP) 50 51 typedef struct IRQMPState IRQMPState; 52 53 typedef struct IRQMP { 54 SysBusDevice parent_obj; 55 56 MemoryRegion iomem; 57 58 void *set_pil_in; 59 void *set_pil_in_opaque; 60 61 IRQMPState *state; 62 } IRQMP; 63 64 struct IRQMPState { 65 uint32_t level; 66 uint32_t pending; 67 uint32_t clear; 68 uint32_t broadcast; 69 70 uint32_t mask[IRQMP_MAX_CPU]; 71 uint32_t force[IRQMP_MAX_CPU]; 72 uint32_t extended[IRQMP_MAX_CPU]; 73 74 IRQMP *parent; 75 }; 76 77 static void grlib_irqmp_check_irqs(IRQMPState *state) 78 { 79 uint32_t pend = 0; 80 uint32_t level0 = 0; 81 uint32_t level1 = 0; 82 set_pil_in_fn set_pil_in; 83 84 assert(state != NULL); 85 assert(state->parent != NULL); 86 87 /* IRQ for CPU 0 (no SMP support) */ 88 pend = (state->pending | state->force[0]) 89 & state->mask[0]; 90 91 level0 = pend & ~state->level; 92 level1 = pend & state->level; 93 94 trace_grlib_irqmp_check_irqs(state->pending, state->force[0], 95 state->mask[0], level1, level0); 96 97 set_pil_in = (set_pil_in_fn)state->parent->set_pil_in; 98 99 /* Trigger level1 interrupt first and level0 if there is no level1 */ 100 if (level1 != 0) { 101 set_pil_in(state->parent->set_pil_in_opaque, level1); 102 } else { 103 set_pil_in(state->parent->set_pil_in_opaque, level0); 104 } 105 } 106 107 void grlib_irqmp_ack(DeviceState *dev, int intno) 108 { 109 IRQMP *irqmp = GRLIB_IRQMP(dev); 110 IRQMPState *state; 111 uint32_t mask; 112 113 state = irqmp->state; 114 assert(state != NULL); 115 116 intno &= 15; 117 mask = 1 << intno; 118 119 trace_grlib_irqmp_ack(intno); 120 121 /* Clear registers */ 122 state->pending &= ~mask; 123 state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ 124 125 grlib_irqmp_check_irqs(state); 126 } 127 128 void grlib_irqmp_set_irq(void *opaque, int irq, int level) 129 { 130 IRQMP *irqmp = GRLIB_IRQMP(opaque); 131 IRQMPState *s; 132 int i = 0; 133 134 s = irqmp->state; 135 assert(s != NULL); 136 assert(s->parent != NULL); 137 138 139 if (level) { 140 trace_grlib_irqmp_set_irq(irq); 141 142 if (s->broadcast & 1 << irq) { 143 /* Broadcasted IRQ */ 144 for (i = 0; i < IRQMP_MAX_CPU; i++) { 145 s->force[i] |= 1 << irq; 146 } 147 } else { 148 s->pending |= 1 << irq; 149 } 150 grlib_irqmp_check_irqs(s); 151 152 } 153 } 154 155 static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, 156 unsigned size) 157 { 158 IRQMP *irqmp = opaque; 159 IRQMPState *state; 160 161 assert(irqmp != NULL); 162 state = irqmp->state; 163 assert(state != NULL); 164 165 addr &= 0xff; 166 167 /* global registers */ 168 switch (addr) { 169 case LEVEL_OFFSET: 170 return state->level; 171 172 case PENDING_OFFSET: 173 return state->pending; 174 175 case FORCE0_OFFSET: 176 /* This register is an "alias" for the force register of CPU 0 */ 177 return state->force[0]; 178 179 case CLEAR_OFFSET: 180 case MP_STATUS_OFFSET: 181 /* Always read as 0 */ 182 return 0; 183 184 case BROADCAST_OFFSET: 185 return state->broadcast; 186 187 default: 188 break; 189 } 190 191 /* mask registers */ 192 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 193 int cpu = (addr - MASK_OFFSET) / 4; 194 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 195 196 return state->mask[cpu]; 197 } 198 199 /* force registers */ 200 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 201 int cpu = (addr - FORCE_OFFSET) / 4; 202 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 203 204 return state->force[cpu]; 205 } 206 207 /* extended (not supported) */ 208 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 209 int cpu = (addr - EXTENDED_OFFSET) / 4; 210 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 211 212 return state->extended[cpu]; 213 } 214 215 trace_grlib_irqmp_readl_unknown(addr); 216 return 0; 217 } 218 219 static void grlib_irqmp_write(void *opaque, hwaddr addr, 220 uint64_t value, unsigned size) 221 { 222 IRQMP *irqmp = opaque; 223 IRQMPState *state; 224 225 assert(irqmp != NULL); 226 state = irqmp->state; 227 assert(state != NULL); 228 229 addr &= 0xff; 230 231 /* global registers */ 232 switch (addr) { 233 case LEVEL_OFFSET: 234 value &= 0xFFFF << 1; /* clean up the value */ 235 state->level = value; 236 return; 237 238 case PENDING_OFFSET: 239 /* Read Only */ 240 return; 241 242 case FORCE0_OFFSET: 243 /* This register is an "alias" for the force register of CPU 0 */ 244 245 value &= 0xFFFE; /* clean up the value */ 246 state->force[0] = value; 247 grlib_irqmp_check_irqs(irqmp->state); 248 return; 249 250 case CLEAR_OFFSET: 251 value &= ~1; /* clean up the value */ 252 state->pending &= ~value; 253 return; 254 255 case MP_STATUS_OFFSET: 256 /* Read Only (no SMP support) */ 257 return; 258 259 case BROADCAST_OFFSET: 260 value &= 0xFFFE; /* clean up the value */ 261 state->broadcast = value; 262 return; 263 264 default: 265 break; 266 } 267 268 /* mask registers */ 269 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 270 int cpu = (addr - MASK_OFFSET) / 4; 271 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 272 273 value &= ~1; /* clean up the value */ 274 state->mask[cpu] = value; 275 grlib_irqmp_check_irqs(irqmp->state); 276 return; 277 } 278 279 /* force registers */ 280 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 281 int cpu = (addr - FORCE_OFFSET) / 4; 282 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 283 284 uint32_t force = value & 0xFFFE; 285 uint32_t clear = (value >> 16) & 0xFFFE; 286 uint32_t old = state->force[cpu]; 287 288 state->force[cpu] = (old | force) & ~clear; 289 grlib_irqmp_check_irqs(irqmp->state); 290 return; 291 } 292 293 /* extended (not supported) */ 294 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 295 int cpu = (addr - EXTENDED_OFFSET) / 4; 296 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 297 298 value &= 0xF; /* clean up the value */ 299 state->extended[cpu] = value; 300 return; 301 } 302 303 trace_grlib_irqmp_writel_unknown(addr, value); 304 } 305 306 static const MemoryRegionOps grlib_irqmp_ops = { 307 .read = grlib_irqmp_read, 308 .write = grlib_irqmp_write, 309 .endianness = DEVICE_NATIVE_ENDIAN, 310 .valid = { 311 .min_access_size = 4, 312 .max_access_size = 4, 313 }, 314 }; 315 316 static void grlib_irqmp_reset(DeviceState *d) 317 { 318 IRQMP *irqmp = GRLIB_IRQMP(d); 319 assert(irqmp->state != NULL); 320 321 memset(irqmp->state, 0, sizeof *irqmp->state); 322 irqmp->state->parent = irqmp; 323 } 324 325 static int grlib_irqmp_init(SysBusDevice *dev) 326 { 327 IRQMP *irqmp = GRLIB_IRQMP(dev); 328 329 /* Check parameters */ 330 if (irqmp->set_pil_in == NULL) { 331 return -1; 332 } 333 334 memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp, 335 "irqmp", IRQMP_REG_SIZE); 336 337 irqmp->state = g_malloc0(sizeof *irqmp->state); 338 339 sysbus_init_mmio(dev, &irqmp->iomem); 340 341 return 0; 342 } 343 344 static Property grlib_irqmp_properties[] = { 345 DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in), 346 DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque), 347 DEFINE_PROP_END_OF_LIST(), 348 }; 349 350 static void grlib_irqmp_class_init(ObjectClass *klass, void *data) 351 { 352 DeviceClass *dc = DEVICE_CLASS(klass); 353 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 354 355 k->init = grlib_irqmp_init; 356 dc->reset = grlib_irqmp_reset; 357 dc->props = grlib_irqmp_properties; 358 /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */ 359 dc->cannot_instantiate_with_device_add_yet = true; 360 } 361 362 static const TypeInfo grlib_irqmp_info = { 363 .name = TYPE_GRLIB_IRQMP, 364 .parent = TYPE_SYS_BUS_DEVICE, 365 .instance_size = sizeof(IRQMP), 366 .class_init = grlib_irqmp_class_init, 367 }; 368 369 static void grlib_irqmp_register_types(void) 370 { 371 type_register_static(&grlib_irqmp_info); 372 } 373 374 type_init(grlib_irqmp_register_types) 375