1 /* 2 * QEMU 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/i386/pc.h" 28 #include "hw/irq.h" 29 #include "hw/isa/isa.h" 30 #include "qemu/timer.h" 31 #include "qemu/log.h" 32 #include "hw/isa/i8259_internal.h" 33 #include "trace.h" 34 35 /* debug PIC */ 36 //#define DEBUG_PIC 37 38 //#define DEBUG_IRQ_LATENCY 39 40 #define TYPE_I8259 "isa-i8259" 41 #define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259) 42 #define PIC_GET_CLASS(obj) OBJECT_GET_CLASS(PICClass, (obj), TYPE_I8259) 43 44 /** 45 * PICClass: 46 * @parent_realize: The parent's realizefn. 47 */ 48 typedef struct PICClass { 49 PICCommonClass parent_class; 50 51 DeviceRealize parent_realize; 52 } PICClass; 53 54 #ifdef DEBUG_IRQ_LATENCY 55 static int64_t irq_time[16]; 56 #endif 57 DeviceState *isa_pic; 58 static PICCommonState *slave_pic; 59 60 /* return the highest priority found in mask (highest = smallest 61 number). Return 8 if no irq */ 62 static int get_priority(PICCommonState *s, int mask) 63 { 64 int priority; 65 66 if (mask == 0) { 67 return 8; 68 } 69 priority = 0; 70 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { 71 priority++; 72 } 73 return priority; 74 } 75 76 /* return the pic wanted interrupt. return -1 if none */ 77 static int pic_get_irq(PICCommonState *s) 78 { 79 int mask, cur_priority, priority; 80 81 mask = s->irr & ~s->imr; 82 priority = get_priority(s, mask); 83 if (priority == 8) { 84 return -1; 85 } 86 /* compute current priority. If special fully nested mode on the 87 master, the IRQ coming from the slave is not taken into account 88 for the priority computation. */ 89 mask = s->isr; 90 if (s->special_mask) { 91 mask &= ~s->imr; 92 } 93 if (s->special_fully_nested_mode && s->master) { 94 mask &= ~(1 << 2); 95 } 96 cur_priority = get_priority(s, mask); 97 if (priority < cur_priority) { 98 /* higher priority found: an irq should be generated */ 99 return (priority + s->priority_add) & 7; 100 } else { 101 return -1; 102 } 103 } 104 105 /* Update INT output. Must be called every time the output may have changed. */ 106 static void pic_update_irq(PICCommonState *s) 107 { 108 int irq; 109 110 irq = pic_get_irq(s); 111 if (irq >= 0) { 112 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); 113 qemu_irq_raise(s->int_out[0]); 114 } else { 115 qemu_irq_lower(s->int_out[0]); 116 } 117 } 118 119 /* set irq level. If an edge is detected, then the IRR is set to 1 */ 120 static void pic_set_irq(void *opaque, int irq, int level) 121 { 122 PICCommonState *s = opaque; 123 int mask = 1 << irq; 124 int irq_index = s->master ? irq : irq + 8; 125 126 trace_pic_set_irq(s->master, irq, level); 127 pic_stat_update_irq(irq_index, level); 128 129 #ifdef DEBUG_IRQ_LATENCY 130 if (level) { 131 irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 132 } 133 #endif 134 135 if (s->elcr & mask) { 136 /* level triggered */ 137 if (level) { 138 s->irr |= mask; 139 s->last_irr |= mask; 140 } else { 141 s->irr &= ~mask; 142 s->last_irr &= ~mask; 143 } 144 } else { 145 /* edge triggered */ 146 if (level) { 147 if ((s->last_irr & mask) == 0) { 148 s->irr |= mask; 149 } 150 s->last_irr |= mask; 151 } else { 152 s->last_irr &= ~mask; 153 } 154 } 155 pic_update_irq(s); 156 } 157 158 /* acknowledge interrupt 'irq' */ 159 static void pic_intack(PICCommonState *s, int irq) 160 { 161 if (s->auto_eoi) { 162 if (s->rotate_on_auto_eoi) { 163 s->priority_add = (irq + 1) & 7; 164 } 165 } else { 166 s->isr |= (1 << irq); 167 } 168 /* We don't clear a level sensitive interrupt here */ 169 if (!(s->elcr & (1 << irq))) { 170 s->irr &= ~(1 << irq); 171 } 172 pic_update_irq(s); 173 } 174 175 int pic_read_irq(DeviceState *d) 176 { 177 PICCommonState *s = PIC_COMMON(d); 178 int irq, irq2, intno; 179 180 irq = pic_get_irq(s); 181 if (irq >= 0) { 182 if (irq == 2) { 183 irq2 = pic_get_irq(slave_pic); 184 if (irq2 >= 0) { 185 pic_intack(slave_pic, irq2); 186 } else { 187 /* spurious IRQ on slave controller */ 188 irq2 = 7; 189 } 190 intno = slave_pic->irq_base + irq2; 191 } else { 192 intno = s->irq_base + irq; 193 } 194 pic_intack(s, irq); 195 } else { 196 /* spurious IRQ on host controller */ 197 irq = 7; 198 intno = s->irq_base + irq; 199 } 200 201 if (irq == 2) { 202 irq = irq2 + 8; 203 } 204 205 #ifdef DEBUG_IRQ_LATENCY 206 printf("IRQ%d latency=%0.3fus\n", 207 irq, 208 (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 209 irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); 210 #endif 211 212 trace_pic_interrupt(irq, intno); 213 return intno; 214 } 215 216 static void pic_init_reset(PICCommonState *s) 217 { 218 pic_reset_common(s); 219 pic_update_irq(s); 220 } 221 222 static void pic_reset(DeviceState *dev) 223 { 224 PICCommonState *s = PIC_COMMON(dev); 225 226 s->elcr = 0; 227 pic_init_reset(s); 228 } 229 230 static void pic_ioport_write(void *opaque, hwaddr addr64, 231 uint64_t val64, unsigned size) 232 { 233 PICCommonState *s = opaque; 234 uint32_t addr = addr64; 235 uint32_t val = val64; 236 int priority, cmd, irq; 237 238 trace_pic_ioport_write(s->master, addr, val); 239 240 if (addr == 0) { 241 if (val & 0x10) { 242 pic_init_reset(s); 243 s->init_state = 1; 244 s->init4 = val & 1; 245 s->single_mode = val & 2; 246 if (val & 0x08) { 247 qemu_log_mask(LOG_UNIMP, 248 "i8259: level sensitive irq not supported\n"); 249 } 250 } else if (val & 0x08) { 251 if (val & 0x04) { 252 s->poll = 1; 253 } 254 if (val & 0x02) { 255 s->read_reg_select = val & 1; 256 } 257 if (val & 0x40) { 258 s->special_mask = (val >> 5) & 1; 259 } 260 } else { 261 cmd = val >> 5; 262 switch (cmd) { 263 case 0: 264 case 4: 265 s->rotate_on_auto_eoi = cmd >> 2; 266 break; 267 case 1: /* end of interrupt */ 268 case 5: 269 priority = get_priority(s, s->isr); 270 if (priority != 8) { 271 irq = (priority + s->priority_add) & 7; 272 s->isr &= ~(1 << irq); 273 if (cmd == 5) { 274 s->priority_add = (irq + 1) & 7; 275 } 276 pic_update_irq(s); 277 } 278 break; 279 case 3: 280 irq = val & 7; 281 s->isr &= ~(1 << irq); 282 pic_update_irq(s); 283 break; 284 case 6: 285 s->priority_add = (val + 1) & 7; 286 pic_update_irq(s); 287 break; 288 case 7: 289 irq = val & 7; 290 s->isr &= ~(1 << irq); 291 s->priority_add = (irq + 1) & 7; 292 pic_update_irq(s); 293 break; 294 default: 295 /* no operation */ 296 break; 297 } 298 } 299 } else { 300 switch (s->init_state) { 301 case 0: 302 /* normal mode */ 303 s->imr = val; 304 pic_update_irq(s); 305 break; 306 case 1: 307 s->irq_base = val & 0xf8; 308 s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; 309 break; 310 case 2: 311 if (s->init4) { 312 s->init_state = 3; 313 } else { 314 s->init_state = 0; 315 } 316 break; 317 case 3: 318 s->special_fully_nested_mode = (val >> 4) & 1; 319 s->auto_eoi = (val >> 1) & 1; 320 s->init_state = 0; 321 break; 322 } 323 } 324 } 325 326 static uint64_t pic_ioport_read(void *opaque, hwaddr addr, 327 unsigned size) 328 { 329 PICCommonState *s = opaque; 330 int ret; 331 332 if (s->poll) { 333 ret = pic_get_irq(s); 334 if (ret >= 0) { 335 pic_intack(s, ret); 336 ret |= 0x80; 337 } else { 338 ret = 0; 339 } 340 s->poll = 0; 341 } else { 342 if (addr == 0) { 343 if (s->read_reg_select) { 344 ret = s->isr; 345 } else { 346 ret = s->irr; 347 } 348 } else { 349 ret = s->imr; 350 } 351 } 352 trace_pic_ioport_read(s->master, addr, ret); 353 return ret; 354 } 355 356 int pic_get_output(DeviceState *d) 357 { 358 PICCommonState *s = PIC_COMMON(d); 359 360 return (pic_get_irq(s) >= 0); 361 } 362 363 static void elcr_ioport_write(void *opaque, hwaddr addr, 364 uint64_t val, unsigned size) 365 { 366 PICCommonState *s = opaque; 367 s->elcr = val & s->elcr_mask; 368 } 369 370 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, 371 unsigned size) 372 { 373 PICCommonState *s = opaque; 374 return s->elcr; 375 } 376 377 static const MemoryRegionOps pic_base_ioport_ops = { 378 .read = pic_ioport_read, 379 .write = pic_ioport_write, 380 .impl = { 381 .min_access_size = 1, 382 .max_access_size = 1, 383 }, 384 }; 385 386 static const MemoryRegionOps pic_elcr_ioport_ops = { 387 .read = elcr_ioport_read, 388 .write = elcr_ioport_write, 389 .impl = { 390 .min_access_size = 1, 391 .max_access_size = 1, 392 }, 393 }; 394 395 static void pic_realize(DeviceState *dev, Error **errp) 396 { 397 PICCommonState *s = PIC_COMMON(dev); 398 PICClass *pc = PIC_GET_CLASS(dev); 399 400 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, 401 "pic", 2); 402 memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s, 403 "elcr", 1); 404 405 qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out)); 406 qdev_init_gpio_in(dev, pic_set_irq, 8); 407 408 pc->parent_realize(dev, errp); 409 } 410 411 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq) 412 { 413 qemu_irq *irq_set; 414 DeviceState *dev; 415 ISADevice *isadev; 416 int i; 417 418 irq_set = g_new0(qemu_irq, ISA_NUM_IRQS); 419 420 isadev = i8259_init_chip(TYPE_I8259, bus, true); 421 dev = DEVICE(isadev); 422 423 qdev_connect_gpio_out(dev, 0, parent_irq); 424 for (i = 0 ; i < 8; i++) { 425 irq_set[i] = qdev_get_gpio_in(dev, i); 426 } 427 428 isa_pic = dev; 429 430 isadev = i8259_init_chip(TYPE_I8259, bus, false); 431 dev = DEVICE(isadev); 432 433 qdev_connect_gpio_out(dev, 0, irq_set[2]); 434 for (i = 0 ; i < 8; i++) { 435 irq_set[i + 8] = qdev_get_gpio_in(dev, i); 436 } 437 438 slave_pic = PIC_COMMON(dev); 439 440 return irq_set; 441 } 442 443 static void i8259_class_init(ObjectClass *klass, void *data) 444 { 445 PICClass *k = PIC_CLASS(klass); 446 DeviceClass *dc = DEVICE_CLASS(klass); 447 448 device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); 449 dc->reset = pic_reset; 450 } 451 452 static const TypeInfo i8259_info = { 453 .name = TYPE_I8259, 454 .instance_size = sizeof(PICCommonState), 455 .parent = TYPE_PIC_COMMON, 456 .class_init = i8259_class_init, 457 .class_size = sizeof(PICClass), 458 }; 459 460 static void pic_register_types(void) 461 { 462 type_register_static(&i8259_info); 463 } 464 465 type_init(pic_register_types) 466