1 /* 2 * i.MX31 Vectored Interrupt Controller 3 * 4 * Note this is NOT the PL192 provided by ARM, but 5 * a custom implementation by Freescale. 6 * 7 * Copyright (c) 2008 OKL 8 * Copyright (c) 2011 NICTA Pty Ltd 9 * Originally written by Hans Jiang 10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 11 * 12 * This code is licensed under the GPL version 2 or later. See 13 * the COPYING file in the top-level directory. 14 * 15 * TODO: implement vectors. 16 */ 17 18 #include "hw/intc/imx_avic.h" 19 20 #define DEBUG_INT 1 21 #undef DEBUG_INT /* comment out for debugging */ 22 23 #ifdef DEBUG_INT 24 #define DPRINTF(fmt, args...) \ 25 do { printf("%s: " fmt , TYPE_IMX_AVIC, ##args); } while (0) 26 #else 27 #define DPRINTF(fmt, args...) do {} while (0) 28 #endif 29 30 /* 31 * Define to 1 for messages about attempts to 32 * access unimplemented registers or similar. 33 */ 34 #define DEBUG_IMPLEMENTATION 1 35 #if DEBUG_IMPLEMENTATION 36 # define IPRINTF(fmt, args...) \ 37 do { fprintf(stderr, "%s: " fmt, TYPE_IMX_AVIC, ##args); } while (0) 38 #else 39 # define IPRINTF(fmt, args...) do {} while (0) 40 #endif 41 42 static const VMStateDescription vmstate_imx_avic = { 43 .name = TYPE_IMX_AVIC, 44 .version_id = 1, 45 .minimum_version_id = 1, 46 .fields = (VMStateField[]) { 47 VMSTATE_UINT64(pending, IMXAVICState), 48 VMSTATE_UINT64(enabled, IMXAVICState), 49 VMSTATE_UINT64(is_fiq, IMXAVICState), 50 VMSTATE_UINT32(intcntl, IMXAVICState), 51 VMSTATE_UINT32(intmask, IMXAVICState), 52 VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS), 53 VMSTATE_END_OF_LIST() 54 }, 55 }; 56 57 static inline int imx_avic_prio(IMXAVICState *s, int irq) 58 { 59 uint32_t word = irq / PRIO_PER_WORD; 60 uint32_t part = 4 * (irq % PRIO_PER_WORD); 61 return 0xf & (s->prio[word] >> part); 62 } 63 64 /* Update interrupts. */ 65 static void imx_avic_update(IMXAVICState *s) 66 { 67 int i; 68 uint64_t new = s->pending & s->enabled; 69 uint64_t flags; 70 71 flags = new & s->is_fiq; 72 qemu_set_irq(s->fiq, !!flags); 73 74 flags = new & ~s->is_fiq; 75 if (!flags || (s->intmask == 0x1f)) { 76 qemu_set_irq(s->irq, !!flags); 77 return; 78 } 79 80 /* 81 * Take interrupt if there's a pending interrupt with 82 * priority higher than the value of intmask 83 */ 84 for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) { 85 if (flags & (1UL << i)) { 86 if (imx_avic_prio(s, i) > s->intmask) { 87 qemu_set_irq(s->irq, 1); 88 return; 89 } 90 } 91 } 92 qemu_set_irq(s->irq, 0); 93 } 94 95 static void imx_avic_set_irq(void *opaque, int irq, int level) 96 { 97 IMXAVICState *s = (IMXAVICState *)opaque; 98 99 if (level) { 100 DPRINTF("Raising IRQ %d, prio %d\n", 101 irq, imx_avic_prio(s, irq)); 102 s->pending |= (1ULL << irq); 103 } else { 104 DPRINTF("Clearing IRQ %d, prio %d\n", 105 irq, imx_avic_prio(s, irq)); 106 s->pending &= ~(1ULL << irq); 107 } 108 109 imx_avic_update(s); 110 } 111 112 113 static uint64_t imx_avic_read(void *opaque, 114 hwaddr offset, unsigned size) 115 { 116 IMXAVICState *s = (IMXAVICState *)opaque; 117 118 119 DPRINTF("read(offset = 0x%x)\n", offset >> 2); 120 switch (offset >> 2) { 121 case 0: /* INTCNTL */ 122 return s->intcntl; 123 124 case 1: /* Normal Interrupt Mask Register, NIMASK */ 125 return s->intmask; 126 127 case 2: /* Interrupt Enable Number Register, INTENNUM */ 128 case 3: /* Interrupt Disable Number Register, INTDISNUM */ 129 return 0; 130 131 case 4: /* Interrupt Enabled Number Register High */ 132 return s->enabled >> 32; 133 134 case 5: /* Interrupt Enabled Number Register Low */ 135 return s->enabled & 0xffffffffULL; 136 137 case 6: /* Interrupt Type Register High */ 138 return s->is_fiq >> 32; 139 140 case 7: /* Interrupt Type Register Low */ 141 return s->is_fiq & 0xffffffffULL; 142 143 case 8: /* Normal Interrupt Priority Register 7 */ 144 case 9: /* Normal Interrupt Priority Register 6 */ 145 case 10:/* Normal Interrupt Priority Register 5 */ 146 case 11:/* Normal Interrupt Priority Register 4 */ 147 case 12:/* Normal Interrupt Priority Register 3 */ 148 case 13:/* Normal Interrupt Priority Register 2 */ 149 case 14:/* Normal Interrupt Priority Register 1 */ 150 case 15:/* Normal Interrupt Priority Register 0 */ 151 return s->prio[15-(offset>>2)]; 152 153 case 16: /* Normal interrupt vector and status register */ 154 { 155 /* 156 * This returns the highest priority 157 * outstanding interrupt. Where there is more than 158 * one pending IRQ with the same priority, 159 * take the highest numbered one. 160 */ 161 uint64_t flags = s->pending & s->enabled & ~s->is_fiq; 162 int i; 163 int prio = -1; 164 int irq = -1; 165 for (i = 63; i >= 0; --i) { 166 if (flags & (1ULL<<i)) { 167 int irq_prio = imx_avic_prio(s, i); 168 if (irq_prio > prio) { 169 irq = i; 170 prio = irq_prio; 171 } 172 } 173 } 174 if (irq >= 0) { 175 imx_avic_set_irq(s, irq, 0); 176 return irq << 16 | prio; 177 } 178 return 0xffffffffULL; 179 } 180 case 17:/* Fast Interrupt vector and status register */ 181 { 182 uint64_t flags = s->pending & s->enabled & s->is_fiq; 183 int i = ctz64(flags); 184 if (i < 64) { 185 imx_avic_set_irq(opaque, i, 0); 186 return i; 187 } 188 return 0xffffffffULL; 189 } 190 case 18:/* Interrupt source register high */ 191 return s->pending >> 32; 192 193 case 19:/* Interrupt source register low */ 194 return s->pending & 0xffffffffULL; 195 196 case 20:/* Interrupt Force Register high */ 197 case 21:/* Interrupt Force Register low */ 198 return 0; 199 200 case 22:/* Normal Interrupt Pending Register High */ 201 return (s->pending & s->enabled & ~s->is_fiq) >> 32; 202 203 case 23:/* Normal Interrupt Pending Register Low */ 204 return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL; 205 206 case 24: /* Fast Interrupt Pending Register High */ 207 return (s->pending & s->enabled & s->is_fiq) >> 32; 208 209 case 25: /* Fast Interrupt Pending Register Low */ 210 return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL; 211 212 case 0x40: /* AVIC vector 0, use for WFI WAR */ 213 return 0x4; 214 215 default: 216 IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset); 217 return 0; 218 } 219 } 220 221 static void imx_avic_write(void *opaque, hwaddr offset, 222 uint64_t val, unsigned size) 223 { 224 IMXAVICState *s = (IMXAVICState *)opaque; 225 226 /* Vector Registers not yet supported */ 227 if (offset >= 0x100 && offset <= 0x2fc) { 228 IPRINTF("%s to vector register %d ignored\n", __func__, 229 (unsigned int)((offset - 0x100) >> 2)); 230 return; 231 } 232 233 DPRINTF("%s(0x%x) = %x\n", __func__, 234 (unsigned int)offset>>2, (unsigned int)val); 235 switch (offset >> 2) { 236 case 0: /* Interrupt Control Register, INTCNTL */ 237 s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM); 238 if (s->intcntl & ABFEN) { 239 s->intcntl &= ~(val & ABFLAG); 240 } 241 break; 242 243 case 1: /* Normal Interrupt Mask Register, NIMASK */ 244 s->intmask = val & 0x1f; 245 break; 246 247 case 2: /* Interrupt Enable Number Register, INTENNUM */ 248 DPRINTF("enable(%d)\n", (int)val); 249 val &= 0x3f; 250 s->enabled |= (1ULL << val); 251 break; 252 253 case 3: /* Interrupt Disable Number Register, INTDISNUM */ 254 DPRINTF("disable(%d)\n", (int)val); 255 val &= 0x3f; 256 s->enabled &= ~(1ULL << val); 257 break; 258 259 case 4: /* Interrupt Enable Number Register High */ 260 s->enabled = (s->enabled & 0xffffffffULL) | (val << 32); 261 break; 262 263 case 5: /* Interrupt Enable Number Register Low */ 264 s->enabled = (s->enabled & 0xffffffff00000000ULL) | val; 265 break; 266 267 case 6: /* Interrupt Type Register High */ 268 s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32); 269 break; 270 271 case 7: /* Interrupt Type Register Low */ 272 s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val; 273 break; 274 275 case 8: /* Normal Interrupt Priority Register 7 */ 276 case 9: /* Normal Interrupt Priority Register 6 */ 277 case 10:/* Normal Interrupt Priority Register 5 */ 278 case 11:/* Normal Interrupt Priority Register 4 */ 279 case 12:/* Normal Interrupt Priority Register 3 */ 280 case 13:/* Normal Interrupt Priority Register 2 */ 281 case 14:/* Normal Interrupt Priority Register 1 */ 282 case 15:/* Normal Interrupt Priority Register 0 */ 283 s->prio[15-(offset>>2)] = val; 284 break; 285 286 /* Read-only registers, writes ignored */ 287 case 16:/* Normal Interrupt Vector and Status register */ 288 case 17:/* Fast Interrupt vector and status register */ 289 case 18:/* Interrupt source register high */ 290 case 19:/* Interrupt source register low */ 291 return; 292 293 case 20:/* Interrupt Force Register high */ 294 s->pending = (s->pending & 0xffffffffULL) | (val << 32); 295 break; 296 297 case 21:/* Interrupt Force Register low */ 298 s->pending = (s->pending & 0xffffffff00000000ULL) | val; 299 break; 300 301 case 22:/* Normal Interrupt Pending Register High */ 302 case 23:/* Normal Interrupt Pending Register Low */ 303 case 24: /* Fast Interrupt Pending Register High */ 304 case 25: /* Fast Interrupt Pending Register Low */ 305 return; 306 307 default: 308 IPRINTF("%s: Bad offset %x\n", __func__, (int)offset); 309 } 310 imx_avic_update(s); 311 } 312 313 static const MemoryRegionOps imx_avic_ops = { 314 .read = imx_avic_read, 315 .write = imx_avic_write, 316 .endianness = DEVICE_NATIVE_ENDIAN, 317 }; 318 319 static void imx_avic_reset(DeviceState *dev) 320 { 321 IMXAVICState *s = IMX_AVIC(dev); 322 323 s->pending = 0; 324 s->enabled = 0; 325 s->is_fiq = 0; 326 s->intmask = 0x1f; 327 s->intcntl = 0; 328 memset(s->prio, 0, sizeof s->prio); 329 } 330 331 static int imx_avic_init(SysBusDevice *sbd) 332 { 333 DeviceState *dev = DEVICE(sbd); 334 IMXAVICState *s = IMX_AVIC(dev); 335 336 memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s, 337 TYPE_IMX_AVIC, 0x1000); 338 sysbus_init_mmio(sbd, &s->iomem); 339 340 qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS); 341 sysbus_init_irq(sbd, &s->irq); 342 sysbus_init_irq(sbd, &s->fiq); 343 344 return 0; 345 } 346 347 348 static void imx_avic_class_init(ObjectClass *klass, void *data) 349 { 350 DeviceClass *dc = DEVICE_CLASS(klass); 351 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 352 k->init = imx_avic_init; 353 dc->vmsd = &vmstate_imx_avic; 354 dc->reset = imx_avic_reset; 355 dc->desc = "i.MX Advanced Vector Interrupt Controller"; 356 } 357 358 static const TypeInfo imx_avic_info = { 359 .name = TYPE_IMX_AVIC, 360 .parent = TYPE_SYS_BUS_DEVICE, 361 .instance_size = sizeof(IMXAVICState), 362 .class_init = imx_avic_class_init, 363 }; 364 365 static void imx_avic_register_types(void) 366 { 367 type_register_static(&imx_avic_info); 368 } 369 370 type_init(imx_avic_register_types) 371