1 /* 2 * ioapic.c IOAPIC emulation logic 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * Split the ioapic logic from apic.c 7 * Xiantao Zhang <xiantao.zhang@intel.com> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "monitor/monitor.h" 26 #include "hw/hw.h" 27 #include "hw/i386/pc.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/ioapic.h" 30 #include "hw/i386/ioapic_internal.h" 31 #include "include/hw/pci/msi.h" 32 #include "sysemu/kvm.h" 33 #include "target/i386/cpu.h" 34 #include "hw/i386/apic-msidef.h" 35 #include "hw/i386/x86-iommu.h" 36 37 //#define DEBUG_IOAPIC 38 39 #ifdef DEBUG_IOAPIC 40 #define DPRINTF(fmt, ...) \ 41 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(fmt, ...) 44 #endif 45 46 #define APIC_DELIVERY_MODE_SHIFT 8 47 #define APIC_POLARITY_SHIFT 14 48 #define APIC_TRIG_MODE_SHIFT 15 49 50 static IOAPICCommonState *ioapics[MAX_IOAPICS]; 51 52 /* global variable from ioapic_common.c */ 53 extern int ioapic_no; 54 55 struct ioapic_entry_info { 56 /* fields parsed from IOAPIC entries */ 57 uint8_t masked; 58 uint8_t trig_mode; 59 uint16_t dest_idx; 60 uint8_t dest_mode; 61 uint8_t delivery_mode; 62 uint8_t vector; 63 64 /* MSI message generated from above parsed fields */ 65 uint32_t addr; 66 uint32_t data; 67 }; 68 69 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) 70 { 71 memset(info, 0, sizeof(*info)); 72 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; 73 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; 74 /* 75 * By default, this would be dest_id[8] + reserved[8]. When IR 76 * is enabled, this would be interrupt_index[15] + 77 * interrupt_format[1]. This field never means anything, but 78 * only used to generate corresponding MSI. 79 */ 80 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; 81 info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 82 info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ 83 & IOAPIC_DM_MASK; 84 if (info->delivery_mode == IOAPIC_DM_EXTINT) { 85 info->vector = pic_read_irq(isa_pic); 86 } else { 87 info->vector = entry & IOAPIC_VECTOR_MASK; 88 } 89 90 info->addr = APIC_DEFAULT_ADDRESS | \ 91 (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ 92 (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); 93 info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ 94 (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ 95 (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); 96 } 97 98 static void ioapic_service(IOAPICCommonState *s) 99 { 100 AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as; 101 struct ioapic_entry_info info; 102 uint8_t i; 103 uint32_t mask; 104 uint64_t entry; 105 106 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 107 mask = 1 << i; 108 if (s->irr & mask) { 109 int coalesce = 0; 110 111 entry = s->ioredtbl[i]; 112 ioapic_entry_parse(entry, &info); 113 if (!info.masked) { 114 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 115 s->irr &= ~mask; 116 } else { 117 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; 118 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; 119 } 120 121 if (coalesce) { 122 /* We are level triggered interrupts, and the 123 * guest should be still working on previous one, 124 * so skip it. */ 125 continue; 126 } 127 128 #ifdef CONFIG_KVM 129 if (kvm_irqchip_is_split()) { 130 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 131 kvm_set_irq(kvm_state, i, 1); 132 kvm_set_irq(kvm_state, i, 0); 133 } else { 134 kvm_set_irq(kvm_state, i, 1); 135 } 136 continue; 137 } 138 #endif 139 140 /* No matter whether IR is enabled, we translate 141 * the IOAPIC message into a MSI one, and its 142 * address space will decide whether we need a 143 * translation. */ 144 stl_le_phys(ioapic_as, info.addr, info.data); 145 } 146 } 147 } 148 } 149 150 static void ioapic_set_irq(void *opaque, int vector, int level) 151 { 152 IOAPICCommonState *s = opaque; 153 154 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps 155 * to GSI 2. GSI maps to ioapic 1-1. This is not 156 * the cleanest way of doing it but it should work. */ 157 158 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector); 159 if (vector == 0) { 160 vector = 2; 161 } 162 if (vector >= 0 && vector < IOAPIC_NUM_PINS) { 163 uint32_t mask = 1 << vector; 164 uint64_t entry = s->ioredtbl[vector]; 165 166 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == 167 IOAPIC_TRIGGER_LEVEL) { 168 /* level triggered */ 169 if (level) { 170 s->irr |= mask; 171 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 172 ioapic_service(s); 173 } 174 } else { 175 s->irr &= ~mask; 176 } 177 } else { 178 /* According to the 82093AA manual, we must ignore edge requests 179 * if the input pin is masked. */ 180 if (level && !(entry & IOAPIC_LVT_MASKED)) { 181 s->irr |= mask; 182 ioapic_service(s); 183 } 184 } 185 } 186 } 187 188 static void ioapic_update_kvm_routes(IOAPICCommonState *s) 189 { 190 #ifdef CONFIG_KVM 191 int i; 192 193 if (kvm_irqchip_is_split()) { 194 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 195 MSIMessage msg; 196 struct ioapic_entry_info info; 197 ioapic_entry_parse(s->ioredtbl[i], &info); 198 msg.address = info.addr; 199 msg.data = info.data; 200 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); 201 } 202 kvm_irqchip_commit_routes(kvm_state); 203 } 204 #endif 205 } 206 207 #ifdef CONFIG_KVM 208 static void ioapic_iec_notifier(void *private, bool global, 209 uint32_t index, uint32_t mask) 210 { 211 IOAPICCommonState *s = (IOAPICCommonState *)private; 212 /* For simplicity, we just update all the routes */ 213 ioapic_update_kvm_routes(s); 214 } 215 #endif 216 217 void ioapic_eoi_broadcast(int vector) 218 { 219 IOAPICCommonState *s; 220 uint64_t entry; 221 int i, n; 222 223 for (i = 0; i < MAX_IOAPICS; i++) { 224 s = ioapics[i]; 225 if (!s) { 226 continue; 227 } 228 for (n = 0; n < IOAPIC_NUM_PINS; n++) { 229 entry = s->ioredtbl[n]; 230 if ((entry & IOAPIC_LVT_REMOTE_IRR) 231 && (entry & IOAPIC_VECTOR_MASK) == vector) { 232 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; 233 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { 234 ioapic_service(s); 235 } 236 } 237 } 238 } 239 } 240 241 void ioapic_dump_state(Monitor *mon, const QDict *qdict) 242 { 243 int i; 244 245 for (i = 0; i < MAX_IOAPICS; i++) { 246 if (ioapics[i] != 0) { 247 ioapic_print_redtbl(mon, ioapics[i]); 248 } 249 } 250 } 251 252 static uint64_t 253 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 254 { 255 IOAPICCommonState *s = opaque; 256 int index; 257 uint32_t val = 0; 258 259 switch (addr & 0xff) { 260 case IOAPIC_IOREGSEL: 261 val = s->ioregsel; 262 break; 263 case IOAPIC_IOWIN: 264 if (size != 4) { 265 break; 266 } 267 switch (s->ioregsel) { 268 case IOAPIC_REG_ID: 269 case IOAPIC_REG_ARB: 270 val = s->id << IOAPIC_ID_SHIFT; 271 break; 272 case IOAPIC_REG_VER: 273 val = s->version | 274 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); 275 break; 276 default: 277 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 278 if (index >= 0 && index < IOAPIC_NUM_PINS) { 279 if (s->ioregsel & 1) { 280 val = s->ioredtbl[index] >> 32; 281 } else { 282 val = s->ioredtbl[index] & 0xffffffff; 283 } 284 } 285 } 286 DPRINTF("read: %08x = %08x\n", s->ioregsel, val); 287 break; 288 } 289 return val; 290 } 291 292 /* 293 * This is to satisfy the hack in Linux kernel. One hack of it is to 294 * simulate clearing the Remote IRR bit of IOAPIC entry using the 295 * following: 296 * 297 * "For IO-APIC's with EOI register, we use that to do an explicit EOI. 298 * Otherwise, we simulate the EOI message manually by changing the trigger 299 * mode to edge and then back to level, with RTE being masked during 300 * this." 301 * 302 * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) 303 * 304 * This is based on the assumption that, Remote IRR bit will be 305 * cleared by IOAPIC hardware when configured as edge-triggered 306 * interrupts. 307 * 308 * Without this, level-triggered interrupts in IR mode might fail to 309 * work correctly. 310 */ 311 static inline void 312 ioapic_fix_edge_remote_irr(uint64_t *entry) 313 { 314 if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { 315 /* Edge-triggered interrupts, make sure remote IRR is zero */ 316 *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); 317 } 318 } 319 320 static void 321 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 322 unsigned int size) 323 { 324 IOAPICCommonState *s = opaque; 325 int index; 326 327 switch (addr & 0xff) { 328 case IOAPIC_IOREGSEL: 329 s->ioregsel = val; 330 break; 331 case IOAPIC_IOWIN: 332 if (size != 4) { 333 break; 334 } 335 DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val); 336 switch (s->ioregsel) { 337 case IOAPIC_REG_ID: 338 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; 339 break; 340 case IOAPIC_REG_VER: 341 case IOAPIC_REG_ARB: 342 break; 343 default: 344 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 345 if (index >= 0 && index < IOAPIC_NUM_PINS) { 346 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; 347 if (s->ioregsel & 1) { 348 s->ioredtbl[index] &= 0xffffffff; 349 s->ioredtbl[index] |= (uint64_t)val << 32; 350 } else { 351 s->ioredtbl[index] &= ~0xffffffffULL; 352 s->ioredtbl[index] |= val; 353 } 354 /* restore RO bits */ 355 s->ioredtbl[index] &= IOAPIC_RW_BITS; 356 s->ioredtbl[index] |= ro_bits; 357 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); 358 ioapic_service(s); 359 } 360 } 361 break; 362 case IOAPIC_EOI: 363 /* Explicit EOI is only supported for IOAPIC version 0x20 */ 364 if (size != 4 || s->version != 0x20) { 365 break; 366 } 367 ioapic_eoi_broadcast(val); 368 break; 369 } 370 371 ioapic_update_kvm_routes(s); 372 } 373 374 static const MemoryRegionOps ioapic_io_ops = { 375 .read = ioapic_mem_read, 376 .write = ioapic_mem_write, 377 .endianness = DEVICE_NATIVE_ENDIAN, 378 }; 379 380 static void ioapic_machine_done_notify(Notifier *notifier, void *data) 381 { 382 #ifdef CONFIG_KVM 383 IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, 384 machine_done); 385 386 if (kvm_irqchip_is_split()) { 387 X86IOMMUState *iommu = x86_iommu_get_default(); 388 if (iommu) { 389 /* Register this IOAPIC with IOMMU IEC notifier, so that 390 * when there are IR invalidates, we can be notified to 391 * update kernel IR cache. */ 392 x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); 393 } 394 } 395 #endif 396 } 397 398 static void ioapic_realize(DeviceState *dev, Error **errp) 399 { 400 IOAPICCommonState *s = IOAPIC_COMMON(dev); 401 402 if (s->version != 0x11 && s->version != 0x20) { 403 error_report("IOAPIC only supports version 0x11 or 0x20 " 404 "(default: 0x11)."); 405 exit(1); 406 } 407 408 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, 409 "ioapic", 0x1000); 410 411 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); 412 413 ioapics[ioapic_no] = s; 414 s->machine_done.notify = ioapic_machine_done_notify; 415 qemu_add_machine_init_done_notifier(&s->machine_done); 416 } 417 418 static Property ioapic_properties[] = { 419 DEFINE_PROP_UINT8("version", IOAPICCommonState, version, 0x20), 420 DEFINE_PROP_END_OF_LIST(), 421 }; 422 423 static void ioapic_class_init(ObjectClass *klass, void *data) 424 { 425 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); 426 DeviceClass *dc = DEVICE_CLASS(klass); 427 428 k->realize = ioapic_realize; 429 dc->reset = ioapic_reset_common; 430 dc->props = ioapic_properties; 431 } 432 433 static const TypeInfo ioapic_info = { 434 .name = "ioapic", 435 .parent = TYPE_IOAPIC_COMMON, 436 .instance_size = sizeof(IOAPICCommonState), 437 .class_init = ioapic_class_init, 438 }; 439 440 static void ioapic_register_types(void) 441 { 442 type_register_static(&ioapic_info); 443 } 444 445 type_init(ioapic_register_types) 446