1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_chip.h" 20 #include "hw/ppc/pnv_core.h" 21 #include "hw/ppc/pnv_xscom.h" 22 #include "hw/ppc/xive2.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/ppc/xive2_regs.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/reset.h" 29 30 #include <libfdt.h> 31 32 #include "pnv_xive2_regs.h" 33 34 #undef XIVE2_DEBUG 35 36 /* 37 * Virtual structures table (VST) 38 */ 39 #define SBE_PER_BYTE 4 40 41 typedef struct XiveVstInfo { 42 const char *name; 43 uint32_t size; 44 uint32_t max_blocks; 45 } XiveVstInfo; 46 47 static const XiveVstInfo vst_infos[] = { 48 49 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 50 [VST_ESB] = { "ESB", 1, 16 }, 51 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 52 53 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 54 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 55 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 56 57 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 58 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 59 60 /* 61 * This table contains the backing store pages for the interrupt 62 * fifos of the VC sub-engine in case of overflow. 63 * 64 * 0 - IPI, 65 * 1 - HWD, 66 * 2 - NxC, 67 * 3 - INT, 68 * 4 - OS-Queue, 69 * 5 - Pool-Queue, 70 * 6 - Hard-Queue 71 */ 72 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 73 }; 74 75 #define xive2_error(xive, fmt, ...) \ 76 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 77 (xive)->chip->chip_id, ## __VA_ARGS__); 78 79 /* 80 * TODO: Document block id override 81 */ 82 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 83 { 84 uint8_t blk = xive->chip->chip_id; 85 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 86 87 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 88 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 89 } 90 91 return blk; 92 } 93 94 /* 95 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 96 * of the chips is good enough. 97 * 98 * TODO: Block scope support 99 */ 100 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 101 { 102 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 103 int i; 104 105 for (i = 0; i < pnv->num_chips; i++) { 106 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 107 PnvXive2 *xive = &chip10->xive; 108 109 if (pnv_xive2_block_id(xive) == blk) { 110 return xive; 111 } 112 } 113 return NULL; 114 } 115 116 /* 117 * VST accessors for ESB, EAT, ENDT, NVP 118 * 119 * Indirect VST tables are arrays of VSDs pointing to a page (of same 120 * size). Each page is a direct VST table. 121 */ 122 123 #define XIVE_VSD_SIZE 8 124 125 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 126 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 127 { 128 return page_shift == 12 || page_shift == 16 || 129 page_shift == 21 || page_shift == 24; 130 } 131 132 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 133 uint64_t vsd, uint32_t idx) 134 { 135 const XiveVstInfo *info = &vst_infos[type]; 136 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 137 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 138 uint32_t idx_max; 139 140 idx_max = vst_tsize / info->size - 1; 141 if (idx > idx_max) { 142 #ifdef XIVE2_DEBUG 143 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 144 info->name, idx, idx_max); 145 #endif 146 return 0; 147 } 148 149 return vst_addr + idx * info->size; 150 } 151 152 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 153 uint64_t vsd, uint32_t idx) 154 { 155 const XiveVstInfo *info = &vst_infos[type]; 156 uint64_t vsd_addr; 157 uint32_t vsd_idx; 158 uint32_t page_shift; 159 uint32_t vst_per_page; 160 161 /* Get the page size of the indirect table. */ 162 vsd_addr = vsd & VSD_ADDRESS_MASK; 163 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 164 165 if (!(vsd & VSD_ADDRESS_MASK)) { 166 #ifdef XIVE2_DEBUG 167 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 168 #endif 169 return 0; 170 } 171 172 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 173 174 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 175 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 176 page_shift); 177 return 0; 178 } 179 180 vst_per_page = (1ull << page_shift) / info->size; 181 vsd_idx = idx / vst_per_page; 182 183 /* Load the VSD we are looking for, if not already done */ 184 if (vsd_idx) { 185 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 186 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 187 MEMTXATTRS_UNSPECIFIED); 188 189 if (!(vsd & VSD_ADDRESS_MASK)) { 190 #ifdef XIVE2_DEBUG 191 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 192 #endif 193 return 0; 194 } 195 196 /* 197 * Check that the pages have a consistent size across the 198 * indirect table 199 */ 200 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 201 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 202 info->name, idx); 203 return 0; 204 } 205 } 206 207 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 208 } 209 210 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 211 uint32_t idx) 212 { 213 const XiveVstInfo *info = &vst_infos[type]; 214 uint64_t vsd; 215 216 if (blk >= info->max_blocks) { 217 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 218 blk, info->name, idx); 219 return 0; 220 } 221 222 vsd = xive->vsds[type][blk]; 223 224 /* Remote VST access */ 225 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 226 xive = pnv_xive2_get_remote(blk); 227 228 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 229 } 230 231 if (VSD_INDIRECT & vsd) { 232 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 233 } 234 235 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 236 } 237 238 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 239 uint32_t idx, void *data) 240 { 241 const XiveVstInfo *info = &vst_infos[type]; 242 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 243 244 if (!addr) { 245 return -1; 246 } 247 248 cpu_physical_memory_read(addr, data, info->size); 249 return 0; 250 } 251 252 #define XIVE_VST_WORD_ALL -1 253 254 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 255 uint32_t idx, void *data, uint32_t word_number) 256 { 257 const XiveVstInfo *info = &vst_infos[type]; 258 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 259 260 if (!addr) { 261 return -1; 262 } 263 264 if (word_number == XIVE_VST_WORD_ALL) { 265 cpu_physical_memory_write(addr, data, info->size); 266 } else { 267 cpu_physical_memory_write(addr + word_number * 4, 268 data + word_number * 4, 4); 269 } 270 return 0; 271 } 272 273 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 274 uint8_t *pq) 275 { 276 PnvXive2 *xive = PNV_XIVE2(xrtr); 277 278 if (pnv_xive2_block_id(xive) != blk) { 279 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 280 return -1; 281 } 282 283 *pq = xive_source_esb_get(&xive->ipi_source, idx); 284 return 0; 285 } 286 287 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 288 uint8_t *pq) 289 { 290 PnvXive2 *xive = PNV_XIVE2(xrtr); 291 292 if (pnv_xive2_block_id(xive) != blk) { 293 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 294 return -1; 295 } 296 297 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 298 return 0; 299 } 300 301 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 302 Xive2End *end) 303 { 304 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 305 } 306 307 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 308 Xive2End *end, uint8_t word_number) 309 { 310 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 311 word_number); 312 } 313 314 static int pnv_xive2_end_update(PnvXive2 *xive) 315 { 316 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 317 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 318 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 319 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 320 int i; 321 uint64_t endc_watch[4]; 322 323 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 324 endc_watch[i] = 325 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 326 } 327 328 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 329 XIVE_VST_WORD_ALL); 330 } 331 332 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 333 { 334 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 335 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 336 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 337 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 338 uint64_t endc_watch[4] = { 0 }; 339 int i; 340 341 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 342 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 343 } 344 345 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 346 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 347 be64_to_cpu(endc_watch[i]); 348 } 349 } 350 351 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 352 Xive2Nvp *nvp) 353 { 354 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 355 } 356 357 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 358 Xive2Nvp *nvp, uint8_t word_number) 359 { 360 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 361 word_number); 362 } 363 364 static int pnv_xive2_nvp_update(PnvXive2 *xive) 365 { 366 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 367 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 368 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 369 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 370 int i; 371 uint64_t nxc_watch[4]; 372 373 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 374 nxc_watch[i] = 375 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 376 } 377 378 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 379 XIVE_VST_WORD_ALL); 380 } 381 382 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 383 { 384 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 385 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 386 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 387 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 388 uint64_t nxc_watch[4] = { 0 }; 389 int i; 390 391 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 392 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 393 } 394 395 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 396 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 397 be64_to_cpu(nxc_watch[i]); 398 } 399 } 400 401 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 402 Xive2Eas *eas) 403 { 404 PnvXive2 *xive = PNV_XIVE2(xrtr); 405 406 if (pnv_xive2_block_id(xive) != blk) { 407 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 408 return -1; 409 } 410 411 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 412 } 413 414 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 415 { 416 PnvXive2 *xive = PNV_XIVE2(xrtr); 417 uint32_t cfg = 0; 418 419 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 420 cfg |= XIVE2_GEN1_TIMA_OS; 421 } 422 423 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 424 cfg |= XIVE2_VP_SAVE_RESTORE; 425 } 426 427 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 428 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { 429 cfg |= XIVE2_THREADID_8BITS; 430 } 431 432 return cfg; 433 } 434 435 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 436 { 437 int pir = ppc_cpu_pir(cpu); 438 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 439 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 440 uint32_t bit = pir & 0x3f; 441 442 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 443 } 444 445 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 446 uint8_t nvt_blk, uint32_t nvt_idx, 447 bool cam_ignore, uint8_t priority, 448 uint32_t logic_serv, XiveTCTXMatch *match) 449 { 450 PnvXive2 *xive = PNV_XIVE2(xptr); 451 PnvChip *chip = xive->chip; 452 int count = 0; 453 int i, j; 454 bool gen1_tima_os = 455 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 456 457 for (i = 0; i < chip->nr_cores; i++) { 458 PnvCore *pc = chip->cores[i]; 459 CPUCore *cc = CPU_CORE(pc); 460 461 for (j = 0; j < cc->nr_threads; j++) { 462 PowerPCCPU *cpu = pc->threads[j]; 463 XiveTCTX *tctx; 464 int ring; 465 466 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 467 continue; 468 } 469 470 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 471 472 if (gen1_tima_os) { 473 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 474 nvt_idx, cam_ignore, 475 logic_serv); 476 } else { 477 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 478 nvt_idx, cam_ignore, 479 logic_serv); 480 } 481 482 /* 483 * Save the context and follow on to catch duplicates, 484 * that we don't support yet. 485 */ 486 if (ring != -1) { 487 if (match->tctx) { 488 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 489 "thread context NVT %x/%x\n", 490 nvt_blk, nvt_idx); 491 return false; 492 } 493 494 match->ring = ring; 495 match->tctx = tctx; 496 count++; 497 } 498 } 499 } 500 501 return count; 502 } 503 504 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 505 { 506 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 507 } 508 509 /* 510 * The TIMA MMIO space is shared among the chips and to identify the 511 * chip from which the access is being done, we extract the chip id 512 * from the PIR. 513 */ 514 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 515 { 516 int pir = ppc_cpu_pir(cpu); 517 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 518 PnvXive2 *xive = PNV_XIVE2(xptr); 519 520 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 521 xive2_error(xive, "IC: CPU %x is not enabled", pir); 522 } 523 return xive; 524 } 525 526 /* 527 * The internal sources of the interrupt controller have no knowledge 528 * of the XIVE2 chip on which they reside. Encode the block id in the 529 * source interrupt number before forwarding the source event 530 * notification to the Router. This is required on a multichip system. 531 */ 532 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 533 { 534 PnvXive2 *xive = PNV_XIVE2(xn); 535 uint8_t blk = pnv_xive2_block_id(xive); 536 537 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 538 } 539 540 /* 541 * Set Translation Tables 542 * 543 * TODO add support for multiple sets 544 */ 545 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 546 { 547 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 548 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 549 xive->cq_regs[CQ_TAR >> 3]); 550 551 switch (tsel) { 552 case CQ_TAR_NVPG: 553 case CQ_TAR_ESB: 554 case CQ_TAR_END: 555 xive->tables[tsel][entry] = val; 556 break; 557 default: 558 xive2_error(xive, "IC: unsupported table %d", tsel); 559 return -1; 560 } 561 562 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 563 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 564 xive->cq_regs[CQ_TAR >> 3], ++entry); 565 } 566 567 return 0; 568 } 569 /* 570 * Virtual Structure Tables (VST) configuration 571 */ 572 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 573 uint8_t blk, uint64_t vsd) 574 { 575 Xive2EndSource *end_xsrc = &xive->end_source; 576 XiveSource *xsrc = &xive->ipi_source; 577 const XiveVstInfo *info = &vst_infos[type]; 578 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 579 uint64_t vst_tsize = 1ull << page_shift; 580 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 581 582 /* Basic checks */ 583 584 if (VSD_INDIRECT & vsd) { 585 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 586 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 587 page_shift); 588 return; 589 } 590 } 591 592 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 593 xive2_error(xive, "VST: %s table address 0x%"PRIx64 594 " is not aligned with page shift %d", 595 info->name, vst_addr, page_shift); 596 return; 597 } 598 599 /* Record the table configuration (in SRAM on HW) */ 600 xive->vsds[type][blk] = vsd; 601 602 /* Now tune the models with the configuration provided by the FW */ 603 604 switch (type) { 605 case VST_ESB: 606 /* 607 * Backing store pages for the source PQ bits. The model does 608 * not use these PQ bits backed in RAM because the XiveSource 609 * model has its own. 610 * 611 * If the table is direct, we can compute the number of PQ 612 * entries provisioned by FW (such as skiboot) and resize the 613 * ESB window accordingly. 614 */ 615 if (!(VSD_INDIRECT & vsd)) { 616 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 617 * (1ull << xsrc->esb_shift)); 618 } 619 620 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 621 break; 622 623 case VST_EAS: /* Nothing to be done */ 624 break; 625 626 case VST_END: 627 /* 628 * Backing store pages for the END. 629 */ 630 if (!(VSD_INDIRECT & vsd)) { 631 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 632 * (1ull << end_xsrc->esb_shift)); 633 } 634 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 635 break; 636 637 case VST_NVP: /* Not modeled */ 638 case VST_NVG: /* Not modeled */ 639 case VST_NVC: /* Not modeled */ 640 case VST_IC: /* Not modeled */ 641 case VST_SYNC: /* Not modeled */ 642 case VST_ERQ: /* Not modeled */ 643 break; 644 645 default: 646 g_assert_not_reached(); 647 } 648 } 649 650 /* 651 * Both PC and VC sub-engines are configured as each use the Virtual 652 * Structure Tables 653 */ 654 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 655 { 656 uint8_t mode = GETFIELD(VSD_MODE, vsd); 657 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 658 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 659 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 660 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 661 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 662 663 if (type > VST_ERQ) { 664 xive2_error(xive, "VST: invalid table type %d", type); 665 return; 666 } 667 668 if (blk >= vst_infos[type].max_blocks) { 669 xive2_error(xive, "VST: invalid block id %d for" 670 " %s table", blk, vst_infos[type].name); 671 return; 672 } 673 674 if (!vst_addr) { 675 xive2_error(xive, "VST: invalid %s table address", 676 vst_infos[type].name); 677 return; 678 } 679 680 switch (mode) { 681 case VSD_MODE_FORWARD: 682 xive->vsds[type][blk] = vsd; 683 break; 684 685 case VSD_MODE_EXCLUSIVE: 686 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 687 break; 688 689 default: 690 xive2_error(xive, "VST: unsupported table mode %d", mode); 691 return; 692 } 693 } 694 695 /* 696 * MMIO handlers 697 */ 698 699 700 /* 701 * IC BAR layout 702 * 703 * Page 0: Internal CQ register accesses (reads & writes) 704 * Page 1: Internal PC register accesses (reads & writes) 705 * Page 2: Internal VC register accesses (reads & writes) 706 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 707 * Page 4: Notify Port page (writes only, w/data), 708 * Page 5: Reserved 709 * Page 6: Sync Poll page (writes only, dataless) 710 * Page 7: Sync Inject page (writes only, dataless) 711 * Page 8: LSI Trigger page (writes only, dataless) 712 * Page 9: LSI SB Management page (reads & writes dataless) 713 * Pages 10-255: Reserved 714 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 715 * covering the 128 threads in P10. 716 * Pages 384-511: Reserved 717 */ 718 typedef struct PnvXive2Region { 719 const char *name; 720 uint32_t pgoff; 721 uint32_t pgsize; 722 const MemoryRegionOps *ops; 723 } PnvXive2Region; 724 725 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 726 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 727 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 728 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 729 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 730 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 731 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 732 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 733 734 /* 512 pages. 4K: 2M range, 64K: 32M range */ 735 static const PnvXive2Region pnv_xive2_ic_regions[] = { 736 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 737 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 738 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 739 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 740 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 741 /* page 5 reserved */ 742 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 743 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 744 /* pages 10-255 reserved */ 745 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 746 /* pages 384-511 reserved */ 747 }; 748 749 /* 750 * CQ operations 751 */ 752 753 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 754 unsigned size) 755 { 756 PnvXive2 *xive = PNV_XIVE2(opaque); 757 uint32_t reg = offset >> 3; 758 uint64_t val = 0; 759 760 switch (offset) { 761 case CQ_XIVE_CAP: /* Set at reset */ 762 case CQ_XIVE_CFG: 763 val = xive->cq_regs[reg]; 764 break; 765 case CQ_MSGSND: /* TODO check the #cores of the machine */ 766 val = 0xffffffff00000000; 767 break; 768 case CQ_CFG_PB_GEN: 769 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 770 break; 771 default: 772 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 773 } 774 775 return val; 776 } 777 778 static uint64_t pnv_xive2_bar_size(uint64_t val) 779 { 780 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 781 } 782 783 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 784 uint64_t val, unsigned size) 785 { 786 PnvXive2 *xive = PNV_XIVE2(opaque); 787 MemoryRegion *sysmem = get_system_memory(); 788 uint32_t reg = offset >> 3; 789 int i; 790 791 switch (offset) { 792 case CQ_XIVE_CFG: 793 case CQ_RST_CTL: /* TODO: reset all BARs */ 794 break; 795 796 case CQ_IC_BAR: 797 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 798 if (!(val & CQ_IC_BAR_VALID)) { 799 xive->ic_base = 0; 800 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 801 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 802 memory_region_del_subregion(&xive->ic_mmio, 803 &xive->ic_mmios[i]); 804 } 805 memory_region_del_subregion(sysmem, &xive->ic_mmio); 806 } 807 } else { 808 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 809 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 810 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 811 memory_region_add_subregion(&xive->ic_mmio, 812 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 813 &xive->ic_mmios[i]); 814 } 815 memory_region_add_subregion(sysmem, xive->ic_base, 816 &xive->ic_mmio); 817 } 818 } 819 break; 820 821 case CQ_TM_BAR: 822 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 823 if (!(val & CQ_TM_BAR_VALID)) { 824 xive->tm_base = 0; 825 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 826 memory_region_del_subregion(sysmem, &xive->tm_mmio); 827 } 828 } else { 829 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 830 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 831 memory_region_add_subregion(sysmem, xive->tm_base, 832 &xive->tm_mmio); 833 } 834 } 835 break; 836 837 case CQ_ESB_BAR: 838 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 839 if (!(val & CQ_BAR_VALID)) { 840 xive->esb_base = 0; 841 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 842 memory_region_del_subregion(sysmem, &xive->esb_mmio); 843 } 844 } else { 845 xive->esb_base = val & CQ_BAR_ADDR; 846 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 847 memory_region_set_size(&xive->esb_mmio, 848 pnv_xive2_bar_size(val)); 849 memory_region_add_subregion(sysmem, xive->esb_base, 850 &xive->esb_mmio); 851 } 852 } 853 break; 854 855 case CQ_END_BAR: 856 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 857 if (!(val & CQ_BAR_VALID)) { 858 xive->end_base = 0; 859 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 860 memory_region_del_subregion(sysmem, &xive->end_mmio); 861 } 862 } else { 863 xive->end_base = val & CQ_BAR_ADDR; 864 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 865 memory_region_set_size(&xive->end_mmio, 866 pnv_xive2_bar_size(val)); 867 memory_region_add_subregion(sysmem, xive->end_base, 868 &xive->end_mmio); 869 } 870 } 871 break; 872 873 case CQ_NVC_BAR: 874 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 875 if (!(val & CQ_BAR_VALID)) { 876 xive->nvc_base = 0; 877 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 878 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 879 } 880 } else { 881 xive->nvc_base = val & CQ_BAR_ADDR; 882 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 883 memory_region_set_size(&xive->nvc_mmio, 884 pnv_xive2_bar_size(val)); 885 memory_region_add_subregion(sysmem, xive->nvc_base, 886 &xive->nvc_mmio); 887 } 888 } 889 break; 890 891 case CQ_NVPG_BAR: 892 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 893 if (!(val & CQ_BAR_VALID)) { 894 xive->nvpg_base = 0; 895 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 896 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 897 } 898 } else { 899 xive->nvpg_base = val & CQ_BAR_ADDR; 900 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 901 memory_region_set_size(&xive->nvpg_mmio, 902 pnv_xive2_bar_size(val)); 903 memory_region_add_subregion(sysmem, xive->nvpg_base, 904 &xive->nvpg_mmio); 905 } 906 } 907 break; 908 909 case CQ_TAR: /* Set Translation Table Address */ 910 break; 911 case CQ_TDR: /* Set Translation Table Data */ 912 pnv_xive2_stt_set_data(xive, val); 913 break; 914 case CQ_FIRMASK_OR: /* FIR error reporting */ 915 break; 916 default: 917 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 918 return; 919 } 920 921 xive->cq_regs[reg] = val; 922 } 923 924 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 925 .read = pnv_xive2_ic_cq_read, 926 .write = pnv_xive2_ic_cq_write, 927 .endianness = DEVICE_BIG_ENDIAN, 928 .valid = { 929 .min_access_size = 8, 930 .max_access_size = 8, 931 }, 932 .impl = { 933 .min_access_size = 8, 934 .max_access_size = 8, 935 }, 936 }; 937 938 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 939 unsigned size) 940 { 941 PnvXive2 *xive = PNV_XIVE2(opaque); 942 uint64_t val = 0; 943 uint32_t reg = offset >> 3; 944 945 switch (offset) { 946 /* 947 * VSD table settings. 948 */ 949 case VC_VSD_TABLE_ADDR: 950 case VC_VSD_TABLE_DATA: 951 val = xive->vc_regs[reg]; 952 break; 953 954 /* 955 * ESB cache updates (not modeled) 956 */ 957 case VC_ESBC_FLUSH_CTRL: 958 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 959 val = xive->vc_regs[reg]; 960 break; 961 962 case VC_ESBC_CFG: 963 val = xive->vc_regs[reg]; 964 break; 965 966 /* 967 * EAS cache updates (not modeled) 968 */ 969 case VC_EASC_FLUSH_CTRL: 970 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 971 val = xive->vc_regs[reg]; 972 break; 973 974 /* 975 * END cache updates 976 */ 977 case VC_ENDC_WATCH0_SPEC: 978 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 979 val = xive->vc_regs[reg]; 980 break; 981 982 case VC_ENDC_WATCH0_DATA0: 983 /* 984 * Load DATA registers from cache with data requested by the 985 * SPEC register 986 */ 987 pnv_xive2_end_cache_load(xive); 988 val = xive->vc_regs[reg]; 989 break; 990 991 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 992 val = xive->vc_regs[reg]; 993 break; 994 995 case VC_ENDC_FLUSH_CTRL: 996 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 997 val = xive->vc_regs[reg]; 998 break; 999 1000 /* 1001 * Indirect invalidation 1002 */ 1003 case VC_AT_MACRO_KILL_MASK: 1004 val = xive->vc_regs[reg]; 1005 break; 1006 1007 case VC_AT_MACRO_KILL: 1008 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1009 val = xive->vc_regs[reg]; 1010 break; 1011 1012 /* 1013 * Interrupt fifo overflow in memory backing store (Not modeled) 1014 */ 1015 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1016 val = xive->vc_regs[reg]; 1017 break; 1018 1019 /* 1020 * Synchronisation 1021 */ 1022 case VC_ENDC_SYNC_DONE: 1023 val = VC_ENDC_SYNC_POLL_DONE; 1024 break; 1025 default: 1026 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1027 } 1028 1029 return val; 1030 } 1031 1032 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1033 uint64_t val, unsigned size) 1034 { 1035 PnvXive2 *xive = PNV_XIVE2(opaque); 1036 uint32_t reg = offset >> 3; 1037 1038 switch (offset) { 1039 /* 1040 * VSD table settings. 1041 */ 1042 case VC_VSD_TABLE_ADDR: 1043 break; 1044 case VC_VSD_TABLE_DATA: 1045 pnv_xive2_vst_set_data(xive, val); 1046 break; 1047 1048 /* 1049 * ESB cache updates (not modeled) 1050 */ 1051 /* case VC_ESBC_FLUSH_CTRL: */ 1052 case VC_ESBC_FLUSH_POLL: 1053 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1054 /* ESB update */ 1055 break; 1056 1057 case VC_ESBC_CFG: 1058 break; 1059 1060 /* 1061 * EAS cache updates (not modeled) 1062 */ 1063 /* case VC_EASC_FLUSH_CTRL: */ 1064 case VC_EASC_FLUSH_POLL: 1065 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1066 /* EAS update */ 1067 break; 1068 1069 /* 1070 * END cache updates 1071 */ 1072 case VC_ENDC_WATCH0_SPEC: 1073 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1074 break; 1075 1076 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1077 break; 1078 case VC_ENDC_WATCH0_DATA0: 1079 /* writing to DATA0 triggers the cache write */ 1080 xive->vc_regs[reg] = val; 1081 pnv_xive2_end_update(xive); 1082 break; 1083 1084 1085 /* case VC_ENDC_FLUSH_CTRL: */ 1086 case VC_ENDC_FLUSH_POLL: 1087 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1088 break; 1089 1090 /* 1091 * Indirect invalidation 1092 */ 1093 case VC_AT_MACRO_KILL: 1094 case VC_AT_MACRO_KILL_MASK: 1095 break; 1096 1097 /* 1098 * Interrupt fifo overflow in memory backing store (Not modeled) 1099 */ 1100 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1101 break; 1102 1103 /* 1104 * Synchronisation 1105 */ 1106 case VC_ENDC_SYNC_DONE: 1107 break; 1108 1109 default: 1110 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1111 return; 1112 } 1113 1114 xive->vc_regs[reg] = val; 1115 } 1116 1117 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1118 .read = pnv_xive2_ic_vc_read, 1119 .write = pnv_xive2_ic_vc_write, 1120 .endianness = DEVICE_BIG_ENDIAN, 1121 .valid = { 1122 .min_access_size = 8, 1123 .max_access_size = 8, 1124 }, 1125 .impl = { 1126 .min_access_size = 8, 1127 .max_access_size = 8, 1128 }, 1129 }; 1130 1131 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1132 unsigned size) 1133 { 1134 PnvXive2 *xive = PNV_XIVE2(opaque); 1135 uint64_t val = -1; 1136 uint32_t reg = offset >> 3; 1137 1138 switch (offset) { 1139 /* 1140 * VSD table settings. 1141 */ 1142 case PC_VSD_TABLE_ADDR: 1143 case PC_VSD_TABLE_DATA: 1144 val = xive->pc_regs[reg]; 1145 break; 1146 1147 /* 1148 * cache updates 1149 */ 1150 case PC_NXC_WATCH0_SPEC: 1151 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1152 val = xive->pc_regs[reg]; 1153 break; 1154 1155 case PC_NXC_WATCH0_DATA0: 1156 /* 1157 * Load DATA registers from cache with data requested by the 1158 * SPEC register 1159 */ 1160 pnv_xive2_nvp_cache_load(xive); 1161 val = xive->pc_regs[reg]; 1162 break; 1163 1164 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1165 val = xive->pc_regs[reg]; 1166 break; 1167 1168 case PC_NXC_FLUSH_CTRL: 1169 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1170 val = xive->pc_regs[reg]; 1171 break; 1172 1173 /* 1174 * Indirect invalidation 1175 */ 1176 case PC_AT_KILL: 1177 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1178 val = xive->pc_regs[reg]; 1179 break; 1180 1181 default: 1182 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1183 } 1184 1185 return val; 1186 } 1187 1188 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1189 uint64_t val, unsigned size) 1190 { 1191 PnvXive2 *xive = PNV_XIVE2(opaque); 1192 uint32_t reg = offset >> 3; 1193 1194 switch (offset) { 1195 1196 /* 1197 * VSD table settings. Only taken into account in the VC 1198 * sub-engine because the Xive2Router model combines both VC and PC 1199 * sub-engines 1200 */ 1201 case PC_VSD_TABLE_ADDR: 1202 case PC_VSD_TABLE_DATA: 1203 break; 1204 1205 /* 1206 * cache updates 1207 */ 1208 case PC_NXC_WATCH0_SPEC: 1209 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1210 break; 1211 1212 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1213 break; 1214 case PC_NXC_WATCH0_DATA0: 1215 /* writing to DATA0 triggers the cache write */ 1216 xive->pc_regs[reg] = val; 1217 pnv_xive2_nvp_update(xive); 1218 break; 1219 1220 /* case PC_NXC_FLUSH_CTRL: */ 1221 case PC_NXC_FLUSH_POLL: 1222 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1223 break; 1224 1225 /* 1226 * Indirect invalidation 1227 */ 1228 case PC_AT_KILL: 1229 case PC_AT_KILL_MASK: 1230 break; 1231 1232 default: 1233 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1234 return; 1235 } 1236 1237 xive->pc_regs[reg] = val; 1238 } 1239 1240 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1241 .read = pnv_xive2_ic_pc_read, 1242 .write = pnv_xive2_ic_pc_write, 1243 .endianness = DEVICE_BIG_ENDIAN, 1244 .valid = { 1245 .min_access_size = 8, 1246 .max_access_size = 8, 1247 }, 1248 .impl = { 1249 .min_access_size = 8, 1250 .max_access_size = 8, 1251 }, 1252 }; 1253 1254 1255 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1256 unsigned size) 1257 { 1258 PnvXive2 *xive = PNV_XIVE2(opaque); 1259 uint64_t val = -1; 1260 uint32_t reg = offset >> 3; 1261 1262 switch (offset) { 1263 /* 1264 * XIVE2 hardware thread enablement 1265 */ 1266 case TCTXT_EN0: 1267 case TCTXT_EN1: 1268 val = xive->tctxt_regs[reg]; 1269 break; 1270 1271 case TCTXT_EN0_SET: 1272 case TCTXT_EN0_RESET: 1273 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1274 break; 1275 case TCTXT_EN1_SET: 1276 case TCTXT_EN1_RESET: 1277 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1278 break; 1279 case TCTXT_CFG: 1280 val = xive->tctxt_regs[reg]; 1281 break; 1282 default: 1283 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1284 } 1285 1286 return val; 1287 } 1288 1289 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1290 uint64_t val, unsigned size) 1291 { 1292 PnvXive2 *xive = PNV_XIVE2(opaque); 1293 uint32_t reg = offset >> 3; 1294 1295 switch (offset) { 1296 /* 1297 * XIVE2 hardware thread enablement 1298 */ 1299 case TCTXT_EN0: /* Physical Thread Enable */ 1300 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1301 xive->tctxt_regs[reg] = val; 1302 break; 1303 1304 case TCTXT_EN0_SET: 1305 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1306 break; 1307 case TCTXT_EN1_SET: 1308 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1309 break; 1310 case TCTXT_EN0_RESET: 1311 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1312 break; 1313 case TCTXT_EN1_RESET: 1314 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1315 break; 1316 case TCTXT_CFG: 1317 xive->tctxt_regs[reg] = val; 1318 break; 1319 default: 1320 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1321 return; 1322 } 1323 } 1324 1325 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1326 .read = pnv_xive2_ic_tctxt_read, 1327 .write = pnv_xive2_ic_tctxt_write, 1328 .endianness = DEVICE_BIG_ENDIAN, 1329 .valid = { 1330 .min_access_size = 8, 1331 .max_access_size = 8, 1332 }, 1333 .impl = { 1334 .min_access_size = 8, 1335 .max_access_size = 8, 1336 }, 1337 }; 1338 1339 /* 1340 * Redirect XSCOM to MMIO handlers 1341 */ 1342 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1343 unsigned size) 1344 { 1345 PnvXive2 *xive = PNV_XIVE2(opaque); 1346 uint64_t val = -1; 1347 uint32_t xscom_reg = offset >> 3; 1348 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1349 1350 switch (xscom_reg) { 1351 case 0x000 ... 0x0FF: 1352 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1353 break; 1354 case 0x100 ... 0x1FF: 1355 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1356 break; 1357 case 0x200 ... 0x2FF: 1358 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1359 break; 1360 case 0x300 ... 0x3FF: 1361 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1362 break; 1363 default: 1364 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1365 } 1366 1367 return val; 1368 } 1369 1370 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1371 uint64_t val, unsigned size) 1372 { 1373 PnvXive2 *xive = PNV_XIVE2(opaque); 1374 uint32_t xscom_reg = offset >> 3; 1375 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1376 1377 switch (xscom_reg) { 1378 case 0x000 ... 0x0FF: 1379 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1380 break; 1381 case 0x100 ... 0x1FF: 1382 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1383 break; 1384 case 0x200 ... 0x2FF: 1385 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1386 break; 1387 case 0x300 ... 0x3FF: 1388 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1389 break; 1390 default: 1391 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1392 } 1393 } 1394 1395 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1396 .read = pnv_xive2_xscom_read, 1397 .write = pnv_xive2_xscom_write, 1398 .endianness = DEVICE_BIG_ENDIAN, 1399 .valid = { 1400 .min_access_size = 8, 1401 .max_access_size = 8, 1402 }, 1403 .impl = { 1404 .min_access_size = 8, 1405 .max_access_size = 8, 1406 }, 1407 }; 1408 1409 /* 1410 * Notify port page. The layout is compatible between 4K and 64K pages : 1411 * 1412 * Page 1 Notify page (writes only) 1413 * 0x000 - 0x7FF IPI interrupt (NPU) 1414 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1415 */ 1416 1417 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1418 uint64_t val) 1419 { 1420 uint8_t blk; 1421 uint32_t idx; 1422 1423 if (val & XIVE_TRIGGER_END) { 1424 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1425 addr, val); 1426 return; 1427 } 1428 1429 /* 1430 * Forward the source event notification directly to the Router. 1431 * The source interrupt number should already be correctly encoded 1432 * with the chip block id by the sending device (PHB, PSI). 1433 */ 1434 blk = XIVE_EAS_BLOCK(val); 1435 idx = XIVE_EAS_INDEX(val); 1436 1437 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1438 !!(val & XIVE_TRIGGER_PQ)); 1439 } 1440 1441 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1442 uint64_t val, unsigned size) 1443 { 1444 PnvXive2 *xive = PNV_XIVE2(opaque); 1445 1446 /* VC: IPI triggers */ 1447 switch (offset) { 1448 case 0x000 ... 0x7FF: 1449 /* TODO: check IPI notify sub-page routing */ 1450 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1451 break; 1452 1453 /* VC: HW triggers */ 1454 case 0x800 ... 0xFFF: 1455 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1456 break; 1457 1458 default: 1459 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1460 } 1461 } 1462 1463 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1464 unsigned size) 1465 { 1466 PnvXive2 *xive = PNV_XIVE2(opaque); 1467 1468 /* loads are invalid */ 1469 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1470 return -1; 1471 } 1472 1473 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1474 .read = pnv_xive2_ic_notify_read, 1475 .write = pnv_xive2_ic_notify_write, 1476 .endianness = DEVICE_BIG_ENDIAN, 1477 .valid = { 1478 .min_access_size = 8, 1479 .max_access_size = 8, 1480 }, 1481 .impl = { 1482 .min_access_size = 8, 1483 .max_access_size = 8, 1484 }, 1485 }; 1486 1487 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1488 unsigned size) 1489 { 1490 PnvXive2 *xive = PNV_XIVE2(opaque); 1491 1492 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1493 return -1; 1494 } 1495 1496 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1497 uint64_t val, unsigned size) 1498 { 1499 PnvXive2 *xive = PNV_XIVE2(opaque); 1500 1501 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1502 } 1503 1504 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1505 .read = pnv_xive2_ic_lsi_read, 1506 .write = pnv_xive2_ic_lsi_write, 1507 .endianness = DEVICE_BIG_ENDIAN, 1508 .valid = { 1509 .min_access_size = 8, 1510 .max_access_size = 8, 1511 }, 1512 .impl = { 1513 .min_access_size = 8, 1514 .max_access_size = 8, 1515 }, 1516 }; 1517 1518 /* 1519 * Sync MMIO page (write only) 1520 */ 1521 #define PNV_XIVE2_SYNC_IPI 0x000 1522 #define PNV_XIVE2_SYNC_HW 0x080 1523 #define PNV_XIVE2_SYNC_NxC 0x100 1524 #define PNV_XIVE2_SYNC_INT 0x180 1525 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1526 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1527 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1528 1529 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1530 unsigned size) 1531 { 1532 PnvXive2 *xive = PNV_XIVE2(opaque); 1533 1534 /* loads are invalid */ 1535 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1536 return -1; 1537 } 1538 1539 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1540 uint64_t val, unsigned size) 1541 { 1542 PnvXive2 *xive = PNV_XIVE2(opaque); 1543 1544 switch (offset) { 1545 case PNV_XIVE2_SYNC_IPI: 1546 case PNV_XIVE2_SYNC_HW: 1547 case PNV_XIVE2_SYNC_NxC: 1548 case PNV_XIVE2_SYNC_INT: 1549 case PNV_XIVE2_SYNC_OS_ESC: 1550 case PNV_XIVE2_SYNC_POOL_ESC: 1551 case PNV_XIVE2_SYNC_HARD_ESC: 1552 break; 1553 default: 1554 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1555 } 1556 } 1557 1558 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1559 .read = pnv_xive2_ic_sync_read, 1560 .write = pnv_xive2_ic_sync_write, 1561 .endianness = DEVICE_BIG_ENDIAN, 1562 .valid = { 1563 .min_access_size = 8, 1564 .max_access_size = 8, 1565 }, 1566 .impl = { 1567 .min_access_size = 8, 1568 .max_access_size = 8, 1569 }, 1570 }; 1571 1572 /* 1573 * When the TM direct pages of the IC controller are accessed, the 1574 * target HW thread is deduced from the page offset. 1575 */ 1576 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset) 1577 { 1578 /* On P10, the node ID shift in the PIR register is 8 bits */ 1579 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; 1580 } 1581 1582 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1583 { 1584 PnvChip *chip = xive->chip; 1585 PowerPCCPU *cpu = NULL; 1586 1587 cpu = pnv_chip_find_cpu(chip, pir); 1588 if (!cpu) { 1589 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1590 return NULL; 1591 } 1592 1593 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1594 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1595 } 1596 1597 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1598 } 1599 1600 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1601 unsigned size) 1602 { 1603 PnvXive2 *xive = PNV_XIVE2(opaque); 1604 uint32_t pir; 1605 XiveTCTX *tctx; 1606 uint64_t val = -1; 1607 1608 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1609 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1610 if (tctx) { 1611 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1612 } 1613 1614 return val; 1615 } 1616 1617 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1618 uint64_t val, unsigned size) 1619 { 1620 PnvXive2 *xive = PNV_XIVE2(opaque); 1621 uint32_t pir; 1622 XiveTCTX *tctx; 1623 1624 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1625 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1626 if (tctx) { 1627 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1628 } 1629 } 1630 1631 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1632 .read = pnv_xive2_ic_tm_indirect_read, 1633 .write = pnv_xive2_ic_tm_indirect_write, 1634 .endianness = DEVICE_BIG_ENDIAN, 1635 .valid = { 1636 .min_access_size = 8, 1637 .max_access_size = 8, 1638 }, 1639 .impl = { 1640 .min_access_size = 8, 1641 .max_access_size = 8, 1642 }, 1643 }; 1644 1645 /* 1646 * TIMA ops 1647 */ 1648 1649 /* 1650 * Special TIMA offsets to handle accesses in a POWER10 way. 1651 * 1652 * Only the CAM line updates done by the hypervisor should be handled 1653 * specifically. 1654 */ 1655 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) 1656 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) 1657 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) 1658 1659 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1660 uint64_t value, unsigned size) 1661 { 1662 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1663 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1664 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1665 XivePresenter *xptr = XIVE_PRESENTER(xive); 1666 bool gen1_tima_os = 1667 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1668 1669 offset &= TM_ADDRESS_MASK; 1670 1671 /* TODO: should we switch the TM ops table instead ? */ 1672 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { 1673 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); 1674 return; 1675 } 1676 1677 /* Other TM ops are the same as XIVE1 */ 1678 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1679 } 1680 1681 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1682 { 1683 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1684 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1685 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1686 XivePresenter *xptr = XIVE_PRESENTER(xive); 1687 bool gen1_tima_os = 1688 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1689 1690 offset &= TM_ADDRESS_MASK; 1691 1692 /* TODO: should we switch the TM ops table instead ? */ 1693 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { 1694 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); 1695 } 1696 1697 /* Other TM ops are the same as XIVE1 */ 1698 return xive_tctx_tm_read(xptr, tctx, offset, size); 1699 } 1700 1701 static const MemoryRegionOps pnv_xive2_tm_ops = { 1702 .read = pnv_xive2_tm_read, 1703 .write = pnv_xive2_tm_write, 1704 .endianness = DEVICE_BIG_ENDIAN, 1705 .valid = { 1706 .min_access_size = 1, 1707 .max_access_size = 8, 1708 }, 1709 .impl = { 1710 .min_access_size = 1, 1711 .max_access_size = 8, 1712 }, 1713 }; 1714 1715 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1716 unsigned size) 1717 { 1718 PnvXive2 *xive = PNV_XIVE2(opaque); 1719 1720 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1721 return -1; 1722 } 1723 1724 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1725 uint64_t val, unsigned size) 1726 { 1727 PnvXive2 *xive = PNV_XIVE2(opaque); 1728 1729 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1730 } 1731 1732 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1733 .read = pnv_xive2_nvc_read, 1734 .write = pnv_xive2_nvc_write, 1735 .endianness = DEVICE_BIG_ENDIAN, 1736 .valid = { 1737 .min_access_size = 8, 1738 .max_access_size = 8, 1739 }, 1740 .impl = { 1741 .min_access_size = 8, 1742 .max_access_size = 8, 1743 }, 1744 }; 1745 1746 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1747 unsigned size) 1748 { 1749 PnvXive2 *xive = PNV_XIVE2(opaque); 1750 1751 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1752 return -1; 1753 } 1754 1755 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1756 uint64_t val, unsigned size) 1757 { 1758 PnvXive2 *xive = PNV_XIVE2(opaque); 1759 1760 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1761 } 1762 1763 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1764 .read = pnv_xive2_nvpg_read, 1765 .write = pnv_xive2_nvpg_write, 1766 .endianness = DEVICE_BIG_ENDIAN, 1767 .valid = { 1768 .min_access_size = 8, 1769 .max_access_size = 8, 1770 }, 1771 .impl = { 1772 .min_access_size = 8, 1773 .max_access_size = 8, 1774 }, 1775 }; 1776 1777 /* 1778 * POWER10 default capabilities: 0x2000120076f000FC 1779 */ 1780 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1781 1782 /* 1783 * POWER10 default configuration: 0x0030000033000000 1784 * 1785 * 8bits thread id was dropped for P10 1786 */ 1787 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1788 1789 static void pnv_xive2_reset(void *dev) 1790 { 1791 PnvXive2 *xive = PNV_XIVE2(dev); 1792 XiveSource *xsrc = &xive->ipi_source; 1793 Xive2EndSource *end_xsrc = &xive->end_source; 1794 1795 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1796 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1797 1798 /* HW hardwires the #Topology of the chip in the block field */ 1799 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1800 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1801 1802 /* Set default page size to 64k */ 1803 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1804 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1805 1806 /* Clear source MMIOs */ 1807 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1808 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1809 } 1810 1811 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1812 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1813 } 1814 } 1815 1816 /* 1817 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1818 * software. 1819 */ 1820 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1821 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1822 1823 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1824 { 1825 PnvXive2 *xive = PNV_XIVE2(dev); 1826 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1827 XiveSource *xsrc = &xive->ipi_source; 1828 Xive2EndSource *end_xsrc = &xive->end_source; 1829 Error *local_err = NULL; 1830 int i; 1831 1832 pxc->parent_realize(dev, &local_err); 1833 if (local_err) { 1834 error_propagate(errp, local_err); 1835 return; 1836 } 1837 1838 assert(xive->chip); 1839 1840 /* 1841 * The XiveSource and Xive2EndSource objects are realized with the 1842 * maximum allowed HW configuration. The ESB MMIO regions will be 1843 * resized dynamically when the controller is configured by the FW 1844 * to limit accesses to resources not provisioned. 1845 */ 1846 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1847 &error_fatal); 1848 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1849 &error_fatal); 1850 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1851 &error_fatal); 1852 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1853 if (local_err) { 1854 error_propagate(errp, local_err); 1855 return; 1856 } 1857 1858 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1859 &error_fatal); 1860 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1861 &error_abort); 1862 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1863 if (local_err) { 1864 error_propagate(errp, local_err); 1865 return; 1866 } 1867 1868 /* XSCOM region, used for initial configuration of the BARs */ 1869 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1870 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1871 PNV10_XSCOM_XIVE2_SIZE << 3); 1872 1873 /* Interrupt controller MMIO regions */ 1874 xive->ic_shift = 16; 1875 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1876 PNV10_XIVE2_IC_SIZE); 1877 1878 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1879 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1880 pnv_xive2_ic_regions[i].ops, xive, 1881 pnv_xive2_ic_regions[i].name, 1882 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1883 } 1884 1885 /* 1886 * VC MMIO regions. 1887 */ 1888 xive->esb_shift = 16; 1889 xive->end_shift = 16; 1890 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1891 PNV10_XIVE2_ESB_SIZE); 1892 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1893 PNV10_XIVE2_END_SIZE); 1894 1895 /* Presenter Controller MMIO region (not modeled) */ 1896 xive->nvc_shift = 16; 1897 xive->nvpg_shift = 16; 1898 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1899 &pnv_xive2_nvc_ops, xive, 1900 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1901 1902 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1903 &pnv_xive2_nvpg_ops, xive, 1904 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1905 1906 /* Thread Interrupt Management Area (Direct) */ 1907 xive->tm_shift = 16; 1908 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1909 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1910 1911 qemu_register_reset(pnv_xive2_reset, dev); 1912 } 1913 1914 static Property pnv_xive2_properties[] = { 1915 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1916 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1917 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1918 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1919 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1920 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1921 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1922 PNV_XIVE2_CAPABILITIES), 1923 DEFINE_PROP_UINT64("config", PnvXive2, config, 1924 PNV_XIVE2_CONFIGURATION), 1925 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1926 DEFINE_PROP_END_OF_LIST(), 1927 }; 1928 1929 static void pnv_xive2_instance_init(Object *obj) 1930 { 1931 PnvXive2 *xive = PNV_XIVE2(obj); 1932 1933 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1934 TYPE_XIVE_SOURCE); 1935 object_initialize_child(obj, "end_source", &xive->end_source, 1936 TYPE_XIVE2_END_SOURCE); 1937 } 1938 1939 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1940 int xscom_offset) 1941 { 1942 const char compat_p10[] = "ibm,power10-xive-x"; 1943 char *name; 1944 int offset; 1945 uint32_t reg[] = { 1946 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1947 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1948 }; 1949 1950 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1951 offset = fdt_add_subnode(fdt, xscom_offset, name); 1952 _FDT(offset); 1953 g_free(name); 1954 1955 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1956 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1957 sizeof(compat_p10))); 1958 return 0; 1959 } 1960 1961 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1962 { 1963 DeviceClass *dc = DEVICE_CLASS(klass); 1964 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1965 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1966 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1967 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1968 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1969 1970 xdc->dt_xscom = pnv_xive2_dt_xscom; 1971 1972 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1973 device_class_set_parent_realize(dc, pnv_xive2_realize, 1974 &pxc->parent_realize); 1975 device_class_set_props(dc, pnv_xive2_properties); 1976 1977 xrc->get_eas = pnv_xive2_get_eas; 1978 xrc->get_pq = pnv_xive2_get_pq; 1979 xrc->set_pq = pnv_xive2_set_pq; 1980 xrc->get_end = pnv_xive2_get_end; 1981 xrc->write_end = pnv_xive2_write_end; 1982 xrc->get_nvp = pnv_xive2_get_nvp; 1983 xrc->write_nvp = pnv_xive2_write_nvp; 1984 xrc->get_config = pnv_xive2_get_config; 1985 xrc->get_block_id = pnv_xive2_get_block_id; 1986 1987 xnc->notify = pnv_xive2_notify; 1988 1989 xpc->match_nvt = pnv_xive2_match_nvt; 1990 }; 1991 1992 static const TypeInfo pnv_xive2_info = { 1993 .name = TYPE_PNV_XIVE2, 1994 .parent = TYPE_XIVE2_ROUTER, 1995 .instance_init = pnv_xive2_instance_init, 1996 .instance_size = sizeof(PnvXive2), 1997 .class_init = pnv_xive2_class_init, 1998 .class_size = sizeof(PnvXive2Class), 1999 .interfaces = (InterfaceInfo[]) { 2000 { TYPE_PNV_XSCOM_INTERFACE }, 2001 { } 2002 } 2003 }; 2004 2005 static void pnv_xive2_register_types(void) 2006 { 2007 type_register_static(&pnv_xive2_info); 2008 } 2009 2010 type_init(pnv_xive2_register_types) 2011 2012 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 2013 Monitor *mon) 2014 { 2015 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 2016 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 2017 2018 if (!xive2_nvp_is_valid(nvp)) { 2019 return; 2020 } 2021 2022 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", 2023 nvp_idx, eq_blk, eq_idx, 2024 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2025 /* 2026 * When the NVP is HW controlled, more fields are updated 2027 */ 2028 if (xive2_nvp_is_hw(nvp)) { 2029 monitor_printf(mon, " CPPR:%02x", 2030 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2031 if (xive2_nvp_is_co(nvp)) { 2032 monitor_printf(mon, " CO:%04x", 2033 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2034 } 2035 } 2036 monitor_printf(mon, "\n"); 2037 } 2038 2039 /* 2040 * If the table is direct, we can compute the number of PQ entries 2041 * provisioned by FW. 2042 */ 2043 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2044 { 2045 uint8_t blk = pnv_xive2_block_id(xive); 2046 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2047 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2048 2049 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2050 } 2051 2052 /* 2053 * Compute the number of entries per indirect subpage. 2054 */ 2055 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2056 { 2057 uint8_t blk = pnv_xive2_block_id(xive); 2058 uint64_t vsd = xive->vsds[type][blk]; 2059 const XiveVstInfo *info = &vst_infos[type]; 2060 uint64_t vsd_addr; 2061 uint32_t page_shift; 2062 2063 /* For direct tables, fake a valid value */ 2064 if (!(VSD_INDIRECT & vsd)) { 2065 return 1; 2066 } 2067 2068 /* Get the page size of the indirect table. */ 2069 vsd_addr = vsd & VSD_ADDRESS_MASK; 2070 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2071 2072 if (!(vsd & VSD_ADDRESS_MASK)) { 2073 #ifdef XIVE2_DEBUG 2074 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2075 #endif 2076 return 0; 2077 } 2078 2079 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2080 2081 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2082 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2083 page_shift); 2084 return 0; 2085 } 2086 2087 return (1ull << page_shift) / info->size; 2088 } 2089 2090 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2091 { 2092 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2093 uint8_t blk = pnv_xive2_block_id(xive); 2094 uint8_t chip_id = xive->chip->chip_id; 2095 uint32_t srcno0 = XIVE_EAS(blk, 0); 2096 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2097 Xive2Eas eas; 2098 Xive2End end; 2099 Xive2Nvp nvp; 2100 int i; 2101 uint64_t xive_nvp_per_subpage; 2102 2103 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2104 srcno0 + nr_esbs - 1); 2105 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2106 2107 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2108 srcno0 + nr_esbs - 1); 2109 for (i = 0; i < nr_esbs; i++) { 2110 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2111 break; 2112 } 2113 if (!xive2_eas_is_masked(&eas)) { 2114 xive2_eas_pic_print_info(&eas, i, mon); 2115 } 2116 } 2117 2118 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2119 i = 0; 2120 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2121 xive2_end_eas_pic_print_info(&end, i++, mon); 2122 } 2123 2124 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2125 i = 0; 2126 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2127 xive2_end_pic_print_info(&end, i++, mon); 2128 } 2129 2130 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2131 0, XIVE2_NVP_COUNT - 1); 2132 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2133 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2134 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2135 xive2_nvp_pic_print_info(&nvp, i++, mon); 2136 } 2137 } 2138 } 2139