1cc63a182SAnup Patel /* 2b8fb878aSAnup Patel * RISC-V ACLINT (Advanced Core Local Interruptor) 3b8fb878aSAnup Patel * URL: https://github.com/riscv/riscv-aclint 4cc63a182SAnup Patel * 5cc63a182SAnup Patel * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 6cc63a182SAnup Patel * Copyright (c) 2017 SiFive, Inc. 7b8fb878aSAnup Patel * Copyright (c) 2021 Western Digital Corporation or its affiliates. 8cc63a182SAnup Patel * 9cc63a182SAnup Patel * This provides real-time clock, timer and interprocessor interrupts. 10cc63a182SAnup Patel * 11cc63a182SAnup Patel * This program is free software; you can redistribute it and/or modify it 12cc63a182SAnup Patel * under the terms and conditions of the GNU General Public License, 13cc63a182SAnup Patel * version 2 or later, as published by the Free Software Foundation. 14cc63a182SAnup Patel * 15cc63a182SAnup Patel * This program is distributed in the hope it will be useful, but WITHOUT 16cc63a182SAnup Patel * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17cc63a182SAnup Patel * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18cc63a182SAnup Patel * more details. 19cc63a182SAnup Patel * 20cc63a182SAnup Patel * You should have received a copy of the GNU General Public License along with 21cc63a182SAnup Patel * this program. If not, see <http://www.gnu.org/licenses/>. 22cc63a182SAnup Patel */ 23cc63a182SAnup Patel 24cc63a182SAnup Patel #include "qemu/osdep.h" 25cc63a182SAnup Patel #include "qapi/error.h" 26cc63a182SAnup Patel #include "qemu/error-report.h" 27b8fb878aSAnup Patel #include "qemu/log.h" 28cc63a182SAnup Patel #include "qemu/module.h" 29cc63a182SAnup Patel #include "hw/sysbus.h" 30cc63a182SAnup Patel #include "target/riscv/cpu.h" 31cc63a182SAnup Patel #include "hw/qdev-properties.h" 32cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h" 33cc63a182SAnup Patel #include "qemu/timer.h" 34cc63a182SAnup Patel #include "hw/irq.h" 35cc63a182SAnup Patel 36b8fb878aSAnup Patel typedef struct riscv_aclint_mtimer_callback { 37b8fb878aSAnup Patel RISCVAclintMTimerState *s; 38cc63a182SAnup Patel int num; 39b8fb878aSAnup Patel } riscv_aclint_mtimer_callback; 40cc63a182SAnup Patel 41cc63a182SAnup Patel static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) 42cc63a182SAnup Patel { 43cc63a182SAnup Patel return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 44cc63a182SAnup Patel timebase_freq, NANOSECONDS_PER_SECOND); 45cc63a182SAnup Patel } 46cc63a182SAnup Patel 47cc63a182SAnup Patel /* 48cc63a182SAnup Patel * Called when timecmp is written to update the QEMU timer or immediately 49cc63a182SAnup Patel * trigger timer interrupt if mtimecmp <= current timer value. 50cc63a182SAnup Patel */ 51b8fb878aSAnup Patel static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, 52b8fb878aSAnup Patel RISCVCPU *cpu, 53cc63a182SAnup Patel int hartid, 54cc63a182SAnup Patel uint64_t value, 55cc63a182SAnup Patel uint32_t timebase_freq) 56cc63a182SAnup Patel { 57cc63a182SAnup Patel uint64_t next; 58cc63a182SAnup Patel uint64_t diff; 59cc63a182SAnup Patel 60cc63a182SAnup Patel uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); 61cc63a182SAnup Patel 62cc63a182SAnup Patel cpu->env.timecmp = value; 63cc63a182SAnup Patel if (cpu->env.timecmp <= rtc_r) { 64b8fb878aSAnup Patel /* 65b8fb878aSAnup Patel * If we're setting an MTIMECMP value in the "past", 66b8fb878aSAnup Patel * immediately raise the timer interrupt 67b8fb878aSAnup Patel */ 68b8fb878aSAnup Patel qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]); 69cc63a182SAnup Patel return; 70cc63a182SAnup Patel } 71cc63a182SAnup Patel 72cc63a182SAnup Patel /* otherwise, set up the future timer interrupt */ 73b8fb878aSAnup Patel qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]); 74cc63a182SAnup Patel diff = cpu->env.timecmp - rtc_r; 75cc63a182SAnup Patel /* back to ns (note args switched in muldiv64) */ 76cc63a182SAnup Patel uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); 77cc63a182SAnup Patel 78cc63a182SAnup Patel /* 79cc63a182SAnup Patel * check if ns_diff overflowed and check if the addition would potentially 80cc63a182SAnup Patel * overflow 81cc63a182SAnup Patel */ 82cc63a182SAnup Patel if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || 83cc63a182SAnup Patel ns_diff > INT64_MAX) { 84cc63a182SAnup Patel next = INT64_MAX; 85cc63a182SAnup Patel } else { 86cc63a182SAnup Patel /* 87cc63a182SAnup Patel * as it is very unlikely qemu_clock_get_ns will return a value 88cc63a182SAnup Patel * greater than INT64_MAX, no additional check is needed for an 89cc63a182SAnup Patel * unsigned integer overflow. 90cc63a182SAnup Patel */ 91cc63a182SAnup Patel next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; 92cc63a182SAnup Patel /* 93cc63a182SAnup Patel * if ns_diff is INT64_MAX next may still be outside the range 94cc63a182SAnup Patel * of a signed integer. 95cc63a182SAnup Patel */ 96cc63a182SAnup Patel next = MIN(next, INT64_MAX); 97cc63a182SAnup Patel } 98cc63a182SAnup Patel 99cc63a182SAnup Patel timer_mod(cpu->env.timer, next); 100cc63a182SAnup Patel } 101cc63a182SAnup Patel 102cc63a182SAnup Patel /* 103cc63a182SAnup Patel * Callback used when the timer set using timer_mod expires. 104cc63a182SAnup Patel * Should raise the timer interrupt line 105cc63a182SAnup Patel */ 106b8fb878aSAnup Patel static void riscv_aclint_mtimer_cb(void *opaque) 107cc63a182SAnup Patel { 108b8fb878aSAnup Patel riscv_aclint_mtimer_callback *state = opaque; 109cc63a182SAnup Patel 110cc63a182SAnup Patel qemu_irq_raise(state->s->timer_irqs[state->num]); 111cc63a182SAnup Patel } 112cc63a182SAnup Patel 113b8fb878aSAnup Patel /* CPU read MTIMER register */ 114b8fb878aSAnup Patel static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, 115b8fb878aSAnup Patel unsigned size) 116cc63a182SAnup Patel { 117b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 118b8fb878aSAnup Patel 119b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 120b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 121b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 122b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 123cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 124cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 125cc63a182SAnup Patel if (!env) { 126b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 127b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 128cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 129cc63a182SAnup Patel /* timecmp_lo */ 130cc63a182SAnup Patel uint64_t timecmp = env->timecmp; 131cc63a182SAnup Patel return timecmp & 0xFFFFFFFF; 132cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 133cc63a182SAnup Patel /* timecmp_hi */ 134cc63a182SAnup Patel uint64_t timecmp = env->timecmp; 135cc63a182SAnup Patel return (timecmp >> 32) & 0xFFFFFFFF; 136cc63a182SAnup Patel } else { 137b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 138b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 139cc63a182SAnup Patel return 0; 140cc63a182SAnup Patel } 141b8fb878aSAnup Patel } else if (addr == mtimer->time_base) { 142cc63a182SAnup Patel /* time_lo */ 143b8fb878aSAnup Patel return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF; 144b8fb878aSAnup Patel } else if (addr == mtimer->time_base + 4) { 145cc63a182SAnup Patel /* time_hi */ 146b8fb878aSAnup Patel return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; 147cc63a182SAnup Patel } 148cc63a182SAnup Patel 149b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 150b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 151cc63a182SAnup Patel return 0; 152cc63a182SAnup Patel } 153cc63a182SAnup Patel 154b8fb878aSAnup Patel /* CPU write MTIMER register */ 155b8fb878aSAnup Patel static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, 156b8fb878aSAnup Patel uint64_t value, unsigned size) 157cc63a182SAnup Patel { 158b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 159cc63a182SAnup Patel 160b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 161b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 162b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 163b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 164cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 165cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 166cc63a182SAnup Patel if (!env) { 167b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 168b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 169cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 170cc63a182SAnup Patel /* timecmp_lo */ 171cc63a182SAnup Patel uint64_t timecmp_hi = env->timecmp >> 32; 172b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 173b8fb878aSAnup Patel timecmp_hi << 32 | (value & 0xFFFFFFFF), 174b8fb878aSAnup Patel mtimer->timebase_freq); 175cc63a182SAnup Patel return; 176cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 177cc63a182SAnup Patel /* timecmp_hi */ 178cc63a182SAnup Patel uint64_t timecmp_lo = env->timecmp; 179b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 180b8fb878aSAnup Patel value << 32 | (timecmp_lo & 0xFFFFFFFF), 181b8fb878aSAnup Patel mtimer->timebase_freq); 182cc63a182SAnup Patel } else { 183b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 184b8fb878aSAnup Patel "aclint-mtimer: invalid timecmp write: %08x", 185b8fb878aSAnup Patel (uint32_t)addr); 186cc63a182SAnup Patel } 187cc63a182SAnup Patel return; 188b8fb878aSAnup Patel } else if (addr == mtimer->time_base) { 189cc63a182SAnup Patel /* time_lo */ 190b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 191b8fb878aSAnup Patel "aclint-mtimer: time_lo write not implemented"); 192cc63a182SAnup Patel return; 193b8fb878aSAnup Patel } else if (addr == mtimer->time_base + 4) { 194cc63a182SAnup Patel /* time_hi */ 195b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 196b8fb878aSAnup Patel "aclint-mtimer: time_hi write not implemented"); 197cc63a182SAnup Patel return; 198cc63a182SAnup Patel } 199cc63a182SAnup Patel 200b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 201b8fb878aSAnup Patel "aclint-mtimer: invalid write: %08x", (uint32_t)addr); 202cc63a182SAnup Patel } 203cc63a182SAnup Patel 204b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_mtimer_ops = { 205b8fb878aSAnup Patel .read = riscv_aclint_mtimer_read, 206b8fb878aSAnup Patel .write = riscv_aclint_mtimer_write, 207cc63a182SAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 208cc63a182SAnup Patel .valid = { 209cc63a182SAnup Patel .min_access_size = 4, 210cc63a182SAnup Patel .max_access_size = 8 211*231a90c0SFrank Chang }, 212*231a90c0SFrank Chang .impl = { 213*231a90c0SFrank Chang .min_access_size = 4, 214*231a90c0SFrank Chang .max_access_size = 8, 215cc63a182SAnup Patel } 216cc63a182SAnup Patel }; 217cc63a182SAnup Patel 218b8fb878aSAnup Patel static Property riscv_aclint_mtimer_properties[] = { 219b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState, 220b8fb878aSAnup Patel hartid_base, 0), 221b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1), 222b8fb878aSAnup Patel DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState, 223b8fb878aSAnup Patel timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP), 224b8fb878aSAnup Patel DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState, 225b8fb878aSAnup Patel time_base, RISCV_ACLINT_DEFAULT_MTIME), 226b8fb878aSAnup Patel DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState, 227b8fb878aSAnup Patel aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE), 228b8fb878aSAnup Patel DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState, 229b8fb878aSAnup Patel timebase_freq, 0), 230cc63a182SAnup Patel DEFINE_PROP_END_OF_LIST(), 231cc63a182SAnup Patel }; 232cc63a182SAnup Patel 233b8fb878aSAnup Patel static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) 234cc63a182SAnup Patel { 235b8fb878aSAnup Patel RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev); 236b8fb878aSAnup Patel int i; 237b8fb878aSAnup Patel 238b8fb878aSAnup Patel memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops, 239b8fb878aSAnup Patel s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size); 240cc63a182SAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 241cc63a182SAnup Patel 242b21e2380SMarkus Armbruster s->timer_irqs = g_new(qemu_irq, s->num_harts); 243cc63a182SAnup Patel qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); 244cc63a182SAnup Patel 245b8fb878aSAnup Patel /* Claim timer interrupt bits */ 246b8fb878aSAnup Patel for (i = 0; i < s->num_harts; i++) { 247b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); 248b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { 249b8fb878aSAnup Patel error_report("MTIP already claimed"); 250b8fb878aSAnup Patel exit(1); 251b8fb878aSAnup Patel } 252b8fb878aSAnup Patel } 253cc63a182SAnup Patel } 254cc63a182SAnup Patel 255b8fb878aSAnup Patel static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) 256cc63a182SAnup Patel { 257cc63a182SAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 258b8fb878aSAnup Patel dc->realize = riscv_aclint_mtimer_realize; 259b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_mtimer_properties); 260cc63a182SAnup Patel } 261cc63a182SAnup Patel 262b8fb878aSAnup Patel static const TypeInfo riscv_aclint_mtimer_info = { 263b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_MTIMER, 264cc63a182SAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 265b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintMTimerState), 266b8fb878aSAnup Patel .class_init = riscv_aclint_mtimer_class_init, 267cc63a182SAnup Patel }; 268cc63a182SAnup Patel 269cc63a182SAnup Patel /* 270b8fb878aSAnup Patel * Create ACLINT MTIMER device. 271cc63a182SAnup Patel */ 272b8fb878aSAnup Patel DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, 273b8fb878aSAnup Patel uint32_t hartid_base, uint32_t num_harts, 274cc63a182SAnup Patel uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, 275cc63a182SAnup Patel bool provide_rdtime) 276cc63a182SAnup Patel { 277cc63a182SAnup Patel int i; 278b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER); 279cc63a182SAnup Patel 280b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 281b8fb878aSAnup Patel assert(!(addr & 0x7)); 282b8fb878aSAnup Patel assert(!(timecmp_base & 0x7)); 283b8fb878aSAnup Patel assert(!(time_base & 0x7)); 284b8fb878aSAnup Patel 285cc63a182SAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 286cc63a182SAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 287cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); 288cc63a182SAnup Patel qdev_prop_set_uint32(dev, "time-base", time_base); 289cc63a182SAnup Patel qdev_prop_set_uint32(dev, "aperture-size", size); 290cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); 291cc63a182SAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 292cc63a182SAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 293cc63a182SAnup Patel 294cc63a182SAnup Patel for (i = 0; i < num_harts; i++) { 295cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 296cc63a182SAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 297cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 298b8fb878aSAnup Patel riscv_aclint_mtimer_callback *cb = 299b21e2380SMarkus Armbruster g_new0(riscv_aclint_mtimer_callback, 1); 300cc63a182SAnup Patel 301cc63a182SAnup Patel if (!env) { 302cc63a182SAnup Patel g_free(cb); 303cc63a182SAnup Patel continue; 304cc63a182SAnup Patel } 305cc63a182SAnup Patel if (provide_rdtime) { 306cc63a182SAnup Patel riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); 307cc63a182SAnup Patel } 308cc63a182SAnup Patel 309b8fb878aSAnup Patel cb->s = RISCV_ACLINT_MTIMER(dev); 310cc63a182SAnup Patel cb->num = i; 311cc63a182SAnup Patel env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 312b8fb878aSAnup Patel &riscv_aclint_mtimer_cb, cb); 313cc63a182SAnup Patel env->timecmp = 0; 314cc63a182SAnup Patel 315cc63a182SAnup Patel qdev_connect_gpio_out(dev, i, 316cc63a182SAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)); 317cc63a182SAnup Patel } 318cc63a182SAnup Patel 319cc63a182SAnup Patel return dev; 320cc63a182SAnup Patel } 321b8fb878aSAnup Patel 322b8fb878aSAnup Patel /* CPU read [M|S]SWI register */ 323b8fb878aSAnup Patel static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr, 324b8fb878aSAnup Patel unsigned size) 325b8fb878aSAnup Patel { 326b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 327b8fb878aSAnup Patel 328b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 329b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 330b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 331b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 332b8fb878aSAnup Patel if (!env) { 333b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 334b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 335b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 336b8fb878aSAnup Patel return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); 337b8fb878aSAnup Patel } 338b8fb878aSAnup Patel } 339b8fb878aSAnup Patel 340b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 341b8fb878aSAnup Patel "aclint-swi: invalid read: %08x", (uint32_t)addr); 342b8fb878aSAnup Patel return 0; 343b8fb878aSAnup Patel } 344b8fb878aSAnup Patel 345b8fb878aSAnup Patel /* CPU write [M|S]SWI register */ 346b8fb878aSAnup Patel static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value, 347b8fb878aSAnup Patel unsigned size) 348b8fb878aSAnup Patel { 349b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 350b8fb878aSAnup Patel 351b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 352b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 353b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 354b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 355b8fb878aSAnup Patel if (!env) { 356b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 357b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 358b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 359b8fb878aSAnup Patel if (value & 0x1) { 360b8fb878aSAnup Patel qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]); 361b8fb878aSAnup Patel } else { 362b8fb878aSAnup Patel if (!swi->sswi) { 363b8fb878aSAnup Patel qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]); 364b8fb878aSAnup Patel } 365b8fb878aSAnup Patel } 366b8fb878aSAnup Patel return; 367b8fb878aSAnup Patel } 368b8fb878aSAnup Patel } 369b8fb878aSAnup Patel 370b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 371b8fb878aSAnup Patel "aclint-swi: invalid write: %08x", (uint32_t)addr); 372b8fb878aSAnup Patel } 373b8fb878aSAnup Patel 374b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_swi_ops = { 375b8fb878aSAnup Patel .read = riscv_aclint_swi_read, 376b8fb878aSAnup Patel .write = riscv_aclint_swi_write, 377b8fb878aSAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 378b8fb878aSAnup Patel .valid = { 379b8fb878aSAnup Patel .min_access_size = 4, 380b8fb878aSAnup Patel .max_access_size = 4 381b8fb878aSAnup Patel } 382b8fb878aSAnup Patel }; 383b8fb878aSAnup Patel 384b8fb878aSAnup Patel static Property riscv_aclint_swi_properties[] = { 385b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0), 386b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1), 387b8fb878aSAnup Patel DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false), 388b8fb878aSAnup Patel DEFINE_PROP_END_OF_LIST(), 389b8fb878aSAnup Patel }; 390b8fb878aSAnup Patel 391b8fb878aSAnup Patel static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) 392b8fb878aSAnup Patel { 393b8fb878aSAnup Patel RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev); 394b8fb878aSAnup Patel int i; 395b8fb878aSAnup Patel 396b8fb878aSAnup Patel memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi, 397b8fb878aSAnup Patel TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE); 398b8fb878aSAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio); 399b8fb878aSAnup Patel 400b21e2380SMarkus Armbruster swi->soft_irqs = g_new(qemu_irq, swi->num_harts); 401b8fb878aSAnup Patel qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts); 402b8fb878aSAnup Patel 403b8fb878aSAnup Patel /* Claim software interrupt bits */ 404b8fb878aSAnup Patel for (i = 0; i < swi->num_harts; i++) { 405b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); 406b8fb878aSAnup Patel /* We don't claim mip.SSIP because it is writeable by software */ 407b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) { 408b8fb878aSAnup Patel error_report("MSIP already claimed"); 409b8fb878aSAnup Patel exit(1); 410b8fb878aSAnup Patel } 411b8fb878aSAnup Patel } 412b8fb878aSAnup Patel } 413b8fb878aSAnup Patel 414b8fb878aSAnup Patel static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) 415b8fb878aSAnup Patel { 416b8fb878aSAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 417b8fb878aSAnup Patel dc->realize = riscv_aclint_swi_realize; 418b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_swi_properties); 419b8fb878aSAnup Patel } 420b8fb878aSAnup Patel 421b8fb878aSAnup Patel static const TypeInfo riscv_aclint_swi_info = { 422b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_SWI, 423b8fb878aSAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 424b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintSwiState), 425b8fb878aSAnup Patel .class_init = riscv_aclint_swi_class_init, 426b8fb878aSAnup Patel }; 427b8fb878aSAnup Patel 428b8fb878aSAnup Patel /* 429b8fb878aSAnup Patel * Create ACLINT [M|S]SWI device. 430b8fb878aSAnup Patel */ 431b8fb878aSAnup Patel DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, 432b8fb878aSAnup Patel uint32_t num_harts, bool sswi) 433b8fb878aSAnup Patel { 434b8fb878aSAnup Patel int i; 435b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI); 436b8fb878aSAnup Patel 437b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 438b8fb878aSAnup Patel assert(!(addr & 0x3)); 439b8fb878aSAnup Patel 440b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 441b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 442b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); 443b8fb878aSAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 444b8fb878aSAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 445b8fb878aSAnup Patel 446b8fb878aSAnup Patel for (i = 0; i < num_harts; i++) { 447b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 448b8fb878aSAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 449b8fb878aSAnup Patel 450b8fb878aSAnup Patel qdev_connect_gpio_out(dev, i, 451b8fb878aSAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), 452b8fb878aSAnup Patel (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT)); 453b8fb878aSAnup Patel } 454b8fb878aSAnup Patel 455b8fb878aSAnup Patel return dev; 456b8fb878aSAnup Patel } 457b8fb878aSAnup Patel 458b8fb878aSAnup Patel static void riscv_aclint_register_types(void) 459b8fb878aSAnup Patel { 460b8fb878aSAnup Patel type_register_static(&riscv_aclint_mtimer_info); 461b8fb878aSAnup Patel type_register_static(&riscv_aclint_swi_info); 462b8fb878aSAnup Patel } 463b8fb878aSAnup Patel 464b8fb878aSAnup Patel type_init(riscv_aclint_register_types) 465