1cc63a182SAnup Patel /* 2b8fb878aSAnup Patel * RISC-V ACLINT (Advanced Core Local Interruptor) 3b8fb878aSAnup Patel * URL: https://github.com/riscv/riscv-aclint 4cc63a182SAnup Patel * 5cc63a182SAnup Patel * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 6cc63a182SAnup Patel * Copyright (c) 2017 SiFive, Inc. 7b8fb878aSAnup Patel * Copyright (c) 2021 Western Digital Corporation or its affiliates. 8cc63a182SAnup Patel * 9cc63a182SAnup Patel * This provides real-time clock, timer and interprocessor interrupts. 10cc63a182SAnup Patel * 11cc63a182SAnup Patel * This program is free software; you can redistribute it and/or modify it 12cc63a182SAnup Patel * under the terms and conditions of the GNU General Public License, 13cc63a182SAnup Patel * version 2 or later, as published by the Free Software Foundation. 14cc63a182SAnup Patel * 15cc63a182SAnup Patel * This program is distributed in the hope it will be useful, but WITHOUT 16cc63a182SAnup Patel * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17cc63a182SAnup Patel * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18cc63a182SAnup Patel * more details. 19cc63a182SAnup Patel * 20cc63a182SAnup Patel * You should have received a copy of the GNU General Public License along with 21cc63a182SAnup Patel * this program. If not, see <http://www.gnu.org/licenses/>. 22cc63a182SAnup Patel */ 23cc63a182SAnup Patel 24cc63a182SAnup Patel #include "qemu/osdep.h" 25cc63a182SAnup Patel #include "qapi/error.h" 26cc63a182SAnup Patel #include "qemu/error-report.h" 27b8fb878aSAnup Patel #include "qemu/log.h" 28cc63a182SAnup Patel #include "qemu/module.h" 29cc63a182SAnup Patel #include "hw/sysbus.h" 30cc63a182SAnup Patel #include "target/riscv/cpu.h" 31cc63a182SAnup Patel #include "hw/qdev-properties.h" 32cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h" 33cc63a182SAnup Patel #include "qemu/timer.h" 34cc63a182SAnup Patel #include "hw/irq.h" 357cbcc538SAtish Patra #include "migration/vmstate.h" 36cc63a182SAnup Patel 37b8fb878aSAnup Patel typedef struct riscv_aclint_mtimer_callback { 38b8fb878aSAnup Patel RISCVAclintMTimerState *s; 39cc63a182SAnup Patel int num; 40b8fb878aSAnup Patel } riscv_aclint_mtimer_callback; 41cc63a182SAnup Patel 42e2f01f3cSFrank Chang static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) 43cc63a182SAnup Patel { 44cc63a182SAnup Patel return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 45cc63a182SAnup Patel timebase_freq, NANOSECONDS_PER_SECOND); 46cc63a182SAnup Patel } 47cc63a182SAnup Patel 48e2f01f3cSFrank Chang static uint64_t cpu_riscv_read_rtc(void *opaque) 49e2f01f3cSFrank Chang { 50e2f01f3cSFrank Chang RISCVAclintMTimerState *mtimer = opaque; 51e2f01f3cSFrank Chang return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; 52e2f01f3cSFrank Chang } 53e2f01f3cSFrank Chang 54cc63a182SAnup Patel /* 55cc63a182SAnup Patel * Called when timecmp is written to update the QEMU timer or immediately 56cc63a182SAnup Patel * trigger timer interrupt if mtimecmp <= current timer value. 57cc63a182SAnup Patel */ 58b8fb878aSAnup Patel static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, 59b8fb878aSAnup Patel RISCVCPU *cpu, 60cc63a182SAnup Patel int hartid, 61e2f01f3cSFrank Chang uint64_t value) 62cc63a182SAnup Patel { 63e2f01f3cSFrank Chang uint32_t timebase_freq = mtimer->timebase_freq; 64cc63a182SAnup Patel uint64_t next; 65cc63a182SAnup Patel uint64_t diff; 66cc63a182SAnup Patel 67e2f01f3cSFrank Chang uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); 68cc63a182SAnup Patel 697cbcc538SAtish Patra /* Compute the relative hartid w.r.t the socket */ 707cbcc538SAtish Patra hartid = hartid - mtimer->hartid_base; 717cbcc538SAtish Patra 727cbcc538SAtish Patra mtimer->timecmp[hartid] = value; 737cbcc538SAtish Patra if (mtimer->timecmp[hartid] <= rtc_r) { 74b8fb878aSAnup Patel /* 75b8fb878aSAnup Patel * If we're setting an MTIMECMP value in the "past", 76b8fb878aSAnup Patel * immediately raise the timer interrupt 77b8fb878aSAnup Patel */ 787cbcc538SAtish Patra qemu_irq_raise(mtimer->timer_irqs[hartid]); 79cc63a182SAnup Patel return; 80cc63a182SAnup Patel } 81cc63a182SAnup Patel 82cc63a182SAnup Patel /* otherwise, set up the future timer interrupt */ 837cbcc538SAtish Patra qemu_irq_lower(mtimer->timer_irqs[hartid]); 847cbcc538SAtish Patra diff = mtimer->timecmp[hartid] - rtc_r; 85cc63a182SAnup Patel /* back to ns (note args switched in muldiv64) */ 86cc63a182SAnup Patel uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); 87cc63a182SAnup Patel 88cc63a182SAnup Patel /* 89cc63a182SAnup Patel * check if ns_diff overflowed and check if the addition would potentially 90cc63a182SAnup Patel * overflow 91cc63a182SAnup Patel */ 92cc63a182SAnup Patel if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || 93cc63a182SAnup Patel ns_diff > INT64_MAX) { 94cc63a182SAnup Patel next = INT64_MAX; 95cc63a182SAnup Patel } else { 96cc63a182SAnup Patel /* 97cc63a182SAnup Patel * as it is very unlikely qemu_clock_get_ns will return a value 98cc63a182SAnup Patel * greater than INT64_MAX, no additional check is needed for an 99cc63a182SAnup Patel * unsigned integer overflow. 100cc63a182SAnup Patel */ 101cc63a182SAnup Patel next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; 102cc63a182SAnup Patel /* 103cc63a182SAnup Patel * if ns_diff is INT64_MAX next may still be outside the range 104cc63a182SAnup Patel * of a signed integer. 105cc63a182SAnup Patel */ 106cc63a182SAnup Patel next = MIN(next, INT64_MAX); 107cc63a182SAnup Patel } 108cc63a182SAnup Patel 1097cbcc538SAtish Patra timer_mod(mtimer->timers[hartid], next); 110cc63a182SAnup Patel } 111cc63a182SAnup Patel 112cc63a182SAnup Patel /* 113cc63a182SAnup Patel * Callback used when the timer set using timer_mod expires. 114cc63a182SAnup Patel * Should raise the timer interrupt line 115cc63a182SAnup Patel */ 116b8fb878aSAnup Patel static void riscv_aclint_mtimer_cb(void *opaque) 117cc63a182SAnup Patel { 118b8fb878aSAnup Patel riscv_aclint_mtimer_callback *state = opaque; 119cc63a182SAnup Patel 120cc63a182SAnup Patel qemu_irq_raise(state->s->timer_irqs[state->num]); 121cc63a182SAnup Patel } 122cc63a182SAnup Patel 123b8fb878aSAnup Patel /* CPU read MTIMER register */ 124b8fb878aSAnup Patel static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, 125b8fb878aSAnup Patel unsigned size) 126cc63a182SAnup Patel { 127b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 128b8fb878aSAnup Patel 129b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 130b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 131b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 132b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 133cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 134cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 135cc63a182SAnup Patel if (!env) { 136b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 137b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 138cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 139d42df0eaSFrank Chang /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ 1407cbcc538SAtish Patra uint64_t timecmp = mtimer->timecmp[hartid]; 141d42df0eaSFrank Chang return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp; 142cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 143cc63a182SAnup Patel /* timecmp_hi */ 1447cbcc538SAtish Patra uint64_t timecmp = mtimer->timecmp[hartid]; 145cc63a182SAnup Patel return (timecmp >> 32) & 0xFFFFFFFF; 146cc63a182SAnup Patel } else { 147b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 148b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 149cc63a182SAnup Patel return 0; 150cc63a182SAnup Patel } 151b8fb878aSAnup Patel } else if (addr == mtimer->time_base) { 152d42df0eaSFrank Chang /* time_lo for RV32/RV64 or timecmp for RV64 */ 153e2f01f3cSFrank Chang uint64_t rtc = cpu_riscv_read_rtc(mtimer); 154d42df0eaSFrank Chang return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; 155b8fb878aSAnup Patel } else if (addr == mtimer->time_base + 4) { 156cc63a182SAnup Patel /* time_hi */ 157e2f01f3cSFrank Chang return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; 158cc63a182SAnup Patel } 159cc63a182SAnup Patel 160b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 161b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 162cc63a182SAnup Patel return 0; 163cc63a182SAnup Patel } 164cc63a182SAnup Patel 165b8fb878aSAnup Patel /* CPU write MTIMER register */ 166b8fb878aSAnup Patel static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, 167b8fb878aSAnup Patel uint64_t value, unsigned size) 168cc63a182SAnup Patel { 169b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 170e2f01f3cSFrank Chang int i; 171cc63a182SAnup Patel 172b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 173b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 174b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 175b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 176cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 177cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 178cc63a182SAnup Patel if (!env) { 179b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 180b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 181cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 182d42df0eaSFrank Chang if (size == 4) { 183d42df0eaSFrank Chang /* timecmp_lo for RV32/RV64 */ 1847cbcc538SAtish Patra uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32; 185b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 186e2f01f3cSFrank Chang timecmp_hi << 32 | (value & 0xFFFFFFFF)); 187d42df0eaSFrank Chang } else { 188d42df0eaSFrank Chang /* timecmp for RV64 */ 189d42df0eaSFrank Chang riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 190e2f01f3cSFrank Chang value); 191d42df0eaSFrank Chang } 192cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 193d42df0eaSFrank Chang if (size == 4) { 194d42df0eaSFrank Chang /* timecmp_hi for RV32/RV64 */ 1957cbcc538SAtish Patra uint64_t timecmp_lo = mtimer->timecmp[hartid]; 196b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 197e2f01f3cSFrank Chang value << 32 | (timecmp_lo & 0xFFFFFFFF)); 198cc63a182SAnup Patel } else { 199d42df0eaSFrank Chang qemu_log_mask(LOG_GUEST_ERROR, 200d42df0eaSFrank Chang "aclint-mtimer: invalid timecmp_hi write: %08x", 201d42df0eaSFrank Chang (uint32_t)addr); 202d42df0eaSFrank Chang } 203d42df0eaSFrank Chang } else { 204b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 205b8fb878aSAnup Patel "aclint-mtimer: invalid timecmp write: %08x", 206b8fb878aSAnup Patel (uint32_t)addr); 207cc63a182SAnup Patel } 208cc63a182SAnup Patel return; 209e2f01f3cSFrank Chang } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { 210e2f01f3cSFrank Chang uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); 211e2f01f3cSFrank Chang 212e2f01f3cSFrank Chang if (addr == mtimer->time_base) { 213e2f01f3cSFrank Chang if (size == 4) { 214e2f01f3cSFrank Chang /* time_lo for RV32/RV64 */ 215e2f01f3cSFrank Chang mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; 216e2f01f3cSFrank Chang } else { 217e2f01f3cSFrank Chang /* time for RV64 */ 218e2f01f3cSFrank Chang mtimer->time_delta = value - rtc_r; 219e2f01f3cSFrank Chang } 220e2f01f3cSFrank Chang } else { 221e2f01f3cSFrank Chang if (size == 4) { 222e2f01f3cSFrank Chang /* time_hi for RV32/RV64 */ 223e2f01f3cSFrank Chang mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; 224e2f01f3cSFrank Chang } else { 225e2f01f3cSFrank Chang qemu_log_mask(LOG_GUEST_ERROR, 226e2f01f3cSFrank Chang "aclint-mtimer: invalid time_hi write: %08x", 227e2f01f3cSFrank Chang (uint32_t)addr); 228cc63a182SAnup Patel return; 229e2f01f3cSFrank Chang } 230e2f01f3cSFrank Chang } 231e2f01f3cSFrank Chang 232e2f01f3cSFrank Chang /* Check if timer interrupt is triggered for each hart. */ 233e2f01f3cSFrank Chang for (i = 0; i < mtimer->num_harts; i++) { 234e2f01f3cSFrank Chang CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); 235e2f01f3cSFrank Chang CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 236e2f01f3cSFrank Chang if (!env) { 237e2f01f3cSFrank Chang continue; 238e2f01f3cSFrank Chang } 239e2f01f3cSFrank Chang riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), 24077046729SAtish Patra mtimer->hartid_base + i, 2417cbcc538SAtish Patra mtimer->timecmp[i]); 242e2f01f3cSFrank Chang } 243cc63a182SAnup Patel return; 244cc63a182SAnup Patel } 245cc63a182SAnup Patel 246b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 247b8fb878aSAnup Patel "aclint-mtimer: invalid write: %08x", (uint32_t)addr); 248cc63a182SAnup Patel } 249cc63a182SAnup Patel 250b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_mtimer_ops = { 251b8fb878aSAnup Patel .read = riscv_aclint_mtimer_read, 252b8fb878aSAnup Patel .write = riscv_aclint_mtimer_write, 253cc63a182SAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 254cc63a182SAnup Patel .valid = { 255cc63a182SAnup Patel .min_access_size = 4, 256cc63a182SAnup Patel .max_access_size = 8 257231a90c0SFrank Chang }, 258231a90c0SFrank Chang .impl = { 259231a90c0SFrank Chang .min_access_size = 4, 260231a90c0SFrank Chang .max_access_size = 8, 261cc63a182SAnup Patel } 262cc63a182SAnup Patel }; 263cc63a182SAnup Patel 264b8fb878aSAnup Patel static Property riscv_aclint_mtimer_properties[] = { 265b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState, 266b8fb878aSAnup Patel hartid_base, 0), 267b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1), 268b8fb878aSAnup Patel DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState, 269b8fb878aSAnup Patel timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP), 270b8fb878aSAnup Patel DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState, 271b8fb878aSAnup Patel time_base, RISCV_ACLINT_DEFAULT_MTIME), 272b8fb878aSAnup Patel DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState, 273b8fb878aSAnup Patel aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE), 274b8fb878aSAnup Patel DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState, 275b8fb878aSAnup Patel timebase_freq, 0), 276cc63a182SAnup Patel DEFINE_PROP_END_OF_LIST(), 277cc63a182SAnup Patel }; 278cc63a182SAnup Patel 279b8fb878aSAnup Patel static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) 280cc63a182SAnup Patel { 281b8fb878aSAnup Patel RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev); 282b8fb878aSAnup Patel int i; 283b8fb878aSAnup Patel 284b8fb878aSAnup Patel memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops, 285b8fb878aSAnup Patel s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size); 286cc63a182SAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 287cc63a182SAnup Patel 288b21e2380SMarkus Armbruster s->timer_irqs = g_new(qemu_irq, s->num_harts); 289cc63a182SAnup Patel qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); 290cc63a182SAnup Patel 2917cbcc538SAtish Patra s->timers = g_new0(QEMUTimer *, s->num_harts); 2927cbcc538SAtish Patra s->timecmp = g_new0(uint64_t, s->num_harts); 293b8fb878aSAnup Patel /* Claim timer interrupt bits */ 294b8fb878aSAnup Patel for (i = 0; i < s->num_harts; i++) { 295b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); 296b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { 297b8fb878aSAnup Patel error_report("MTIP already claimed"); 298b8fb878aSAnup Patel exit(1); 299b8fb878aSAnup Patel } 300b8fb878aSAnup Patel } 301cc63a182SAnup Patel } 302cc63a182SAnup Patel 3038124f819SJim Shu static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) 3048124f819SJim Shu { 3058124f819SJim Shu /* 3068124f819SJim Shu * According to RISC-V ACLINT spec: 3078124f819SJim Shu * - On MTIMER device reset, the MTIME register is cleared to zero. 3088124f819SJim Shu * - On MTIMER device reset, the MTIMECMP registers are in unknown state. 3098124f819SJim Shu */ 3108124f819SJim Shu RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); 3118124f819SJim Shu 3128124f819SJim Shu /* 3138124f819SJim Shu * Clear mtime register by writing to 0 it. 3148124f819SJim Shu * Pending mtime interrupts will also be cleared at the same time. 3158124f819SJim Shu */ 3168124f819SJim Shu riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); 3178124f819SJim Shu } 3188124f819SJim Shu 3197cbcc538SAtish Patra static const VMStateDescription vmstate_riscv_mtimer = { 3207cbcc538SAtish Patra .name = "riscv_mtimer", 3217cbcc538SAtish Patra .version_id = 1, 3227cbcc538SAtish Patra .minimum_version_id = 1, 3237cbcc538SAtish Patra .fields = (VMStateField[]) { 3247cbcc538SAtish Patra VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState, 3257cbcc538SAtish Patra num_harts, 0, 3267cbcc538SAtish Patra vmstate_info_uint64, uint64_t), 3277cbcc538SAtish Patra VMSTATE_END_OF_LIST() 3287cbcc538SAtish Patra } 3297cbcc538SAtish Patra }; 3307cbcc538SAtish Patra 331b8fb878aSAnup Patel static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) 332cc63a182SAnup Patel { 333cc63a182SAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 334b8fb878aSAnup Patel dc->realize = riscv_aclint_mtimer_realize; 335b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_mtimer_properties); 3368124f819SJim Shu ResettableClass *rc = RESETTABLE_CLASS(klass); 3378124f819SJim Shu rc->phases.enter = riscv_aclint_mtimer_reset_enter; 3387cbcc538SAtish Patra dc->vmsd = &vmstate_riscv_mtimer; 339cc63a182SAnup Patel } 340cc63a182SAnup Patel 341b8fb878aSAnup Patel static const TypeInfo riscv_aclint_mtimer_info = { 342b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_MTIMER, 343cc63a182SAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 344b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintMTimerState), 345b8fb878aSAnup Patel .class_init = riscv_aclint_mtimer_class_init, 346cc63a182SAnup Patel }; 347cc63a182SAnup Patel 348cc63a182SAnup Patel /* 349b8fb878aSAnup Patel * Create ACLINT MTIMER device. 350cc63a182SAnup Patel */ 351b8fb878aSAnup Patel DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, 352b8fb878aSAnup Patel uint32_t hartid_base, uint32_t num_harts, 353cc63a182SAnup Patel uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, 354cc63a182SAnup Patel bool provide_rdtime) 355cc63a182SAnup Patel { 356cc63a182SAnup Patel int i; 357b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER); 3587cbcc538SAtish Patra RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev); 359cc63a182SAnup Patel 360b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 361b8fb878aSAnup Patel assert(!(addr & 0x7)); 362b8fb878aSAnup Patel assert(!(timecmp_base & 0x7)); 363b8fb878aSAnup Patel assert(!(time_base & 0x7)); 364b8fb878aSAnup Patel 365cc63a182SAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 366cc63a182SAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 367cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); 368cc63a182SAnup Patel qdev_prop_set_uint32(dev, "time-base", time_base); 369cc63a182SAnup Patel qdev_prop_set_uint32(dev, "aperture-size", size); 370cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); 371cc63a182SAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 372cc63a182SAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 373cc63a182SAnup Patel 374cc63a182SAnup Patel for (i = 0; i < num_harts; i++) { 375cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 376cc63a182SAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 377cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 378b8fb878aSAnup Patel riscv_aclint_mtimer_callback *cb = 379b21e2380SMarkus Armbruster g_new0(riscv_aclint_mtimer_callback, 1); 380cc63a182SAnup Patel 381cc63a182SAnup Patel if (!env) { 382cc63a182SAnup Patel g_free(cb); 383cc63a182SAnup Patel continue; 384cc63a182SAnup Patel } 385cc63a182SAnup Patel if (provide_rdtime) { 386e2f01f3cSFrank Chang riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); 387cc63a182SAnup Patel } 388cc63a182SAnup Patel 3897cbcc538SAtish Patra cb->s = s; 390cc63a182SAnup Patel cb->num = i; 3917cbcc538SAtish Patra s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, 392b8fb878aSAnup Patel &riscv_aclint_mtimer_cb, cb); 3937cbcc538SAtish Patra s->timecmp[i] = 0; 394cc63a182SAnup Patel 395cc63a182SAnup Patel qdev_connect_gpio_out(dev, i, 396cc63a182SAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)); 397cc63a182SAnup Patel } 398cc63a182SAnup Patel 399cc63a182SAnup Patel return dev; 400cc63a182SAnup Patel } 401b8fb878aSAnup Patel 402b8fb878aSAnup Patel /* CPU read [M|S]SWI register */ 403b8fb878aSAnup Patel static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr, 404b8fb878aSAnup Patel unsigned size) 405b8fb878aSAnup Patel { 406b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 407b8fb878aSAnup Patel 408b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 409b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 410b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 411b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 412b8fb878aSAnup Patel if (!env) { 413b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 414b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 415b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 416b8fb878aSAnup Patel return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); 417b8fb878aSAnup Patel } 418b8fb878aSAnup Patel } 419b8fb878aSAnup Patel 420b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 421b8fb878aSAnup Patel "aclint-swi: invalid read: %08x", (uint32_t)addr); 422b8fb878aSAnup Patel return 0; 423b8fb878aSAnup Patel } 424b8fb878aSAnup Patel 425b8fb878aSAnup Patel /* CPU write [M|S]SWI register */ 426b8fb878aSAnup Patel static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value, 427b8fb878aSAnup Patel unsigned size) 428b8fb878aSAnup Patel { 429b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 430b8fb878aSAnup Patel 431b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 432b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 433b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 434b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 435b8fb878aSAnup Patel if (!env) { 436b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 437b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 438b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 439b8fb878aSAnup Patel if (value & 0x1) { 440b8fb878aSAnup Patel qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]); 441b8fb878aSAnup Patel } else { 442b8fb878aSAnup Patel if (!swi->sswi) { 443b8fb878aSAnup Patel qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]); 444b8fb878aSAnup Patel } 445b8fb878aSAnup Patel } 446b8fb878aSAnup Patel return; 447b8fb878aSAnup Patel } 448b8fb878aSAnup Patel } 449b8fb878aSAnup Patel 450b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 451b8fb878aSAnup Patel "aclint-swi: invalid write: %08x", (uint32_t)addr); 452b8fb878aSAnup Patel } 453b8fb878aSAnup Patel 454b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_swi_ops = { 455b8fb878aSAnup Patel .read = riscv_aclint_swi_read, 456b8fb878aSAnup Patel .write = riscv_aclint_swi_write, 457b8fb878aSAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 458b8fb878aSAnup Patel .valid = { 459b8fb878aSAnup Patel .min_access_size = 4, 460b8fb878aSAnup Patel .max_access_size = 4 461b8fb878aSAnup Patel } 462b8fb878aSAnup Patel }; 463b8fb878aSAnup Patel 464b8fb878aSAnup Patel static Property riscv_aclint_swi_properties[] = { 465b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0), 466b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1), 467b8fb878aSAnup Patel DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false), 468b8fb878aSAnup Patel DEFINE_PROP_END_OF_LIST(), 469b8fb878aSAnup Patel }; 470b8fb878aSAnup Patel 471b8fb878aSAnup Patel static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) 472b8fb878aSAnup Patel { 473b8fb878aSAnup Patel RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev); 474b8fb878aSAnup Patel int i; 475b8fb878aSAnup Patel 476b8fb878aSAnup Patel memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi, 477b8fb878aSAnup Patel TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE); 478b8fb878aSAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio); 479b8fb878aSAnup Patel 480b21e2380SMarkus Armbruster swi->soft_irqs = g_new(qemu_irq, swi->num_harts); 481b8fb878aSAnup Patel qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts); 482b8fb878aSAnup Patel 483b8fb878aSAnup Patel /* Claim software interrupt bits */ 484b8fb878aSAnup Patel for (i = 0; i < swi->num_harts; i++) { 485b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); 4869323e79fSPeter Maydell /* We don't claim mip.SSIP because it is writable by software */ 487b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) { 488b8fb878aSAnup Patel error_report("MSIP already claimed"); 489b8fb878aSAnup Patel exit(1); 490b8fb878aSAnup Patel } 491b8fb878aSAnup Patel } 492b8fb878aSAnup Patel } 493b8fb878aSAnup Patel 4948124f819SJim Shu static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) 4958124f819SJim Shu { 4968124f819SJim Shu /* 4978124f819SJim Shu * According to RISC-V ACLINT spec: 4988124f819SJim Shu * - On MSWI device reset, each MSIP register is cleared to zero. 4998124f819SJim Shu * 5008124f819SJim Shu * p.s. SSWI device reset does nothing since SETSIP register always reads 0. 5018124f819SJim Shu */ 5028124f819SJim Shu RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); 5038124f819SJim Shu int i; 5048124f819SJim Shu 5058124f819SJim Shu if (!swi->sswi) { 5068124f819SJim Shu for (i = 0; i < swi->num_harts; i++) { 5078124f819SJim Shu /* Clear MSIP registers by lowering software interrupts. */ 5088124f819SJim Shu qemu_irq_lower(swi->soft_irqs[i]); 5098124f819SJim Shu } 5108124f819SJim Shu } 5118124f819SJim Shu } 5128124f819SJim Shu 513b8fb878aSAnup Patel static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) 514b8fb878aSAnup Patel { 515b8fb878aSAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 516b8fb878aSAnup Patel dc->realize = riscv_aclint_swi_realize; 517b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_swi_properties); 5188124f819SJim Shu ResettableClass *rc = RESETTABLE_CLASS(klass); 5198124f819SJim Shu rc->phases.enter = riscv_aclint_swi_reset_enter; 520b8fb878aSAnup Patel } 521b8fb878aSAnup Patel 522b8fb878aSAnup Patel static const TypeInfo riscv_aclint_swi_info = { 523b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_SWI, 524b8fb878aSAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 525b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintSwiState), 526b8fb878aSAnup Patel .class_init = riscv_aclint_swi_class_init, 527b8fb878aSAnup Patel }; 528b8fb878aSAnup Patel 529b8fb878aSAnup Patel /* 530b8fb878aSAnup Patel * Create ACLINT [M|S]SWI device. 531b8fb878aSAnup Patel */ 532b8fb878aSAnup Patel DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, 533b8fb878aSAnup Patel uint32_t num_harts, bool sswi) 534b8fb878aSAnup Patel { 535b8fb878aSAnup Patel int i; 536b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI); 537b8fb878aSAnup Patel 538b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 539b8fb878aSAnup Patel assert(!(addr & 0x3)); 540b8fb878aSAnup Patel 541b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 542b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 543b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); 544b8fb878aSAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 545b8fb878aSAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 546b8fb878aSAnup Patel 547b8fb878aSAnup Patel for (i = 0; i < num_harts; i++) { 548b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 549b8fb878aSAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 550b8fb878aSAnup Patel 551b8fb878aSAnup Patel qdev_connect_gpio_out(dev, i, 552b8fb878aSAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), 553b8fb878aSAnup Patel (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT)); 554b8fb878aSAnup Patel } 555b8fb878aSAnup Patel 556b8fb878aSAnup Patel return dev; 557b8fb878aSAnup Patel } 558b8fb878aSAnup Patel 559b8fb878aSAnup Patel static void riscv_aclint_register_types(void) 560b8fb878aSAnup Patel { 561b8fb878aSAnup Patel type_register_static(&riscv_aclint_mtimer_info); 562b8fb878aSAnup Patel type_register_static(&riscv_aclint_swi_info); 563b8fb878aSAnup Patel } 564b8fb878aSAnup Patel 565b8fb878aSAnup Patel type_init(riscv_aclint_register_types) 566