1cc63a182SAnup Patel /* 2b8fb878aSAnup Patel * RISC-V ACLINT (Advanced Core Local Interruptor) 3b8fb878aSAnup Patel * URL: https://github.com/riscv/riscv-aclint 4cc63a182SAnup Patel * 5cc63a182SAnup Patel * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 6cc63a182SAnup Patel * Copyright (c) 2017 SiFive, Inc. 7b8fb878aSAnup Patel * Copyright (c) 2021 Western Digital Corporation or its affiliates. 8cc63a182SAnup Patel * 9cc63a182SAnup Patel * This provides real-time clock, timer and interprocessor interrupts. 10cc63a182SAnup Patel * 11cc63a182SAnup Patel * This program is free software; you can redistribute it and/or modify it 12cc63a182SAnup Patel * under the terms and conditions of the GNU General Public License, 13cc63a182SAnup Patel * version 2 or later, as published by the Free Software Foundation. 14cc63a182SAnup Patel * 15cc63a182SAnup Patel * This program is distributed in the hope it will be useful, but WITHOUT 16cc63a182SAnup Patel * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17cc63a182SAnup Patel * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18cc63a182SAnup Patel * more details. 19cc63a182SAnup Patel * 20cc63a182SAnup Patel * You should have received a copy of the GNU General Public License along with 21cc63a182SAnup Patel * this program. If not, see <http://www.gnu.org/licenses/>. 22cc63a182SAnup Patel */ 23cc63a182SAnup Patel 24cc63a182SAnup Patel #include "qemu/osdep.h" 25cc63a182SAnup Patel #include "qapi/error.h" 26cc63a182SAnup Patel #include "qemu/error-report.h" 27b8fb878aSAnup Patel #include "qemu/log.h" 28cc63a182SAnup Patel #include "qemu/module.h" 29cc63a182SAnup Patel #include "hw/sysbus.h" 30cc63a182SAnup Patel #include "target/riscv/cpu.h" 31cc63a182SAnup Patel #include "hw/qdev-properties.h" 32cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h" 33cc63a182SAnup Patel #include "qemu/timer.h" 34cc63a182SAnup Patel #include "hw/irq.h" 35cc63a182SAnup Patel 36b8fb878aSAnup Patel typedef struct riscv_aclint_mtimer_callback { 37b8fb878aSAnup Patel RISCVAclintMTimerState *s; 38cc63a182SAnup Patel int num; 39b8fb878aSAnup Patel } riscv_aclint_mtimer_callback; 40cc63a182SAnup Patel 41e2f01f3cSFrank Chang static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) 42cc63a182SAnup Patel { 43cc63a182SAnup Patel return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 44cc63a182SAnup Patel timebase_freq, NANOSECONDS_PER_SECOND); 45cc63a182SAnup Patel } 46cc63a182SAnup Patel 47e2f01f3cSFrank Chang static uint64_t cpu_riscv_read_rtc(void *opaque) 48e2f01f3cSFrank Chang { 49e2f01f3cSFrank Chang RISCVAclintMTimerState *mtimer = opaque; 50e2f01f3cSFrank Chang return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; 51e2f01f3cSFrank Chang } 52e2f01f3cSFrank Chang 53cc63a182SAnup Patel /* 54cc63a182SAnup Patel * Called when timecmp is written to update the QEMU timer or immediately 55cc63a182SAnup Patel * trigger timer interrupt if mtimecmp <= current timer value. 56cc63a182SAnup Patel */ 57b8fb878aSAnup Patel static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, 58b8fb878aSAnup Patel RISCVCPU *cpu, 59cc63a182SAnup Patel int hartid, 60e2f01f3cSFrank Chang uint64_t value) 61cc63a182SAnup Patel { 62e2f01f3cSFrank Chang uint32_t timebase_freq = mtimer->timebase_freq; 63cc63a182SAnup Patel uint64_t next; 64cc63a182SAnup Patel uint64_t diff; 65cc63a182SAnup Patel 66e2f01f3cSFrank Chang uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); 67cc63a182SAnup Patel 68cc63a182SAnup Patel cpu->env.timecmp = value; 69cc63a182SAnup Patel if (cpu->env.timecmp <= rtc_r) { 70b8fb878aSAnup Patel /* 71b8fb878aSAnup Patel * If we're setting an MTIMECMP value in the "past", 72b8fb878aSAnup Patel * immediately raise the timer interrupt 73b8fb878aSAnup Patel */ 74b8fb878aSAnup Patel qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]); 75cc63a182SAnup Patel return; 76cc63a182SAnup Patel } 77cc63a182SAnup Patel 78cc63a182SAnup Patel /* otherwise, set up the future timer interrupt */ 79b8fb878aSAnup Patel qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]); 80cc63a182SAnup Patel diff = cpu->env.timecmp - rtc_r; 81cc63a182SAnup Patel /* back to ns (note args switched in muldiv64) */ 82cc63a182SAnup Patel uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); 83cc63a182SAnup Patel 84cc63a182SAnup Patel /* 85cc63a182SAnup Patel * check if ns_diff overflowed and check if the addition would potentially 86cc63a182SAnup Patel * overflow 87cc63a182SAnup Patel */ 88cc63a182SAnup Patel if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || 89cc63a182SAnup Patel ns_diff > INT64_MAX) { 90cc63a182SAnup Patel next = INT64_MAX; 91cc63a182SAnup Patel } else { 92cc63a182SAnup Patel /* 93cc63a182SAnup Patel * as it is very unlikely qemu_clock_get_ns will return a value 94cc63a182SAnup Patel * greater than INT64_MAX, no additional check is needed for an 95cc63a182SAnup Patel * unsigned integer overflow. 96cc63a182SAnup Patel */ 97cc63a182SAnup Patel next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; 98cc63a182SAnup Patel /* 99cc63a182SAnup Patel * if ns_diff is INT64_MAX next may still be outside the range 100cc63a182SAnup Patel * of a signed integer. 101cc63a182SAnup Patel */ 102cc63a182SAnup Patel next = MIN(next, INT64_MAX); 103cc63a182SAnup Patel } 104cc63a182SAnup Patel 105cc63a182SAnup Patel timer_mod(cpu->env.timer, next); 106cc63a182SAnup Patel } 107cc63a182SAnup Patel 108cc63a182SAnup Patel /* 109cc63a182SAnup Patel * Callback used when the timer set using timer_mod expires. 110cc63a182SAnup Patel * Should raise the timer interrupt line 111cc63a182SAnup Patel */ 112b8fb878aSAnup Patel static void riscv_aclint_mtimer_cb(void *opaque) 113cc63a182SAnup Patel { 114b8fb878aSAnup Patel riscv_aclint_mtimer_callback *state = opaque; 115cc63a182SAnup Patel 116cc63a182SAnup Patel qemu_irq_raise(state->s->timer_irqs[state->num]); 117cc63a182SAnup Patel } 118cc63a182SAnup Patel 119b8fb878aSAnup Patel /* CPU read MTIMER register */ 120b8fb878aSAnup Patel static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, 121b8fb878aSAnup Patel unsigned size) 122cc63a182SAnup Patel { 123b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 124b8fb878aSAnup Patel 125b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 126b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 127b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 128b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 129cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 130cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 131cc63a182SAnup Patel if (!env) { 132b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 133b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 134cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 135d42df0eaSFrank Chang /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ 136cc63a182SAnup Patel uint64_t timecmp = env->timecmp; 137d42df0eaSFrank Chang return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp; 138cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 139cc63a182SAnup Patel /* timecmp_hi */ 140cc63a182SAnup Patel uint64_t timecmp = env->timecmp; 141cc63a182SAnup Patel return (timecmp >> 32) & 0xFFFFFFFF; 142cc63a182SAnup Patel } else { 143b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 144b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 145cc63a182SAnup Patel return 0; 146cc63a182SAnup Patel } 147b8fb878aSAnup Patel } else if (addr == mtimer->time_base) { 148d42df0eaSFrank Chang /* time_lo for RV32/RV64 or timecmp for RV64 */ 149e2f01f3cSFrank Chang uint64_t rtc = cpu_riscv_read_rtc(mtimer); 150d42df0eaSFrank Chang return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; 151b8fb878aSAnup Patel } else if (addr == mtimer->time_base + 4) { 152cc63a182SAnup Patel /* time_hi */ 153e2f01f3cSFrank Chang return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; 154cc63a182SAnup Patel } 155cc63a182SAnup Patel 156b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 157b8fb878aSAnup Patel "aclint-mtimer: invalid read: %08x", (uint32_t)addr); 158cc63a182SAnup Patel return 0; 159cc63a182SAnup Patel } 160cc63a182SAnup Patel 161b8fb878aSAnup Patel /* CPU write MTIMER register */ 162b8fb878aSAnup Patel static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, 163b8fb878aSAnup Patel uint64_t value, unsigned size) 164cc63a182SAnup Patel { 165b8fb878aSAnup Patel RISCVAclintMTimerState *mtimer = opaque; 166e2f01f3cSFrank Chang int i; 167cc63a182SAnup Patel 168b8fb878aSAnup Patel if (addr >= mtimer->timecmp_base && 169b8fb878aSAnup Patel addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { 170b8fb878aSAnup Patel size_t hartid = mtimer->hartid_base + 171b8fb878aSAnup Patel ((addr - mtimer->timecmp_base) >> 3); 172cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 173cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 174cc63a182SAnup Patel if (!env) { 175b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 176b8fb878aSAnup Patel "aclint-mtimer: invalid hartid: %zu", hartid); 177cc63a182SAnup Patel } else if ((addr & 0x7) == 0) { 178d42df0eaSFrank Chang if (size == 4) { 179d42df0eaSFrank Chang /* timecmp_lo for RV32/RV64 */ 180cc63a182SAnup Patel uint64_t timecmp_hi = env->timecmp >> 32; 181b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 182e2f01f3cSFrank Chang timecmp_hi << 32 | (value & 0xFFFFFFFF)); 183d42df0eaSFrank Chang } else { 184d42df0eaSFrank Chang /* timecmp for RV64 */ 185d42df0eaSFrank Chang riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 186e2f01f3cSFrank Chang value); 187d42df0eaSFrank Chang } 188cc63a182SAnup Patel } else if ((addr & 0x7) == 4) { 189d42df0eaSFrank Chang if (size == 4) { 190d42df0eaSFrank Chang /* timecmp_hi for RV32/RV64 */ 191cc63a182SAnup Patel uint64_t timecmp_lo = env->timecmp; 192b8fb878aSAnup Patel riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, 193e2f01f3cSFrank Chang value << 32 | (timecmp_lo & 0xFFFFFFFF)); 194cc63a182SAnup Patel } else { 195d42df0eaSFrank Chang qemu_log_mask(LOG_GUEST_ERROR, 196d42df0eaSFrank Chang "aclint-mtimer: invalid timecmp_hi write: %08x", 197d42df0eaSFrank Chang (uint32_t)addr); 198d42df0eaSFrank Chang } 199d42df0eaSFrank Chang } else { 200b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 201b8fb878aSAnup Patel "aclint-mtimer: invalid timecmp write: %08x", 202b8fb878aSAnup Patel (uint32_t)addr); 203cc63a182SAnup Patel } 204cc63a182SAnup Patel return; 205e2f01f3cSFrank Chang } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { 206e2f01f3cSFrank Chang uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); 207e2f01f3cSFrank Chang 208e2f01f3cSFrank Chang if (addr == mtimer->time_base) { 209e2f01f3cSFrank Chang if (size == 4) { 210e2f01f3cSFrank Chang /* time_lo for RV32/RV64 */ 211e2f01f3cSFrank Chang mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; 212e2f01f3cSFrank Chang } else { 213e2f01f3cSFrank Chang /* time for RV64 */ 214e2f01f3cSFrank Chang mtimer->time_delta = value - rtc_r; 215e2f01f3cSFrank Chang } 216e2f01f3cSFrank Chang } else { 217e2f01f3cSFrank Chang if (size == 4) { 218e2f01f3cSFrank Chang /* time_hi for RV32/RV64 */ 219e2f01f3cSFrank Chang mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; 220e2f01f3cSFrank Chang } else { 221e2f01f3cSFrank Chang qemu_log_mask(LOG_GUEST_ERROR, 222e2f01f3cSFrank Chang "aclint-mtimer: invalid time_hi write: %08x", 223e2f01f3cSFrank Chang (uint32_t)addr); 224cc63a182SAnup Patel return; 225e2f01f3cSFrank Chang } 226e2f01f3cSFrank Chang } 227e2f01f3cSFrank Chang 228e2f01f3cSFrank Chang /* Check if timer interrupt is triggered for each hart. */ 229e2f01f3cSFrank Chang for (i = 0; i < mtimer->num_harts; i++) { 230e2f01f3cSFrank Chang CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); 231e2f01f3cSFrank Chang CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 232e2f01f3cSFrank Chang if (!env) { 233e2f01f3cSFrank Chang continue; 234e2f01f3cSFrank Chang } 235e2f01f3cSFrank Chang riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), 23677046729SAtish Patra mtimer->hartid_base + i, 23777046729SAtish Patra env->timecmp); 238e2f01f3cSFrank Chang } 239cc63a182SAnup Patel return; 240cc63a182SAnup Patel } 241cc63a182SAnup Patel 242b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 243b8fb878aSAnup Patel "aclint-mtimer: invalid write: %08x", (uint32_t)addr); 244cc63a182SAnup Patel } 245cc63a182SAnup Patel 246b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_mtimer_ops = { 247b8fb878aSAnup Patel .read = riscv_aclint_mtimer_read, 248b8fb878aSAnup Patel .write = riscv_aclint_mtimer_write, 249cc63a182SAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 250cc63a182SAnup Patel .valid = { 251cc63a182SAnup Patel .min_access_size = 4, 252cc63a182SAnup Patel .max_access_size = 8 253231a90c0SFrank Chang }, 254231a90c0SFrank Chang .impl = { 255231a90c0SFrank Chang .min_access_size = 4, 256231a90c0SFrank Chang .max_access_size = 8, 257cc63a182SAnup Patel } 258cc63a182SAnup Patel }; 259cc63a182SAnup Patel 260b8fb878aSAnup Patel static Property riscv_aclint_mtimer_properties[] = { 261b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState, 262b8fb878aSAnup Patel hartid_base, 0), 263b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1), 264b8fb878aSAnup Patel DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState, 265b8fb878aSAnup Patel timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP), 266b8fb878aSAnup Patel DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState, 267b8fb878aSAnup Patel time_base, RISCV_ACLINT_DEFAULT_MTIME), 268b8fb878aSAnup Patel DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState, 269b8fb878aSAnup Patel aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE), 270b8fb878aSAnup Patel DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState, 271b8fb878aSAnup Patel timebase_freq, 0), 272cc63a182SAnup Patel DEFINE_PROP_END_OF_LIST(), 273cc63a182SAnup Patel }; 274cc63a182SAnup Patel 275b8fb878aSAnup Patel static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) 276cc63a182SAnup Patel { 277b8fb878aSAnup Patel RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev); 278b8fb878aSAnup Patel int i; 279b8fb878aSAnup Patel 280b8fb878aSAnup Patel memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops, 281b8fb878aSAnup Patel s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size); 282cc63a182SAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 283cc63a182SAnup Patel 284b21e2380SMarkus Armbruster s->timer_irqs = g_new(qemu_irq, s->num_harts); 285cc63a182SAnup Patel qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); 286cc63a182SAnup Patel 287b8fb878aSAnup Patel /* Claim timer interrupt bits */ 288b8fb878aSAnup Patel for (i = 0; i < s->num_harts; i++) { 289b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); 290b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { 291b8fb878aSAnup Patel error_report("MTIP already claimed"); 292b8fb878aSAnup Patel exit(1); 293b8fb878aSAnup Patel } 294b8fb878aSAnup Patel } 295cc63a182SAnup Patel } 296cc63a182SAnup Patel 2978124f819SJim Shu static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) 2988124f819SJim Shu { 2998124f819SJim Shu /* 3008124f819SJim Shu * According to RISC-V ACLINT spec: 3018124f819SJim Shu * - On MTIMER device reset, the MTIME register is cleared to zero. 3028124f819SJim Shu * - On MTIMER device reset, the MTIMECMP registers are in unknown state. 3038124f819SJim Shu */ 3048124f819SJim Shu RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); 3058124f819SJim Shu 3068124f819SJim Shu /* 3078124f819SJim Shu * Clear mtime register by writing to 0 it. 3088124f819SJim Shu * Pending mtime interrupts will also be cleared at the same time. 3098124f819SJim Shu */ 3108124f819SJim Shu riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); 3118124f819SJim Shu } 3128124f819SJim Shu 313b8fb878aSAnup Patel static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) 314cc63a182SAnup Patel { 315cc63a182SAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 316b8fb878aSAnup Patel dc->realize = riscv_aclint_mtimer_realize; 317b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_mtimer_properties); 3188124f819SJim Shu ResettableClass *rc = RESETTABLE_CLASS(klass); 3198124f819SJim Shu rc->phases.enter = riscv_aclint_mtimer_reset_enter; 320cc63a182SAnup Patel } 321cc63a182SAnup Patel 322b8fb878aSAnup Patel static const TypeInfo riscv_aclint_mtimer_info = { 323b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_MTIMER, 324cc63a182SAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 325b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintMTimerState), 326b8fb878aSAnup Patel .class_init = riscv_aclint_mtimer_class_init, 327cc63a182SAnup Patel }; 328cc63a182SAnup Patel 329cc63a182SAnup Patel /* 330b8fb878aSAnup Patel * Create ACLINT MTIMER device. 331cc63a182SAnup Patel */ 332b8fb878aSAnup Patel DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, 333b8fb878aSAnup Patel uint32_t hartid_base, uint32_t num_harts, 334cc63a182SAnup Patel uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, 335cc63a182SAnup Patel bool provide_rdtime) 336cc63a182SAnup Patel { 337cc63a182SAnup Patel int i; 338b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER); 339cc63a182SAnup Patel 340b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 341b8fb878aSAnup Patel assert(!(addr & 0x7)); 342b8fb878aSAnup Patel assert(!(timecmp_base & 0x7)); 343b8fb878aSAnup Patel assert(!(time_base & 0x7)); 344b8fb878aSAnup Patel 345cc63a182SAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 346cc63a182SAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 347cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); 348cc63a182SAnup Patel qdev_prop_set_uint32(dev, "time-base", time_base); 349cc63a182SAnup Patel qdev_prop_set_uint32(dev, "aperture-size", size); 350cc63a182SAnup Patel qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); 351cc63a182SAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 352cc63a182SAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 353cc63a182SAnup Patel 354cc63a182SAnup Patel for (i = 0; i < num_harts; i++) { 355cc63a182SAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 356cc63a182SAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 357cc63a182SAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 358b8fb878aSAnup Patel riscv_aclint_mtimer_callback *cb = 359b21e2380SMarkus Armbruster g_new0(riscv_aclint_mtimer_callback, 1); 360cc63a182SAnup Patel 361cc63a182SAnup Patel if (!env) { 362cc63a182SAnup Patel g_free(cb); 363cc63a182SAnup Patel continue; 364cc63a182SAnup Patel } 365cc63a182SAnup Patel if (provide_rdtime) { 366e2f01f3cSFrank Chang riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); 367cc63a182SAnup Patel } 368cc63a182SAnup Patel 369b8fb878aSAnup Patel cb->s = RISCV_ACLINT_MTIMER(dev); 370cc63a182SAnup Patel cb->num = i; 371cc63a182SAnup Patel env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 372b8fb878aSAnup Patel &riscv_aclint_mtimer_cb, cb); 373cc63a182SAnup Patel env->timecmp = 0; 374cc63a182SAnup Patel 375cc63a182SAnup Patel qdev_connect_gpio_out(dev, i, 376cc63a182SAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)); 377cc63a182SAnup Patel } 378cc63a182SAnup Patel 379cc63a182SAnup Patel return dev; 380cc63a182SAnup Patel } 381b8fb878aSAnup Patel 382b8fb878aSAnup Patel /* CPU read [M|S]SWI register */ 383b8fb878aSAnup Patel static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr, 384b8fb878aSAnup Patel unsigned size) 385b8fb878aSAnup Patel { 386b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 387b8fb878aSAnup Patel 388b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 389b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 390b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 391b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 392b8fb878aSAnup Patel if (!env) { 393b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 394b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 395b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 396b8fb878aSAnup Patel return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); 397b8fb878aSAnup Patel } 398b8fb878aSAnup Patel } 399b8fb878aSAnup Patel 400b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 401b8fb878aSAnup Patel "aclint-swi: invalid read: %08x", (uint32_t)addr); 402b8fb878aSAnup Patel return 0; 403b8fb878aSAnup Patel } 404b8fb878aSAnup Patel 405b8fb878aSAnup Patel /* CPU write [M|S]SWI register */ 406b8fb878aSAnup Patel static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value, 407b8fb878aSAnup Patel unsigned size) 408b8fb878aSAnup Patel { 409b8fb878aSAnup Patel RISCVAclintSwiState *swi = opaque; 410b8fb878aSAnup Patel 411b8fb878aSAnup Patel if (addr < (swi->num_harts << 2)) { 412b8fb878aSAnup Patel size_t hartid = swi->hartid_base + (addr >> 2); 413b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid); 414b8fb878aSAnup Patel CPURISCVState *env = cpu ? cpu->env_ptr : NULL; 415b8fb878aSAnup Patel if (!env) { 416b8fb878aSAnup Patel qemu_log_mask(LOG_GUEST_ERROR, 417b8fb878aSAnup Patel "aclint-swi: invalid hartid: %zu", hartid); 418b8fb878aSAnup Patel } else if ((addr & 0x3) == 0) { 419b8fb878aSAnup Patel if (value & 0x1) { 420b8fb878aSAnup Patel qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]); 421b8fb878aSAnup Patel } else { 422b8fb878aSAnup Patel if (!swi->sswi) { 423b8fb878aSAnup Patel qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]); 424b8fb878aSAnup Patel } 425b8fb878aSAnup Patel } 426b8fb878aSAnup Patel return; 427b8fb878aSAnup Patel } 428b8fb878aSAnup Patel } 429b8fb878aSAnup Patel 430b8fb878aSAnup Patel qemu_log_mask(LOG_UNIMP, 431b8fb878aSAnup Patel "aclint-swi: invalid write: %08x", (uint32_t)addr); 432b8fb878aSAnup Patel } 433b8fb878aSAnup Patel 434b8fb878aSAnup Patel static const MemoryRegionOps riscv_aclint_swi_ops = { 435b8fb878aSAnup Patel .read = riscv_aclint_swi_read, 436b8fb878aSAnup Patel .write = riscv_aclint_swi_write, 437b8fb878aSAnup Patel .endianness = DEVICE_LITTLE_ENDIAN, 438b8fb878aSAnup Patel .valid = { 439b8fb878aSAnup Patel .min_access_size = 4, 440b8fb878aSAnup Patel .max_access_size = 4 441b8fb878aSAnup Patel } 442b8fb878aSAnup Patel }; 443b8fb878aSAnup Patel 444b8fb878aSAnup Patel static Property riscv_aclint_swi_properties[] = { 445b8fb878aSAnup Patel DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0), 446b8fb878aSAnup Patel DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1), 447b8fb878aSAnup Patel DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false), 448b8fb878aSAnup Patel DEFINE_PROP_END_OF_LIST(), 449b8fb878aSAnup Patel }; 450b8fb878aSAnup Patel 451b8fb878aSAnup Patel static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) 452b8fb878aSAnup Patel { 453b8fb878aSAnup Patel RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev); 454b8fb878aSAnup Patel int i; 455b8fb878aSAnup Patel 456b8fb878aSAnup Patel memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi, 457b8fb878aSAnup Patel TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE); 458b8fb878aSAnup Patel sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio); 459b8fb878aSAnup Patel 460b21e2380SMarkus Armbruster swi->soft_irqs = g_new(qemu_irq, swi->num_harts); 461b8fb878aSAnup Patel qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts); 462b8fb878aSAnup Patel 463b8fb878aSAnup Patel /* Claim software interrupt bits */ 464b8fb878aSAnup Patel for (i = 0; i < swi->num_harts; i++) { 465b8fb878aSAnup Patel RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); 466*9323e79fSPeter Maydell /* We don't claim mip.SSIP because it is writable by software */ 467b8fb878aSAnup Patel if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) { 468b8fb878aSAnup Patel error_report("MSIP already claimed"); 469b8fb878aSAnup Patel exit(1); 470b8fb878aSAnup Patel } 471b8fb878aSAnup Patel } 472b8fb878aSAnup Patel } 473b8fb878aSAnup Patel 4748124f819SJim Shu static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) 4758124f819SJim Shu { 4768124f819SJim Shu /* 4778124f819SJim Shu * According to RISC-V ACLINT spec: 4788124f819SJim Shu * - On MSWI device reset, each MSIP register is cleared to zero. 4798124f819SJim Shu * 4808124f819SJim Shu * p.s. SSWI device reset does nothing since SETSIP register always reads 0. 4818124f819SJim Shu */ 4828124f819SJim Shu RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); 4838124f819SJim Shu int i; 4848124f819SJim Shu 4858124f819SJim Shu if (!swi->sswi) { 4868124f819SJim Shu for (i = 0; i < swi->num_harts; i++) { 4878124f819SJim Shu /* Clear MSIP registers by lowering software interrupts. */ 4888124f819SJim Shu qemu_irq_lower(swi->soft_irqs[i]); 4898124f819SJim Shu } 4908124f819SJim Shu } 4918124f819SJim Shu } 4928124f819SJim Shu 493b8fb878aSAnup Patel static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) 494b8fb878aSAnup Patel { 495b8fb878aSAnup Patel DeviceClass *dc = DEVICE_CLASS(klass); 496b8fb878aSAnup Patel dc->realize = riscv_aclint_swi_realize; 497b8fb878aSAnup Patel device_class_set_props(dc, riscv_aclint_swi_properties); 4988124f819SJim Shu ResettableClass *rc = RESETTABLE_CLASS(klass); 4998124f819SJim Shu rc->phases.enter = riscv_aclint_swi_reset_enter; 500b8fb878aSAnup Patel } 501b8fb878aSAnup Patel 502b8fb878aSAnup Patel static const TypeInfo riscv_aclint_swi_info = { 503b8fb878aSAnup Patel .name = TYPE_RISCV_ACLINT_SWI, 504b8fb878aSAnup Patel .parent = TYPE_SYS_BUS_DEVICE, 505b8fb878aSAnup Patel .instance_size = sizeof(RISCVAclintSwiState), 506b8fb878aSAnup Patel .class_init = riscv_aclint_swi_class_init, 507b8fb878aSAnup Patel }; 508b8fb878aSAnup Patel 509b8fb878aSAnup Patel /* 510b8fb878aSAnup Patel * Create ACLINT [M|S]SWI device. 511b8fb878aSAnup Patel */ 512b8fb878aSAnup Patel DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, 513b8fb878aSAnup Patel uint32_t num_harts, bool sswi) 514b8fb878aSAnup Patel { 515b8fb878aSAnup Patel int i; 516b8fb878aSAnup Patel DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI); 517b8fb878aSAnup Patel 518b8fb878aSAnup Patel assert(num_harts <= RISCV_ACLINT_MAX_HARTS); 519b8fb878aSAnup Patel assert(!(addr & 0x3)); 520b8fb878aSAnup Patel 521b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 522b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "num-harts", num_harts); 523b8fb878aSAnup Patel qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); 524b8fb878aSAnup Patel sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 525b8fb878aSAnup Patel sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 526b8fb878aSAnup Patel 527b8fb878aSAnup Patel for (i = 0; i < num_harts; i++) { 528b8fb878aSAnup Patel CPUState *cpu = qemu_get_cpu(hartid_base + i); 529b8fb878aSAnup Patel RISCVCPU *rvcpu = RISCV_CPU(cpu); 530b8fb878aSAnup Patel 531b8fb878aSAnup Patel qdev_connect_gpio_out(dev, i, 532b8fb878aSAnup Patel qdev_get_gpio_in(DEVICE(rvcpu), 533b8fb878aSAnup Patel (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT)); 534b8fb878aSAnup Patel } 535b8fb878aSAnup Patel 536b8fb878aSAnup Patel return dev; 537b8fb878aSAnup Patel } 538b8fb878aSAnup Patel 539b8fb878aSAnup Patel static void riscv_aclint_register_types(void) 540b8fb878aSAnup Patel { 541b8fb878aSAnup Patel type_register_static(&riscv_aclint_mtimer_info); 542b8fb878aSAnup Patel type_register_static(&riscv_aclint_swi_info); 543b8fb878aSAnup Patel } 544b8fb878aSAnup Patel 545b8fb878aSAnup Patel type_init(riscv_aclint_register_types) 546