1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 /* 152 * kvm_irqchip_in_kernel() will cause the compiler to turn this 153 * info a nop if CONFIG_KVM isn't defined. 154 */ 155 #define spapr_xive_in_kernel(xive) \ 156 (kvm_irqchip_in_kernel() && (xive)->fd != -1) 157 158 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 159 { 160 XiveSource *xsrc = &xive->source; 161 int i; 162 163 if (spapr_xive_in_kernel(xive)) { 164 Error *local_err = NULL; 165 166 kvmppc_xive_synchronize_state(xive, &local_err); 167 if (local_err) { 168 error_report_err(local_err); 169 return; 170 } 171 } 172 173 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 174 175 for (i = 0; i < xive->nr_irqs; i++) { 176 uint8_t pq = xive_source_esb_get(xsrc, i); 177 XiveEAS *eas = &xive->eat[i]; 178 179 if (!xive_eas_is_valid(eas)) { 180 continue; 181 } 182 183 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 184 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 185 pq & XIVE_ESB_VAL_P ? 'P' : '-', 186 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 187 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 188 xive_eas_is_masked(eas) ? "M" : " ", 189 (int) xive_get_field64(EAS_END_DATA, eas->w)); 190 191 if (!xive_eas_is_masked(eas)) { 192 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 193 XiveEND *end; 194 195 assert(end_idx < xive->nr_ends); 196 end = &xive->endt[end_idx]; 197 198 if (xive_end_is_valid(end)) { 199 spapr_xive_end_pic_print_info(xive, end, mon); 200 } 201 } 202 monitor_printf(mon, "\n"); 203 } 204 } 205 206 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 207 { 208 memory_region_set_enabled(&xive->source.esb_mmio, enable); 209 memory_region_set_enabled(&xive->tm_mmio, enable); 210 211 /* Disable the END ESBs until a guest OS makes use of them */ 212 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 213 } 214 215 static void spapr_xive_tm_write(void *opaque, hwaddr offset, 216 uint64_t value, unsigned size) 217 { 218 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 219 220 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 221 } 222 223 static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 224 { 225 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 226 227 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 228 } 229 230 const MemoryRegionOps spapr_xive_tm_ops = { 231 .read = spapr_xive_tm_read, 232 .write = spapr_xive_tm_write, 233 .endianness = DEVICE_BIG_ENDIAN, 234 .valid = { 235 .min_access_size = 1, 236 .max_access_size = 8, 237 }, 238 .impl = { 239 .min_access_size = 1, 240 .max_access_size = 8, 241 }, 242 }; 243 244 static void spapr_xive_end_reset(XiveEND *end) 245 { 246 memset(end, 0, sizeof(*end)); 247 248 /* switch off the escalation and notification ESBs */ 249 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 250 } 251 252 static void spapr_xive_reset(void *dev) 253 { 254 SpaprXive *xive = SPAPR_XIVE(dev); 255 int i; 256 257 /* 258 * The XiveSource has its own reset handler, which mask off all 259 * IRQs (!P|Q) 260 */ 261 262 /* Mask all valid EASs in the IRQ number space. */ 263 for (i = 0; i < xive->nr_irqs; i++) { 264 XiveEAS *eas = &xive->eat[i]; 265 if (xive_eas_is_valid(eas)) { 266 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 267 } else { 268 eas->w = 0; 269 } 270 } 271 272 /* Clear all ENDs */ 273 for (i = 0; i < xive->nr_ends; i++) { 274 spapr_xive_end_reset(&xive->endt[i]); 275 } 276 } 277 278 static void spapr_xive_instance_init(Object *obj) 279 { 280 SpaprXive *xive = SPAPR_XIVE(obj); 281 282 object_initialize_child(obj, "source", &xive->source, TYPE_XIVE_SOURCE); 283 284 object_initialize_child(obj, "end_source", &xive->end_source, 285 TYPE_XIVE_END_SOURCE); 286 287 /* Not connected to the KVM XIVE device */ 288 xive->fd = -1; 289 } 290 291 static void spapr_xive_realize(DeviceState *dev, Error **errp) 292 { 293 SpaprXive *xive = SPAPR_XIVE(dev); 294 SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive); 295 XiveSource *xsrc = &xive->source; 296 XiveENDSource *end_xsrc = &xive->end_source; 297 Error *local_err = NULL; 298 299 sxc->parent_realize(dev, &local_err); 300 if (local_err) { 301 error_propagate(errp, local_err); 302 return; 303 } 304 305 if (!xive->nr_irqs) { 306 error_setg(errp, "Number of interrupt needs to be greater 0"); 307 return; 308 } 309 310 if (!xive->nr_ends) { 311 error_setg(errp, "Number of interrupt needs to be greater 0"); 312 return; 313 } 314 315 /* 316 * Initialize the internal sources, for IPIs and virtual devices. 317 */ 318 object_property_set_int(OBJECT(xsrc), "nr-irqs", xive->nr_irqs, 319 &error_fatal); 320 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); 321 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 322 return; 323 } 324 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 325 326 /* 327 * Initialize the END ESB source 328 */ 329 object_property_set_int(OBJECT(end_xsrc), "nr-ends", xive->nr_irqs, 330 &error_fatal); 331 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 332 &error_abort); 333 if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) { 334 return; 335 } 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 337 338 /* Set the mapping address of the END ESB pages after the source ESBs */ 339 xive->end_base = xive->vc_base + xive_source_esb_len(xsrc); 340 341 /* 342 * Allocate the routing tables 343 */ 344 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 345 xive->endt = g_new0(XiveEND, xive->nr_ends); 346 347 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 348 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 349 350 qemu_register_reset(spapr_xive_reset, dev); 351 352 /* TIMA initialization */ 353 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, 354 xive, "xive.tima", 4ull << TM_SHIFT); 355 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 356 357 /* 358 * Map all regions. These will be enabled or disabled at reset and 359 * can also be overridden by KVM memory regions if active 360 */ 361 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 362 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 363 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 364 } 365 366 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 367 uint32_t eas_idx, XiveEAS *eas) 368 { 369 SpaprXive *xive = SPAPR_XIVE(xrtr); 370 371 if (eas_idx >= xive->nr_irqs) { 372 return -1; 373 } 374 375 *eas = xive->eat[eas_idx]; 376 return 0; 377 } 378 379 static int spapr_xive_get_end(XiveRouter *xrtr, 380 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 381 { 382 SpaprXive *xive = SPAPR_XIVE(xrtr); 383 384 if (end_idx >= xive->nr_ends) { 385 return -1; 386 } 387 388 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 389 return 0; 390 } 391 392 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 393 uint32_t end_idx, XiveEND *end, 394 uint8_t word_number) 395 { 396 SpaprXive *xive = SPAPR_XIVE(xrtr); 397 398 if (end_idx >= xive->nr_ends) { 399 return -1; 400 } 401 402 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 403 return 0; 404 } 405 406 static int spapr_xive_get_nvt(XiveRouter *xrtr, 407 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 408 { 409 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 410 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 411 412 if (!cpu) { 413 /* TODO: should we assert() if we can find a NVT ? */ 414 return -1; 415 } 416 417 /* 418 * sPAPR does not maintain a NVT table. Return that the NVT is 419 * valid if we have found a matching CPU 420 */ 421 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 422 return 0; 423 } 424 425 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 426 uint32_t nvt_idx, XiveNVT *nvt, 427 uint8_t word_number) 428 { 429 /* 430 * We don't need to write back to the NVTs because the sPAPR 431 * machine should never hit a non-scheduled NVT. It should never 432 * get called. 433 */ 434 g_assert_not_reached(); 435 } 436 437 static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, 438 uint8_t nvt_blk, uint32_t nvt_idx, 439 bool cam_ignore, uint8_t priority, 440 uint32_t logic_serv, XiveTCTXMatch *match) 441 { 442 CPUState *cs; 443 int count = 0; 444 445 CPU_FOREACH(cs) { 446 PowerPCCPU *cpu = POWERPC_CPU(cs); 447 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 448 int ring; 449 450 /* 451 * Skip partially initialized vCPUs. This can happen when 452 * vCPUs are hotplugged. 453 */ 454 if (!tctx) { 455 continue; 456 } 457 458 /* 459 * Check the thread context CAM lines and record matches. 460 */ 461 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, 462 cam_ignore, logic_serv); 463 /* 464 * Save the matching thread interrupt context and follow on to 465 * check for duplicates which are invalid. 466 */ 467 if (ring != -1) { 468 if (match->tctx) { 469 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 470 "context NVT %x/%x\n", nvt_blk, nvt_idx); 471 return -1; 472 } 473 474 match->ring = ring; 475 match->tctx = tctx; 476 count++; 477 } 478 } 479 480 return count; 481 } 482 483 static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) 484 { 485 return SPAPR_XIVE_BLOCK_ID; 486 } 487 488 static const VMStateDescription vmstate_spapr_xive_end = { 489 .name = TYPE_SPAPR_XIVE "/end", 490 .version_id = 1, 491 .minimum_version_id = 1, 492 .fields = (VMStateField []) { 493 VMSTATE_UINT32(w0, XiveEND), 494 VMSTATE_UINT32(w1, XiveEND), 495 VMSTATE_UINT32(w2, XiveEND), 496 VMSTATE_UINT32(w3, XiveEND), 497 VMSTATE_UINT32(w4, XiveEND), 498 VMSTATE_UINT32(w5, XiveEND), 499 VMSTATE_UINT32(w6, XiveEND), 500 VMSTATE_UINT32(w7, XiveEND), 501 VMSTATE_END_OF_LIST() 502 }, 503 }; 504 505 static const VMStateDescription vmstate_spapr_xive_eas = { 506 .name = TYPE_SPAPR_XIVE "/eas", 507 .version_id = 1, 508 .minimum_version_id = 1, 509 .fields = (VMStateField []) { 510 VMSTATE_UINT64(w, XiveEAS), 511 VMSTATE_END_OF_LIST() 512 }, 513 }; 514 515 static int vmstate_spapr_xive_pre_save(void *opaque) 516 { 517 SpaprXive *xive = SPAPR_XIVE(opaque); 518 519 if (spapr_xive_in_kernel(xive)) { 520 return kvmppc_xive_pre_save(xive); 521 } 522 523 return 0; 524 } 525 526 /* 527 * Called by the sPAPR IRQ backend 'post_load' method at the machine 528 * level. 529 */ 530 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 531 { 532 SpaprXive *xive = SPAPR_XIVE(intc); 533 534 if (spapr_xive_in_kernel(xive)) { 535 return kvmppc_xive_post_load(xive, version_id); 536 } 537 538 return 0; 539 } 540 541 static const VMStateDescription vmstate_spapr_xive = { 542 .name = TYPE_SPAPR_XIVE, 543 .version_id = 1, 544 .minimum_version_id = 1, 545 .pre_save = vmstate_spapr_xive_pre_save, 546 .post_load = NULL, /* handled at the machine level */ 547 .fields = (VMStateField[]) { 548 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 549 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 550 vmstate_spapr_xive_eas, XiveEAS), 551 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 552 vmstate_spapr_xive_end, XiveEND), 553 VMSTATE_END_OF_LIST() 554 }, 555 }; 556 557 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 558 bool lsi, Error **errp) 559 { 560 SpaprXive *xive = SPAPR_XIVE(intc); 561 XiveSource *xsrc = &xive->source; 562 563 assert(lisn < xive->nr_irqs); 564 565 if (xive_eas_is_valid(&xive->eat[lisn])) { 566 error_setg(errp, "IRQ %d is not free", lisn); 567 return -EBUSY; 568 } 569 570 /* 571 * Set default values when allocating an IRQ number 572 */ 573 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 574 if (lsi) { 575 xive_source_irq_set_lsi(xsrc, lisn); 576 } 577 578 if (spapr_xive_in_kernel(xive)) { 579 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 580 } 581 582 return 0; 583 } 584 585 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 586 { 587 SpaprXive *xive = SPAPR_XIVE(intc); 588 assert(lisn < xive->nr_irqs); 589 590 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 591 } 592 593 static Property spapr_xive_properties[] = { 594 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 595 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 596 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 597 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 598 DEFINE_PROP_UINT8("hv-prio", SpaprXive, hv_prio, 7), 599 DEFINE_PROP_END_OF_LIST(), 600 }; 601 602 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 603 PowerPCCPU *cpu, Error **errp) 604 { 605 SpaprXive *xive = SPAPR_XIVE(intc); 606 Object *obj; 607 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 608 609 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp); 610 if (!obj) { 611 return -1; 612 } 613 614 spapr_cpu->tctx = XIVE_TCTX(obj); 615 return 0; 616 } 617 618 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 619 { 620 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 621 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 622 } 623 624 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 625 PowerPCCPU *cpu) 626 { 627 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 628 uint8_t nvt_blk; 629 uint32_t nvt_idx; 630 631 xive_tctx_reset(tctx); 632 633 /* 634 * When a Virtual Processor is scheduled to run on a HW thread, 635 * the hypervisor pushes its identifier in the OS CAM line. 636 * Emulate the same behavior under QEMU. 637 */ 638 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 639 640 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 641 } 642 643 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, 644 PowerPCCPU *cpu) 645 { 646 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 647 648 xive_tctx_destroy(spapr_cpu->tctx); 649 spapr_cpu->tctx = NULL; 650 } 651 652 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 653 { 654 SpaprXive *xive = SPAPR_XIVE(intc); 655 656 if (spapr_xive_in_kernel(xive)) { 657 kvmppc_xive_source_set_irq(&xive->source, irq, val); 658 } else { 659 xive_source_set_irq(&xive->source, irq, val); 660 } 661 } 662 663 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 664 { 665 SpaprXive *xive = SPAPR_XIVE(intc); 666 CPUState *cs; 667 668 CPU_FOREACH(cs) { 669 PowerPCCPU *cpu = POWERPC_CPU(cs); 670 671 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 672 } 673 674 spapr_xive_pic_print_info(xive, mon); 675 } 676 677 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 678 void *fdt, uint32_t phandle) 679 { 680 SpaprXive *xive = SPAPR_XIVE(intc); 681 int node; 682 uint64_t timas[2 * 2]; 683 /* Interrupt number ranges for the IPIs */ 684 uint32_t lisn_ranges[] = { 685 cpu_to_be32(SPAPR_IRQ_IPI), 686 cpu_to_be32(SPAPR_IRQ_IPI + nr_servers), 687 }; 688 /* 689 * EQ size - the sizes of pages supported by the system 4K, 64K, 690 * 2M, 16M. We only advertise 64K for the moment. 691 */ 692 uint32_t eq_sizes[] = { 693 cpu_to_be32(16), /* 64K */ 694 }; 695 /* 696 * QEMU/KVM only needs to define a single range to reserve the 697 * escalation priority. A priority bitmask would have been more 698 * appropriate. 699 */ 700 uint32_t plat_res_int_priorities[] = { 701 cpu_to_be32(xive->hv_prio), /* start */ 702 cpu_to_be32(0xff - xive->hv_prio), /* count */ 703 }; 704 705 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 706 timas[0] = cpu_to_be64(xive->tm_base + 707 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 708 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 709 timas[2] = cpu_to_be64(xive->tm_base + 710 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 711 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 712 713 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 714 715 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 716 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 717 718 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 719 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 720 sizeof(eq_sizes))); 721 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 722 sizeof(lisn_ranges))); 723 724 /* For Linux to link the LSIs to the interrupt controller. */ 725 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 726 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 727 728 /* For SLOF */ 729 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 730 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 731 732 /* 733 * The "ibm,plat-res-int-priorities" property defines the priority 734 * ranges reserved by the hypervisor 735 */ 736 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 737 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 738 } 739 740 static int spapr_xive_activate(SpaprInterruptController *intc, 741 uint32_t nr_servers, Error **errp) 742 { 743 SpaprXive *xive = SPAPR_XIVE(intc); 744 745 if (kvm_enabled()) { 746 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, 747 errp); 748 if (rc < 0) { 749 return rc; 750 } 751 } 752 753 /* Activate the XIVE MMIOs */ 754 spapr_xive_mmio_set_enabled(xive, true); 755 756 return 0; 757 } 758 759 static void spapr_xive_deactivate(SpaprInterruptController *intc) 760 { 761 SpaprXive *xive = SPAPR_XIVE(intc); 762 763 spapr_xive_mmio_set_enabled(xive, false); 764 765 if (spapr_xive_in_kernel(xive)) { 766 kvmppc_xive_disconnect(intc); 767 } 768 } 769 770 static bool spapr_xive_in_kernel_xptr(const XivePresenter *xptr) 771 { 772 return spapr_xive_in_kernel(SPAPR_XIVE(xptr)); 773 } 774 775 static void spapr_xive_class_init(ObjectClass *klass, void *data) 776 { 777 DeviceClass *dc = DEVICE_CLASS(klass); 778 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 779 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 780 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 781 SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); 782 783 dc->desc = "sPAPR XIVE Interrupt Controller"; 784 device_class_set_props(dc, spapr_xive_properties); 785 device_class_set_parent_realize(dc, spapr_xive_realize, 786 &sxc->parent_realize); 787 dc->vmsd = &vmstate_spapr_xive; 788 789 xrc->get_eas = spapr_xive_get_eas; 790 xrc->get_end = spapr_xive_get_end; 791 xrc->write_end = spapr_xive_write_end; 792 xrc->get_nvt = spapr_xive_get_nvt; 793 xrc->write_nvt = spapr_xive_write_nvt; 794 xrc->get_block_id = spapr_xive_get_block_id; 795 796 sicc->activate = spapr_xive_activate; 797 sicc->deactivate = spapr_xive_deactivate; 798 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 799 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 800 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; 801 sicc->claim_irq = spapr_xive_claim_irq; 802 sicc->free_irq = spapr_xive_free_irq; 803 sicc->set_irq = spapr_xive_set_irq; 804 sicc->print_info = spapr_xive_print_info; 805 sicc->dt = spapr_xive_dt; 806 sicc->post_load = spapr_xive_post_load; 807 808 xpc->match_nvt = spapr_xive_match_nvt; 809 xpc->in_kernel = spapr_xive_in_kernel_xptr; 810 } 811 812 static const TypeInfo spapr_xive_info = { 813 .name = TYPE_SPAPR_XIVE, 814 .parent = TYPE_XIVE_ROUTER, 815 .instance_init = spapr_xive_instance_init, 816 .instance_size = sizeof(SpaprXive), 817 .class_init = spapr_xive_class_init, 818 .class_size = sizeof(SpaprXiveClass), 819 .interfaces = (InterfaceInfo[]) { 820 { TYPE_SPAPR_INTC }, 821 { } 822 }, 823 }; 824 825 static void spapr_xive_register_types(void) 826 { 827 type_register_static(&spapr_xive_info); 828 } 829 830 type_init(spapr_xive_register_types) 831 832 /* 833 * XIVE hcalls 834 * 835 * The terminology used by the XIVE hcalls is the following : 836 * 837 * TARGET vCPU number 838 * EQ Event Queue assigned by OS to receive event data 839 * ESB page for source interrupt management 840 * LISN Logical Interrupt Source Number identifying a source in the 841 * machine 842 * EISN Effective Interrupt Source Number used by guest OS to 843 * identify source in the guest 844 * 845 * The EAS, END, NVT structures are not exposed. 846 */ 847 848 /* 849 * On POWER9, the KVM XIVE device uses priority 7 for the escalation 850 * interrupts. So we only allow the guest to use priorities [0..6]. 851 */ 852 static bool spapr_xive_priority_is_reserved(SpaprXive *xive, uint8_t priority) 853 { 854 return priority >= xive->hv_prio; 855 } 856 857 /* 858 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 859 * real address of the MMIO page through which the Event State Buffer 860 * entry associated with the value of the "lisn" parameter is managed. 861 * 862 * Parameters: 863 * Input 864 * - R4: "flags" 865 * Bits 0-63 reserved 866 * - R5: "lisn" is per "interrupts", "interrupt-map", or 867 * "ibm,xive-lisn-ranges" properties, or as returned by the 868 * ibm,query-interrupt-source-number RTAS call, or as returned 869 * by the H_ALLOCATE_VAS_WINDOW hcall 870 * 871 * Output 872 * - R4: "flags" 873 * Bits 0-59: Reserved 874 * Bit 60: H_INT_ESB must be used for Event State Buffer 875 * management 876 * Bit 61: 1 == LSI 0 == MSI 877 * Bit 62: the full function page supports trigger 878 * Bit 63: Store EOI Supported 879 * - R5: Logical Real address of full function Event State Buffer 880 * management page, -1 if H_INT_ESB hcall flag is set to 1. 881 * - R6: Logical Real Address of trigger only Event State Buffer 882 * management page or -1. 883 * - R7: Power of 2 page size for the ESB management pages returned in 884 * R5 and R6. 885 */ 886 887 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 888 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 889 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 890 on same page */ 891 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 892 893 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 894 SpaprMachineState *spapr, 895 target_ulong opcode, 896 target_ulong *args) 897 { 898 SpaprXive *xive = spapr->xive; 899 XiveSource *xsrc = &xive->source; 900 target_ulong flags = args[0]; 901 target_ulong lisn = args[1]; 902 903 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 904 return H_FUNCTION; 905 } 906 907 if (flags) { 908 return H_PARAMETER; 909 } 910 911 if (lisn >= xive->nr_irqs) { 912 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 913 lisn); 914 return H_P2; 915 } 916 917 if (!xive_eas_is_valid(&xive->eat[lisn])) { 918 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 919 lisn); 920 return H_P2; 921 } 922 923 /* 924 * All sources are emulated under the main XIVE object and share 925 * the same characteristics. 926 */ 927 args[0] = 0; 928 if (!xive_source_esb_has_2page(xsrc)) { 929 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 930 } 931 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 932 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 933 } 934 935 /* 936 * Force the use of the H_INT_ESB hcall in case of an LSI 937 * interrupt. This is necessary under KVM to re-trigger the 938 * interrupt if the level is still asserted 939 */ 940 if (xive_source_irq_is_lsi(xsrc, lisn)) { 941 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 942 } 943 944 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 945 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 946 } else { 947 args[1] = -1; 948 } 949 950 if (xive_source_esb_has_2page(xsrc) && 951 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 952 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 953 } else { 954 args[2] = -1; 955 } 956 957 if (xive_source_esb_has_2page(xsrc)) { 958 args[3] = xsrc->esb_shift - 1; 959 } else { 960 args[3] = xsrc->esb_shift; 961 } 962 963 return H_SUCCESS; 964 } 965 966 /* 967 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 968 * Interrupt Source to a target. The Logical Interrupt Source is 969 * designated with the "lisn" parameter and the target is designated 970 * with the "target" and "priority" parameters. Upon return from the 971 * hcall(), no additional interrupts will be directed to the old EQ. 972 * 973 * Parameters: 974 * Input: 975 * - R4: "flags" 976 * Bits 0-61: Reserved 977 * Bit 62: set the "eisn" in the EAS 978 * Bit 63: masks the interrupt source in the hardware interrupt 979 * control structure. An interrupt masked by this mechanism will 980 * be dropped, but it's source state bits will still be 981 * set. There is no race-free way of unmasking and restoring the 982 * source. Thus this should only be used in interrupts that are 983 * also masked at the source, and only in cases where the 984 * interrupt is not meant to be used for a large amount of time 985 * because no valid target exists for it for example 986 * - R5: "lisn" is per "interrupts", "interrupt-map", or 987 * "ibm,xive-lisn-ranges" properties, or as returned by the 988 * ibm,query-interrupt-source-number RTAS call, or as returned by 989 * the H_ALLOCATE_VAS_WINDOW hcall 990 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 991 * "ibm,ppc-interrupt-gserver#s" 992 * - R7: "priority" is a valid priority not in 993 * "ibm,plat-res-int-priorities" 994 * - R8: "eisn" is the guest EISN associated with the "lisn" 995 * 996 * Output: 997 * - None 998 */ 999 1000 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 1001 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 1002 1003 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 1004 SpaprMachineState *spapr, 1005 target_ulong opcode, 1006 target_ulong *args) 1007 { 1008 SpaprXive *xive = spapr->xive; 1009 XiveEAS eas, new_eas; 1010 target_ulong flags = args[0]; 1011 target_ulong lisn = args[1]; 1012 target_ulong target = args[2]; 1013 target_ulong priority = args[3]; 1014 target_ulong eisn = args[4]; 1015 uint8_t end_blk; 1016 uint32_t end_idx; 1017 1018 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1019 return H_FUNCTION; 1020 } 1021 1022 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 1023 return H_PARAMETER; 1024 } 1025 1026 if (lisn >= xive->nr_irqs) { 1027 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1028 lisn); 1029 return H_P2; 1030 } 1031 1032 eas = xive->eat[lisn]; 1033 if (!xive_eas_is_valid(&eas)) { 1034 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1035 lisn); 1036 return H_P2; 1037 } 1038 1039 /* priority 0xff is used to reset the EAS */ 1040 if (priority == 0xff) { 1041 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 1042 goto out; 1043 } 1044 1045 if (flags & SPAPR_XIVE_SRC_MASK) { 1046 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 1047 } else { 1048 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 1049 } 1050 1051 if (spapr_xive_priority_is_reserved(xive, priority)) { 1052 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1053 " is reserved\n", priority); 1054 return H_P4; 1055 } 1056 1057 /* 1058 * Validate that "target" is part of the list of threads allocated 1059 * to the partition. For that, find the END corresponding to the 1060 * target. 1061 */ 1062 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1063 return H_P3; 1064 } 1065 1066 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 1067 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 1068 1069 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 1070 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 1071 } 1072 1073 if (spapr_xive_in_kernel(xive)) { 1074 Error *local_err = NULL; 1075 1076 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 1077 if (local_err) { 1078 error_report_err(local_err); 1079 return H_HARDWARE; 1080 } 1081 } 1082 1083 out: 1084 xive->eat[lisn] = new_eas; 1085 return H_SUCCESS; 1086 } 1087 1088 /* 1089 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1090 * target/priority pair is assigned to the specified Logical Interrupt 1091 * Source. 1092 * 1093 * Parameters: 1094 * Input: 1095 * - R4: "flags" 1096 * Bits 0-63 Reserved 1097 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1098 * "ibm,xive-lisn-ranges" properties, or as returned by the 1099 * ibm,query-interrupt-source-number RTAS call, or as 1100 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1101 * 1102 * Output: 1103 * - R4: Target to which the specified Logical Interrupt Source is 1104 * assigned 1105 * - R5: Priority to which the specified Logical Interrupt Source is 1106 * assigned 1107 * - R6: EISN for the specified Logical Interrupt Source (this will be 1108 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1109 */ 1110 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1111 SpaprMachineState *spapr, 1112 target_ulong opcode, 1113 target_ulong *args) 1114 { 1115 SpaprXive *xive = spapr->xive; 1116 target_ulong flags = args[0]; 1117 target_ulong lisn = args[1]; 1118 XiveEAS eas; 1119 XiveEND *end; 1120 uint8_t nvt_blk; 1121 uint32_t end_idx, nvt_idx; 1122 1123 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1124 return H_FUNCTION; 1125 } 1126 1127 if (flags) { 1128 return H_PARAMETER; 1129 } 1130 1131 if (lisn >= xive->nr_irqs) { 1132 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1133 lisn); 1134 return H_P2; 1135 } 1136 1137 eas = xive->eat[lisn]; 1138 if (!xive_eas_is_valid(&eas)) { 1139 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1140 lisn); 1141 return H_P2; 1142 } 1143 1144 /* EAS_END_BLOCK is unused on sPAPR */ 1145 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1146 1147 assert(end_idx < xive->nr_ends); 1148 end = &xive->endt[end_idx]; 1149 1150 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1151 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1152 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1153 1154 if (xive_eas_is_masked(&eas)) { 1155 args[1] = 0xff; 1156 } else { 1157 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1158 } 1159 1160 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1161 1162 return H_SUCCESS; 1163 } 1164 1165 /* 1166 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1167 * address of the notification management page associated with the 1168 * specified target and priority. 1169 * 1170 * Parameters: 1171 * Input: 1172 * - R4: "flags" 1173 * Bits 0-63 Reserved 1174 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1175 * "ibm,ppc-interrupt-gserver#s" 1176 * - R6: "priority" is a valid priority not in 1177 * "ibm,plat-res-int-priorities" 1178 * 1179 * Output: 1180 * - R4: Logical real address of notification page 1181 * - R5: Power of 2 page size of the notification page 1182 */ 1183 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1184 SpaprMachineState *spapr, 1185 target_ulong opcode, 1186 target_ulong *args) 1187 { 1188 SpaprXive *xive = spapr->xive; 1189 XiveENDSource *end_xsrc = &xive->end_source; 1190 target_ulong flags = args[0]; 1191 target_ulong target = args[1]; 1192 target_ulong priority = args[2]; 1193 XiveEND *end; 1194 uint8_t end_blk; 1195 uint32_t end_idx; 1196 1197 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1198 return H_FUNCTION; 1199 } 1200 1201 if (flags) { 1202 return H_PARAMETER; 1203 } 1204 1205 /* 1206 * H_STATE should be returned if a H_INT_RESET is in progress. 1207 * This is not needed when running the emulation under QEMU 1208 */ 1209 1210 if (spapr_xive_priority_is_reserved(xive, priority)) { 1211 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1212 " is reserved\n", priority); 1213 return H_P3; 1214 } 1215 1216 /* 1217 * Validate that "target" is part of the list of threads allocated 1218 * to the partition. For that, find the END corresponding to the 1219 * target. 1220 */ 1221 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1222 return H_P2; 1223 } 1224 1225 assert(end_idx < xive->nr_ends); 1226 end = &xive->endt[end_idx]; 1227 1228 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1229 if (xive_end_is_enqueue(end)) { 1230 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1231 } else { 1232 args[1] = 0; 1233 } 1234 1235 return H_SUCCESS; 1236 } 1237 1238 /* 1239 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1240 * a given "target" and "priority". It is also used to set the 1241 * notification config associated with the EQ. An EQ size of 0 is 1242 * used to reset the EQ config for a given target and priority. If 1243 * resetting the EQ config, the END associated with the given "target" 1244 * and "priority" will be changed to disable queueing. 1245 * 1246 * Upon return from the hcall(), no additional interrupts will be 1247 * directed to the old EQ (if one was set). The old EQ (if one was 1248 * set) should be investigated for interrupts that occurred prior to 1249 * or during the hcall(). 1250 * 1251 * Parameters: 1252 * Input: 1253 * - R4: "flags" 1254 * Bits 0-62: Reserved 1255 * Bit 63: Unconditional Notify (n) per the XIVE spec 1256 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1257 * "ibm,ppc-interrupt-gserver#s" 1258 * - R6: "priority" is a valid priority not in 1259 * "ibm,plat-res-int-priorities" 1260 * - R7: "eventQueue": The logical real address of the start of the EQ 1261 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1262 * 1263 * Output: 1264 * - None 1265 */ 1266 1267 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1268 1269 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1270 SpaprMachineState *spapr, 1271 target_ulong opcode, 1272 target_ulong *args) 1273 { 1274 SpaprXive *xive = spapr->xive; 1275 target_ulong flags = args[0]; 1276 target_ulong target = args[1]; 1277 target_ulong priority = args[2]; 1278 target_ulong qpage = args[3]; 1279 target_ulong qsize = args[4]; 1280 XiveEND end; 1281 uint8_t end_blk, nvt_blk; 1282 uint32_t end_idx, nvt_idx; 1283 1284 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1285 return H_FUNCTION; 1286 } 1287 1288 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1289 return H_PARAMETER; 1290 } 1291 1292 /* 1293 * H_STATE should be returned if a H_INT_RESET is in progress. 1294 * This is not needed when running the emulation under QEMU 1295 */ 1296 1297 if (spapr_xive_priority_is_reserved(xive, priority)) { 1298 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1299 " is reserved\n", priority); 1300 return H_P3; 1301 } 1302 1303 /* 1304 * Validate that "target" is part of the list of threads allocated 1305 * to the partition. For that, find the END corresponding to the 1306 * target. 1307 */ 1308 1309 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1310 return H_P2; 1311 } 1312 1313 assert(end_idx < xive->nr_ends); 1314 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1315 1316 switch (qsize) { 1317 case 12: 1318 case 16: 1319 case 21: 1320 case 24: 1321 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1322 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1323 " is not naturally aligned with %" HWADDR_PRIx "\n", 1324 qpage, (hwaddr)1 << qsize); 1325 return H_P4; 1326 } 1327 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1328 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1329 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1330 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1331 break; 1332 case 0: 1333 /* reset queue and disable queueing */ 1334 spapr_xive_end_reset(&end); 1335 goto out; 1336 1337 default: 1338 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1339 qsize); 1340 return H_P5; 1341 } 1342 1343 if (qsize) { 1344 hwaddr plen = 1 << qsize; 1345 void *eq; 1346 1347 /* 1348 * Validate the guest EQ. We should also check that the queue 1349 * has been zeroed by the OS. 1350 */ 1351 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1352 MEMTXATTRS_UNSPECIFIED); 1353 if (plen != 1 << qsize) { 1354 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1355 HWADDR_PRIx "\n", qpage); 1356 return H_P4; 1357 } 1358 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1359 } 1360 1361 /* "target" should have been validated above */ 1362 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1363 g_assert_not_reached(); 1364 } 1365 1366 /* 1367 * Ensure the priority and target are correctly set (they will not 1368 * be right after allocation) 1369 */ 1370 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1371 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1372 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1373 1374 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1375 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1376 } else { 1377 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1378 } 1379 1380 /* 1381 * The generation bit for the END starts at 1 and The END page 1382 * offset counter starts at 0. 1383 */ 1384 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1385 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1386 end.w0 |= cpu_to_be32(END_W0_VALID); 1387 1388 /* 1389 * TODO: issue syncs required to ensure all in-flight interrupts 1390 * are complete on the old END 1391 */ 1392 1393 out: 1394 if (spapr_xive_in_kernel(xive)) { 1395 Error *local_err = NULL; 1396 1397 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1398 if (local_err) { 1399 error_report_err(local_err); 1400 return H_HARDWARE; 1401 } 1402 } 1403 1404 /* Update END */ 1405 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1406 return H_SUCCESS; 1407 } 1408 1409 /* 1410 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1411 * target and priority. 1412 * 1413 * Parameters: 1414 * Input: 1415 * - R4: "flags" 1416 * Bits 0-62: Reserved 1417 * Bit 63: Debug: Return debug data 1418 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1419 * "ibm,ppc-interrupt-gserver#s" 1420 * - R6: "priority" is a valid priority not in 1421 * "ibm,plat-res-int-priorities" 1422 * 1423 * Output: 1424 * - R4: "flags": 1425 * Bits 0-61: Reserved 1426 * Bit 62: The value of Event Queue Generation Number (g) per 1427 * the XIVE spec if "Debug" = 1 1428 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1429 * - R5: The logical real address of the start of the EQ 1430 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1431 * - R7: The value of Event Queue Offset Counter per XIVE spec 1432 * if "Debug" = 1, else 0 1433 * 1434 */ 1435 1436 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1437 1438 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1439 SpaprMachineState *spapr, 1440 target_ulong opcode, 1441 target_ulong *args) 1442 { 1443 SpaprXive *xive = spapr->xive; 1444 target_ulong flags = args[0]; 1445 target_ulong target = args[1]; 1446 target_ulong priority = args[2]; 1447 XiveEND *end; 1448 uint8_t end_blk; 1449 uint32_t end_idx; 1450 1451 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1452 return H_FUNCTION; 1453 } 1454 1455 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1456 return H_PARAMETER; 1457 } 1458 1459 /* 1460 * H_STATE should be returned if a H_INT_RESET is in progress. 1461 * This is not needed when running the emulation under QEMU 1462 */ 1463 1464 if (spapr_xive_priority_is_reserved(xive, priority)) { 1465 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1466 " is reserved\n", priority); 1467 return H_P3; 1468 } 1469 1470 /* 1471 * Validate that "target" is part of the list of threads allocated 1472 * to the partition. For that, find the END corresponding to the 1473 * target. 1474 */ 1475 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1476 return H_P2; 1477 } 1478 1479 assert(end_idx < xive->nr_ends); 1480 end = &xive->endt[end_idx]; 1481 1482 args[0] = 0; 1483 if (xive_end_is_notify(end)) { 1484 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1485 } 1486 1487 if (xive_end_is_enqueue(end)) { 1488 args[1] = xive_end_qaddr(end); 1489 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1490 } else { 1491 args[1] = 0; 1492 args[2] = 0; 1493 } 1494 1495 if (spapr_xive_in_kernel(xive)) { 1496 Error *local_err = NULL; 1497 1498 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1499 if (local_err) { 1500 error_report_err(local_err); 1501 return H_HARDWARE; 1502 } 1503 } 1504 1505 /* TODO: do we need any locking on the END ? */ 1506 if (flags & SPAPR_XIVE_END_DEBUG) { 1507 /* Load the event queue generation number into the return flags */ 1508 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1509 1510 /* Load R7 with the event queue offset counter */ 1511 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1512 } else { 1513 args[3] = 0; 1514 } 1515 1516 return H_SUCCESS; 1517 } 1518 1519 /* 1520 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1521 * reporting cache line pair for the calling thread. The reporting 1522 * cache lines will contain the OS interrupt context when the OS 1523 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1524 * interrupt. The reporting cache lines can be reset by inputting -1 1525 * in "reportingLine". Issuing the CI store byte without reporting 1526 * cache lines registered will result in the data not being accessible 1527 * to the OS. 1528 * 1529 * Parameters: 1530 * Input: 1531 * - R4: "flags" 1532 * Bits 0-63: Reserved 1533 * - R5: "reportingLine": The logical real address of the reporting cache 1534 * line pair 1535 * 1536 * Output: 1537 * - None 1538 */ 1539 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1540 SpaprMachineState *spapr, 1541 target_ulong opcode, 1542 target_ulong *args) 1543 { 1544 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1545 return H_FUNCTION; 1546 } 1547 1548 /* 1549 * H_STATE should be returned if a H_INT_RESET is in progress. 1550 * This is not needed when running the emulation under QEMU 1551 */ 1552 1553 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1554 return H_FUNCTION; 1555 } 1556 1557 /* 1558 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1559 * real address of the reporting cache line pair set for the input 1560 * "target". If no reporting cache line pair has been set, -1 is 1561 * returned. 1562 * 1563 * Parameters: 1564 * Input: 1565 * - R4: "flags" 1566 * Bits 0-63: Reserved 1567 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1568 * "ibm,ppc-interrupt-gserver#s" 1569 * - R6: "reportingLine": The logical real address of the reporting 1570 * cache line pair 1571 * 1572 * Output: 1573 * - R4: The logical real address of the reporting line if set, else -1 1574 */ 1575 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1576 SpaprMachineState *spapr, 1577 target_ulong opcode, 1578 target_ulong *args) 1579 { 1580 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1581 return H_FUNCTION; 1582 } 1583 1584 /* 1585 * H_STATE should be returned if a H_INT_RESET is in progress. 1586 * This is not needed when running the emulation under QEMU 1587 */ 1588 1589 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1590 return H_FUNCTION; 1591 } 1592 1593 /* 1594 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1595 * page for the input "lisn". This hcall is only supported for LISNs 1596 * that have the ESB hcall flag set to 1 when returned from hcall() 1597 * H_INT_GET_SOURCE_INFO. 1598 * 1599 * Parameters: 1600 * Input: 1601 * - R4: "flags" 1602 * Bits 0-62: Reserved 1603 * bit 63: Store: Store=1, store operation, else load operation 1604 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1605 * "ibm,xive-lisn-ranges" properties, or as returned by the 1606 * ibm,query-interrupt-source-number RTAS call, or as 1607 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1608 * - R6: "esbOffset" is the offset into the ESB page for the load or 1609 * store operation 1610 * - R7: "storeData" is the data to write for a store operation 1611 * 1612 * Output: 1613 * - R4: The value of the load if load operation, else -1 1614 */ 1615 1616 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1617 1618 static target_ulong h_int_esb(PowerPCCPU *cpu, 1619 SpaprMachineState *spapr, 1620 target_ulong opcode, 1621 target_ulong *args) 1622 { 1623 SpaprXive *xive = spapr->xive; 1624 XiveEAS eas; 1625 target_ulong flags = args[0]; 1626 target_ulong lisn = args[1]; 1627 target_ulong offset = args[2]; 1628 target_ulong data = args[3]; 1629 hwaddr mmio_addr; 1630 XiveSource *xsrc = &xive->source; 1631 1632 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1633 return H_FUNCTION; 1634 } 1635 1636 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1637 return H_PARAMETER; 1638 } 1639 1640 if (lisn >= xive->nr_irqs) { 1641 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1642 lisn); 1643 return H_P2; 1644 } 1645 1646 eas = xive->eat[lisn]; 1647 if (!xive_eas_is_valid(&eas)) { 1648 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1649 lisn); 1650 return H_P2; 1651 } 1652 1653 if (offset > (1ull << xsrc->esb_shift)) { 1654 return H_P3; 1655 } 1656 1657 if (spapr_xive_in_kernel(xive)) { 1658 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1659 flags & SPAPR_XIVE_ESB_STORE); 1660 } else { 1661 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1662 1663 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1664 (flags & SPAPR_XIVE_ESB_STORE))) { 1665 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1666 HWADDR_PRIx "\n", mmio_addr); 1667 return H_HARDWARE; 1668 } 1669 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1670 } 1671 return H_SUCCESS; 1672 } 1673 1674 /* 1675 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1676 * ensure any in flight events for the input lisn are in the event 1677 * queue. 1678 * 1679 * Parameters: 1680 * Input: 1681 * - R4: "flags" 1682 * Bits 0-63: Reserved 1683 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1684 * "ibm,xive-lisn-ranges" properties, or as returned by the 1685 * ibm,query-interrupt-source-number RTAS call, or as 1686 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1687 * 1688 * Output: 1689 * - None 1690 */ 1691 static target_ulong h_int_sync(PowerPCCPU *cpu, 1692 SpaprMachineState *spapr, 1693 target_ulong opcode, 1694 target_ulong *args) 1695 { 1696 SpaprXive *xive = spapr->xive; 1697 XiveEAS eas; 1698 target_ulong flags = args[0]; 1699 target_ulong lisn = args[1]; 1700 1701 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1702 return H_FUNCTION; 1703 } 1704 1705 if (flags) { 1706 return H_PARAMETER; 1707 } 1708 1709 if (lisn >= xive->nr_irqs) { 1710 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1711 lisn); 1712 return H_P2; 1713 } 1714 1715 eas = xive->eat[lisn]; 1716 if (!xive_eas_is_valid(&eas)) { 1717 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1718 lisn); 1719 return H_P2; 1720 } 1721 1722 /* 1723 * H_STATE should be returned if a H_INT_RESET is in progress. 1724 * This is not needed when running the emulation under QEMU 1725 */ 1726 1727 /* 1728 * This is not real hardware. Nothing to be done unless when 1729 * under KVM 1730 */ 1731 1732 if (spapr_xive_in_kernel(xive)) { 1733 Error *local_err = NULL; 1734 1735 kvmppc_xive_sync_source(xive, lisn, &local_err); 1736 if (local_err) { 1737 error_report_err(local_err); 1738 return H_HARDWARE; 1739 } 1740 } 1741 return H_SUCCESS; 1742 } 1743 1744 /* 1745 * The H_INT_RESET hcall() is used to reset all of the partition's 1746 * interrupt exploitation structures to their initial state. This 1747 * means losing all previously set interrupt state set via 1748 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1749 * 1750 * Parameters: 1751 * Input: 1752 * - R4: "flags" 1753 * Bits 0-63: Reserved 1754 * 1755 * Output: 1756 * - None 1757 */ 1758 static target_ulong h_int_reset(PowerPCCPU *cpu, 1759 SpaprMachineState *spapr, 1760 target_ulong opcode, 1761 target_ulong *args) 1762 { 1763 SpaprXive *xive = spapr->xive; 1764 target_ulong flags = args[0]; 1765 1766 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1767 return H_FUNCTION; 1768 } 1769 1770 if (flags) { 1771 return H_PARAMETER; 1772 } 1773 1774 device_legacy_reset(DEVICE(xive)); 1775 1776 if (spapr_xive_in_kernel(xive)) { 1777 Error *local_err = NULL; 1778 1779 kvmppc_xive_reset(xive, &local_err); 1780 if (local_err) { 1781 error_report_err(local_err); 1782 return H_HARDWARE; 1783 } 1784 } 1785 return H_SUCCESS; 1786 } 1787 1788 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1789 { 1790 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1791 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1792 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1793 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1794 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1795 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1796 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1797 h_int_set_os_reporting_line); 1798 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1799 h_int_get_os_reporting_line); 1800 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1801 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1802 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1803 } 1804