1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "qemu-common.h" 31 #include "cpu.h" 32 #include "hw/hw.h" 33 #include "trace.h" 34 #include "qemu/timer.h" 35 #include "hw/ppc/xics.h" 36 #include "qemu/error-report.h" 37 #include "qapi/visitor.h" 38 #include "monitor/monitor.h" 39 #include "hw/intc/intc.h" 40 41 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) 42 { 43 CPUState *cs = CPU(cpu); 44 ICPState *icp = ICP(cpu->intc); 45 46 assert(icp); 47 assert(cs == icp->cs); 48 49 icp->output = NULL; 50 icp->cs = NULL; 51 } 52 53 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp) 54 { 55 CPUState *cs = CPU(cpu); 56 CPUPPCState *env = &cpu->env; 57 ICPStateClass *icpc; 58 59 assert(icp); 60 61 cpu->intc = OBJECT(icp); 62 icp->cs = cs; 63 64 icpc = ICP_GET_CLASS(icp); 65 if (icpc->cpu_setup) { 66 icpc->cpu_setup(icp, cpu); 67 } 68 69 switch (PPC_INPUT(env)) { 70 case PPC_FLAGS_INPUT_POWER7: 71 icp->output = env->irq_inputs[POWER7_INPUT_INT]; 72 break; 73 74 case PPC_FLAGS_INPUT_970: 75 icp->output = env->irq_inputs[PPC970_INPUT_INT]; 76 break; 77 78 default: 79 error_report("XICS interrupt controller does not support this CPU " 80 "bus model"); 81 abort(); 82 } 83 } 84 85 void icp_pic_print_info(ICPState *icp, Monitor *mon) 86 { 87 int cpu_index = icp->cs ? icp->cs->cpu_index : -1; 88 89 if (!icp->output) { 90 return; 91 } 92 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", 93 cpu_index, icp->xirr, icp->xirr_owner, 94 icp->pending_priority, icp->mfrr); 95 } 96 97 void ics_pic_print_info(ICSState *ics, Monitor *mon) 98 { 99 uint32_t i; 100 101 monitor_printf(mon, "ICS %4x..%4x %p\n", 102 ics->offset, ics->offset + ics->nr_irqs - 1, ics); 103 104 if (!ics->irqs) { 105 return; 106 } 107 108 for (i = 0; i < ics->nr_irqs; i++) { 109 ICSIRQState *irq = ics->irqs + i; 110 111 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { 112 continue; 113 } 114 monitor_printf(mon, " %4x %s %02x %02x\n", 115 ics->offset + i, 116 (irq->flags & XICS_FLAGS_IRQ_LSI) ? 117 "LSI" : "MSI", 118 irq->priority, irq->status); 119 } 120 } 121 122 /* 123 * ICP: Presentation layer 124 */ 125 126 #define XISR_MASK 0x00ffffff 127 #define CPPR_MASK 0xff000000 128 129 #define XISR(icp) (((icp)->xirr) & XISR_MASK) 130 #define CPPR(icp) (((icp)->xirr) >> 24) 131 132 static void ics_reject(ICSState *ics, uint32_t nr) 133 { 134 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 135 136 if (k->reject) { 137 k->reject(ics, nr); 138 } 139 } 140 141 void ics_resend(ICSState *ics) 142 { 143 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 144 145 if (k->resend) { 146 k->resend(ics); 147 } 148 } 149 150 static void ics_eoi(ICSState *ics, int nr) 151 { 152 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 153 154 if (k->eoi) { 155 k->eoi(ics, nr); 156 } 157 } 158 159 static void icp_check_ipi(ICPState *icp) 160 { 161 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { 162 return; 163 } 164 165 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); 166 167 if (XISR(icp) && icp->xirr_owner) { 168 ics_reject(icp->xirr_owner, XISR(icp)); 169 } 170 171 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; 172 icp->pending_priority = icp->mfrr; 173 icp->xirr_owner = NULL; 174 qemu_irq_raise(icp->output); 175 } 176 177 void icp_resend(ICPState *icp) 178 { 179 XICSFabric *xi = icp->xics; 180 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 181 182 if (icp->mfrr < CPPR(icp)) { 183 icp_check_ipi(icp); 184 } 185 186 xic->ics_resend(xi); 187 } 188 189 void icp_set_cppr(ICPState *icp, uint8_t cppr) 190 { 191 uint8_t old_cppr; 192 uint32_t old_xisr; 193 194 old_cppr = CPPR(icp); 195 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); 196 197 if (cppr < old_cppr) { 198 if (XISR(icp) && (cppr <= icp->pending_priority)) { 199 old_xisr = XISR(icp); 200 icp->xirr &= ~XISR_MASK; /* Clear XISR */ 201 icp->pending_priority = 0xff; 202 qemu_irq_lower(icp->output); 203 if (icp->xirr_owner) { 204 ics_reject(icp->xirr_owner, old_xisr); 205 icp->xirr_owner = NULL; 206 } 207 } 208 } else { 209 if (!XISR(icp)) { 210 icp_resend(icp); 211 } 212 } 213 } 214 215 void icp_set_mfrr(ICPState *icp, uint8_t mfrr) 216 { 217 icp->mfrr = mfrr; 218 if (mfrr < CPPR(icp)) { 219 icp_check_ipi(icp); 220 } 221 } 222 223 uint32_t icp_accept(ICPState *icp) 224 { 225 uint32_t xirr = icp->xirr; 226 227 qemu_irq_lower(icp->output); 228 icp->xirr = icp->pending_priority << 24; 229 icp->pending_priority = 0xff; 230 icp->xirr_owner = NULL; 231 232 trace_xics_icp_accept(xirr, icp->xirr); 233 234 return xirr; 235 } 236 237 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) 238 { 239 if (mfrr) { 240 *mfrr = icp->mfrr; 241 } 242 return icp->xirr; 243 } 244 245 void icp_eoi(ICPState *icp, uint32_t xirr) 246 { 247 XICSFabric *xi = icp->xics; 248 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 249 ICSState *ics; 250 uint32_t irq; 251 252 /* Send EOI -> ICS */ 253 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); 254 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); 255 irq = xirr & XISR_MASK; 256 257 ics = xic->ics_get(xi, irq); 258 if (ics) { 259 ics_eoi(ics, irq); 260 } 261 if (!XISR(icp)) { 262 icp_resend(icp); 263 } 264 } 265 266 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) 267 { 268 ICPState *icp = xics_icp_get(ics->xics, server); 269 270 trace_xics_icp_irq(server, nr, priority); 271 272 if ((priority >= CPPR(icp)) 273 || (XISR(icp) && (icp->pending_priority <= priority))) { 274 ics_reject(ics, nr); 275 } else { 276 if (XISR(icp) && icp->xirr_owner) { 277 ics_reject(icp->xirr_owner, XISR(icp)); 278 icp->xirr_owner = NULL; 279 } 280 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); 281 icp->xirr_owner = ics; 282 icp->pending_priority = priority; 283 trace_xics_icp_raise(icp->xirr, icp->pending_priority); 284 qemu_irq_raise(icp->output); 285 } 286 } 287 288 static void icp_dispatch_pre_save(void *opaque) 289 { 290 ICPState *icp = opaque; 291 ICPStateClass *info = ICP_GET_CLASS(icp); 292 293 if (info->pre_save) { 294 info->pre_save(icp); 295 } 296 } 297 298 static int icp_dispatch_post_load(void *opaque, int version_id) 299 { 300 ICPState *icp = opaque; 301 ICPStateClass *info = ICP_GET_CLASS(icp); 302 303 if (info->post_load) { 304 return info->post_load(icp, version_id); 305 } 306 307 return 0; 308 } 309 310 static const VMStateDescription vmstate_icp_server = { 311 .name = "icp/server", 312 .version_id = 1, 313 .minimum_version_id = 1, 314 .pre_save = icp_dispatch_pre_save, 315 .post_load = icp_dispatch_post_load, 316 .fields = (VMStateField[]) { 317 /* Sanity check */ 318 VMSTATE_UINT32(xirr, ICPState), 319 VMSTATE_UINT8(pending_priority, ICPState), 320 VMSTATE_UINT8(mfrr, ICPState), 321 VMSTATE_END_OF_LIST() 322 }, 323 }; 324 325 static void icp_reset(void *dev) 326 { 327 ICPState *icp = ICP(dev); 328 329 icp->xirr = 0; 330 icp->pending_priority = 0xff; 331 icp->mfrr = 0xff; 332 333 /* Make all outputs are deasserted */ 334 qemu_set_irq(icp->output, 0); 335 } 336 337 static void icp_realize(DeviceState *dev, Error **errp) 338 { 339 ICPState *icp = ICP(dev); 340 ICPStateClass *icpc = ICP_GET_CLASS(dev); 341 Object *obj; 342 Error *err = NULL; 343 344 obj = object_property_get_link(OBJECT(dev), "xics", &err); 345 if (!obj) { 346 error_setg(errp, "%s: required link 'xics' not found: %s", 347 __func__, error_get_pretty(err)); 348 return; 349 } 350 351 icp->xics = XICS_FABRIC(obj); 352 353 if (icpc->realize) { 354 icpc->realize(dev, errp); 355 } 356 357 qemu_register_reset(icp_reset, dev); 358 } 359 360 static void icp_unrealize(DeviceState *dev, Error **errp) 361 { 362 qemu_unregister_reset(icp_reset, dev); 363 } 364 365 static void icp_class_init(ObjectClass *klass, void *data) 366 { 367 DeviceClass *dc = DEVICE_CLASS(klass); 368 369 dc->vmsd = &vmstate_icp_server; 370 dc->realize = icp_realize; 371 dc->unrealize = icp_unrealize; 372 } 373 374 static const TypeInfo icp_info = { 375 .name = TYPE_ICP, 376 .parent = TYPE_DEVICE, 377 .instance_size = sizeof(ICPState), 378 .class_init = icp_class_init, 379 .class_size = sizeof(ICPStateClass), 380 }; 381 382 /* 383 * ICS: Source layer 384 */ 385 static void ics_simple_resend_msi(ICSState *ics, int srcno) 386 { 387 ICSIRQState *irq = ics->irqs + srcno; 388 389 /* FIXME: filter by server#? */ 390 if (irq->status & XICS_STATUS_REJECTED) { 391 irq->status &= ~XICS_STATUS_REJECTED; 392 if (irq->priority != 0xff) { 393 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 394 } 395 } 396 } 397 398 static void ics_simple_resend_lsi(ICSState *ics, int srcno) 399 { 400 ICSIRQState *irq = ics->irqs + srcno; 401 402 if ((irq->priority != 0xff) 403 && (irq->status & XICS_STATUS_ASSERTED) 404 && !(irq->status & XICS_STATUS_SENT)) { 405 irq->status |= XICS_STATUS_SENT; 406 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 407 } 408 } 409 410 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val) 411 { 412 ICSIRQState *irq = ics->irqs + srcno; 413 414 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset); 415 416 if (val) { 417 if (irq->priority == 0xff) { 418 irq->status |= XICS_STATUS_MASKED_PENDING; 419 trace_xics_masked_pending(); 420 } else { 421 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 422 } 423 } 424 } 425 426 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val) 427 { 428 ICSIRQState *irq = ics->irqs + srcno; 429 430 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset); 431 if (val) { 432 irq->status |= XICS_STATUS_ASSERTED; 433 } else { 434 irq->status &= ~XICS_STATUS_ASSERTED; 435 } 436 ics_simple_resend_lsi(ics, srcno); 437 } 438 439 static void ics_simple_set_irq(void *opaque, int srcno, int val) 440 { 441 ICSState *ics = (ICSState *)opaque; 442 443 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 444 ics_simple_set_irq_lsi(ics, srcno, val); 445 } else { 446 ics_simple_set_irq_msi(ics, srcno, val); 447 } 448 } 449 450 static void ics_simple_write_xive_msi(ICSState *ics, int srcno) 451 { 452 ICSIRQState *irq = ics->irqs + srcno; 453 454 if (!(irq->status & XICS_STATUS_MASKED_PENDING) 455 || (irq->priority == 0xff)) { 456 return; 457 } 458 459 irq->status &= ~XICS_STATUS_MASKED_PENDING; 460 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 461 } 462 463 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno) 464 { 465 ics_simple_resend_lsi(ics, srcno); 466 } 467 468 void ics_simple_write_xive(ICSState *ics, int srcno, int server, 469 uint8_t priority, uint8_t saved_priority) 470 { 471 ICSIRQState *irq = ics->irqs + srcno; 472 473 irq->server = server; 474 irq->priority = priority; 475 irq->saved_priority = saved_priority; 476 477 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server, 478 priority); 479 480 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 481 ics_simple_write_xive_lsi(ics, srcno); 482 } else { 483 ics_simple_write_xive_msi(ics, srcno); 484 } 485 } 486 487 static void ics_simple_reject(ICSState *ics, uint32_t nr) 488 { 489 ICSIRQState *irq = ics->irqs + nr - ics->offset; 490 491 trace_xics_ics_simple_reject(nr, nr - ics->offset); 492 if (irq->flags & XICS_FLAGS_IRQ_MSI) { 493 irq->status |= XICS_STATUS_REJECTED; 494 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { 495 irq->status &= ~XICS_STATUS_SENT; 496 } 497 } 498 499 static void ics_simple_resend(ICSState *ics) 500 { 501 int i; 502 503 for (i = 0; i < ics->nr_irqs; i++) { 504 /* FIXME: filter by server#? */ 505 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { 506 ics_simple_resend_lsi(ics, i); 507 } else { 508 ics_simple_resend_msi(ics, i); 509 } 510 } 511 } 512 513 static void ics_simple_eoi(ICSState *ics, uint32_t nr) 514 { 515 int srcno = nr - ics->offset; 516 ICSIRQState *irq = ics->irqs + srcno; 517 518 trace_xics_ics_simple_eoi(nr); 519 520 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 521 irq->status &= ~XICS_STATUS_SENT; 522 } 523 } 524 525 static void ics_simple_reset(void *dev) 526 { 527 ICSState *ics = ICS_SIMPLE(dev); 528 int i; 529 uint8_t flags[ics->nr_irqs]; 530 531 for (i = 0; i < ics->nr_irqs; i++) { 532 flags[i] = ics->irqs[i].flags; 533 } 534 535 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); 536 537 for (i = 0; i < ics->nr_irqs; i++) { 538 ics->irqs[i].priority = 0xff; 539 ics->irqs[i].saved_priority = 0xff; 540 ics->irqs[i].flags = flags[i]; 541 } 542 } 543 544 static void ics_simple_dispatch_pre_save(void *opaque) 545 { 546 ICSState *ics = opaque; 547 ICSStateClass *info = ICS_BASE_GET_CLASS(ics); 548 549 if (info->pre_save) { 550 info->pre_save(ics); 551 } 552 } 553 554 static int ics_simple_dispatch_post_load(void *opaque, int version_id) 555 { 556 ICSState *ics = opaque; 557 ICSStateClass *info = ICS_BASE_GET_CLASS(ics); 558 559 if (info->post_load) { 560 return info->post_load(ics, version_id); 561 } 562 563 return 0; 564 } 565 566 static const VMStateDescription vmstate_ics_simple_irq = { 567 .name = "ics/irq", 568 .version_id = 2, 569 .minimum_version_id = 1, 570 .fields = (VMStateField[]) { 571 VMSTATE_UINT32(server, ICSIRQState), 572 VMSTATE_UINT8(priority, ICSIRQState), 573 VMSTATE_UINT8(saved_priority, ICSIRQState), 574 VMSTATE_UINT8(status, ICSIRQState), 575 VMSTATE_UINT8(flags, ICSIRQState), 576 VMSTATE_END_OF_LIST() 577 }, 578 }; 579 580 static const VMStateDescription vmstate_ics_simple = { 581 .name = "ics", 582 .version_id = 1, 583 .minimum_version_id = 1, 584 .pre_save = ics_simple_dispatch_pre_save, 585 .post_load = ics_simple_dispatch_post_load, 586 .fields = (VMStateField[]) { 587 /* Sanity check */ 588 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), 589 590 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, 591 vmstate_ics_simple_irq, 592 ICSIRQState), 593 VMSTATE_END_OF_LIST() 594 }, 595 }; 596 597 static void ics_simple_initfn(Object *obj) 598 { 599 ICSState *ics = ICS_SIMPLE(obj); 600 601 ics->offset = XICS_IRQ_BASE; 602 } 603 604 static void ics_simple_realize(DeviceState *dev, Error **errp) 605 { 606 ICSState *ics = ICS_SIMPLE(dev); 607 608 if (!ics->nr_irqs) { 609 error_setg(errp, "Number of interrupts needs to be greater 0"); 610 return; 611 } 612 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); 613 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs); 614 615 qemu_register_reset(ics_simple_reset, dev); 616 } 617 618 static Property ics_simple_properties[] = { 619 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), 620 DEFINE_PROP_END_OF_LIST(), 621 }; 622 623 static void ics_simple_class_init(ObjectClass *klass, void *data) 624 { 625 DeviceClass *dc = DEVICE_CLASS(klass); 626 ICSStateClass *isc = ICS_BASE_CLASS(klass); 627 628 isc->realize = ics_simple_realize; 629 dc->props = ics_simple_properties; 630 dc->vmsd = &vmstate_ics_simple; 631 isc->reject = ics_simple_reject; 632 isc->resend = ics_simple_resend; 633 isc->eoi = ics_simple_eoi; 634 } 635 636 static const TypeInfo ics_simple_info = { 637 .name = TYPE_ICS_SIMPLE, 638 .parent = TYPE_ICS_BASE, 639 .instance_size = sizeof(ICSState), 640 .class_init = ics_simple_class_init, 641 .class_size = sizeof(ICSStateClass), 642 .instance_init = ics_simple_initfn, 643 }; 644 645 static void ics_base_realize(DeviceState *dev, Error **errp) 646 { 647 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev); 648 ICSState *ics = ICS_BASE(dev); 649 Object *obj; 650 Error *err = NULL; 651 652 obj = object_property_get_link(OBJECT(dev), "xics", &err); 653 if (!obj) { 654 error_setg(errp, "%s: required link 'xics' not found: %s", 655 __func__, error_get_pretty(err)); 656 return; 657 } 658 ics->xics = XICS_FABRIC(obj); 659 660 661 if (icsc->realize) { 662 icsc->realize(dev, errp); 663 } 664 } 665 666 static void ics_base_class_init(ObjectClass *klass, void *data) 667 { 668 DeviceClass *dc = DEVICE_CLASS(klass); 669 670 dc->realize = ics_base_realize; 671 } 672 673 static const TypeInfo ics_base_info = { 674 .name = TYPE_ICS_BASE, 675 .parent = TYPE_DEVICE, 676 .abstract = true, 677 .instance_size = sizeof(ICSState), 678 .class_init = ics_base_class_init, 679 .class_size = sizeof(ICSStateClass), 680 }; 681 682 static const TypeInfo xics_fabric_info = { 683 .name = TYPE_XICS_FABRIC, 684 .parent = TYPE_INTERFACE, 685 .class_size = sizeof(XICSFabricClass), 686 }; 687 688 /* 689 * Exported functions 690 */ 691 qemu_irq xics_get_qirq(XICSFabric *xi, int irq) 692 { 693 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 694 ICSState *ics = xic->ics_get(xi, irq); 695 696 if (ics) { 697 return ics->qirqs[irq - ics->offset]; 698 } 699 700 return NULL; 701 } 702 703 ICPState *xics_icp_get(XICSFabric *xi, int server) 704 { 705 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 706 707 return xic->icp_get(xi, server); 708 } 709 710 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) 711 { 712 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); 713 714 ics->irqs[srcno].flags |= 715 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; 716 } 717 718 static void xics_register_types(void) 719 { 720 type_register_static(&ics_simple_info); 721 type_register_static(&ics_base_info); 722 type_register_static(&icp_info); 723 type_register_static(&xics_fabric_info); 724 } 725 726 type_init(xics_register_types) 727